drivers/pinctrl/actions/pinctrl-owl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * OWL SoC's Pinctrl driver
   4  *
   5  * Copyright (c) 2014 Actions Semi Inc.
   6  * Author: David Liu <liuwei@actions-semi.com>
   7  *
   8  * Copyright (c) 2018 Linaro Ltd.
   9  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/err.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pinctrl/machine.h>
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27
  28 #include "../core.h"
  29 #include "../pinctrl-utils.h"
  30 #include "pinctrl-owl.h"
  31
  32 /**
  33  * struct owl_pinctrl - pinctrl state of the device
  34  * @dev: device handle
  35  * @pctrldev: pinctrl handle
  36  * @chip: gpio chip
  37  * @lock: spinlock to protect registers
  38  * @soc: reference to soc_data
  39  * @base: pinctrl register base address
  40  */
  41 struct owl_pinctrl {
  42         struct device *dev;
  43         struct pinctrl_dev *pctrldev;
  44         struct gpio_chip chip;
  45         raw_spinlock_t lock;
  46         struct clk *clk;
  47         const struct owl_pinctrl_soc_data *soc;
  48         void __iomem *base;
  49         struct irq_chip irq_chip;
  50         unsigned int num_irq;
  51         unsigned int *irq;
  52 };
  53
  54 static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
  55 {
  56         u32 reg_val;
  57
  58         reg_val = readl_relaxed(base);
  59
  60         reg_val = (reg_val & ~mask) | (val & mask);
  61
  62         writel_relaxed(reg_val, base);
  63 }
  64
  65 static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
  66                                 u32 bit, u32 width)
  67 {
  68         u32 tmp, mask;
  69
  70         tmp = readl_relaxed(pctrl->base + reg);
  71         mask = (1 << width) - 1;
  72
  73         return (tmp >> bit) & mask;
  74 }
  75
  76 static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
  77                                 u32 bit, u32 width)
  78 {
  79         u32 mask;
  80
  81         mask = (1 << width) - 1;
  82         mask = mask << bit;
  83
  84         owl_update_bits(pctrl->base + reg, mask, (arg << bit));
  85 }
  86
  87 static int owl_get_groups_count(struct pinctrl_dev *pctrldev)
  88 {
  89         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
  90
  91         return pctrl->soc->ngroups;
  92 }
  93
  94 static const char *owl_get_group_name(struct pinctrl_dev *pctrldev,
  95                                 unsigned int group)
  96 {
  97         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
  98
  99         return pctrl->soc->groups[group].name;
 100 }
 101
 102 static int owl_get_group_pins(struct pinctrl_dev *pctrldev,
 103                                 unsigned int group,
 104                                 const unsigned int **pins,
 105                                 unsigned int *num_pins)
 106 {
 107         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 108
 109         *pins = pctrl->soc->groups[group].pads;
 110         *num_pins = pctrl->soc->groups[group].npads;
 111
 112         return 0;
 113 }
 114
 115 static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
 116                                 struct seq_file *s,
 117                                 unsigned int offset)
 118 {
 119         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 120
 121         seq_printf(s, "%s", dev_name(pctrl->dev));
 122 }
 123
 124 static struct pinctrl_ops owl_pinctrl_ops = {
 125         .get_groups_count = owl_get_groups_count,
 126         .get_group_name = owl_get_group_name,
 127         .get_group_pins = owl_get_group_pins,
 128         .pin_dbg_show = owl_pin_dbg_show,
 129         .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
 130         .dt_free_map = pinctrl_utils_free_map,
 131 };
 132
 133 static int owl_get_funcs_count(struct pinctrl_dev *pctrldev)
 134 {
 135         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 136
 137         return pctrl->soc->nfunctions;
 138 }
 139
 140 static const char *owl_get_func_name(struct pinctrl_dev *pctrldev,
 141                                 unsigned int function)
 142 {
 143         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 144
 145         return pctrl->soc->functions[function].name;
 146 }
 147
 148 static int owl_get_func_groups(struct pinctrl_dev *pctrldev,
 149                                 unsigned int function,
 150                                 const char * const **groups,
 151                                 unsigned int * const num_groups)
 152 {
 153         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 154
 155         *groups = pctrl->soc->functions[function].groups;
 156         *num_groups = pctrl->soc->functions[function].ngroups;
 157
 158         return 0;
 159 }
 160
 161 static inline int get_group_mfp_mask_val(const struct owl_pingroup *g,
 162                                 int function,
 163                                 u32 *mask,
 164                                 u32 *val)
 165 {
 166         int id;
 167         u32 option_num;
 168         u32 option_mask;
 169
 170         for (id = 0; id < g->nfuncs; id++) {
 171                 if (g->funcs[id] == function)
 172                         break;
 173         }
 174         if (WARN_ON(id == g->nfuncs))
 175                 return -EINVAL;
 176
 177         option_num = (1 << g->mfpctl_width);
 178         if (id > option_num)
 179                 id -= option_num;
 180
 181         option_mask = option_num - 1;
 182         *mask = (option_mask  << g->mfpctl_shift);
 183         *val = (id << g->mfpctl_shift);
 184
 185         return 0;
 186 }
 187
 188 static int owl_set_mux(struct pinctrl_dev *pctrldev,
 189                                 unsigned int function,
 190                                 unsigned int group)
 191 {
 192         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 193         const struct owl_pingroup *g;
 194         unsigned long flags;
 195         u32 val, mask;
 196
 197         g = &pctrl->soc->groups[group];
 198
 199         if (get_group_mfp_mask_val(g, function, &mask, &val))
 200                 return -EINVAL;
 201
 202         raw_spin_lock_irqsave(&pctrl->lock, flags);
 203
 204         owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
 205
 206         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 207
 208         return 0;
 209 }
 210
 211 static struct pinmux_ops owl_pinmux_ops = {
 212         .get_functions_count = owl_get_funcs_count,
 213         .get_function_name = owl_get_func_name,
 214         .get_function_groups = owl_get_func_groups,
 215         .set_mux = owl_set_mux,
 216 };
 217
 218 static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
 219                                 unsigned int param,
 220                                 u32 *reg,
 221                                 u32 *bit,
 222                                 u32 *width)
 223 {
 224         switch (param) {
 225         case PIN_CONFIG_BIAS_BUS_HOLD:
 226         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 227         case PIN_CONFIG_BIAS_PULL_DOWN:
 228         case PIN_CONFIG_BIAS_PULL_UP:
 229                 if (!info->pullctl)
 230                         return -EINVAL;
 231                 *reg = info->pullctl->reg;
 232                 *bit = info->pullctl->shift;
 233                 *width = info->pullctl->width;
 234                 break;
 235         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 236                 if (!info->st)
 237                         return -EINVAL;
 238                 *reg = info->st->reg;
 239                 *bit = info->st->shift;
 240                 *width = info->st->width;
 241                 break;
 242         default:
 243                 return -ENOTSUPP;
 244         }
 245
 246         return 0;
 247 }
 248
 249 static int owl_pad_pinconf_arg2val(const struct owl_padinfo *info,
 250                                 unsigned int param,
 251                                 u32 *arg)
 252 {
 253         switch (param) {
 254         case PIN_CONFIG_BIAS_BUS_HOLD:
 255                 *arg = OWL_PINCONF_PULL_HOLD;
 256                 break;
 257         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 258                 *arg = OWL_PINCONF_PULL_HIZ;
 259                 break;
 260         case PIN_CONFIG_BIAS_PULL_DOWN:
 261                 *arg = OWL_PINCONF_PULL_DOWN;
 262                 break;
 263         case PIN_CONFIG_BIAS_PULL_UP:
 264                 *arg = OWL_PINCONF_PULL_UP;
 265                 break;
 266         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 267                 *arg = (*arg >= 1 ? 1 : 0);
 268                 break;
 269         default:
 270                 return -ENOTSUPP;
 271         }
 272
 273         return 0;
 274 }
 275
 276 static int owl_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
 277                                 unsigned int param,
 278                                 u32 *arg)
 279 {
 280         switch (param) {
 281         case PIN_CONFIG_BIAS_BUS_HOLD:
 282                 *arg = *arg == OWL_PINCONF_PULL_HOLD;
 283                 break;
 284         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 285                 *arg = *arg == OWL_PINCONF_PULL_HIZ;
 286                 break;
 287         case PIN_CONFIG_BIAS_PULL_DOWN:
 288                 *arg = *arg == OWL_PINCONF_PULL_DOWN;
 289                 break;
 290         case PIN_CONFIG_BIAS_PULL_UP:
 291                 *arg = *arg == OWL_PINCONF_PULL_UP;
 292                 break;
 293         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 294                 *arg = *arg == 1;
 295                 break;
 296         default:
 297                 return -ENOTSUPP;
 298         }
 299
 300         return 0;
 301 }
 302
 303 static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
 304                                 unsigned int pin,
 305                                 unsigned long *config)
 306 {
 307         int ret = 0;
 308         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 309         const struct owl_padinfo *info;
 310         unsigned int param = pinconf_to_config_param(*config);
 311         u32 reg, bit, width, arg;
 312
 313         info = &pctrl->soc->padinfo[pin];
 314
 315         ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);
 316         if (ret)
 317                 return ret;
 318
 319         arg = owl_read_field(pctrl, reg, bit, width);
 320
 321         ret = owl_pad_pinconf_val2arg(info, param, &arg);
 322         if (ret)
 323                 return ret;
 324
 325         *config = pinconf_to_config_packed(param, arg);
 326
 327         return ret;
 328 }
 329
 330 static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
 331                                 unsigned int pin,
 332                                 unsigned long *configs,
 333                                 unsigned int num_configs)
 334 {
 335         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 336         const struct owl_padinfo *info;
 337         unsigned long flags;
 338         unsigned int param;
 339         u32 reg, bit, width, arg;
 340         int ret = 0, i;
 341
 342         info = &pctrl->soc->padinfo[pin];
 343
 344         for (i = 0; i < num_configs; i++) {
 345                 param = pinconf_to_config_param(configs[i]);
 346                 arg = pinconf_to_config_argument(configs[i]);
 347
 348                 ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);
 349                 if (ret)
 350                         return ret;
 351
 352                 ret = owl_pad_pinconf_arg2val(info, param, &arg);
 353                 if (ret)
 354                         return ret;
 355
 356                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 357
 358                 owl_write_field(pctrl, reg, arg, bit, width);
 359
 360                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 361         }
 362
 363         return ret;
 364 }
 365
 366 static int owl_group_pinconf_reg(const struct owl_pingroup *g,
 367                                 unsigned int param,
 368                                 u32 *reg,
 369                                 u32 *bit,
 370                                 u32 *width)
 371 {
 372         switch (param) {
 373         case PIN_CONFIG_DRIVE_STRENGTH:
 374                 if (g->drv_reg < 0)
 375                         return -EINVAL;
 376                 *reg = g->drv_reg;
 377                 *bit = g->drv_shift;
 378                 *width = g->drv_width;
 379                 break;
 380         case PIN_CONFIG_SLEW_RATE:
 381                 if (g->sr_reg < 0)
 382                         return -EINVAL;
 383                 *reg = g->sr_reg;
 384                 *bit = g->sr_shift;
 385                 *width = g->sr_width;
 386                 break;
 387         default:
 388                 return -ENOTSUPP;
 389         }
 390
 391         return 0;
 392 }
 393
 394 static int owl_group_pinconf_arg2val(const struct owl_pingroup *g,
 395                                 unsigned int param,
 396                                 u32 *arg)
 397 {
 398         switch (param) {
 399         case PIN_CONFIG_DRIVE_STRENGTH:
 400                 switch (*arg) {
 401                 case 2:
 402                         *arg = OWL_PINCONF_DRV_2MA;
 403                         break;
 404                 case 4:
 405                         *arg = OWL_PINCONF_DRV_4MA;
 406                         break;
 407                 case 8:
 408                         *arg = OWL_PINCONF_DRV_8MA;
 409                         break;
 410                 case 12:
 411                         *arg = OWL_PINCONF_DRV_12MA;
 412                         break;
 413                 default:
 414                         return -EINVAL;
 415                 }
 416                 break;
 417         case PIN_CONFIG_SLEW_RATE:
 418                 if (*arg)
 419                         *arg = OWL_PINCONF_SLEW_FAST;
 420                 else
 421                         *arg = OWL_PINCONF_SLEW_SLOW;
 422                 break;
 423         default:
 424                 return -ENOTSUPP;
 425         }
 426
 427         return 0;
 428 }
 429
 430 static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
 431                                 unsigned int param,
 432                                 u32 *arg)
 433 {
 434         switch (param) {
 435         case PIN_CONFIG_DRIVE_STRENGTH:
 436                 switch (*arg) {
 437                 case OWL_PINCONF_DRV_2MA:
 438                         *arg = 2;
 439                         break;
 440                 case OWL_PINCONF_DRV_4MA:
 441                         *arg = 4;
 442                         break;
 443                 case OWL_PINCONF_DRV_8MA:
 444                         *arg = 8;
 445                         break;
 446                 case OWL_PINCONF_DRV_12MA:
 447                         *arg = 12;
 448                         break;
 449                 default:
 450                         return -EINVAL;
 451                 }
 452                 break;
 453         case PIN_CONFIG_SLEW_RATE:
 454                 if (*arg)
 455                         *arg = 1;
 456                 else
 457                         *arg = 0;
 458                 break;
 459         default:
 460                 return -ENOTSUPP;
 461         }
 462
 463         return 0;
 464 }
 465
 466 static int owl_group_config_get(struct pinctrl_dev *pctrldev,
 467                                 unsigned int group,
 468                                 unsigned long *config)
 469 {
 470         const struct owl_pingroup *g;
 471         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 472         unsigned int param = pinconf_to_config_param(*config);
 473         u32 reg, bit, width, arg;
 474         int ret;
 475
 476         g = &pctrl->soc->groups[group];
 477
 478         ret = owl_group_pinconf_reg(g, param, &reg, &bit, &width);
 479         if (ret)
 480                 return ret;
 481
 482         arg = owl_read_field(pctrl, reg, bit, width);
 483
 484         ret = owl_group_pinconf_val2arg(g, param, &arg);
 485         if (ret)
 486                 return ret;
 487
 488         *config = pinconf_to_config_packed(param, arg);
 489
 490         return ret;
 491
 492 }
 493
 494 static int owl_group_config_set(struct pinctrl_dev *pctrldev,
 495                                 unsigned int group,
 496                                 unsigned long *configs,
 497                                 unsigned int num_configs)
 498 {
 499         const struct owl_pingroup *g;
 500         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 501         unsigned long flags;
 502         unsigned int param;
 503         u32 reg, bit, width, arg;
 504         int ret, i;
 505
 506         g = &pctrl->soc->groups[group];
 507
 508         for (i = 0; i < num_configs; i++) {
 509                 param = pinconf_to_config_param(configs[i]);
 510                 arg = pinconf_to_config_argument(configs[i]);
 511
 512                 ret = owl_group_pinconf_reg(g, param, &reg, &bit, &width);
 513                 if (ret)
 514                         return ret;
 515
 516                 ret = owl_group_pinconf_arg2val(g, param, &arg);
 517                 if (ret)
 518                         return ret;
 519
 520                 /* Update register */
 521                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 522
 523                 owl_write_field(pctrl, reg, arg, bit, width);
 524
 525                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 526         }
 527
 528         return 0;
 529 }
 530
 531 static const struct pinconf_ops owl_pinconf_ops = {
 532         .is_generic = true,
 533         .pin_config_get = owl_pin_config_get,
 534         .pin_config_set = owl_pin_config_set,
 535         .pin_config_group_get = owl_group_config_get,
 536         .pin_config_group_set = owl_group_config_set,
 537 };
 538
 539 static struct pinctrl_desc owl_pinctrl_desc = {
 540         .pctlops = &owl_pinctrl_ops,
 541         .pmxops = &owl_pinmux_ops,
 542         .confops = &owl_pinconf_ops,
 543         .owner = THIS_MODULE,
 544 };
 545
 546 static const struct owl_gpio_port *
 547 owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
 548 {
 549         unsigned int start = 0, i;
 550
 551         for (i = 0; i < pctrl->soc->nports; i++) {
 552                 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
 553
 554                 if (*pin >= start && *pin < start + port->pins) {
 555                         *pin -= start;
 556                         return port;
 557                 }
 558
 559                 start += port->pins;
 560         }
 561
 562         return NULL;
 563 }
 564
 565 static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
 566 {
 567         u32 val;
 568
 569         val = readl_relaxed(base);
 570
 571         if (flag)
 572                 val |= BIT(pin);
 573         else
 574                 val &= ~BIT(pin);
 575
 576         writel_relaxed(val, base);
 577 }
 578
 579 static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
 580 {
 581         struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
 582         const struct owl_gpio_port *port;
 583         void __iomem *gpio_base;
 584         unsigned long flags;
 585
 586         port = owl_gpio_get_port(pctrl, &offset);
 587         if (WARN_ON(port == NULL))
 588                 return -ENODEV;
 589
 590         gpio_base = pctrl->base + port->offset;
 591
 592         /*
 593          * GPIOs have higher priority over other modules, so either setting
 594          * them as OUT or IN is sufficient
 595          */
 596         raw_spin_lock_irqsave(&pctrl->lock, flags);
 597         owl_gpio_update_reg(gpio_base + port->outen, offset, true);
 598         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 599
 600         return 0;
 601 }
 602
 603 static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
 604 {
 605         struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
 606         const struct owl_gpio_port *port;
 607         void __iomem *gpio_base;
 608         unsigned long flags;
 609
 610         port = owl_gpio_get_port(pctrl, &offset);
 611         if (WARN_ON(port == NULL))
 612                 return;
 613
 614         gpio_base = pctrl->base + port->offset;
 615
 616         raw_spin_lock_irqsave(&pctrl->lock, flags);
 617         /* disable gpio output */
 618         owl_gpio_update_reg(gpio_base + port->outen, offset, false);
 619
 620         /* disable gpio input */
 621         owl_gpio_update_reg(gpio_base + port->inen, offset, false);
 622         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 623 }
 624
 625 static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
 626 {
 627         struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
 628         const struct owl_gpio_port *port;
 629         void __iomem *gpio_base;
 630         unsigned long flags;
 631         u32 val;
 632
 633         port = owl_gpio_get_port(pctrl, &offset);
 634         if (WARN_ON(port == NULL))
 635                 return -ENODEV;
 636
 637         gpio_base = pctrl->base + port->offset;
 638
 639         raw_spin_lock_irqsave(&pctrl->lock, flags);
 640         val = readl_relaxed(gpio_base + port->dat);
 641         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 642
 643         return !!(val & BIT(offset));
 644 }
 645
 646 static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
 647 {
 648         struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
 649         const struct owl_gpio_port *port;
 650         void __iomem *gpio_base;
 651         unsigned long flags;
 652
 653         port = owl_gpio_get_port(pctrl, &offset);
 654         if (WARN_ON(port == NULL))
 655                 return;
 656
 657         gpio_base = pctrl->base + port->offset;
 658
 659         raw_spin_lock_irqsave(&pctrl->lock, flags);
 660         owl_gpio_update_reg(gpio_base + port->dat, offset, value);
 661         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 662 }
 663
 664 static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 665 {
 666         struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
 667         const struct owl_gpio_port *port;
 668         void __iomem *gpio_base;
 669         unsigned long flags;
 670
 671         port = owl_gpio_get_port(pctrl, &offset);
 672         if (WARN_ON(port == NULL))
 673                 return -ENODEV;
 674
 675         gpio_base = pctrl->base + port->offset;
 676
 677         raw_spin_lock_irqsave(&pctrl->lock, flags);
 678         owl_gpio_update_reg(gpio_base + port->outen, offset, false);
 679         owl_gpio_update_reg(gpio_base + port->inen, offset, true);
 680         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 681
 682         return 0;
 683 }
 684
 685 static int owl_gpio_direction_output(struct gpio_chip *chip,
 686                                 unsigned int offset, int value)
 687 {
 688         struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
 689         const struct owl_gpio_port *port;
 690         void __iomem *gpio_base;
 691         unsigned long flags;
 692
 693         port = owl_gpio_get_port(pctrl, &offset);
 694         if (WARN_ON(port == NULL))
 695                 return -ENODEV;
 696
 697         gpio_base = pctrl->base + port->offset;
 698
 699         raw_spin_lock_irqsave(&pctrl->lock, flags);
 700         owl_gpio_update_reg(gpio_base + port->inen, offset, false);
 701         owl_gpio_update_reg(gpio_base + port->outen, offset, true);
 702         owl_gpio_update_reg(gpio_base + port->dat, offset, value);
 703         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 704
 705         return 0;
 706 }
 707
 708 static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
 709 {
 710         const struct owl_gpio_port *port;
 711         void __iomem *gpio_base;
 712         unsigned long flags;
 713         unsigned int offset, value, irq_type = 0;
 714
 715         switch (type) {
 716         case IRQ_TYPE_EDGE_BOTH:
 717                 /*
 718                  * Since the hardware doesn't support interrupts on both edges,
 719                  * emulate it in the software by setting the single edge
 720                  * interrupt and switching to the opposite edge while ACKing
 721                  * the interrupt
 722                  */
 723                 if (owl_gpio_get(&pctrl->chip, gpio))
 724                         irq_type = OWL_GPIO_INT_EDGE_FALLING;
 725                 else
 726                         irq_type = OWL_GPIO_INT_EDGE_RISING;
 727                 break;
 728
 729         case IRQ_TYPE_EDGE_RISING:
 730                 irq_type = OWL_GPIO_INT_EDGE_RISING;
 731                 break;
 732
 733         case IRQ_TYPE_EDGE_FALLING:
 734                 irq_type = OWL_GPIO_INT_EDGE_FALLING;
 735                 break;
 736
 737         case IRQ_TYPE_LEVEL_HIGH:
 738                 irq_type = OWL_GPIO_INT_LEVEL_HIGH;
 739                 break;
 740
 741         case IRQ_TYPE_LEVEL_LOW:
 742                 irq_type = OWL_GPIO_INT_LEVEL_LOW;
 743                 break;
 744
 745         default:
 746                 break;
 747         }
 748
 749         port = owl_gpio_get_port(pctrl, &gpio);
 750         if (WARN_ON(port == NULL))
 751                 return;
 752
 753         gpio_base = pctrl->base + port->offset;
 754
 755         raw_spin_lock_irqsave(&pctrl->lock, flags);
 756
 757         offset = (gpio < 16) ? 4 : 0;
 758         value = readl_relaxed(gpio_base + port->intc_type + offset);
 759         value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2));
 760         value |= irq_type << ((gpio % 16) * 2);
 761         writel_relaxed(value, gpio_base + port->intc_type + offset);
 762
 763         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 764 }
 765
 766 static void owl_gpio_irq_mask(struct irq_data *data)
 767 {
 768         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
 769         struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
 770         const struct owl_gpio_port *port;
 771         void __iomem *gpio_base;
 772         unsigned long flags;
 773         unsigned int gpio = data->hwirq;
 774         u32 val;
 775
 776         port = owl_gpio_get_port(pctrl, &gpio);
 777         if (WARN_ON(port == NULL))
 778                 return;
 779
 780         gpio_base = pctrl->base + port->offset;
 781
 782         raw_spin_lock_irqsave(&pctrl->lock, flags);
 783
 784         owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false);
 785
 786         /* disable port interrupt if no interrupt pending bit is active */
 787         val = readl_relaxed(gpio_base + port->intc_msk);
 788         if (val == 0)
 789                 owl_gpio_update_reg(gpio_base + port->intc_ctl,
 790                                         OWL_GPIO_CTLR_ENABLE, false);
 791
 792         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 793 }
 794
 795 static void owl_gpio_irq_unmask(struct irq_data *data)
 796 {
 797         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
 798         struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
 799         const struct owl_gpio_port *port;
 800         void __iomem *gpio_base;
 801         unsigned long flags;
 802         unsigned int gpio = data->hwirq;
 803         u32 value;
 804
 805         port = owl_gpio_get_port(pctrl, &gpio);
 806         if (WARN_ON(port == NULL))
 807                 return;
 808
 809         gpio_base = pctrl->base + port->offset;
 810         raw_spin_lock_irqsave(&pctrl->lock, flags);
 811
 812         /* enable port interrupt */
 813         value = readl_relaxed(gpio_base + port->intc_ctl);
 814         value |= BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M);
 815         writel_relaxed(value, gpio_base + port->intc_ctl);
 816
 817         /* enable GPIO interrupt */
 818         owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true);
 819
 820         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 821 }
 822
 823 static void owl_gpio_irq_ack(struct irq_data *data)
 824 {
 825         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
 826         struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
 827         const struct owl_gpio_port *port;
 828         void __iomem *gpio_base;
 829         unsigned long flags;
 830         unsigned int gpio = data->hwirq;
 831
 832         /*
 833          * Switch the interrupt edge to the opposite edge of the interrupt
 834          * which got triggered for the case of emulating both edges
 835          */
 836         if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
 837                 if (owl_gpio_get(gc, gpio))
 838                         irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING);
 839                 else
 840                         irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING);
 841         }
 842
 843         port = owl_gpio_get_port(pctrl, &gpio);
 844         if (WARN_ON(port == NULL))
 845                 return;
 846
 847         gpio_base = pctrl->base + port->offset;
 848
 849         raw_spin_lock_irqsave(&pctrl->lock, flags);
 850
 851         owl_gpio_update_reg(gpio_base + port->intc_ctl,
 852                                 OWL_GPIO_CTLR_PENDING, true);
 853
 854         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 855 }
 856
 857 static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
 858 {
 859         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
 860         struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
 861
 862         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 863                 irq_set_handler_locked(data, handle_level_irq);
 864         else
 865                 irq_set_handler_locked(data, handle_edge_irq);
 866
 867         irq_set_type(pctrl, data->hwirq, type);
 868
 869         return 0;
 870 }
 871
 872 static void owl_gpio_irq_handler(struct irq_desc *desc)
 873 {
 874         struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
 875         struct irq_chip *chip = irq_desc_get_chip(desc);
 876         struct irq_domain *domain = pctrl->chip.irq.domain;
 877         unsigned int parent = irq_desc_get_irq(desc);
 878         const struct owl_gpio_port *port;
 879         void __iomem *base;
 880         unsigned int pin, irq, offset = 0, i;
 881         unsigned long pending_irq;
 882
 883         chained_irq_enter(chip, desc);
 884
 885         for (i = 0; i < pctrl->soc->nports; i++) {
 886                 port = &pctrl->soc->ports[i];
 887                 base = pctrl->base + port->offset;
 888
 889                 /* skip ports that are not associated with this irq */
 890                 if (parent != pctrl->irq[i])
 891                         goto skip;
 892
 893                 pending_irq = readl_relaxed(base + port->intc_pd);
 894
 895                 for_each_set_bit(pin, &pending_irq, port->pins) {
 896                         irq = irq_find_mapping(domain, offset + pin);
 897                         generic_handle_irq(irq);
 898
 899                         /* clear pending interrupt */
 900                         owl_gpio_update_reg(base + port->intc_pd, pin, true);
 901                 }
 902
 903 skip:
 904                 offset += port->pins;
 905         }
 906
 907         chained_irq_exit(chip, desc);
 908 }
 909
 910 static int owl_gpio_init(struct owl_pinctrl *pctrl)
 911 {
 912         struct gpio_chip *chip;
 913         struct gpio_irq_chip *gpio_irq;
 914         int ret, i, j, offset;
 915
 916         chip = &pctrl->chip;
 917         chip->base = -1;
 918         chip->ngpio = pctrl->soc->ngpios;
 919         chip->label = dev_name(pctrl->dev);
 920         chip->parent = pctrl->dev;
 921         chip->owner = THIS_MODULE;
 922         chip->of_node = pctrl->dev->of_node;
 923
 924         pctrl->irq_chip.name = chip->of_node->name;
 925         pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
 926         pctrl->irq_chip.irq_mask = owl_gpio_irq_mask;
 927         pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask;
 928         pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type;
 929
 930         gpio_irq = &chip->irq;
 931         gpio_irq->chip = &pctrl->irq_chip;
 932         gpio_irq->handler = handle_simple_irq;
 933         gpio_irq->default_type = IRQ_TYPE_NONE;
 934         gpio_irq->parent_handler = owl_gpio_irq_handler;
 935         gpio_irq->parent_handler_data = pctrl;
 936         gpio_irq->num_parents = pctrl->num_irq;
 937         gpio_irq->parents = pctrl->irq;
 938
 939         gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
 940                                 sizeof(*gpio_irq->map), GFP_KERNEL);
 941         if (!gpio_irq->map)
 942                 return -ENOMEM;
 943
 944         for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
 945                 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
 946
 947                 for (j = 0; j < port->pins; j++)
 948                         gpio_irq->map[offset + j] = gpio_irq->parents[i];
 949
 950                 offset += port->pins;
 951         }
 952
 953         ret = gpiochip_add_data(&pctrl->chip, pctrl);
 954         if (ret) {
 955                 dev_err(pctrl->dev, "failed to register gpiochip\n");
 956                 return ret;
 957         }
 958
 959         return 0;
 960 }
 961
 962 int owl_pinctrl_probe(struct platform_device *pdev,
 963                                 struct owl_pinctrl_soc_data *soc_data)
 964 {
 965         struct resource *res;
 966         struct owl_pinctrl *pctrl;
 967         int ret, i;
 968
 969         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 970         if (!pctrl)
 971                 return -ENOMEM;
 972
 973         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 974         pctrl->base = devm_ioremap_resource(&pdev->dev, res);
 975         if (IS_ERR(pctrl->base))
 976                 return PTR_ERR(pctrl->base);
 977
 978         /* enable GPIO/MFP clock */
 979         pctrl->clk = devm_clk_get(&pdev->dev, NULL);
 980         if (IS_ERR(pctrl->clk)) {
 981                 dev_err(&pdev->dev, "no clock defined\n");
 982                 return PTR_ERR(pctrl->clk);
 983         }
 984
 985         ret = clk_prepare_enable(pctrl->clk);
 986         if (ret) {
 987                 dev_err(&pdev->dev, "clk enable failed\n");
 988                 return ret;
 989         }
 990
 991         raw_spin_lock_init(&pctrl->lock);
 992
 993         owl_pinctrl_desc.name = dev_name(&pdev->dev);
 994         owl_pinctrl_desc.pins = soc_data->pins;
 995         owl_pinctrl_desc.npins = soc_data->npins;
 996
 997         pctrl->chip.direction_input  = owl_gpio_direction_input;
 998         pctrl->chip.direction_output = owl_gpio_direction_output;
 999         pctrl->chip.get = owl_gpio_get;
1000         pctrl->chip.set = owl_gpio_set;
1001         pctrl->chip.request = owl_gpio_request;
1002         pctrl->chip.free = owl_gpio_free;
1003
1004         pctrl->soc = soc_data;
1005         pctrl->dev = &pdev->dev;
1006
1007         pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
1008                                         &owl_pinctrl_desc, pctrl);
1009         if (IS_ERR(pctrl->pctrldev)) {
1010                 dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
1011                 ret = PTR_ERR(pctrl->pctrldev);
1012                 goto err_exit;
1013         }
1014
1015         ret = platform_irq_count(pdev);
1016         if (ret < 0)
1017                 goto err_exit;
1018
1019         pctrl->num_irq = ret;
1020
1021         pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
1022                                         sizeof(*pctrl->irq), GFP_KERNEL);
1023         if (!pctrl->irq) {
1024                 ret = -ENOMEM;
1025                 goto err_exit;
1026         }
1027
1028         for (i = 0; i < pctrl->num_irq ; i++) {
1029                 ret = platform_get_irq(pdev, i);
1030                 if (ret < 0)
1031                         goto err_exit;
1032                 pctrl->irq[i] = ret;
1033         }
1034
1035         ret = owl_gpio_init(pctrl);
1036         if (ret)
1037                 goto err_exit;
1038
1039         platform_set_drvdata(pdev, pctrl);
1040
1041         return 0;
1042
1043 err_exit:
1044         clk_disable_unprepare(pctrl->clk);
1045
1046         return ret;
1047 }