drivers/pinctrl/intel/pinctrl-baytrail.c

   1 /*
   2  * Pinctrl GPIO driver for Intel Baytrail
   3  * Copyright (c) 2012-2013, Intel Corporation.
   4  *
   5  * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/types.h>
  20 #include <linux/bitops.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/gpio.h>
  23 #include <linux/gpio/driver.h>
  24 #include <linux/acpi.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/io.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/pinctrl/pinctrl.h>
  30 #include <linux/pinctrl/pinmux.h>
  31 #include <linux/pinctrl/pinconf.h>
  32 #include <linux/pinctrl/pinconf-generic.h>
  33
  34 /* memory mapped register offsets */
  35 #define BYT_CONF0_REG           0x000
  36 #define BYT_CONF1_REG           0x004
  37 #define BYT_VAL_REG             0x008
  38 #define BYT_DFT_REG             0x00c
  39 #define BYT_INT_STAT_REG        0x800
  40 #define BYT_DEBOUNCE_REG        0x9d0
  41
  42 /* BYT_CONF0_REG register bits */
  43 #define BYT_IODEN               BIT(31)
  44 #define BYT_DIRECT_IRQ_EN       BIT(27)
  45 #define BYT_TRIG_NEG            BIT(26)
  46 #define BYT_TRIG_POS            BIT(25)
  47 #define BYT_TRIG_LVL            BIT(24)
  48 #define BYT_DEBOUNCE_EN         BIT(20)
  49 #define BYT_GLITCH_FILTER_EN    BIT(19)
  50 #define BYT_GLITCH_F_SLOW_CLK   BIT(17)
  51 #define BYT_GLITCH_F_FAST_CLK   BIT(16)
  52 #define BYT_PULL_STR_SHIFT      9
  53 #define BYT_PULL_STR_MASK       (3 << BYT_PULL_STR_SHIFT)
  54 #define BYT_PULL_STR_2K         (0 << BYT_PULL_STR_SHIFT)
  55 #define BYT_PULL_STR_10K        (1 << BYT_PULL_STR_SHIFT)
  56 #define BYT_PULL_STR_20K        (2 << BYT_PULL_STR_SHIFT)
  57 #define BYT_PULL_STR_40K        (3 << BYT_PULL_STR_SHIFT)
  58 #define BYT_PULL_ASSIGN_SHIFT   7
  59 #define BYT_PULL_ASSIGN_MASK    (3 << BYT_PULL_ASSIGN_SHIFT)
  60 #define BYT_PULL_ASSIGN_UP      (1 << BYT_PULL_ASSIGN_SHIFT)
  61 #define BYT_PULL_ASSIGN_DOWN    (2 << BYT_PULL_ASSIGN_SHIFT)
  62 #define BYT_PIN_MUX             0x07
  63
  64 /* BYT_VAL_REG register bits */
  65 #define BYT_INPUT_EN            BIT(2)  /* 0: input enabled (active low)*/
  66 #define BYT_OUTPUT_EN           BIT(1)  /* 0: output enabled (active low)*/
  67 #define BYT_LEVEL               BIT(0)
  68
  69 #define BYT_DIR_MASK            (BIT(1) | BIT(2))
  70 #define BYT_TRIG_MASK           (BIT(26) | BIT(25) | BIT(24))
  71
  72 #define BYT_CONF0_RESTORE_MASK  (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \
  73                                  BYT_PIN_MUX)
  74 #define BYT_VAL_RESTORE_MASK    (BYT_DIR_MASK | BYT_LEVEL)
  75
  76 /* BYT_DEBOUNCE_REG bits */
  77 #define BYT_DEBOUNCE_PULSE_MASK         0x7
  78 #define BYT_DEBOUNCE_PULSE_375US        1
  79 #define BYT_DEBOUNCE_PULSE_750US        2
  80 #define BYT_DEBOUNCE_PULSE_1500US       3
  81 #define BYT_DEBOUNCE_PULSE_3MS          4
  82 #define BYT_DEBOUNCE_PULSE_6MS          5
  83 #define BYT_DEBOUNCE_PULSE_12MS         6
  84 #define BYT_DEBOUNCE_PULSE_24MS         7
  85
  86 #define BYT_NGPIO_SCORE         102
  87 #define BYT_NGPIO_NCORE         28
  88 #define BYT_NGPIO_SUS           44
  89
  90 #define BYT_SCORE_ACPI_UID      "1"
  91 #define BYT_NCORE_ACPI_UID      "2"
  92 #define BYT_SUS_ACPI_UID        "3"
  93
  94 /*
  95  * This is the function value most pins have for GPIO muxing. If the value
  96  * differs from the default one, it must be explicitly mentioned. Otherwise, the
  97  * pin control implementation will set the muxing value to default GPIO if it
  98  * does not find a match for the requested function.
  99  */
 100 #define BYT_DEFAULT_GPIO_MUX    0
 101
 102 struct byt_gpio_pin_context {
 103         u32 conf0;
 104         u32 val;
 105 };
 106
 107 struct byt_simple_func_mux {
 108         const char *name;
 109         unsigned short func;
 110 };
 111
 112 struct byt_mixed_func_mux {
 113         const char *name;
 114         const unsigned short *func_values;
 115 };
 116
 117 struct byt_pingroup {
 118         const char *name;
 119         const unsigned int *pins;
 120         size_t npins;
 121         unsigned short has_simple_funcs;
 122         union {
 123                 const struct byt_simple_func_mux *simple_funcs;
 124                 const struct byt_mixed_func_mux *mixed_funcs;
 125         };
 126         size_t nfuncs;
 127 };
 128
 129 struct byt_function {
 130         const char *name;
 131         const char * const *groups;
 132         size_t ngroups;
 133 };
 134
 135 struct byt_community {
 136         unsigned int pin_base;
 137         size_t npins;
 138         const unsigned int *pad_map;
 139         void __iomem *reg_base;
 140 };
 141
 142 #define SIMPLE_FUNC(n, f)       \
 143         {                       \
 144                 .name   = (n),  \
 145                 .func   = (f),  \
 146         }
 147 #define MIXED_FUNC(n, f)                \
 148         {                               \
 149                 .name           = (n),  \
 150                 .func_values    = (f),  \
 151         }
 152
 153 #define PIN_GROUP_SIMPLE(n, p, f)                               \
 154         {                                                       \
 155                 .name                   = (n),                  \
 156                 .pins                   = (p),                  \
 157                 .npins                  = ARRAY_SIZE((p)),      \
 158                 .has_simple_funcs       = 1,                    \
 159                 {                                               \
 160                         .simple_funcs           = (f),          \
 161                 },                                              \
 162                 .nfuncs                 = ARRAY_SIZE((f)),      \
 163         }
 164 #define PIN_GROUP_MIXED(n, p, f)                                \
 165         {                                                       \
 166                 .name                   = (n),                  \
 167                 .pins                   = (p),                  \
 168                 .npins                  = ARRAY_SIZE((p)),      \
 169                 .has_simple_funcs       = 0,                    \
 170                 {                                               \
 171                         .mixed_funcs            = (f),          \
 172                 },                                              \
 173                 .nfuncs                 = ARRAY_SIZE((f)),      \
 174         }
 175
 176 #define FUNCTION(n, g)                                  \
 177         {                                               \
 178                 .name           = (n),                  \
 179                 .groups         = (g),                  \
 180                 .ngroups        = ARRAY_SIZE((g)),      \
 181         }
 182
 183 #define COMMUNITY(p, n, map)            \
 184         {                               \
 185                 .pin_base       = (p),  \
 186                 .npins          = (n),  \
 187                 .pad_map        = (map),\
 188         }
 189
 190 struct byt_pinctrl_soc_data {
 191         const char *uid;
 192         const struct pinctrl_pin_desc *pins;
 193         size_t npins;
 194         const struct byt_pingroup *groups;
 195         size_t ngroups;
 196         const struct byt_function *functions;
 197         size_t nfunctions;
 198         const struct byt_community *communities;
 199         size_t ncommunities;
 200 };
 201
 202 struct byt_gpio {
 203         struct gpio_chip chip;
 204         struct platform_device *pdev;
 205         struct pinctrl_dev *pctl_dev;
 206         struct pinctrl_desc pctl_desc;
 207         const struct byt_pinctrl_soc_data *soc_data;
 208         struct byt_community *communities_copy;
 209         struct byt_gpio_pin_context *saved_context;
 210 };
 211
 212 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
 213 static const struct pinctrl_pin_desc byt_score_pins[] = {
 214         PINCTRL_PIN(0, "SATA_GP0"),
 215         PINCTRL_PIN(1, "SATA_GP1"),
 216         PINCTRL_PIN(2, "SATA_LED#"),
 217         PINCTRL_PIN(3, "PCIE_CLKREQ0"),
 218         PINCTRL_PIN(4, "PCIE_CLKREQ1"),
 219         PINCTRL_PIN(5, "PCIE_CLKREQ2"),
 220         PINCTRL_PIN(6, "PCIE_CLKREQ3"),
 221         PINCTRL_PIN(7, "SD3_WP"),
 222         PINCTRL_PIN(8, "HDA_RST"),
 223         PINCTRL_PIN(9, "HDA_SYNC"),
 224         PINCTRL_PIN(10, "HDA_CLK"),
 225         PINCTRL_PIN(11, "HDA_SDO"),
 226         PINCTRL_PIN(12, "HDA_SDI0"),
 227         PINCTRL_PIN(13, "HDA_SDI1"),
 228         PINCTRL_PIN(14, "GPIO_S0_SC14"),
 229         PINCTRL_PIN(15, "GPIO_S0_SC15"),
 230         PINCTRL_PIN(16, "MMC1_CLK"),
 231         PINCTRL_PIN(17, "MMC1_D0"),
 232         PINCTRL_PIN(18, "MMC1_D1"),
 233         PINCTRL_PIN(19, "MMC1_D2"),
 234         PINCTRL_PIN(20, "MMC1_D3"),
 235         PINCTRL_PIN(21, "MMC1_D4"),
 236         PINCTRL_PIN(22, "MMC1_D5"),
 237         PINCTRL_PIN(23, "MMC1_D6"),
 238         PINCTRL_PIN(24, "MMC1_D7"),
 239         PINCTRL_PIN(25, "MMC1_CMD"),
 240         PINCTRL_PIN(26, "MMC1_RST"),
 241         PINCTRL_PIN(27, "SD2_CLK"),
 242         PINCTRL_PIN(28, "SD2_D0"),
 243         PINCTRL_PIN(29, "SD2_D1"),
 244         PINCTRL_PIN(30, "SD2_D2"),
 245         PINCTRL_PIN(31, "SD2_D3_CD"),
 246         PINCTRL_PIN(32, "SD2_CMD"),
 247         PINCTRL_PIN(33, "SD3_CLK"),
 248         PINCTRL_PIN(34, "SD3_D0"),
 249         PINCTRL_PIN(35, "SD3_D1"),
 250         PINCTRL_PIN(36, "SD3_D2"),
 251         PINCTRL_PIN(37, "SD3_D3"),
 252         PINCTRL_PIN(38, "SD3_CD"),
 253         PINCTRL_PIN(39, "SD3_CMD"),
 254         PINCTRL_PIN(40, "SD3_1P8EN"),
 255         PINCTRL_PIN(41, "SD3_PWREN#"),
 256         PINCTRL_PIN(42, "ILB_LPC_AD0"),
 257         PINCTRL_PIN(43, "ILB_LPC_AD1"),
 258         PINCTRL_PIN(44, "ILB_LPC_AD2"),
 259         PINCTRL_PIN(45, "ILB_LPC_AD3"),
 260         PINCTRL_PIN(46, "ILB_LPC_FRAME"),
 261         PINCTRL_PIN(47, "ILB_LPC_CLK0"),
 262         PINCTRL_PIN(48, "ILB_LPC_CLK1"),
 263         PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
 264         PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
 265         PINCTRL_PIN(51, "PCU_SMB_DATA"),
 266         PINCTRL_PIN(52, "PCU_SMB_CLK"),
 267         PINCTRL_PIN(53, "PCU_SMB_ALERT"),
 268         PINCTRL_PIN(54, "ILB_8254_SPKR"),
 269         PINCTRL_PIN(55, "GPIO_S0_SC55"),
 270         PINCTRL_PIN(56, "GPIO_S0_SC56"),
 271         PINCTRL_PIN(57, "GPIO_S0_SC57"),
 272         PINCTRL_PIN(58, "GPIO_S0_SC58"),
 273         PINCTRL_PIN(59, "GPIO_S0_SC59"),
 274         PINCTRL_PIN(60, "GPIO_S0_SC60"),
 275         PINCTRL_PIN(61, "GPIO_S0_SC61"),
 276         PINCTRL_PIN(62, "LPE_I2S2_CLK"),
 277         PINCTRL_PIN(63, "LPE_I2S2_FRM"),
 278         PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
 279         PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
 280         PINCTRL_PIN(66, "SIO_SPI_CS"),
 281         PINCTRL_PIN(67, "SIO_SPI_MISO"),
 282         PINCTRL_PIN(68, "SIO_SPI_MOSI"),
 283         PINCTRL_PIN(69, "SIO_SPI_CLK"),
 284         PINCTRL_PIN(70, "SIO_UART1_RXD"),
 285         PINCTRL_PIN(71, "SIO_UART1_TXD"),
 286         PINCTRL_PIN(72, "SIO_UART1_RTS"),
 287         PINCTRL_PIN(73, "SIO_UART1_CTS"),
 288         PINCTRL_PIN(74, "SIO_UART2_RXD"),
 289         PINCTRL_PIN(75, "SIO_UART2_TXD"),
 290         PINCTRL_PIN(76, "SIO_UART2_RTS"),
 291         PINCTRL_PIN(77, "SIO_UART2_CTS"),
 292         PINCTRL_PIN(78, "SIO_I2C0_DATA"),
 293         PINCTRL_PIN(79, "SIO_I2C0_CLK"),
 294         PINCTRL_PIN(80, "SIO_I2C1_DATA"),
 295         PINCTRL_PIN(81, "SIO_I2C1_CLK"),
 296         PINCTRL_PIN(82, "SIO_I2C2_DATA"),
 297         PINCTRL_PIN(83, "SIO_I2C2_CLK"),
 298         PINCTRL_PIN(84, "SIO_I2C3_DATA"),
 299         PINCTRL_PIN(85, "SIO_I2C3_CLK"),
 300         PINCTRL_PIN(86, "SIO_I2C4_DATA"),
 301         PINCTRL_PIN(87, "SIO_I2C4_CLK"),
 302         PINCTRL_PIN(88, "SIO_I2C5_DATA"),
 303         PINCTRL_PIN(89, "SIO_I2C5_CLK"),
 304         PINCTRL_PIN(90, "SIO_I2C6_DATA"),
 305         PINCTRL_PIN(91, "SIO_I2C6_CLK"),
 306         PINCTRL_PIN(92, "GPIO_S0_SC92"),
 307         PINCTRL_PIN(93, "GPIO_S0_SC93"),
 308         PINCTRL_PIN(94, "SIO_PWM0"),
 309         PINCTRL_PIN(95, "SIO_PWM1"),
 310         PINCTRL_PIN(96, "PMC_PLT_CLK0"),
 311         PINCTRL_PIN(97, "PMC_PLT_CLK1"),
 312         PINCTRL_PIN(98, "PMC_PLT_CLK2"),
 313         PINCTRL_PIN(99, "PMC_PLT_CLK3"),
 314         PINCTRL_PIN(100, "PMC_PLT_CLK4"),
 315         PINCTRL_PIN(101, "PMC_PLT_CLK5"),
 316 };
 317
 318 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
 319         85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
 320         36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
 321         54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
 322         52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
 323         95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
 324         86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
 325         80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
 326         2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
 327         31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
 328         24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
 329         97, 100,
 330 };
 331
 332 /* SCORE groups */
 333 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
 334 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
 335 static const struct byt_simple_func_mux byt_score_uart_mux[] = {
 336         SIMPLE_FUNC("uart", 1),
 337 };
 338
 339 static const unsigned int byt_score_pwm0_pins[] = { 94 };
 340 static const unsigned int byt_score_pwm1_pins[] = { 95 };
 341 static const struct byt_simple_func_mux byt_score_pwm_mux[] = {
 342         SIMPLE_FUNC("pwm", 1),
 343 };
 344
 345 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
 346 static const struct byt_simple_func_mux byt_score_spi_mux[] = {
 347         SIMPLE_FUNC("spi", 1),
 348 };
 349
 350 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
 351 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
 352 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
 353 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
 354 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
 355 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
 356 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
 357 static const struct byt_simple_func_mux byt_score_i2c_mux[] = {
 358         SIMPLE_FUNC("i2c", 1),
 359 };
 360
 361 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
 362 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
 363 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
 364 static const struct byt_simple_func_mux byt_score_ssp_mux[] = {
 365         SIMPLE_FUNC("ssp", 1),
 366 };
 367
 368 static const unsigned int byt_score_sdcard_pins[] = {
 369         7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
 370 };
 371 static const unsigned short byt_score_sdcard_mux_values[] = {
 372         2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 373 };
 374 static const struct byt_mixed_func_mux byt_score_sdcard_mux[] = {
 375         MIXED_FUNC("sdcard", byt_score_sdcard_mux_values),
 376 };
 377
 378 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
 379 static const struct byt_simple_func_mux byt_score_sdio_mux[] = {
 380         SIMPLE_FUNC("sdio", 1),
 381 };
 382
 383 static const unsigned int byt_score_emmc_pins[] = {
 384         16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
 385 };
 386 static const struct byt_simple_func_mux byt_score_emmc_mux[] = {
 387         SIMPLE_FUNC("emmc", 1),
 388 };
 389
 390 static const unsigned int byt_score_ilb_lpc_pins[] = {
 391         42, 43, 44, 45, 46, 47, 48, 49, 50,
 392 };
 393 static const struct byt_simple_func_mux byt_score_lpc_mux[] = {
 394         SIMPLE_FUNC("lpc", 1),
 395 };
 396
 397 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
 398 static const struct byt_simple_func_mux byt_score_sata_mux[] = {
 399         SIMPLE_FUNC("sata", 1),
 400 };
 401
 402 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
 403 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
 404 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
 405 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
 406 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
 407 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
 408 static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = {
 409         SIMPLE_FUNC("plt_clk", 1),
 410 };
 411
 412 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
 413 static const struct byt_simple_func_mux byt_score_smbus_mux[] = {
 414         SIMPLE_FUNC("smbus", 1),
 415 };
 416
 417 static const struct byt_pingroup byt_score_groups[] = {
 418         PIN_GROUP_SIMPLE("uart1_grp",
 419                          byt_score_uart1_pins, byt_score_uart_mux),
 420         PIN_GROUP_SIMPLE("uart2_grp",
 421                          byt_score_uart2_pins, byt_score_uart_mux),
 422         PIN_GROUP_SIMPLE("pwm0_grp",
 423                          byt_score_pwm0_pins, byt_score_pwm_mux),
 424         PIN_GROUP_SIMPLE("pwm1_grp",
 425                          byt_score_pwm1_pins, byt_score_pwm_mux),
 426         PIN_GROUP_SIMPLE("ssp2_grp",
 427                          byt_score_ssp2_pins, byt_score_pwm_mux),
 428         PIN_GROUP_SIMPLE("sio_spi_grp",
 429                          byt_score_sio_spi_pins, byt_score_spi_mux),
 430         PIN_GROUP_SIMPLE("i2c5_grp",
 431                          byt_score_i2c5_pins, byt_score_i2c_mux),
 432         PIN_GROUP_SIMPLE("i2c6_grp",
 433                          byt_score_i2c6_pins, byt_score_i2c_mux),
 434         PIN_GROUP_SIMPLE("i2c4_grp",
 435                          byt_score_i2c4_pins, byt_score_i2c_mux),
 436         PIN_GROUP_SIMPLE("i2c3_grp",
 437                          byt_score_i2c3_pins, byt_score_i2c_mux),
 438         PIN_GROUP_SIMPLE("i2c2_grp",
 439                          byt_score_i2c2_pins, byt_score_i2c_mux),
 440         PIN_GROUP_SIMPLE("i2c1_grp",
 441                          byt_score_i2c1_pins, byt_score_i2c_mux),
 442         PIN_GROUP_SIMPLE("i2c0_grp",
 443                          byt_score_i2c0_pins, byt_score_i2c_mux),
 444         PIN_GROUP_SIMPLE("ssp0_grp",
 445                          byt_score_ssp0_pins, byt_score_ssp_mux),
 446         PIN_GROUP_SIMPLE("ssp1_grp",
 447                          byt_score_ssp1_pins, byt_score_ssp_mux),
 448         PIN_GROUP_MIXED("sdcard_grp",
 449                         byt_score_sdcard_pins, byt_score_sdcard_mux),
 450         PIN_GROUP_SIMPLE("sdio_grp",
 451                          byt_score_sdio_pins, byt_score_sdio_mux),
 452         PIN_GROUP_SIMPLE("emmc_grp",
 453                          byt_score_emmc_pins, byt_score_emmc_mux),
 454         PIN_GROUP_SIMPLE("lpc_grp",
 455                          byt_score_ilb_lpc_pins, byt_score_lpc_mux),
 456         PIN_GROUP_SIMPLE("sata_grp",
 457                          byt_score_sata_pins, byt_score_sata_mux),
 458         PIN_GROUP_SIMPLE("plt_clk0_grp",
 459                          byt_score_plt_clk0_pins, byt_score_plt_clk_mux),
 460         PIN_GROUP_SIMPLE("plt_clk1_grp",
 461                          byt_score_plt_clk1_pins, byt_score_plt_clk_mux),
 462         PIN_GROUP_SIMPLE("plt_clk2_grp",
 463                          byt_score_plt_clk2_pins, byt_score_plt_clk_mux),
 464         PIN_GROUP_SIMPLE("plt_clk3_grp",
 465                          byt_score_plt_clk3_pins, byt_score_plt_clk_mux),
 466         PIN_GROUP_SIMPLE("plt_clk4_grp",
 467                          byt_score_plt_clk4_pins, byt_score_plt_clk_mux),
 468         PIN_GROUP_SIMPLE("plt_clk5_grp",
 469                          byt_score_plt_clk5_pins, byt_score_plt_clk_mux),
 470         PIN_GROUP_SIMPLE("smbus_grp",
 471                          byt_score_smbus_pins, byt_score_smbus_mux),
 472 };
 473
 474 static const char * const byt_score_uart_groups[] = {
 475         "uart1_grp", "uart2_grp",
 476 };
 477 static const char * const byt_score_pwm_groups[] = {
 478         "pwm0_grp", "pwm1_grp",
 479 };
 480 static const char * const byt_score_ssp_groups[] = {
 481         "ssp0_grp", "ssp1_grp", "ssp2_grp",
 482 };
 483 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
 484 static const char * const byt_score_i2c_groups[] = {
 485         "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
 486         "i2c6_grp",
 487 };
 488 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
 489 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
 490 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
 491 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
 492 static const char * const byt_score_sata_groups[] = { "sata_grp" };
 493 static const char * const byt_score_plt_clk_groups[] = {
 494         "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
 495         "plt_clk4_grp", "plt_clk5_grp",
 496 };
 497 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
 498 static const char * const byt_score_gpio_groups[] = {
 499         "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
 500         "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
 501         "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
 502         "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
 503         "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
 504         "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
 505
 506 };
 507
 508 static const struct byt_function byt_score_functions[] = {
 509         FUNCTION("uart", byt_score_uart_groups),
 510         FUNCTION("pwm", byt_score_pwm_groups),
 511         FUNCTION("ssp", byt_score_ssp_groups),
 512         FUNCTION("spi", byt_score_spi_groups),
 513         FUNCTION("i2c", byt_score_i2c_groups),
 514         FUNCTION("sdcard", byt_score_sdcard_groups),
 515         FUNCTION("sdio", byt_score_sdio_groups),
 516         FUNCTION("emmc", byt_score_emmc_groups),
 517         FUNCTION("lpc", byt_score_lpc_groups),
 518         FUNCTION("sata", byt_score_sata_groups),
 519         FUNCTION("plt_clk", byt_score_plt_clk_groups),
 520         FUNCTION("smbus", byt_score_smbus_groups),
 521         FUNCTION("gpio", byt_score_gpio_groups),
 522 };
 523
 524 static const struct byt_community byt_score_communities[] = {
 525         COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
 526 };
 527
 528 static const struct byt_pinctrl_soc_data byt_score_soc_data = {
 529         .uid            = BYT_SCORE_ACPI_UID,
 530         .pins           = byt_score_pins,
 531         .npins          = ARRAY_SIZE(byt_score_pins),
 532         .groups         = byt_score_groups,
 533         .ngroups        = ARRAY_SIZE(byt_score_groups),
 534         .functions      = byt_score_functions,
 535         .nfunctions     = ARRAY_SIZE(byt_score_functions),
 536         .communities    = byt_score_communities,
 537         .ncommunities   = ARRAY_SIZE(byt_score_communities),
 538 };
 539
 540 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>]  */
 541 static const struct pinctrl_pin_desc byt_sus_pins[] = {
 542         PINCTRL_PIN(0, "GPIO_S50"),
 543         PINCTRL_PIN(1, "GPIO_S51"),
 544         PINCTRL_PIN(2, "GPIO_S52"),
 545         PINCTRL_PIN(3, "GPIO_S53"),
 546         PINCTRL_PIN(4, "GPIO_S54"),
 547         PINCTRL_PIN(5, "GPIO_S55"),
 548         PINCTRL_PIN(6, "GPIO_S56"),
 549         PINCTRL_PIN(7, "GPIO_S57"),
 550         PINCTRL_PIN(8, "GPIO_S58"),
 551         PINCTRL_PIN(9, "GPIO_S59"),
 552         PINCTRL_PIN(10, "GPIO_S510"),
 553         PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
 554         PINCTRL_PIN(12, "PMC_SUSCLK0"),
 555         PINCTRL_PIN(13, "GPIO_S513"),
 556         PINCTRL_PIN(14, "USB_ULPI_RST"),
 557         PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
 558         PINCTRL_PIN(16, "PMC_PWRBTN"),
 559         PINCTRL_PIN(17, "GPIO_S517"),
 560         PINCTRL_PIN(18, "PMC_SUS_STAT"),
 561         PINCTRL_PIN(19, "USB_OC0"),
 562         PINCTRL_PIN(20, "USB_OC1"),
 563         PINCTRL_PIN(21, "PCU_SPI_CS1"),
 564         PINCTRL_PIN(22, "GPIO_S522"),
 565         PINCTRL_PIN(23, "GPIO_S523"),
 566         PINCTRL_PIN(24, "GPIO_S524"),
 567         PINCTRL_PIN(25, "GPIO_S525"),
 568         PINCTRL_PIN(26, "GPIO_S526"),
 569         PINCTRL_PIN(27, "GPIO_S527"),
 570         PINCTRL_PIN(28, "GPIO_S528"),
 571         PINCTRL_PIN(29, "GPIO_S529"),
 572         PINCTRL_PIN(30, "GPIO_S530"),
 573         PINCTRL_PIN(31, "USB_ULPI_CLK"),
 574         PINCTRL_PIN(32, "USB_ULPI_DATA0"),
 575         PINCTRL_PIN(33, "USB_ULPI_DATA1"),
 576         PINCTRL_PIN(34, "USB_ULPI_DATA2"),
 577         PINCTRL_PIN(35, "USB_ULPI_DATA3"),
 578         PINCTRL_PIN(36, "USB_ULPI_DATA4"),
 579         PINCTRL_PIN(37, "USB_ULPI_DATA5"),
 580         PINCTRL_PIN(38, "USB_ULPI_DATA6"),
 581         PINCTRL_PIN(39, "USB_ULPI_DATA7"),
 582         PINCTRL_PIN(40, "USB_ULPI_DIR"),
 583         PINCTRL_PIN(41, "USB_ULPI_NXT"),
 584         PINCTRL_PIN(42, "USB_ULPI_STP"),
 585         PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
 586 };
 587
 588 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
 589         29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
 590         18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
 591         0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
 592         26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
 593         52, 53, 59, 40,
 594 };
 595
 596 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
 597 static const struct byt_simple_func_mux byt_sus_usb_oc_mux[] = {
 598         SIMPLE_FUNC("usb", 0),
 599         SIMPLE_FUNC("gpio", 1),
 600 };
 601
 602 static const unsigned int byt_sus_usb_ulpi_pins[] = {
 603         14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
 604 };
 605 static const unsigned short byt_sus_usb_ulpi_mode_values[] = {
 606         2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 607 };
 608 static const unsigned short byt_sus_usb_ulpi_gpio_mode_values[] = {
 609         1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 610 };
 611 static const struct byt_mixed_func_mux byt_sus_usb_ulpi_mux[] = {
 612         MIXED_FUNC("usb", byt_sus_usb_ulpi_mode_values),
 613         MIXED_FUNC("gpio", byt_sus_usb_ulpi_gpio_mode_values),
 614 };
 615
 616 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
 617 static const struct byt_simple_func_mux byt_sus_pcu_spi_mux[] = {
 618         SIMPLE_FUNC("spi", 0),
 619         SIMPLE_FUNC("gpio", 1),
 620 };
 621
 622 static const struct byt_pingroup byt_sus_groups[] = {
 623         PIN_GROUP_SIMPLE("usb_oc_grp",
 624                         byt_sus_usb_over_current_pins, byt_sus_usb_oc_mux),
 625         PIN_GROUP_MIXED("usb_ulpi_grp",
 626                         byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mux),
 627         PIN_GROUP_SIMPLE("pcu_spi_grp",
 628                         byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mux),
 629 };
 630
 631 static const char * const byt_sus_usb_groups[] = {
 632         "usb_oc_grp", "usb_ulpi_grp",
 633 };
 634 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
 635 static const char * const byt_sus_gpio_groups[] = {
 636         "usb_oc_grp", "usb_ulpi_grp", "pcu_spi_grp",
 637 };
 638
 639 static const struct byt_function byt_sus_functions[] = {
 640         FUNCTION("usb", byt_sus_usb_groups),
 641         FUNCTION("spi", byt_sus_spi_groups),
 642         FUNCTION("gpio", byt_sus_gpio_groups),
 643 };
 644
 645 static const struct byt_community byt_sus_communities[] = {
 646         COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
 647 };
 648
 649 static const struct byt_pinctrl_soc_data byt_sus_soc_data = {
 650         .uid            = BYT_SUS_ACPI_UID,
 651         .pins           = byt_sus_pins,
 652         .npins          = ARRAY_SIZE(byt_sus_pins),
 653         .groups         = byt_sus_groups,
 654         .ngroups        = ARRAY_SIZE(byt_sus_groups),
 655         .functions      = byt_sus_functions,
 656         .nfunctions     = ARRAY_SIZE(byt_sus_functions),
 657         .communities    = byt_sus_communities,
 658         .ncommunities   = ARRAY_SIZE(byt_sus_communities),
 659 };
 660
 661 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
 662         PINCTRL_PIN(0, "GPIO_NCORE0"),
 663         PINCTRL_PIN(1, "GPIO_NCORE1"),
 664         PINCTRL_PIN(2, "GPIO_NCORE2"),
 665         PINCTRL_PIN(3, "GPIO_NCORE3"),
 666         PINCTRL_PIN(4, "GPIO_NCORE4"),
 667         PINCTRL_PIN(5, "GPIO_NCORE5"),
 668         PINCTRL_PIN(6, "GPIO_NCORE6"),
 669         PINCTRL_PIN(7, "GPIO_NCORE7"),
 670         PINCTRL_PIN(8, "GPIO_NCORE8"),
 671         PINCTRL_PIN(9, "GPIO_NCORE9"),
 672         PINCTRL_PIN(10, "GPIO_NCORE10"),
 673         PINCTRL_PIN(11, "GPIO_NCORE11"),
 674         PINCTRL_PIN(12, "GPIO_NCORE12"),
 675         PINCTRL_PIN(13, "GPIO_NCORE13"),
 676         PINCTRL_PIN(14, "GPIO_NCORE14"),
 677         PINCTRL_PIN(15, "GPIO_NCORE15"),
 678         PINCTRL_PIN(16, "GPIO_NCORE16"),
 679         PINCTRL_PIN(17, "GPIO_NCORE17"),
 680         PINCTRL_PIN(18, "GPIO_NCORE18"),
 681         PINCTRL_PIN(19, "GPIO_NCORE19"),
 682         PINCTRL_PIN(20, "GPIO_NCORE20"),
 683         PINCTRL_PIN(21, "GPIO_NCORE21"),
 684         PINCTRL_PIN(22, "GPIO_NCORE22"),
 685         PINCTRL_PIN(23, "GPIO_NCORE23"),
 686         PINCTRL_PIN(24, "GPIO_NCORE24"),
 687         PINCTRL_PIN(25, "GPIO_NCORE25"),
 688         PINCTRL_PIN(26, "GPIO_NCORE26"),
 689         PINCTRL_PIN(27, "GPIO_NCORE27"),
 690 };
 691
 692 static unsigned const byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
 693         19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
 694         14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
 695         3, 6, 10, 13, 2, 5, 9, 7,
 696 };
 697
 698 static const struct byt_community byt_ncore_communities[] = {
 699         COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
 700 };
 701
 702 static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
 703         .uid            = BYT_NCORE_ACPI_UID,
 704         .pins           = byt_ncore_pins,
 705         .npins          = ARRAY_SIZE(byt_ncore_pins),
 706         .communities    = byt_ncore_communities,
 707         .ncommunities   = ARRAY_SIZE(byt_ncore_communities),
 708 };
 709
 710 static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
 711         &byt_score_soc_data,
 712         &byt_sus_soc_data,
 713         &byt_ncore_soc_data,
 714         NULL,
 715 };
 716
 717 static DEFINE_RAW_SPINLOCK(byt_lock);
 718
 719 static struct byt_community *byt_get_community(struct byt_gpio *vg,
 720                                                unsigned int pin)
 721 {
 722         struct byt_community *comm;
 723         int i;
 724
 725         for (i = 0; i < vg->soc_data->ncommunities; i++) {
 726                 comm = vg->communities_copy + i;
 727                 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
 728                         return comm;
 729         }
 730
 731         return NULL;
 732 }
 733
 734 static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
 735                                   int reg)
 736 {
 737         struct byt_community *comm = byt_get_community(vg, offset);
 738         u32 reg_offset;
 739
 740         if (!comm)
 741                 return NULL;
 742
 743         offset -= comm->pin_base;
 744         switch (reg) {
 745         case BYT_INT_STAT_REG:
 746                 reg_offset = (offset / 32) * 4;
 747                 break;
 748         case BYT_DEBOUNCE_REG:
 749                 reg_offset = 0;
 750                 break;
 751         default:
 752                 reg_offset = comm->pad_map[offset] * 16;
 753                 break;
 754         }
 755
 756         return comm->reg_base + reg_offset + reg;
 757 }
 758
 759 static int byt_get_groups_count(struct pinctrl_dev *pctldev)
 760 {
 761         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 762
 763         return vg->soc_data->ngroups;
 764 }
 765
 766 static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
 767                                       unsigned int selector)
 768 {
 769         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 770
 771         return vg->soc_data->groups[selector].name;
 772 }
 773
 774 static int byt_get_group_pins(struct pinctrl_dev *pctldev,
 775                               unsigned int selector,
 776                               const unsigned int **pins,
 777                               unsigned int *num_pins)
 778 {
 779         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 780
 781         *pins           = vg->soc_data->groups[selector].pins;
 782         *num_pins       = vg->soc_data->groups[selector].npins;
 783
 784         return 0;
 785 }
 786
 787 static const struct pinctrl_ops byt_pinctrl_ops = {
 788         .get_groups_count       = byt_get_groups_count,
 789         .get_group_name         = byt_get_group_name,
 790         .get_group_pins         = byt_get_group_pins,
 791 };
 792
 793 static int byt_get_functions_count(struct pinctrl_dev *pctldev)
 794 {
 795         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 796
 797         return vg->soc_data->nfunctions;
 798 }
 799
 800 static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
 801                                          unsigned int selector)
 802 {
 803         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 804
 805         return vg->soc_data->functions[selector].name;
 806 }
 807
 808 static int byt_get_function_groups(struct pinctrl_dev *pctldev,
 809                                    unsigned int selector,
 810                                    const char * const **groups,
 811                                    unsigned int *num_groups)
 812 {
 813         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 814
 815         *groups         = vg->soc_data->functions[selector].groups;
 816         *num_groups     = vg->soc_data->functions[selector].ngroups;
 817
 818         return 0;
 819 }
 820
 821 static int byt_get_group_simple_mux(const struct byt_pingroup group,
 822                                     const char *func_name,
 823                                     unsigned short *func)
 824 {
 825         int i;
 826
 827         for (i = 0; i < group.nfuncs; i++) {
 828                 if (!strcmp(group.simple_funcs[i].name, func_name)) {
 829                         *func = group.simple_funcs[i].func;
 830                         return 0;
 831                 }
 832         }
 833
 834         return 1;
 835 }
 836
 837 static int byt_get_group_mixed_mux(const struct byt_pingroup group,
 838                                    const char *func_name,
 839                                    const unsigned short **func)
 840 {
 841         int i;
 842
 843         for (i = 0; i < group.nfuncs; i++) {
 844                 if (!strcmp(group.mixed_funcs[i].name, func_name)) {
 845                         *func = group.mixed_funcs[i].func_values;
 846                         return 0;
 847                 }
 848         }
 849
 850         return 1;
 851 }
 852
 853 static void byt_set_group_simple_mux(struct byt_gpio *vg,
 854                                      const struct byt_pingroup group,
 855                                      unsigned short func)
 856 {
 857         unsigned long flags;
 858         int i;
 859
 860         raw_spin_lock_irqsave(&byt_lock, flags);
 861
 862         for (i = 0; i < group.npins; i++) {
 863                 void __iomem *padcfg0;
 864                 u32 value;
 865
 866                 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
 867                 if (!padcfg0) {
 868                         dev_warn(&vg->pdev->dev,
 869                                  "Group %s, pin %i not muxed (no padcfg0)\n",
 870                                  group.name, i);
 871                         continue;
 872                 }
 873
 874                 value = readl(padcfg0);
 875                 value &= ~BYT_PIN_MUX;
 876                 value |= func;
 877                 writel(value, padcfg0);
 878         }
 879
 880         raw_spin_unlock_irqrestore(&byt_lock, flags);
 881 }
 882
 883 static void byt_set_group_mixed_mux(struct byt_gpio *vg,
 884                                     const struct byt_pingroup group,
 885                                     const unsigned short *func)
 886 {
 887         unsigned long flags;
 888         int i;
 889
 890         raw_spin_lock_irqsave(&byt_lock, flags);
 891
 892         for (i = 0; i < group.npins; i++) {
 893                 void __iomem *padcfg0;
 894                 u32 value;
 895
 896                 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
 897                 if (!padcfg0) {
 898                         dev_warn(&vg->pdev->dev,
 899                                  "Group %s, pin %i not muxed (no padcfg0)\n",
 900                                  group.name, i);
 901                         continue;
 902                 }
 903
 904                 value = readl(padcfg0);
 905                 value &= ~BYT_PIN_MUX;
 906                 value |= func[i];
 907                 writel(value, padcfg0);
 908         }
 909
 910         raw_spin_unlock_irqrestore(&byt_lock, flags);
 911 }
 912
 913 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
 914                        unsigned int group_selector)
 915 {
 916         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
 917         const struct byt_function func = vg->soc_data->functions[func_selector];
 918         const struct byt_pingroup group = vg->soc_data->groups[group_selector];
 919         const unsigned short *mixed_func;
 920         unsigned short simple_func;
 921         int ret = 1;
 922
 923         if (group.has_simple_funcs)
 924                 ret = byt_get_group_simple_mux(group, func.name, &simple_func);
 925         else
 926                 ret = byt_get_group_mixed_mux(group, func.name, &mixed_func);
 927
 928         if (ret)
 929                 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
 930         else if (group.has_simple_funcs)
 931                 byt_set_group_simple_mux(vg, group, simple_func);
 932         else
 933                 byt_set_group_mixed_mux(vg, group, mixed_func);
 934
 935         return 0;
 936 }
 937
 938 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
 939 {
 940         /* SCORE pin 92-93 */
 941         if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
 942             offset >= 92 && offset <= 93)
 943                 return 1;
 944
 945         /* SUS pin 11-21 */
 946         if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
 947             offset >= 11 && offset <= 21)
 948                 return 1;
 949
 950         return 0;
 951 }
 952
 953 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
 954 {
 955         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 956         unsigned long flags;
 957         u32 value;
 958
 959         raw_spin_lock_irqsave(&byt_lock, flags);
 960         value = readl(reg);
 961
 962         /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
 963         if (value & BYT_DIRECT_IRQ_EN)
 964                 /* nothing to do */ ;
 965         else
 966                 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
 967
 968         writel(value, reg);
 969         raw_spin_unlock_irqrestore(&byt_lock, flags);
 970 }
 971
 972 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
 973                                    struct pinctrl_gpio_range *range,
 974                                    unsigned int offset)
 975 {
 976         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
 977         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 978         u32 value, gpio_mux;
 979         unsigned long flags;
 980
 981         raw_spin_lock_irqsave(&byt_lock, flags);
 982
 983         /*
 984          * In most cases, func pin mux 000 means GPIO function.
 985          * But, some pins may have func pin mux 001 represents
 986          * GPIO function.
 987          *
 988          * Because there are devices out there where some pins were not
 989          * configured correctly we allow changing the mux value from
 990          * request (but print out warning about that).
 991          */
 992         value = readl(reg) & BYT_PIN_MUX;
 993         gpio_mux = byt_get_gpio_mux(vg, offset);
 994         if (gpio_mux != value) {
 995                 value = readl(reg) & ~BYT_PIN_MUX;
 996                 value |= gpio_mux;
 997                 writel(value, reg);
 998
 999                 dev_warn(&vg->pdev->dev, FW_BUG
1000                          "pin %u forcibly re-configured as GPIO\n", offset);
1001         }
1002
1003         raw_spin_unlock_irqrestore(&byt_lock, flags);
1004
1005         pm_runtime_get(&vg->pdev->dev);
1006
1007         return 0;
1008 }
1009
1010 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
1011                                   struct pinctrl_gpio_range *range,
1012                                   unsigned int offset)
1013 {
1014         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1015
1016         byt_gpio_clear_triggering(vg, offset);
1017         pm_runtime_put(&vg->pdev->dev);
1018 }
1019
1020 static void byt_gpio_direct_irq_check(struct byt_gpio *vg,
1021                                       unsigned int offset)
1022 {
1023         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1024
1025         /*
1026          * Before making any direction modifications, do a check if gpio is set
1027          * for direct IRQ. On Bay Trail, setting GPIO to output does not make
1028          * sense, so let's at least inform the caller before they shoot
1029          * themselves in the foot.
1030          */
1031         if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
1032                 dev_info_once(&vg->pdev->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
1033 }
1034
1035 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
1036                                   struct pinctrl_gpio_range *range,
1037                                   unsigned int offset,
1038                                   bool input)
1039 {
1040         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1041         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1042         unsigned long flags;
1043         u32 value;
1044
1045         raw_spin_lock_irqsave(&byt_lock, flags);
1046
1047         value = readl(val_reg);
1048         value &= ~BYT_DIR_MASK;
1049         if (input)
1050                 value |= BYT_OUTPUT_EN;
1051         else
1052                 byt_gpio_direct_irq_check(vg, offset);
1053
1054         writel(value, val_reg);
1055
1056         raw_spin_unlock_irqrestore(&byt_lock, flags);
1057
1058         return 0;
1059 }
1060
1061 static const struct pinmux_ops byt_pinmux_ops = {
1062         .get_functions_count    = byt_get_functions_count,
1063         .get_function_name      = byt_get_function_name,
1064         .get_function_groups    = byt_get_function_groups,
1065         .set_mux                = byt_set_mux,
1066         .gpio_request_enable    = byt_gpio_request_enable,
1067         .gpio_disable_free      = byt_gpio_disable_free,
1068         .gpio_set_direction     = byt_gpio_set_direction,
1069 };
1070
1071 static void byt_get_pull_strength(u32 reg, u16 *strength)
1072 {
1073         switch (reg & BYT_PULL_STR_MASK) {
1074         case BYT_PULL_STR_2K:
1075                 *strength = 2000;
1076                 break;
1077         case BYT_PULL_STR_10K:
1078                 *strength = 10000;
1079                 break;
1080         case BYT_PULL_STR_20K:
1081                 *strength = 20000;
1082                 break;
1083         case BYT_PULL_STR_40K:
1084                 *strength = 40000;
1085                 break;
1086         }
1087 }
1088
1089 static int byt_set_pull_strength(u32 *reg, u16 strength)
1090 {
1091         *reg &= ~BYT_PULL_STR_MASK;
1092
1093         switch (strength) {
1094         case 2000:
1095                 *reg |= BYT_PULL_STR_2K;
1096                 break;
1097         case 10000:
1098                 *reg |= BYT_PULL_STR_10K;
1099                 break;
1100         case 20000:
1101                 *reg |= BYT_PULL_STR_20K;
1102                 break;
1103         case 40000:
1104                 *reg |= BYT_PULL_STR_40K;
1105                 break;
1106         default:
1107                 return -EINVAL;
1108         }
1109
1110         return 0;
1111 }
1112
1113 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
1114                               unsigned long *config)
1115 {
1116         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1117         enum pin_config_param param = pinconf_to_config_param(*config);
1118         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1119         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1120         void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1121         unsigned long flags;
1122         u32 conf, pull, val, debounce;
1123         u16 arg = 0;
1124
1125         raw_spin_lock_irqsave(&byt_lock, flags);
1126         conf = readl(conf_reg);
1127         pull = conf & BYT_PULL_ASSIGN_MASK;
1128         val = readl(val_reg);
1129         raw_spin_unlock_irqrestore(&byt_lock, flags);
1130
1131         switch (param) {
1132         case PIN_CONFIG_BIAS_DISABLE:
1133                 if (pull)
1134                         return -EINVAL;
1135                 break;
1136         case PIN_CONFIG_BIAS_PULL_DOWN:
1137                 /* Pull assignment is only applicable in input mode */
1138                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
1139                         return -EINVAL;
1140
1141                 byt_get_pull_strength(conf, &arg);
1142
1143                 break;
1144         case PIN_CONFIG_BIAS_PULL_UP:
1145                 /* Pull assignment is only applicable in input mode */
1146                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
1147                         return -EINVAL;
1148
1149                 byt_get_pull_strength(conf, &arg);
1150
1151                 break;
1152         case PIN_CONFIG_INPUT_DEBOUNCE:
1153                 if (!(conf & BYT_DEBOUNCE_EN))
1154                         return -EINVAL;
1155
1156                 raw_spin_lock_irqsave(&byt_lock, flags);
1157                 debounce = readl(db_reg);
1158                 raw_spin_unlock_irqrestore(&byt_lock, flags);
1159
1160                 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
1161                 case BYT_DEBOUNCE_PULSE_375US:
1162                         arg = 375;
1163                         break;
1164                 case BYT_DEBOUNCE_PULSE_750US:
1165                         arg = 750;
1166                         break;
1167                 case BYT_DEBOUNCE_PULSE_1500US:
1168                         arg = 1500;
1169                         break;
1170                 case BYT_DEBOUNCE_PULSE_3MS:
1171                         arg = 3000;
1172                         break;
1173                 case BYT_DEBOUNCE_PULSE_6MS:
1174                         arg = 6000;
1175                         break;
1176                 case BYT_DEBOUNCE_PULSE_12MS:
1177                         arg = 12000;
1178                         break;
1179                 case BYT_DEBOUNCE_PULSE_24MS:
1180                         arg = 24000;
1181                         break;
1182                 default:
1183                         return -EINVAL;
1184                 }
1185
1186                 break;
1187         default:
1188                 return -ENOTSUPP;
1189         }
1190
1191         *config = pinconf_to_config_packed(param, arg);
1192
1193         return 0;
1194 }
1195
1196 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
1197                               unsigned int offset,
1198                               unsigned long *configs,
1199                               unsigned int num_configs)
1200 {
1201         struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1202         unsigned int param, arg;
1203         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1204         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1205         void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1206         unsigned long flags;
1207         u32 conf, val, debounce;
1208         int i, ret = 0;
1209
1210         raw_spin_lock_irqsave(&byt_lock, flags);
1211
1212         conf = readl(conf_reg);
1213         val = readl(val_reg);
1214
1215         for (i = 0; i < num_configs; i++) {
1216                 param = pinconf_to_config_param(configs[i]);
1217                 arg = pinconf_to_config_argument(configs[i]);
1218
1219                 switch (param) {
1220                 case PIN_CONFIG_BIAS_DISABLE:
1221                         conf &= ~BYT_PULL_ASSIGN_MASK;
1222                         break;
1223                 case PIN_CONFIG_BIAS_PULL_DOWN:
1224                         /* Set default strength value in case none is given */
1225                         if (arg == 1)
1226                                 arg = 2000;
1227
1228                         /*
1229                          * Pull assignment is only applicable in input mode. If
1230                          * chip is not in input mode, set it and warn about it.
1231                          */
1232                         if (val & BYT_INPUT_EN) {
1233                                 val &= ~BYT_INPUT_EN;
1234                                 writel(val, val_reg);
1235                                 dev_warn(&vg->pdev->dev,
1236                                          "pin %u forcibly set to input mode\n",
1237                                          offset);
1238                         }
1239
1240                         conf &= ~BYT_PULL_ASSIGN_MASK;
1241                         conf |= BYT_PULL_ASSIGN_DOWN;
1242                         ret = byt_set_pull_strength(&conf, arg);
1243
1244                         break;
1245                 case PIN_CONFIG_BIAS_PULL_UP:
1246                         /* Set default strength value in case none is given */
1247                         if (arg == 1)
1248                                 arg = 2000;
1249
1250                         /*
1251                          * Pull assignment is only applicable in input mode. If
1252                          * chip is not in input mode, set it and warn about it.
1253                          */
1254                         if (val & BYT_INPUT_EN) {
1255                                 val &= ~BYT_INPUT_EN;
1256                                 writel(val, val_reg);
1257                                 dev_warn(&vg->pdev->dev,
1258                                          "pin %u forcibly set to input mode\n",
1259                                          offset);
1260                         }
1261
1262                         conf &= ~BYT_PULL_ASSIGN_MASK;
1263                         conf |= BYT_PULL_ASSIGN_UP;
1264                         ret = byt_set_pull_strength(&conf, arg);
1265
1266                         break;
1267                 case PIN_CONFIG_INPUT_DEBOUNCE:
1268                         debounce = readl(db_reg);
1269
1270                         if (arg)
1271                                 conf |= BYT_DEBOUNCE_EN;
1272                         else
1273                                 conf &= ~BYT_DEBOUNCE_EN;
1274
1275                         switch (arg) {
1276                         case 375:
1277                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1278                                 debounce |= BYT_DEBOUNCE_PULSE_375US;
1279                                 break;
1280                         case 750:
1281                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1282                                 debounce |= BYT_DEBOUNCE_PULSE_750US;
1283                                 break;
1284                         case 1500:
1285                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1286                                 debounce |= BYT_DEBOUNCE_PULSE_1500US;
1287                                 break;
1288                         case 3000:
1289                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1290                                 debounce |= BYT_DEBOUNCE_PULSE_3MS;
1291                                 break;
1292                         case 6000:
1293                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1294                                 debounce |= BYT_DEBOUNCE_PULSE_6MS;
1295                                 break;
1296                         case 12000:
1297                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1298                                 debounce |= BYT_DEBOUNCE_PULSE_12MS;
1299                                 break;
1300                         case 24000:
1301                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1302                                 debounce |= BYT_DEBOUNCE_PULSE_24MS;
1303                                 break;
1304                         default:
1305                                 if (arg)
1306                                         ret = -EINVAL;
1307                                 break;
1308                         }
1309
1310                         if (!ret)
1311                                 writel(debounce, db_reg);
1312                         break;
1313                 default:
1314                         ret = -ENOTSUPP;
1315                 }
1316
1317                 if (ret)
1318                         break;
1319         }
1320
1321         if (!ret)
1322                 writel(conf, conf_reg);
1323
1324         raw_spin_unlock_irqrestore(&byt_lock, flags);
1325
1326         return ret;
1327 }
1328
1329 static const struct pinconf_ops byt_pinconf_ops = {
1330         .is_generic     = true,
1331         .pin_config_get = byt_pin_config_get,
1332         .pin_config_set = byt_pin_config_set,
1333 };
1334
1335 static const struct pinctrl_desc byt_pinctrl_desc = {
1336         .pctlops        = &byt_pinctrl_ops,
1337         .pmxops         = &byt_pinmux_ops,
1338         .confops        = &byt_pinconf_ops,
1339         .owner          = THIS_MODULE,
1340 };
1341
1342 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
1343 {
1344         struct byt_gpio *vg = gpiochip_get_data(chip);
1345         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1346         unsigned long flags;
1347         u32 val;
1348
1349         raw_spin_lock_irqsave(&byt_lock, flags);
1350         val = readl(reg);
1351         raw_spin_unlock_irqrestore(&byt_lock, flags);
1352
1353         return !!(val & BYT_LEVEL);
1354 }
1355
1356 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1357 {
1358         struct byt_gpio *vg = gpiochip_get_data(chip);
1359         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1360         unsigned long flags;
1361         u32 old_val;
1362
1363         if (!reg)
1364                 return;
1365
1366         raw_spin_lock_irqsave(&byt_lock, flags);
1367         old_val = readl(reg);
1368         if (value)
1369                 writel(old_val | BYT_LEVEL, reg);
1370         else
1371                 writel(old_val & ~BYT_LEVEL, reg);
1372         raw_spin_unlock_irqrestore(&byt_lock, flags);
1373 }
1374
1375 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1376 {
1377         struct byt_gpio *vg = gpiochip_get_data(chip);
1378         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1379         unsigned long flags;
1380         u32 value;
1381
1382         if (!reg)
1383                 return -EINVAL;
1384
1385         raw_spin_lock_irqsave(&byt_lock, flags);
1386         value = readl(reg);
1387         raw_spin_unlock_irqrestore(&byt_lock, flags);
1388
1389         if (!(value & BYT_OUTPUT_EN))
1390                 return GPIOF_DIR_OUT;
1391         if (!(value & BYT_INPUT_EN))
1392                 return GPIOF_DIR_IN;
1393
1394         return -EINVAL;
1395 }
1396
1397 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1398 {
1399         struct byt_gpio *vg = gpiochip_get_data(chip);
1400         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1401         unsigned long flags;
1402         u32 reg;
1403
1404         raw_spin_lock_irqsave(&byt_lock, flags);
1405
1406         reg = readl(val_reg);
1407         reg &= ~BYT_DIR_MASK;
1408         reg |= BYT_OUTPUT_EN;
1409         writel(reg, val_reg);
1410
1411         raw_spin_unlock_irqrestore(&byt_lock, flags);
1412         return 0;
1413 }
1414
1415 /*
1416  * Note despite the temptation this MUST NOT be converted into a call to
1417  * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this
1418  * MUST be done as a single BYT_VAL_REG register write.
1419  * See the commit message of the commit adding this comment for details.
1420  */
1421 static int byt_gpio_direction_output(struct gpio_chip *chip,
1422                                      unsigned int offset, int value)
1423 {
1424         struct byt_gpio *vg = gpiochip_get_data(chip);
1425         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1426         unsigned long flags;
1427         u32 reg;
1428
1429         raw_spin_lock_irqsave(&byt_lock, flags);
1430
1431         byt_gpio_direct_irq_check(vg, offset);
1432
1433         reg = readl(val_reg);
1434         reg &= ~BYT_DIR_MASK;
1435         if (value)
1436                 reg |= BYT_LEVEL;
1437         else
1438                 reg &= ~BYT_LEVEL;
1439
1440         writel(reg, val_reg);
1441
1442         raw_spin_unlock_irqrestore(&byt_lock, flags);
1443         return 0;
1444 }
1445
1446 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1447 {
1448         struct byt_gpio *vg = gpiochip_get_data(chip);
1449         int i;
1450         u32 conf0, val;
1451
1452         for (i = 0; i < vg->soc_data->npins; i++) {
1453                 const struct byt_community *comm;
1454                 const char *pull_str = NULL;
1455                 const char *pull = NULL;
1456                 void __iomem *reg;
1457                 unsigned long flags;
1458                 const char *label;
1459                 unsigned int pin;
1460
1461                 raw_spin_lock_irqsave(&byt_lock, flags);
1462                 pin = vg->soc_data->pins[i].number;
1463                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1464                 if (!reg) {
1465                         seq_printf(s,
1466                                    "Could not retrieve pin %i conf0 reg\n",
1467                                    pin);
1468                         raw_spin_unlock_irqrestore(&byt_lock, flags);
1469                         continue;
1470                 }
1471                 conf0 = readl(reg);
1472
1473                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1474                 if (!reg) {
1475                         seq_printf(s,
1476                                    "Could not retrieve pin %i val reg\n", pin);
1477                         raw_spin_unlock_irqrestore(&byt_lock, flags);
1478                         continue;
1479                 }
1480                 val = readl(reg);
1481                 raw_spin_unlock_irqrestore(&byt_lock, flags);
1482
1483                 comm = byt_get_community(vg, pin);
1484                 if (!comm) {
1485                         seq_printf(s,
1486                                    "Could not get community for pin %i\n", pin);
1487                         continue;
1488                 }
1489                 label = gpiochip_is_requested(chip, i);
1490                 if (!label)
1491                         label = "Unrequested";
1492
1493                 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1494                 case BYT_PULL_ASSIGN_UP:
1495                         pull = "up";
1496                         break;
1497                 case BYT_PULL_ASSIGN_DOWN:
1498                         pull = "down";
1499                         break;
1500                 }
1501
1502                 switch (conf0 & BYT_PULL_STR_MASK) {
1503                 case BYT_PULL_STR_2K:
1504                         pull_str = "2k";
1505                         break;
1506                 case BYT_PULL_STR_10K:
1507                         pull_str = "10k";
1508                         break;
1509                 case BYT_PULL_STR_20K:
1510                         pull_str = "20k";
1511                         break;
1512                 case BYT_PULL_STR_40K:
1513                         pull_str = "40k";
1514                         break;
1515                 }
1516
1517                 seq_printf(s,
1518                            " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1519                            pin,
1520                            label,
1521                            val & BYT_INPUT_EN ? "  " : "in",
1522                            val & BYT_OUTPUT_EN ? "   " : "out",
1523                            val & BYT_LEVEL ? "hi" : "lo",
1524                            comm->pad_map[i], comm->pad_map[i] * 16,
1525                            conf0 & 0x7,
1526                            conf0 & BYT_TRIG_NEG ? " fall" : "     ",
1527                            conf0 & BYT_TRIG_POS ? " rise" : "     ",
1528                            conf0 & BYT_TRIG_LVL ? " level" : "      ");
1529
1530                 if (pull && pull_str)
1531                         seq_printf(s, " %-4s %-3s", pull, pull_str);
1532                 else
1533                         seq_puts(s, "          ");
1534
1535                 if (conf0 & BYT_IODEN)
1536                         seq_puts(s, " open-drain");
1537
1538                 seq_puts(s, "\n");
1539         }
1540 }
1541
1542 static const struct gpio_chip byt_gpio_chip = {
1543         .owner                  = THIS_MODULE,
1544         .request                = gpiochip_generic_request,
1545         .free                   = gpiochip_generic_free,
1546         .get_direction          = byt_gpio_get_direction,
1547         .direction_input        = byt_gpio_direction_input,
1548         .direction_output       = byt_gpio_direction_output,
1549         .get                    = byt_gpio_get,
1550         .set                    = byt_gpio_set,
1551         .set_config             = gpiochip_generic_config,
1552         .dbg_show               = byt_gpio_dbg_show,
1553 };
1554
1555 static void byt_irq_ack(struct irq_data *d)
1556 {
1557         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1558         struct byt_gpio *vg = gpiochip_get_data(gc);
1559         unsigned offset = irqd_to_hwirq(d);
1560         void __iomem *reg;
1561
1562         reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1563         if (!reg)
1564                 return;
1565
1566         raw_spin_lock(&byt_lock);
1567         writel(BIT(offset % 32), reg);
1568         raw_spin_unlock(&byt_lock);
1569 }
1570
1571 static void byt_irq_mask(struct irq_data *d)
1572 {
1573         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1574         struct byt_gpio *vg = gpiochip_get_data(gc);
1575
1576         byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1577 }
1578
1579 static void byt_irq_unmask(struct irq_data *d)
1580 {
1581         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1582         struct byt_gpio *vg = gpiochip_get_data(gc);
1583         unsigned offset = irqd_to_hwirq(d);
1584         unsigned long flags;
1585         void __iomem *reg;
1586         u32 value;
1587
1588         reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1589         if (!reg)
1590                 return;
1591
1592         raw_spin_lock_irqsave(&byt_lock, flags);
1593         value = readl(reg);
1594
1595         switch (irqd_get_trigger_type(d)) {
1596         case IRQ_TYPE_LEVEL_HIGH:
1597                 value |= BYT_TRIG_LVL;
1598         case IRQ_TYPE_EDGE_RISING:
1599                 value |= BYT_TRIG_POS;
1600                 break;
1601         case IRQ_TYPE_LEVEL_LOW:
1602                 value |= BYT_TRIG_LVL;
1603         case IRQ_TYPE_EDGE_FALLING:
1604                 value |= BYT_TRIG_NEG;
1605                 break;
1606         case IRQ_TYPE_EDGE_BOTH:
1607                 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1608                 break;
1609         }
1610
1611         writel(value, reg);
1612
1613         raw_spin_unlock_irqrestore(&byt_lock, flags);
1614 }
1615
1616 static int byt_irq_type(struct irq_data *d, unsigned int type)
1617 {
1618         struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1619         u32 offset = irqd_to_hwirq(d);
1620         u32 value;
1621         unsigned long flags;
1622         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1623
1624         if (!reg || offset >= vg->chip.ngpio)
1625                 return -EINVAL;
1626
1627         raw_spin_lock_irqsave(&byt_lock, flags);
1628         value = readl(reg);
1629
1630         WARN(value & BYT_DIRECT_IRQ_EN,
1631              "Bad pad config for io mode, force direct_irq_en bit clearing");
1632
1633         /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1634          * are used to indicate high and low level triggering
1635          */
1636         value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1637                    BYT_TRIG_LVL);
1638         /* Enable glitch filtering */
1639         value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1640                  BYT_GLITCH_F_FAST_CLK;
1641
1642         writel(value, reg);
1643
1644         if (type & IRQ_TYPE_EDGE_BOTH)
1645                 irq_set_handler_locked(d, handle_edge_irq);
1646         else if (type & IRQ_TYPE_LEVEL_MASK)
1647                 irq_set_handler_locked(d, handle_level_irq);
1648
1649         raw_spin_unlock_irqrestore(&byt_lock, flags);
1650
1651         return 0;
1652 }
1653
1654 static struct irq_chip byt_irqchip = {
1655         .name           = "BYT-GPIO",
1656         .irq_ack        = byt_irq_ack,
1657         .irq_mask       = byt_irq_mask,
1658         .irq_unmask     = byt_irq_unmask,
1659         .irq_set_type   = byt_irq_type,
1660         .flags          = IRQCHIP_SKIP_SET_WAKE,
1661 };
1662
1663 static void byt_gpio_irq_handler(struct irq_desc *desc)
1664 {
1665         struct irq_data *data = irq_desc_get_irq_data(desc);
1666         struct byt_gpio *vg = gpiochip_get_data(
1667                                 irq_desc_get_handler_data(desc));
1668         struct irq_chip *chip = irq_data_get_irq_chip(data);
1669         u32 base, pin;
1670         void __iomem *reg;
1671         unsigned long pending;
1672         unsigned int virq;
1673
1674         /* check from GPIO controller which pin triggered the interrupt */
1675         for (base = 0; base < vg->chip.ngpio; base += 32) {
1676                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1677
1678                 if (!reg) {
1679                         dev_warn(&vg->pdev->dev,
1680                                  "Pin %i: could not retrieve interrupt status register\n",
1681                                  base);
1682                         continue;
1683                 }
1684
1685                 raw_spin_lock(&byt_lock);
1686                 pending = readl(reg);
1687                 raw_spin_unlock(&byt_lock);
1688                 for_each_set_bit(pin, &pending, 32) {
1689                         virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
1690                         generic_handle_irq(virq);
1691                 }
1692         }
1693         chip->irq_eoi(data);
1694 }
1695
1696 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
1697 {
1698         struct gpio_chip *gc = &vg->chip;
1699         struct device *dev = &vg->pdev->dev;
1700         void __iomem *reg;
1701         u32 base, value;
1702         int i;
1703
1704         /*
1705          * Clear interrupt triggers for all pins that are GPIOs and
1706          * do not use direct IRQ mode. This will prevent spurious
1707          * interrupts from misconfigured pins.
1708          */
1709         for (i = 0; i < vg->soc_data->npins; i++) {
1710                 unsigned int pin = vg->soc_data->pins[i].number;
1711
1712                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1713                 if (!reg) {
1714                         dev_warn(&vg->pdev->dev,
1715                                  "Pin %i: could not retrieve conf0 register\n",
1716                                  i);
1717                         continue;
1718                 }
1719
1720                 value = readl(reg);
1721                 if (value & BYT_DIRECT_IRQ_EN) {
1722                         clear_bit(i, gc->irq_valid_mask);
1723                         dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
1724                 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1725                         byt_gpio_clear_triggering(vg, i);
1726                         dev_dbg(dev, "disabling GPIO %d\n", i);
1727                 }
1728         }
1729
1730         /* clear interrupt status trigger registers */
1731         for (base = 0; base < vg->soc_data->npins; base += 32) {
1732                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1733
1734                 if (!reg) {
1735                         dev_warn(&vg->pdev->dev,
1736                                  "Pin %i: could not retrieve irq status reg\n",
1737                                  base);
1738                         continue;
1739                 }
1740
1741                 writel(0xffffffff, reg);
1742                 /* make sure trigger bits are cleared, if not then a pin
1743                    might be misconfigured in bios */
1744                 value = readl(reg);
1745                 if (value)
1746                         dev_err(&vg->pdev->dev,
1747                                 "GPIO interrupt error, pins misconfigured\n");
1748         }
1749 }
1750
1751 static int byt_gpio_probe(struct byt_gpio *vg)
1752 {
1753         struct gpio_chip *gc;
1754         struct resource *irq_rc;
1755         int ret;
1756
1757         /* Set up gpio chip */
1758         vg->chip        = byt_gpio_chip;
1759         gc              = &vg->chip;
1760         gc->label       = dev_name(&vg->pdev->dev);
1761         gc->base        = -1;
1762         gc->can_sleep   = false;
1763         gc->parent      = &vg->pdev->dev;
1764         gc->ngpio       = vg->soc_data->npins;
1765         gc->irq_need_valid_mask = true;
1766
1767 #ifdef CONFIG_PM_SLEEP
1768         vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
1769                                        sizeof(*vg->saved_context), GFP_KERNEL);
1770 #endif
1771         ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
1772         if (ret) {
1773                 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
1774                 return ret;
1775         }
1776
1777         ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
1778                                      0, 0, vg->soc_data->npins);
1779         if (ret) {
1780                 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
1781                 return ret;
1782         }
1783
1784         /* set up interrupts  */
1785         irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
1786         if (irq_rc && irq_rc->start) {
1787                 byt_gpio_irq_init_hw(vg);
1788                 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
1789                                            handle_bad_irq, IRQ_TYPE_NONE);
1790                 if (ret) {
1791                         dev_err(&vg->pdev->dev, "failed to add irqchip\n");
1792                         return ret;
1793                 }
1794
1795                 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
1796                                              (unsigned)irq_rc->start,
1797                                              byt_gpio_irq_handler);
1798         }
1799
1800         return ret;
1801 }
1802
1803 static int byt_set_soc_data(struct byt_gpio *vg,
1804                             const struct byt_pinctrl_soc_data *soc_data)
1805 {
1806         int i;
1807
1808         vg->soc_data = soc_data;
1809         vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
1810                                             soc_data->ncommunities,
1811                                             sizeof(*vg->communities_copy),
1812                                             GFP_KERNEL);
1813         if (!vg->communities_copy)
1814                 return -ENOMEM;
1815
1816         for (i = 0; i < soc_data->ncommunities; i++) {
1817                 struct byt_community *comm = vg->communities_copy + i;
1818                 struct resource *mem_rc;
1819
1820                 *comm = vg->soc_data->communities[i];
1821
1822                 mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0);
1823                 comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc);
1824                 if (IS_ERR(comm->reg_base))
1825                         return PTR_ERR(comm->reg_base);
1826         }
1827
1828         return 0;
1829 }
1830
1831 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1832         { "INT33B2", (kernel_ulong_t)byt_soc_data },
1833         { "INT33FC", (kernel_ulong_t)byt_soc_data },
1834         { }
1835 };
1836 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
1837
1838 static int byt_pinctrl_probe(struct platform_device *pdev)
1839 {
1840         const struct byt_pinctrl_soc_data *soc_data = NULL;
1841         const struct byt_pinctrl_soc_data **soc_table;
1842         const struct acpi_device_id *acpi_id;
1843         struct acpi_device *acpi_dev;
1844         struct byt_gpio *vg;
1845         int i, ret;
1846
1847         acpi_dev = ACPI_COMPANION(&pdev->dev);
1848         if (!acpi_dev)
1849                 return -ENODEV;
1850
1851         acpi_id = acpi_match_device(byt_gpio_acpi_match, &pdev->dev);
1852         if (!acpi_id)
1853                 return -ENODEV;
1854
1855         soc_table = (const struct byt_pinctrl_soc_data **)acpi_id->driver_data;
1856
1857         for (i = 0; soc_table[i]; i++) {
1858                 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
1859                         soc_data = soc_table[i];
1860                         break;
1861                 }
1862         }
1863
1864         if (!soc_data)
1865                 return -ENODEV;
1866
1867         vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
1868         if (!vg)
1869                 return -ENOMEM;
1870
1871         vg->pdev = pdev;
1872         ret = byt_set_soc_data(vg, soc_data);
1873         if (ret) {
1874                 dev_err(&pdev->dev, "failed to set soc data\n");
1875                 return ret;
1876         }
1877
1878         vg->pctl_desc           = byt_pinctrl_desc;
1879         vg->pctl_desc.name      = dev_name(&pdev->dev);
1880         vg->pctl_desc.pins      = vg->soc_data->pins;
1881         vg->pctl_desc.npins     = vg->soc_data->npins;
1882
1883         vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg);
1884         if (IS_ERR(vg->pctl_dev)) {
1885                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1886                 return PTR_ERR(vg->pctl_dev);
1887         }
1888
1889         ret = byt_gpio_probe(vg);
1890         if (ret)
1891                 return ret;
1892
1893         platform_set_drvdata(pdev, vg);
1894         pm_runtime_enable(&pdev->dev);
1895
1896         return 0;
1897 }
1898
1899 #ifdef CONFIG_PM_SLEEP
1900 static int byt_gpio_suspend(struct device *dev)
1901 {
1902         struct platform_device *pdev = to_platform_device(dev);
1903         struct byt_gpio *vg = platform_get_drvdata(pdev);
1904         unsigned long flags;
1905         int i;
1906
1907         raw_spin_lock_irqsave(&byt_lock, flags);
1908
1909         for (i = 0; i < vg->soc_data->npins; i++) {
1910                 void __iomem *reg;
1911                 u32 value;
1912                 unsigned int pin = vg->soc_data->pins[i].number;
1913
1914                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1915                 if (!reg) {
1916                         dev_warn(&vg->pdev->dev,
1917                                  "Pin %i: could not retrieve conf0 register\n",
1918                                  i);
1919                         continue;
1920                 }
1921                 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1922                 vg->saved_context[i].conf0 = value;
1923
1924                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1925                 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1926                 vg->saved_context[i].val = value;
1927         }
1928
1929         raw_spin_unlock_irqrestore(&byt_lock, flags);
1930         return 0;
1931 }
1932
1933 static int byt_gpio_resume(struct device *dev)
1934 {
1935         struct platform_device *pdev = to_platform_device(dev);
1936         struct byt_gpio *vg = platform_get_drvdata(pdev);
1937         unsigned long flags;
1938         int i;
1939
1940         raw_spin_lock_irqsave(&byt_lock, flags);
1941
1942         for (i = 0; i < vg->soc_data->npins; i++) {
1943                 void __iomem *reg;
1944                 u32 value;
1945                 unsigned int pin = vg->soc_data->pins[i].number;
1946
1947                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1948                 if (!reg) {
1949                         dev_warn(&vg->pdev->dev,
1950                                  "Pin %i: could not retrieve conf0 register\n",
1951                                  i);
1952                         continue;
1953                 }
1954                 value = readl(reg);
1955                 if ((value & BYT_CONF0_RESTORE_MASK) !=
1956                      vg->saved_context[i].conf0) {
1957                         value &= ~BYT_CONF0_RESTORE_MASK;
1958                         value |= vg->saved_context[i].conf0;
1959                         writel(value, reg);
1960                         dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1961                 }
1962
1963                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1964                 value = readl(reg);
1965                 if ((value & BYT_VAL_RESTORE_MASK) !=
1966                      vg->saved_context[i].val) {
1967                         u32 v;
1968
1969                         v = value & ~BYT_VAL_RESTORE_MASK;
1970                         v |= vg->saved_context[i].val;
1971                         if (v != value) {
1972                                 writel(v, reg);
1973                                 dev_dbg(dev, "restored pin %d val %#08x\n",
1974                                         i, v);
1975                         }
1976                 }
1977         }
1978
1979         raw_spin_unlock_irqrestore(&byt_lock, flags);
1980         return 0;
1981 }
1982 #endif
1983
1984 #ifdef CONFIG_PM
1985 static int byt_gpio_runtime_suspend(struct device *dev)
1986 {
1987         return 0;
1988 }
1989
1990 static int byt_gpio_runtime_resume(struct device *dev)
1991 {
1992         return 0;
1993 }
1994 #endif
1995
1996 static const struct dev_pm_ops byt_gpio_pm_ops = {
1997         SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1998         SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1999                            NULL)
2000 };
2001
2002 static struct platform_driver byt_gpio_driver = {
2003         .probe          = byt_pinctrl_probe,
2004         .driver         = {
2005                 .name                   = "byt_gpio",
2006                 .pm                     = &byt_gpio_pm_ops,
2007                 .suppress_bind_attrs    = true,
2008
2009                 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
2010         },
2011 };
2012
2013 static int __init byt_gpio_init(void)
2014 {
2015         return platform_driver_register(&byt_gpio_driver);
2016 }
2017 subsys_initcall(byt_gpio_init);