drivers/pinctrl/intel/pinctrl-intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel pinctrl/GPIO core driver.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/gpio/driver.h>
  13 #include <linux/log2.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pinctrl/pinctrl.h>
  16 #include <linux/pinctrl/pinmux.h>
  17 #include <linux/pinctrl/pinconf.h>
  18 #include <linux/pinctrl/pinconf-generic.h>
  19
  20 #include "../core.h"
  21 #include "pinctrl-intel.h"
  22
  23 /* Offset from regs */
  24 #define REVID                           0x000
  25 #define REVID_SHIFT                     16
  26 #define REVID_MASK                      GENMASK(31, 16)
  27
  28 #define PADBAR                          0x00c
  29 #define GPI_IS                          0x100
  30
  31 #define PADOWN_BITS                     4
  32 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  33 #define PADOWN_MASK(p)                  (0xf << PADOWN_SHIFT(p))
  34 #define PADOWN_GPP(p)                   ((p) / 8)
  35
  36 /* Offset from pad_regs */
  37 #define PADCFG0                         0x000
  38 #define PADCFG0_RXEVCFG_SHIFT           25
  39 #define PADCFG0_RXEVCFG_MASK            (3 << PADCFG0_RXEVCFG_SHIFT)
  40 #define PADCFG0_RXEVCFG_LEVEL           0
  41 #define PADCFG0_RXEVCFG_EDGE            1
  42 #define PADCFG0_RXEVCFG_DISABLED        2
  43 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  44 #define PADCFG0_PREGFRXSEL              BIT(24)
  45 #define PADCFG0_RXINV                   BIT(23)
  46 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  47 #define PADCFG0_GPIROUTSCI              BIT(19)
  48 #define PADCFG0_GPIROUTSMI              BIT(18)
  49 #define PADCFG0_GPIROUTNMI              BIT(17)
  50 #define PADCFG0_PMODE_SHIFT             10
  51 #define PADCFG0_PMODE_MASK              (0xf << PADCFG0_PMODE_SHIFT)
  52 #define PADCFG0_PMODE_GPIO              0
  53 #define PADCFG0_GPIORXDIS               BIT(9)
  54 #define PADCFG0_GPIOTXDIS               BIT(8)
  55 #define PADCFG0_GPIORXSTATE             BIT(1)
  56 #define PADCFG0_GPIOTXSTATE             BIT(0)
  57
  58 #define PADCFG1                         0x004
  59 #define PADCFG1_TERM_UP                 BIT(13)
  60 #define PADCFG1_TERM_SHIFT              10
  61 #define PADCFG1_TERM_MASK               (7 << PADCFG1_TERM_SHIFT)
  62 #define PADCFG1_TERM_20K                4
  63 #define PADCFG1_TERM_2K                 3
  64 #define PADCFG1_TERM_5K                 2
  65 #define PADCFG1_TERM_1K                 1
  66
  67 #define PADCFG2                         0x008
  68 #define PADCFG2_DEBEN                   BIT(0)
  69 #define PADCFG2_DEBOUNCE_SHIFT          1
  70 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
  71
  72 #define DEBOUNCE_PERIOD                 31250 /* ns */
  73
  74 struct intel_pad_context {
  75         u32 padcfg0;
  76         u32 padcfg1;
  77         u32 padcfg2;
  78 };
  79
  80 struct intel_community_context {
  81         u32 *intmask;
  82 };
  83
  84 struct intel_pinctrl_context {
  85         struct intel_pad_context *pads;
  86         struct intel_community_context *communities;
  87 };
  88
  89 /**
  90  * struct intel_pinctrl - Intel pinctrl private structure
  91  * @dev: Pointer to the device structure
  92  * @lock: Lock to serialize register access
  93  * @pctldesc: Pin controller description
  94  * @pctldev: Pointer to the pin controller device
  95  * @chip: GPIO chip in this pin controller
  96  * @soc: SoC/PCH specific pin configuration data
  97  * @communities: All communities in this pin controller
  98  * @ncommunities: Number of communities in this pin controller
  99  * @context: Configuration saved over system sleep
 100  * @irq: pinctrl/GPIO chip irq number
 101  */
 102 struct intel_pinctrl {
 103         struct device *dev;
 104         raw_spinlock_t lock;
 105         struct pinctrl_desc pctldesc;
 106         struct pinctrl_dev *pctldev;
 107         struct gpio_chip chip;
 108         const struct intel_pinctrl_soc_data *soc;
 109         struct intel_community *communities;
 110         size_t ncommunities;
 111         struct intel_pinctrl_context context;
 112         int irq;
 113 };
 114
 115 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 116 #define padgroup_offset(g, p)   ((p) - (g)->base)
 117
 118 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
 119                                                    unsigned pin)
 120 {
 121         struct intel_community *community;
 122         int i;
 123
 124         for (i = 0; i < pctrl->ncommunities; i++) {
 125                 community = &pctrl->communities[i];
 126                 if (pin >= community->pin_base &&
 127                     pin < community->pin_base + community->npins)
 128                         return community;
 129         }
 130
 131         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 132         return NULL;
 133 }
 134
 135 static const struct intel_padgroup *
 136 intel_community_get_padgroup(const struct intel_community *community,
 137                              unsigned pin)
 138 {
 139         int i;
 140
 141         for (i = 0; i < community->ngpps; i++) {
 142                 const struct intel_padgroup *padgrp = &community->gpps[i];
 143
 144                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 145                         return padgrp;
 146         }
 147
 148         return NULL;
 149 }
 150
 151 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
 152                                       unsigned reg)
 153 {
 154         const struct intel_community *community;
 155         unsigned padno;
 156         size_t nregs;
 157
 158         community = intel_get_community(pctrl, pin);
 159         if (!community)
 160                 return NULL;
 161
 162         padno = pin_to_padno(community, pin);
 163         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 164
 165         if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
 166                 return NULL;
 167
 168         return community->pad_regs + reg + padno * nregs * 4;
 169 }
 170
 171 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
 172 {
 173         const struct intel_community *community;
 174         const struct intel_padgroup *padgrp;
 175         unsigned gpp, offset, gpp_offset;
 176         void __iomem *padown;
 177
 178         community = intel_get_community(pctrl, pin);
 179         if (!community)
 180                 return false;
 181         if (!community->padown_offset)
 182                 return true;
 183
 184         padgrp = intel_community_get_padgroup(community, pin);
 185         if (!padgrp)
 186                 return false;
 187
 188         gpp_offset = padgroup_offset(padgrp, pin);
 189         gpp = PADOWN_GPP(gpp_offset);
 190         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 191         padown = community->regs + offset;
 192
 193         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 194 }
 195
 196 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
 197 {
 198         const struct intel_community *community;
 199         const struct intel_padgroup *padgrp;
 200         unsigned offset, gpp_offset;
 201         void __iomem *hostown;
 202
 203         community = intel_get_community(pctrl, pin);
 204         if (!community)
 205                 return true;
 206         if (!community->hostown_offset)
 207                 return false;
 208
 209         padgrp = intel_community_get_padgroup(community, pin);
 210         if (!padgrp)
 211                 return true;
 212
 213         gpp_offset = padgroup_offset(padgrp, pin);
 214         offset = community->hostown_offset + padgrp->reg_num * 4;
 215         hostown = community->regs + offset;
 216
 217         return !(readl(hostown) & BIT(gpp_offset));
 218 }
 219
 220 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
 221 {
 222         struct intel_community *community;
 223         const struct intel_padgroup *padgrp;
 224         unsigned offset, gpp_offset;
 225         u32 value;
 226
 227         community = intel_get_community(pctrl, pin);
 228         if (!community)
 229                 return true;
 230         if (!community->padcfglock_offset)
 231                 return false;
 232
 233         padgrp = intel_community_get_padgroup(community, pin);
 234         if (!padgrp)
 235                 return true;
 236
 237         gpp_offset = padgroup_offset(padgrp, pin);
 238
 239         /*
 240          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 241          * the pad is considered unlocked. Any other case means that it is
 242          * either fully or partially locked and we don't touch it.
 243          */
 244         offset = community->padcfglock_offset + padgrp->reg_num * 8;
 245         value = readl(community->regs + offset);
 246         if (value & BIT(gpp_offset))
 247                 return true;
 248
 249         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 250         value = readl(community->regs + offset);
 251         if (value & BIT(gpp_offset))
 252                 return true;
 253
 254         return false;
 255 }
 256
 257 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
 258 {
 259         return intel_pad_owned_by_host(pctrl, pin) &&
 260                 !intel_pad_locked(pctrl, pin);
 261 }
 262
 263 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 264 {
 265         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 266
 267         return pctrl->soc->ngroups;
 268 }
 269
 270 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 271                                       unsigned group)
 272 {
 273         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 274
 275         return pctrl->soc->groups[group].name;
 276 }
 277
 278 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
 279                               const unsigned **pins, unsigned *npins)
 280 {
 281         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 282
 283         *pins = pctrl->soc->groups[group].pins;
 284         *npins = pctrl->soc->groups[group].npins;
 285         return 0;
 286 }
 287
 288 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 289                                unsigned pin)
 290 {
 291         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 292         void __iomem *padcfg;
 293         u32 cfg0, cfg1, mode;
 294         bool locked, acpi;
 295
 296         if (!intel_pad_owned_by_host(pctrl, pin)) {
 297                 seq_puts(s, "not available");
 298                 return;
 299         }
 300
 301         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 302         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 303
 304         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 305         if (mode == PADCFG0_PMODE_GPIO)
 306                 seq_puts(s, "GPIO ");
 307         else
 308                 seq_printf(s, "mode %d ", mode);
 309
 310         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 311
 312         /* Dump the additional PADCFG registers if available */
 313         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 314         if (padcfg)
 315                 seq_printf(s, " 0x%08x", readl(padcfg));
 316
 317         locked = intel_pad_locked(pctrl, pin);
 318         acpi = intel_pad_acpi_mode(pctrl, pin);
 319
 320         if (locked || acpi) {
 321                 seq_puts(s, " [");
 322                 if (locked) {
 323                         seq_puts(s, "LOCKED");
 324                         if (acpi)
 325                                 seq_puts(s, ", ");
 326                 }
 327                 if (acpi)
 328                         seq_puts(s, "ACPI");
 329                 seq_puts(s, "]");
 330         }
 331 }
 332
 333 static const struct pinctrl_ops intel_pinctrl_ops = {
 334         .get_groups_count = intel_get_groups_count,
 335         .get_group_name = intel_get_group_name,
 336         .get_group_pins = intel_get_group_pins,
 337         .pin_dbg_show = intel_pin_dbg_show,
 338 };
 339
 340 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 341 {
 342         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 343
 344         return pctrl->soc->nfunctions;
 345 }
 346
 347 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 348                                            unsigned function)
 349 {
 350         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 351
 352         return pctrl->soc->functions[function].name;
 353 }
 354
 355 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 356                                      unsigned function,
 357                                      const char * const **groups,
 358                                      unsigned * const ngroups)
 359 {
 360         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 361
 362         *groups = pctrl->soc->functions[function].groups;
 363         *ngroups = pctrl->soc->functions[function].ngroups;
 364         return 0;
 365 }
 366
 367 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 368                                 unsigned group)
 369 {
 370         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 371         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 372         unsigned long flags;
 373         int i;
 374
 375         raw_spin_lock_irqsave(&pctrl->lock, flags);
 376
 377         /*
 378          * All pins in the groups needs to be accessible and writable
 379          * before we can enable the mux for this group.
 380          */
 381         for (i = 0; i < grp->npins; i++) {
 382                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
 383                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 384                         return -EBUSY;
 385                 }
 386         }
 387
 388         /* Now enable the mux setting for each pin in the group */
 389         for (i = 0; i < grp->npins; i++) {
 390                 void __iomem *padcfg0;
 391                 u32 value;
 392
 393                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
 394                 value = readl(padcfg0);
 395
 396                 value &= ~PADCFG0_PMODE_MASK;
 397
 398                 if (grp->modes)
 399                         value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
 400                 else
 401                         value |= grp->mode << PADCFG0_PMODE_SHIFT;
 402
 403                 writel(value, padcfg0);
 404         }
 405
 406         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 407
 408         return 0;
 409 }
 410
 411 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 412 {
 413         u32 value;
 414
 415         value = readl(padcfg0);
 416         if (input) {
 417                 value &= ~PADCFG0_GPIORXDIS;
 418                 value |= PADCFG0_GPIOTXDIS;
 419         } else {
 420                 value &= ~PADCFG0_GPIOTXDIS;
 421                 value |= PADCFG0_GPIORXDIS;
 422         }
 423         writel(value, padcfg0);
 424 }
 425
 426 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
 427 {
 428         return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 429 }
 430
 431 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 432 {
 433         u32 value;
 434
 435         /* Put the pad into GPIO mode */
 436         value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
 437         /* Disable SCI/SMI/NMI generation */
 438         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 439         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 440         writel(value, padcfg0);
 441 }
 442
 443 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 444                                      struct pinctrl_gpio_range *range,
 445                                      unsigned pin)
 446 {
 447         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 448         void __iomem *padcfg0;
 449         unsigned long flags;
 450
 451         raw_spin_lock_irqsave(&pctrl->lock, flags);
 452
 453         if (!intel_pad_usable(pctrl, pin)) {
 454                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 455                 return -EBUSY;
 456         }
 457
 458         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 459
 460         /*
 461          * If pin is already configured in GPIO mode, we assume that
 462          * firmware provides correct settings. In such case we avoid
 463          * potential glitches on the pin. Otherwise, for the pin in
 464          * alternative mode, consumer has to supply respective flags.
 465          */
 466         if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
 467                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 468                 return 0;
 469         }
 470
 471         intel_gpio_set_gpio_mode(padcfg0);
 472
 473         /* Disable TX buffer and enable RX (this will be input) */
 474         __intel_gpio_set_direction(padcfg0, true);
 475
 476         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 477
 478         return 0;
 479 }
 480
 481 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 482                                     struct pinctrl_gpio_range *range,
 483                                     unsigned pin, bool input)
 484 {
 485         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 486         void __iomem *padcfg0;
 487         unsigned long flags;
 488
 489         raw_spin_lock_irqsave(&pctrl->lock, flags);
 490
 491         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 492         __intel_gpio_set_direction(padcfg0, input);
 493
 494         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 495
 496         return 0;
 497 }
 498
 499 static const struct pinmux_ops intel_pinmux_ops = {
 500         .get_functions_count = intel_get_functions_count,
 501         .get_function_name = intel_get_function_name,
 502         .get_function_groups = intel_get_function_groups,
 503         .set_mux = intel_pinmux_set_mux,
 504         .gpio_request_enable = intel_gpio_request_enable,
 505         .gpio_set_direction = intel_gpio_set_direction,
 506 };
 507
 508 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
 509                             unsigned long *config)
 510 {
 511         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 512         enum pin_config_param param = pinconf_to_config_param(*config);
 513         const struct intel_community *community;
 514         u32 value, term;
 515         u32 arg = 0;
 516
 517         if (!intel_pad_owned_by_host(pctrl, pin))
 518                 return -ENOTSUPP;
 519
 520         community = intel_get_community(pctrl, pin);
 521         value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 522         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 523
 524         switch (param) {
 525         case PIN_CONFIG_BIAS_DISABLE:
 526                 if (term)
 527                         return -EINVAL;
 528                 break;
 529
 530         case PIN_CONFIG_BIAS_PULL_UP:
 531                 if (!term || !(value & PADCFG1_TERM_UP))
 532                         return -EINVAL;
 533
 534                 switch (term) {
 535                 case PADCFG1_TERM_1K:
 536                         arg = 1000;
 537                         break;
 538                 case PADCFG1_TERM_2K:
 539                         arg = 2000;
 540                         break;
 541                 case PADCFG1_TERM_5K:
 542                         arg = 5000;
 543                         break;
 544                 case PADCFG1_TERM_20K:
 545                         arg = 20000;
 546                         break;
 547                 }
 548
 549                 break;
 550
 551         case PIN_CONFIG_BIAS_PULL_DOWN:
 552                 if (!term || value & PADCFG1_TERM_UP)
 553                         return -EINVAL;
 554
 555                 switch (term) {
 556                 case PADCFG1_TERM_1K:
 557                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 558                                 return -EINVAL;
 559                         arg = 1000;
 560                         break;
 561                 case PADCFG1_TERM_5K:
 562                         arg = 5000;
 563                         break;
 564                 case PADCFG1_TERM_20K:
 565                         arg = 20000;
 566                         break;
 567                 }
 568
 569                 break;
 570
 571         case PIN_CONFIG_INPUT_DEBOUNCE: {
 572                 void __iomem *padcfg2;
 573                 u32 v;
 574
 575                 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 576                 if (!padcfg2)
 577                         return -ENOTSUPP;
 578
 579                 v = readl(padcfg2);
 580                 if (!(v & PADCFG2_DEBEN))
 581                         return -EINVAL;
 582
 583                 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 584                 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
 585
 586                 break;
 587         }
 588
 589         default:
 590                 return -ENOTSUPP;
 591         }
 592
 593         *config = pinconf_to_config_packed(param, arg);
 594         return 0;
 595 }
 596
 597 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
 598                                  unsigned long config)
 599 {
 600         unsigned param = pinconf_to_config_param(config);
 601         unsigned arg = pinconf_to_config_argument(config);
 602         const struct intel_community *community;
 603         void __iomem *padcfg1;
 604         unsigned long flags;
 605         int ret = 0;
 606         u32 value;
 607
 608         raw_spin_lock_irqsave(&pctrl->lock, flags);
 609
 610         community = intel_get_community(pctrl, pin);
 611         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 612         value = readl(padcfg1);
 613
 614         switch (param) {
 615         case PIN_CONFIG_BIAS_DISABLE:
 616                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 617                 break;
 618
 619         case PIN_CONFIG_BIAS_PULL_UP:
 620                 value &= ~PADCFG1_TERM_MASK;
 621
 622                 value |= PADCFG1_TERM_UP;
 623
 624                 /* Set default strength value in case none is given */
 625                 if (arg == 1)
 626                         arg = 5000;
 627
 628                 switch (arg) {
 629                 case 20000:
 630                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 631                         break;
 632                 case 5000:
 633                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 634                         break;
 635                 case 2000:
 636                         value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
 637                         break;
 638                 case 1000:
 639                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 640                         break;
 641                 default:
 642                         ret = -EINVAL;
 643                 }
 644
 645                 break;
 646
 647         case PIN_CONFIG_BIAS_PULL_DOWN:
 648                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 649
 650                 /* Set default strength value in case none is given */
 651                 if (arg == 1)
 652                         arg = 5000;
 653
 654                 switch (arg) {
 655                 case 20000:
 656                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 657                         break;
 658                 case 5000:
 659                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 660                         break;
 661                 case 1000:
 662                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 663                                 ret = -EINVAL;
 664                                 break;
 665                         }
 666                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 667                         break;
 668                 default:
 669                         ret = -EINVAL;
 670                 }
 671
 672                 break;
 673         }
 674
 675         if (!ret)
 676                 writel(value, padcfg1);
 677
 678         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 679
 680         return ret;
 681 }
 682
 683 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
 684                                      unsigned debounce)
 685 {
 686         void __iomem *padcfg0, *padcfg2;
 687         unsigned long flags;
 688         u32 value0, value2;
 689         int ret = 0;
 690
 691         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 692         if (!padcfg2)
 693                 return -ENOTSUPP;
 694
 695         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 696
 697         raw_spin_lock_irqsave(&pctrl->lock, flags);
 698
 699         value0 = readl(padcfg0);
 700         value2 = readl(padcfg2);
 701
 702         /* Disable glitch filter and debouncer */
 703         value0 &= ~PADCFG0_PREGFRXSEL;
 704         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
 705
 706         if (debounce) {
 707                 unsigned long v;
 708
 709                 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
 710                 if (v < 3 || v > 15) {
 711                         ret = -EINVAL;
 712                         goto exit_unlock;
 713                 } else {
 714                         /* Enable glitch filter and debouncer */
 715                         value0 |= PADCFG0_PREGFRXSEL;
 716                         value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
 717                         value2 |= PADCFG2_DEBEN;
 718                 }
 719         }
 720
 721         writel(value0, padcfg0);
 722         writel(value2, padcfg2);
 723
 724 exit_unlock:
 725         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 726
 727         return ret;
 728 }
 729
 730 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
 731                           unsigned long *configs, unsigned nconfigs)
 732 {
 733         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 734         int i, ret;
 735
 736         if (!intel_pad_usable(pctrl, pin))
 737                 return -ENOTSUPP;
 738
 739         for (i = 0; i < nconfigs; i++) {
 740                 switch (pinconf_to_config_param(configs[i])) {
 741                 case PIN_CONFIG_BIAS_DISABLE:
 742                 case PIN_CONFIG_BIAS_PULL_UP:
 743                 case PIN_CONFIG_BIAS_PULL_DOWN:
 744                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 745                         if (ret)
 746                                 return ret;
 747                         break;
 748
 749                 case PIN_CONFIG_INPUT_DEBOUNCE:
 750                         ret = intel_config_set_debounce(pctrl, pin,
 751                                 pinconf_to_config_argument(configs[i]));
 752                         if (ret)
 753                                 return ret;
 754                         break;
 755
 756                 default:
 757                         return -ENOTSUPP;
 758                 }
 759         }
 760
 761         return 0;
 762 }
 763
 764 static const struct pinconf_ops intel_pinconf_ops = {
 765         .is_generic = true,
 766         .pin_config_get = intel_config_get,
 767         .pin_config_set = intel_config_set,
 768 };
 769
 770 static const struct pinctrl_desc intel_pinctrl_desc = {
 771         .pctlops = &intel_pinctrl_ops,
 772         .pmxops = &intel_pinmux_ops,
 773         .confops = &intel_pinconf_ops,
 774         .owner = THIS_MODULE,
 775 };
 776
 777 /**
 778  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 779  * @pctrl: Pinctrl structure
 780  * @offset: GPIO offset from gpiolib
 781  * @commmunity: Community is filled here if not %NULL
 782  * @padgrp: Pad group is filled here if not %NULL
 783  *
 784  * When coming through gpiolib irqchip, the GPIO offset is not
 785  * automatically translated to pinctrl pin number. This function can be
 786  * used to find out the corresponding pinctrl pin.
 787  */
 788 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
 789                              const struct intel_community **community,
 790                              const struct intel_padgroup **padgrp)
 791 {
 792         int i;
 793
 794         for (i = 0; i < pctrl->ncommunities; i++) {
 795                 const struct intel_community *comm = &pctrl->communities[i];
 796                 int j;
 797
 798                 for (j = 0; j < comm->ngpps; j++) {
 799                         const struct intel_padgroup *pgrp = &comm->gpps[j];
 800
 801                         if (pgrp->gpio_base < 0)
 802                                 continue;
 803
 804                         if (offset >= pgrp->gpio_base &&
 805                             offset < pgrp->gpio_base + pgrp->size) {
 806                                 int pin;
 807
 808                                 pin = pgrp->base + offset - pgrp->gpio_base;
 809                                 if (community)
 810                                         *community = comm;
 811                                 if (padgrp)
 812                                         *padgrp = pgrp;
 813
 814                                 return pin;
 815                         }
 816                 }
 817         }
 818
 819         return -EINVAL;
 820 }
 821
 822 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
 823 {
 824         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 825         void __iomem *reg;
 826         u32 padcfg0;
 827         int pin;
 828
 829         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 830         if (pin < 0)
 831                 return -EINVAL;
 832
 833         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 834         if (!reg)
 835                 return -EINVAL;
 836
 837         padcfg0 = readl(reg);
 838         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
 839                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
 840
 841         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 842 }
 843
 844 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 845 {
 846         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 847         unsigned long flags;
 848         void __iomem *reg;
 849         u32 padcfg0;
 850         int pin;
 851
 852         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 853         if (pin < 0)
 854                 return;
 855
 856         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 857         if (!reg)
 858                 return;
 859
 860         raw_spin_lock_irqsave(&pctrl->lock, flags);
 861         padcfg0 = readl(reg);
 862         if (value)
 863                 padcfg0 |= PADCFG0_GPIOTXSTATE;
 864         else
 865                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 866         writel(padcfg0, reg);
 867         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 868 }
 869
 870 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 871 {
 872         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 873         void __iomem *reg;
 874         u32 padcfg0;
 875         int pin;
 876
 877         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 878         if (pin < 0)
 879                 return -EINVAL;
 880
 881         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 882         if (!reg)
 883                 return -EINVAL;
 884
 885         padcfg0 = readl(reg);
 886
 887         if (padcfg0 & PADCFG0_PMODE_MASK)
 888                 return -EINVAL;
 889
 890         return !!(padcfg0 & PADCFG0_GPIOTXDIS);
 891 }
 892
 893 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 894 {
 895         return pinctrl_gpio_direction_input(chip->base + offset);
 896 }
 897
 898 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 899                                        int value)
 900 {
 901         intel_gpio_set(chip, offset, value);
 902         return pinctrl_gpio_direction_output(chip->base + offset);
 903 }
 904
 905 static const struct gpio_chip intel_gpio_chip = {
 906         .owner = THIS_MODULE,
 907         .request = gpiochip_generic_request,
 908         .free = gpiochip_generic_free,
 909         .get_direction = intel_gpio_get_direction,
 910         .direction_input = intel_gpio_direction_input,
 911         .direction_output = intel_gpio_direction_output,
 912         .get = intel_gpio_get,
 913         .set = intel_gpio_set,
 914         .set_config = gpiochip_generic_config,
 915 };
 916
 917 static void intel_gpio_irq_ack(struct irq_data *d)
 918 {
 919         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 920         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 921         const struct intel_community *community;
 922         const struct intel_padgroup *padgrp;
 923         int pin;
 924
 925         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 926         if (pin >= 0) {
 927                 unsigned gpp, gpp_offset, is_offset;
 928
 929                 gpp = padgrp->reg_num;
 930                 gpp_offset = padgroup_offset(padgrp, pin);
 931                 is_offset = community->is_offset + gpp * 4;
 932
 933                 raw_spin_lock(&pctrl->lock);
 934                 writel(BIT(gpp_offset), community->regs + is_offset);
 935                 raw_spin_unlock(&pctrl->lock);
 936         }
 937 }
 938
 939 static void intel_gpio_irq_enable(struct irq_data *d)
 940 {
 941         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 942         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 943         const struct intel_community *community;
 944         const struct intel_padgroup *padgrp;
 945         int pin;
 946
 947         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 948         if (pin >= 0) {
 949                 unsigned gpp, gpp_offset, is_offset;
 950                 unsigned long flags;
 951                 u32 value;
 952
 953                 gpp = padgrp->reg_num;
 954                 gpp_offset = padgroup_offset(padgrp, pin);
 955                 is_offset = community->is_offset + gpp * 4;
 956
 957                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 958                 /* Clear interrupt status first to avoid unexpected interrupt */
 959                 writel(BIT(gpp_offset), community->regs + is_offset);
 960
 961                 value = readl(community->regs + community->ie_offset + gpp * 4);
 962                 value |= BIT(gpp_offset);
 963                 writel(value, community->regs + community->ie_offset + gpp * 4);
 964                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 965         }
 966 }
 967
 968 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
 969 {
 970         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 971         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 972         const struct intel_community *community;
 973         const struct intel_padgroup *padgrp;
 974         int pin;
 975
 976         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 977         if (pin >= 0) {
 978                 unsigned gpp, gpp_offset;
 979                 unsigned long flags;
 980                 void __iomem *reg;
 981                 u32 value;
 982
 983                 gpp = padgrp->reg_num;
 984                 gpp_offset = padgroup_offset(padgrp, pin);
 985
 986                 reg = community->regs + community->ie_offset + gpp * 4;
 987
 988                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 989                 value = readl(reg);
 990                 if (mask)
 991                         value &= ~BIT(gpp_offset);
 992                 else
 993                         value |= BIT(gpp_offset);
 994                 writel(value, reg);
 995                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 996         }
 997 }
 998
 999 static void intel_gpio_irq_mask(struct irq_data *d)
1000 {
1001         intel_gpio_irq_mask_unmask(d, true);
1002 }
1003
1004 static void intel_gpio_irq_unmask(struct irq_data *d)
1005 {
1006         intel_gpio_irq_mask_unmask(d, false);
1007 }
1008
1009 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
1010 {
1011         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1012         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1013         unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1014         unsigned long flags;
1015         void __iomem *reg;
1016         u32 value;
1017
1018         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1019         if (!reg)
1020                 return -EINVAL;
1021
1022         /*
1023          * If the pin is in ACPI mode it is still usable as a GPIO but it
1024          * cannot be used as IRQ because GPI_IS status bit will not be
1025          * updated by the host controller hardware.
1026          */
1027         if (intel_pad_acpi_mode(pctrl, pin)) {
1028                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1029                 return -EPERM;
1030         }
1031
1032         raw_spin_lock_irqsave(&pctrl->lock, flags);
1033
1034         intel_gpio_set_gpio_mode(reg);
1035
1036         value = readl(reg);
1037
1038         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1039
1040         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1041                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1042         } else if (type & IRQ_TYPE_EDGE_FALLING) {
1043                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1044                 value |= PADCFG0_RXINV;
1045         } else if (type & IRQ_TYPE_EDGE_RISING) {
1046                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1047         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1048                 if (type & IRQ_TYPE_LEVEL_LOW)
1049                         value |= PADCFG0_RXINV;
1050         } else {
1051                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1052         }
1053
1054         writel(value, reg);
1055
1056         if (type & IRQ_TYPE_EDGE_BOTH)
1057                 irq_set_handler_locked(d, handle_edge_irq);
1058         else if (type & IRQ_TYPE_LEVEL_MASK)
1059                 irq_set_handler_locked(d, handle_level_irq);
1060
1061         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1062
1063         return 0;
1064 }
1065
1066 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1067 {
1068         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1069         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1070         unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1071
1072         if (on)
1073                 enable_irq_wake(pctrl->irq);
1074         else
1075                 disable_irq_wake(pctrl->irq);
1076
1077         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1078         return 0;
1079 }
1080
1081 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1082         const struct intel_community *community)
1083 {
1084         struct gpio_chip *gc = &pctrl->chip;
1085         irqreturn_t ret = IRQ_NONE;
1086         int gpp;
1087
1088         for (gpp = 0; gpp < community->ngpps; gpp++) {
1089                 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1090                 unsigned long pending, enabled, gpp_offset;
1091
1092                 pending = readl(community->regs + community->is_offset +
1093                                 padgrp->reg_num * 4);
1094                 enabled = readl(community->regs + community->ie_offset +
1095                                 padgrp->reg_num * 4);
1096
1097                 /* Only interrupts that are enabled */
1098                 pending &= enabled;
1099
1100                 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1101                         unsigned irq;
1102
1103                         irq = irq_find_mapping(gc->irq.domain,
1104                                                padgrp->gpio_base + gpp_offset);
1105                         generic_handle_irq(irq);
1106
1107                         ret |= IRQ_HANDLED;
1108                 }
1109         }
1110
1111         return ret;
1112 }
1113
1114 static irqreturn_t intel_gpio_irq(int irq, void *data)
1115 {
1116         const struct intel_community *community;
1117         struct intel_pinctrl *pctrl = data;
1118         irqreturn_t ret = IRQ_NONE;
1119         int i;
1120
1121         /* Need to check all communities for pending interrupts */
1122         for (i = 0; i < pctrl->ncommunities; i++) {
1123                 community = &pctrl->communities[i];
1124                 ret |= intel_gpio_community_irq_handler(pctrl, community);
1125         }
1126
1127         return ret;
1128 }
1129
1130 static struct irq_chip intel_gpio_irqchip = {
1131         .name = "intel-gpio",
1132         .irq_enable = intel_gpio_irq_enable,
1133         .irq_ack = intel_gpio_irq_ack,
1134         .irq_mask = intel_gpio_irq_mask,
1135         .irq_unmask = intel_gpio_irq_unmask,
1136         .irq_set_type = intel_gpio_irq_type,
1137         .irq_set_wake = intel_gpio_irq_wake,
1138         .flags = IRQCHIP_MASK_ON_SUSPEND,
1139 };
1140
1141 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1142                                      const struct intel_community *community)
1143 {
1144         int ret = 0, i;
1145
1146         for (i = 0; i < community->ngpps; i++) {
1147                 const struct intel_padgroup *gpp = &community->gpps[i];
1148
1149                 if (gpp->gpio_base < 0)
1150                         continue;
1151
1152                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1153                                              gpp->gpio_base, gpp->base,
1154                                              gpp->size);
1155                 if (ret)
1156                         return ret;
1157         }
1158
1159         return ret;
1160 }
1161
1162 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1163 {
1164         const struct intel_community *community;
1165         unsigned ngpio = 0;
1166         int i, j;
1167
1168         for (i = 0; i < pctrl->ncommunities; i++) {
1169                 community = &pctrl->communities[i];
1170                 for (j = 0; j < community->ngpps; j++) {
1171                         const struct intel_padgroup *gpp = &community->gpps[j];
1172
1173                         if (gpp->gpio_base < 0)
1174                                 continue;
1175
1176                         if (gpp->gpio_base + gpp->size > ngpio)
1177                                 ngpio = gpp->gpio_base + gpp->size;
1178                 }
1179         }
1180
1181         return ngpio;
1182 }
1183
1184 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1185 {
1186         int ret, i;
1187
1188         pctrl->chip = intel_gpio_chip;
1189
1190         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1191         pctrl->chip.label = dev_name(pctrl->dev);
1192         pctrl->chip.parent = pctrl->dev;
1193         pctrl->chip.base = -1;
1194         pctrl->irq = irq;
1195
1196         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1197         if (ret) {
1198                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1199                 return ret;
1200         }
1201
1202         for (i = 0; i < pctrl->ncommunities; i++) {
1203                 struct intel_community *community = &pctrl->communities[i];
1204
1205                 ret = intel_gpio_add_pin_ranges(pctrl, community);
1206                 if (ret) {
1207                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1208                         return ret;
1209                 }
1210         }
1211
1212         /*
1213          * We need to request the interrupt here (instead of providing chip
1214          * to the irq directly) because on some platforms several GPIO
1215          * controllers share the same interrupt line.
1216          */
1217         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1218                                IRQF_SHARED | IRQF_NO_THREAD,
1219                                dev_name(pctrl->dev), pctrl);
1220         if (ret) {
1221                 dev_err(pctrl->dev, "failed to request interrupt\n");
1222                 return ret;
1223         }
1224
1225         ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1226                                    handle_bad_irq, IRQ_TYPE_NONE);
1227         if (ret) {
1228                 dev_err(pctrl->dev, "failed to add irqchip\n");
1229                 return ret;
1230         }
1231
1232         gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1233                                      NULL);
1234         return 0;
1235 }
1236
1237 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1238                                        struct intel_community *community)
1239 {
1240         struct intel_padgroup *gpps;
1241         unsigned npins = community->npins;
1242         unsigned padown_num = 0;
1243         size_t ngpps, i;
1244
1245         if (community->gpps)
1246                 ngpps = community->ngpps;
1247         else
1248                 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1249
1250         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1251         if (!gpps)
1252                 return -ENOMEM;
1253
1254         for (i = 0; i < ngpps; i++) {
1255                 if (community->gpps) {
1256                         gpps[i] = community->gpps[i];
1257                 } else {
1258                         unsigned gpp_size = community->gpp_size;
1259
1260                         gpps[i].reg_num = i;
1261                         gpps[i].base = community->pin_base + i * gpp_size;
1262                         gpps[i].size = min(gpp_size, npins);
1263                         npins -= gpps[i].size;
1264                 }
1265
1266                 if (gpps[i].size > 32)
1267                         return -EINVAL;
1268
1269                 if (!gpps[i].gpio_base)
1270                         gpps[i].gpio_base = gpps[i].base;
1271
1272                 gpps[i].padown_num = padown_num;
1273
1274                 /*
1275                  * In older hardware the number of padown registers per
1276                  * group is fixed regardless of the group size.
1277                  */
1278                 if (community->gpp_num_padown_regs)
1279                         padown_num += community->gpp_num_padown_regs;
1280                 else
1281                         padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1282         }
1283
1284         community->ngpps = ngpps;
1285         community->gpps = gpps;
1286
1287         return 0;
1288 }
1289
1290 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1291 {
1292 #ifdef CONFIG_PM_SLEEP
1293         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1294         struct intel_community_context *communities;
1295         struct intel_pad_context *pads;
1296         int i;
1297
1298         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1299         if (!pads)
1300                 return -ENOMEM;
1301
1302         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1303                                    sizeof(*communities), GFP_KERNEL);
1304         if (!communities)
1305                 return -ENOMEM;
1306
1307
1308         for (i = 0; i < pctrl->ncommunities; i++) {
1309                 struct intel_community *community = &pctrl->communities[i];
1310                 u32 *intmask;
1311
1312                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1313                                        sizeof(*intmask), GFP_KERNEL);
1314                 if (!intmask)
1315                         return -ENOMEM;
1316
1317                 communities[i].intmask = intmask;
1318         }
1319
1320         pctrl->context.pads = pads;
1321         pctrl->context.communities = communities;
1322 #endif
1323
1324         return 0;
1325 }
1326
1327 int intel_pinctrl_probe(struct platform_device *pdev,
1328                         const struct intel_pinctrl_soc_data *soc_data)
1329 {
1330         struct intel_pinctrl *pctrl;
1331         int i, ret, irq;
1332
1333         if (!soc_data)
1334                 return -EINVAL;
1335
1336         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1337         if (!pctrl)
1338                 return -ENOMEM;
1339
1340         pctrl->dev = &pdev->dev;
1341         pctrl->soc = soc_data;
1342         raw_spin_lock_init(&pctrl->lock);
1343
1344         /*
1345          * Make a copy of the communities which we can use to hold pointers
1346          * to the registers.
1347          */
1348         pctrl->ncommunities = pctrl->soc->ncommunities;
1349         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1350                                   sizeof(*pctrl->communities), GFP_KERNEL);
1351         if (!pctrl->communities)
1352                 return -ENOMEM;
1353
1354         for (i = 0; i < pctrl->ncommunities; i++) {
1355                 struct intel_community *community = &pctrl->communities[i];
1356                 struct resource *res;
1357                 void __iomem *regs;
1358                 u32 padbar;
1359
1360                 *community = pctrl->soc->communities[i];
1361
1362                 res = platform_get_resource(pdev, IORESOURCE_MEM,
1363                                             community->barno);
1364                 regs = devm_ioremap_resource(&pdev->dev, res);
1365                 if (IS_ERR(regs))
1366                         return PTR_ERR(regs);
1367
1368                 /*
1369                  * Determine community features based on the revision if
1370                  * not specified already.
1371                  */
1372                 if (!community->features) {
1373                         u32 rev;
1374
1375                         rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1376                         if (rev >= 0x94) {
1377                                 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1378                                 community->features |= PINCTRL_FEATURE_1K_PD;
1379                         }
1380                 }
1381
1382                 /* Read offset of the pad configuration registers */
1383                 padbar = readl(regs + PADBAR);
1384
1385                 community->regs = regs;
1386                 community->pad_regs = regs + padbar;
1387
1388                 if (!community->is_offset)
1389                         community->is_offset = GPI_IS;
1390
1391                 ret = intel_pinctrl_add_padgroups(pctrl, community);
1392                 if (ret)
1393                         return ret;
1394         }
1395
1396         irq = platform_get_irq(pdev, 0);
1397         if (irq < 0) {
1398                 dev_err(&pdev->dev, "failed to get interrupt number\n");
1399                 return irq;
1400         }
1401
1402         ret = intel_pinctrl_pm_init(pctrl);
1403         if (ret)
1404                 return ret;
1405
1406         pctrl->pctldesc = intel_pinctrl_desc;
1407         pctrl->pctldesc.name = dev_name(&pdev->dev);
1408         pctrl->pctldesc.pins = pctrl->soc->pins;
1409         pctrl->pctldesc.npins = pctrl->soc->npins;
1410
1411         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1412                                                pctrl);
1413         if (IS_ERR(pctrl->pctldev)) {
1414                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1415                 return PTR_ERR(pctrl->pctldev);
1416         }
1417
1418         ret = intel_gpio_probe(pctrl, irq);
1419         if (ret)
1420                 return ret;
1421
1422         platform_set_drvdata(pdev, pctrl);
1423
1424         return 0;
1425 }
1426 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1427
1428 #ifdef CONFIG_PM_SLEEP
1429 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1430 {
1431         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1432
1433         if (!pd || !intel_pad_usable(pctrl, pin))
1434                 return false;
1435
1436         /*
1437          * Only restore the pin if it is actually in use by the kernel (or
1438          * by userspace). It is possible that some pins are used by the
1439          * BIOS during resume and those are not always locked down so leave
1440          * them alone.
1441          */
1442         if (pd->mux_owner || pd->gpio_owner ||
1443             gpiochip_line_is_irq(&pctrl->chip, pin))
1444                 return true;
1445
1446         return false;
1447 }
1448
1449 int intel_pinctrl_suspend(struct device *dev)
1450 {
1451         struct platform_device *pdev = to_platform_device(dev);
1452         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1453         struct intel_community_context *communities;
1454         struct intel_pad_context *pads;
1455         int i;
1456
1457         pads = pctrl->context.pads;
1458         for (i = 0; i < pctrl->soc->npins; i++) {
1459                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1460                 void __iomem *padcfg;
1461                 u32 val;
1462
1463                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1464                         continue;
1465
1466                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1467                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1468                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1469                 pads[i].padcfg1 = val;
1470
1471                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1472                 if (padcfg)
1473                         pads[i].padcfg2 = readl(padcfg);
1474         }
1475
1476         communities = pctrl->context.communities;
1477         for (i = 0; i < pctrl->ncommunities; i++) {
1478                 struct intel_community *community = &pctrl->communities[i];
1479                 void __iomem *base;
1480                 unsigned gpp;
1481
1482                 base = community->regs + community->ie_offset;
1483                 for (gpp = 0; gpp < community->ngpps; gpp++)
1484                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1485         }
1486
1487         return 0;
1488 }
1489 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1490
1491 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1492 {
1493         size_t i;
1494
1495         for (i = 0; i < pctrl->ncommunities; i++) {
1496                 const struct intel_community *community;
1497                 void __iomem *base;
1498                 unsigned gpp;
1499
1500                 community = &pctrl->communities[i];
1501                 base = community->regs;
1502
1503                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1504                         /* Mask and clear all interrupts */
1505                         writel(0, base + community->ie_offset + gpp * 4);
1506                         writel(0xffff, base + community->is_offset + gpp * 4);
1507                 }
1508         }
1509 }
1510
1511 int intel_pinctrl_resume(struct device *dev)
1512 {
1513         struct platform_device *pdev = to_platform_device(dev);
1514         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1515         const struct intel_community_context *communities;
1516         const struct intel_pad_context *pads;
1517         int i;
1518
1519         /* Mask all interrupts */
1520         intel_gpio_irq_init(pctrl);
1521
1522         pads = pctrl->context.pads;
1523         for (i = 0; i < pctrl->soc->npins; i++) {
1524                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1525                 void __iomem *padcfg;
1526                 u32 val;
1527
1528                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1529                         continue;
1530
1531                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1532                 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1533                 if (val != pads[i].padcfg0) {
1534                         writel(pads[i].padcfg0, padcfg);
1535                         dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1536                                 desc->number, readl(padcfg));
1537                 }
1538
1539                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1540                 val = readl(padcfg);
1541                 if (val != pads[i].padcfg1) {
1542                         writel(pads[i].padcfg1, padcfg);
1543                         dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1544                                 desc->number, readl(padcfg));
1545                 }
1546
1547                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1548                 if (padcfg) {
1549                         val = readl(padcfg);
1550                         if (val != pads[i].padcfg2) {
1551                                 writel(pads[i].padcfg2, padcfg);
1552                                 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1553                                         desc->number, readl(padcfg));
1554                         }
1555                 }
1556         }
1557
1558         communities = pctrl->context.communities;
1559         for (i = 0; i < pctrl->ncommunities; i++) {
1560                 struct intel_community *community = &pctrl->communities[i];
1561                 void __iomem *base;
1562                 unsigned gpp;
1563
1564                 base = community->regs + community->ie_offset;
1565                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1566                         writel(communities[i].intmask[gpp], base + gpp * 4);
1567                         dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1568                                 readl(base + gpp * 4));
1569                 }
1570         }
1571
1572         return 0;
1573 }
1574 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1575 #endif
1576
1577 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1578 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1579 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1580 MODULE_LICENSE("GPL v2");