drivers/pinctrl/pinctrl-amd.c

   1 /*
   2  * GPIO driver for AMD
   3  *
   4  * Copyright (c) 2014,2015 AMD Corporation.
   5  * Authors: Ken Xue <Ken.Xue@amd.com>
   6  *      Wu, Jeff <Jeff.Wu@amd.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/err.h>
  14 #include <linux/bug.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/compiler.h>
  19 #include <linux/types.h>
  20 #include <linux/errno.h>
  21 #include <linux/log2.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio.h>
  24 #include <linux/slab.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/mutex.h>
  27 #include <linux/acpi.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/list.h>
  31 #include <linux/bitops.h>
  32 #include <linux/pinctrl/pinconf.h>
  33 #include <linux/pinctrl/pinconf-generic.h>
  34
  35 #include "pinctrl-utils.h"
  36 #include "pinctrl-amd.h"
  37
  38 static inline struct amd_gpio *to_amd_gpio(struct gpio_chip *gc)
  39 {
  40         return container_of(gc, struct amd_gpio, gc);
  41 }
  42
  43 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  44 {
  45         unsigned long flags;
  46         u32 pin_reg;
  47         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
  48
  49         spin_lock_irqsave(&gpio_dev->lock, flags);
  50         pin_reg = readl(gpio_dev->base + offset * 4);
  51         pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
  52         writel(pin_reg, gpio_dev->base + offset * 4);
  53         spin_unlock_irqrestore(&gpio_dev->lock, flags);
  54
  55         return 0;
  56 }
  57
  58 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
  59                 int value)
  60 {
  61         u32 pin_reg;
  62         unsigned long flags;
  63         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
  64
  65         spin_lock_irqsave(&gpio_dev->lock, flags);
  66         pin_reg = readl(gpio_dev->base + offset * 4);
  67         pin_reg |= BIT(OUTPUT_ENABLE_OFF);
  68         if (value)
  69                 pin_reg |= BIT(OUTPUT_VALUE_OFF);
  70         else
  71                 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
  72         writel(pin_reg, gpio_dev->base + offset * 4);
  73         spin_unlock_irqrestore(&gpio_dev->lock, flags);
  74
  75         return 0;
  76 }
  77
  78 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
  79 {
  80         u32 pin_reg;
  81         unsigned long flags;
  82         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
  83
  84         spin_lock_irqsave(&gpio_dev->lock, flags);
  85         pin_reg = readl(gpio_dev->base + offset * 4);
  86         spin_unlock_irqrestore(&gpio_dev->lock, flags);
  87
  88         return !!(pin_reg & BIT(PIN_STS_OFF));
  89 }
  90
  91 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
  92 {
  93         u32 pin_reg;
  94         unsigned long flags;
  95         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
  96
  97         spin_lock_irqsave(&gpio_dev->lock, flags);
  98         pin_reg = readl(gpio_dev->base + offset * 4);
  99         if (value)
 100                 pin_reg |= BIT(OUTPUT_VALUE_OFF);
 101         else
 102                 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
 103         writel(pin_reg, gpio_dev->base + offset * 4);
 104         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 105 }
 106
 107 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
 108                 unsigned debounce)
 109 {
 110         u32 time;
 111         u32 pin_reg;
 112         int ret = 0;
 113         unsigned long flags;
 114         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 115
 116         spin_lock_irqsave(&gpio_dev->lock, flags);
 117         pin_reg = readl(gpio_dev->base + offset * 4);
 118
 119         if (debounce) {
 120                 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
 121                 pin_reg &= ~DB_TMR_OUT_MASK;
 122                 /*
 123                 Debounce        Debounce        Timer   Max
 124                 TmrLarge        TmrOutUnit      Unit    Debounce
 125                                                         Time
 126                 0       0       61 usec (2 RtcClk)      976 usec
 127                 0       1       244 usec (8 RtcClk)     3.9 msec
 128                 1       0       15.6 msec (512 RtcClk)  250 msec
 129                 1       1       62.5 msec (2048 RtcClk) 1 sec
 130                 */
 131
 132                 if (debounce < 61) {
 133                         pin_reg |= 1;
 134                         pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 135                         pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 136                 } else if (debounce < 976) {
 137                         time = debounce / 61;
 138                         pin_reg |= time & DB_TMR_OUT_MASK;
 139                         pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 140                         pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 141                 } else if (debounce < 3900) {
 142                         time = debounce / 244;
 143                         pin_reg |= time & DB_TMR_OUT_MASK;
 144                         pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
 145                         pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 146                 } else if (debounce < 250000) {
 147                         time = debounce / 15625;
 148                         pin_reg |= time & DB_TMR_OUT_MASK;
 149                         pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 150                         pin_reg |= BIT(DB_TMR_LARGE_OFF);
 151                 } else if (debounce < 1000000) {
 152                         time = debounce / 62500;
 153                         pin_reg |= time & DB_TMR_OUT_MASK;
 154                         pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
 155                         pin_reg |= BIT(DB_TMR_LARGE_OFF);
 156                 } else {
 157                         pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
 158                         ret = -EINVAL;
 159                 }
 160         } else {
 161                 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 162                 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 163                 pin_reg &= ~DB_TMR_OUT_MASK;
 164                 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
 165         }
 166         writel(pin_reg, gpio_dev->base + offset * 4);
 167         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 168
 169         return ret;
 170 }
 171
 172 #ifdef CONFIG_DEBUG_FS
 173 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
 174 {
 175         u32 pin_reg;
 176         unsigned long flags;
 177         unsigned int bank, i, pin_num;
 178         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 179
 180         char *level_trig;
 181         char *active_level;
 182         char *interrupt_enable;
 183         char *interrupt_mask;
 184         char *wake_cntrl0;
 185         char *wake_cntrl1;
 186         char *wake_cntrl2;
 187         char *pin_sts;
 188         char *pull_up_sel;
 189         char *pull_up_enable;
 190         char *pull_down_enable;
 191         char *output_value;
 192         char *output_enable;
 193
 194         for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) {
 195                 seq_printf(s, "GPIO bank%d\t", bank);
 196
 197                 switch (bank) {
 198                 case 0:
 199                         i = 0;
 200                         pin_num = AMD_GPIO_PINS_BANK0;
 201                         break;
 202                 case 1:
 203                         i = 64;
 204                         pin_num = AMD_GPIO_PINS_BANK1 + i;
 205                         break;
 206                 case 2:
 207                         i = 128;
 208                         pin_num = AMD_GPIO_PINS_BANK2 + i;
 209                         break;
 210                 }
 211
 212                 for (; i < pin_num; i++) {
 213                         seq_printf(s, "pin%d\t", i);
 214                         spin_lock_irqsave(&gpio_dev->lock, flags);
 215                         pin_reg = readl(gpio_dev->base + i * 4);
 216                         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 217
 218                         if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
 219                                 interrupt_enable = "interrupt is enabled|";
 220
 221                                 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
 222                                 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
 223                                         active_level = "Active low|";
 224                                 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
 225                                 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
 226                                         active_level = "Active high|";
 227                                 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
 228                                         && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
 229                                         active_level = "Active on both|";
 230                                 else
 231                                         active_level = "Unknow Active level|";
 232
 233                                 if (pin_reg & BIT(LEVEL_TRIG_OFF))
 234                                         level_trig = "Level trigger|";
 235                                 else
 236                                         level_trig = "Edge trigger|";
 237
 238                         } else {
 239                                 interrupt_enable =
 240                                         "interrupt is disabled|";
 241                                 active_level = " ";
 242                                 level_trig = " ";
 243                         }
 244
 245                         if (pin_reg & BIT(INTERRUPT_MASK_OFF))
 246                                 interrupt_mask =
 247                                         "interrupt is unmasked|";
 248                         else
 249                                 interrupt_mask =
 250                                         "interrupt is masked|";
 251
 252                         if (pin_reg & BIT(WAKE_CNTRL_OFF))
 253                                 wake_cntrl0 = "enable wakeup in S0i3 state|";
 254                         else
 255                                 wake_cntrl0 = "disable wakeup in S0i3 state|";
 256
 257                         if (pin_reg & BIT(WAKE_CNTRL_OFF))
 258                                 wake_cntrl1 = "enable wakeup in S3 state|";
 259                         else
 260                                 wake_cntrl1 = "disable wakeup in S3 state|";
 261
 262                         if (pin_reg & BIT(WAKE_CNTRL_OFF))
 263                                 wake_cntrl2 = "enable wakeup in S4/S5 state|";
 264                         else
 265                                 wake_cntrl2 = "disable wakeup in S4/S5 state|";
 266
 267                         if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
 268                                 pull_up_enable = "pull-up is enabled|";
 269                                 if (pin_reg & BIT(PULL_UP_SEL_OFF))
 270                                         pull_up_sel = "8k pull-up|";
 271                                 else
 272                                         pull_up_sel = "4k pull-up|";
 273                         } else {
 274                                 pull_up_enable = "pull-up is disabled|";
 275                                 pull_up_sel = " ";
 276                         }
 277
 278                         if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
 279                                 pull_down_enable = "pull-down is enabled|";
 280                         else
 281                                 pull_down_enable = "Pull-down is disabled|";
 282
 283                         if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
 284                                 pin_sts = " ";
 285                                 output_enable = "output is enabled|";
 286                                 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
 287                                         output_value = "output is high|";
 288                                 else
 289                                         output_value = "output is low|";
 290                         } else {
 291                                 output_enable = "output is disabled|";
 292                                 output_value = " ";
 293
 294                                 if (pin_reg & BIT(PIN_STS_OFF))
 295                                         pin_sts = "input is high|";
 296                                 else
 297                                         pin_sts = "input is low|";
 298                         }
 299
 300                         seq_printf(s, "%s %s %s %s %s %s\n"
 301                                 " %s %s %s %s %s %s %s 0x%x\n",
 302                                 level_trig, active_level, interrupt_enable,
 303                                 interrupt_mask, wake_cntrl0, wake_cntrl1,
 304                                 wake_cntrl2, pin_sts, pull_up_sel,
 305                                 pull_up_enable, pull_down_enable,
 306                                 output_value, output_enable, pin_reg);
 307                 }
 308         }
 309 }
 310 #else
 311 #define amd_gpio_dbg_show NULL
 312 #endif
 313
 314 static void amd_gpio_irq_enable(struct irq_data *d)
 315 {
 316         u32 pin_reg;
 317         unsigned long flags;
 318         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 319         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 320
 321         spin_lock_irqsave(&gpio_dev->lock, flags);
 322         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 323         pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
 324         pin_reg |= BIT(INTERRUPT_MASK_OFF);
 325         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 326         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 327 }
 328
 329 static void amd_gpio_irq_disable(struct irq_data *d)
 330 {
 331         u32 pin_reg;
 332         unsigned long flags;
 333         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 334         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 335
 336         spin_lock_irqsave(&gpio_dev->lock, flags);
 337         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 338         pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
 339         pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
 340         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 341         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 342 }
 343
 344 static void amd_gpio_irq_mask(struct irq_data *d)
 345 {
 346         u32 pin_reg;
 347         unsigned long flags;
 348         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 349         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 350
 351         spin_lock_irqsave(&gpio_dev->lock, flags);
 352         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 353         pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
 354         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 355         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 356 }
 357
 358 static void amd_gpio_irq_unmask(struct irq_data *d)
 359 {
 360         u32 pin_reg;
 361         unsigned long flags;
 362         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 363         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 364
 365         spin_lock_irqsave(&gpio_dev->lock, flags);
 366         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 367         pin_reg |= BIT(INTERRUPT_MASK_OFF);
 368         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 369         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 370 }
 371
 372 static void amd_gpio_irq_eoi(struct irq_data *d)
 373 {
 374         u32 reg;
 375         unsigned long flags;
 376         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 377         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 378
 379         spin_lock_irqsave(&gpio_dev->lock, flags);
 380         reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
 381         reg |= EOI_MASK;
 382         writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
 383         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 384 }
 385
 386 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 387 {
 388         int ret = 0;
 389         u32 pin_reg;
 390         unsigned long flags;
 391         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 392         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 393
 394         spin_lock_irqsave(&gpio_dev->lock, flags);
 395         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 396
 397         switch (type & IRQ_TYPE_SENSE_MASK) {
 398         case IRQ_TYPE_EDGE_RISING:
 399                 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
 400                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 401                 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
 402                 irq_set_handler_locked(d, handle_edge_irq);
 403                 break;
 404
 405         case IRQ_TYPE_EDGE_FALLING:
 406                 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
 407                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 408                 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
 409                 irq_set_handler_locked(d, handle_edge_irq);
 410                 break;
 411
 412         case IRQ_TYPE_EDGE_BOTH:
 413                 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
 414                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 415                 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
 416                 irq_set_handler_locked(d, handle_edge_irq);
 417                 break;
 418
 419         case IRQ_TYPE_LEVEL_HIGH:
 420                 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
 421                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 422                 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
 423                 irq_set_handler_locked(d, handle_level_irq);
 424                 break;
 425
 426         case IRQ_TYPE_LEVEL_LOW:
 427                 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
 428                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 429                 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
 430                 irq_set_handler_locked(d, handle_level_irq);
 431                 break;
 432
 433         case IRQ_TYPE_NONE:
 434                 break;
 435
 436         default:
 437                 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
 438                 ret = -EINVAL;
 439         }
 440
 441         pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
 442         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 443         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 444
 445         return ret;
 446 }
 447
 448 static void amd_irq_ack(struct irq_data *d)
 449 {
 450         /*
 451          * based on HW design,there is no need to ack HW
 452          * before handle current irq. But this routine is
 453          * necessary for handle_edge_irq
 454         */
 455 }
 456
 457 static struct irq_chip amd_gpio_irqchip = {
 458         .name         = "amd_gpio",
 459         .irq_ack      = amd_irq_ack,
 460         .irq_enable   = amd_gpio_irq_enable,
 461         .irq_disable  = amd_gpio_irq_disable,
 462         .irq_mask     = amd_gpio_irq_mask,
 463         .irq_unmask   = amd_gpio_irq_unmask,
 464         .irq_eoi      = amd_gpio_irq_eoi,
 465         .irq_set_type = amd_gpio_irq_set_type,
 466 };
 467
 468 static void amd_gpio_irq_handler(struct irq_desc *desc)
 469 {
 470         u32 i;
 471         u32 off;
 472         u32 reg;
 473         u32 pin_reg;
 474         u64 reg64;
 475         int handled = 0;
 476         unsigned int irq;
 477         unsigned long flags;
 478         struct irq_chip *chip = irq_desc_get_chip(desc);
 479         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 480         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 481
 482         chained_irq_enter(chip, desc);
 483         /*enable GPIO interrupt again*/
 484         spin_lock_irqsave(&gpio_dev->lock, flags);
 485         reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
 486         reg64 = reg;
 487         reg64 = reg64 << 32;
 488
 489         reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
 490         reg64 |= reg;
 491         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 492
 493         /*
 494          * first 46 bits indicates interrupt status.
 495          * one bit represents four interrupt sources.
 496         */
 497         for (off = 0; off < 46 ; off++) {
 498                 if (reg64 & BIT(off)) {
 499                         for (i = 0; i < 4; i++) {
 500                                 pin_reg = readl(gpio_dev->base +
 501                                                 (off * 4 + i) * 4);
 502                                 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
 503                                         (pin_reg & BIT(WAKE_STS_OFF))) {
 504                                         irq = irq_find_mapping(gc->irqdomain,
 505                                                                 off * 4 + i);
 506                                         generic_handle_irq(irq);
 507                                         writel(pin_reg,
 508                                                 gpio_dev->base
 509                                                 + (off * 4 + i) * 4);
 510                                         handled++;
 511                                 }
 512                         }
 513                 }
 514         }
 515
 516         if (handled == 0)
 517                 handle_bad_irq(desc);
 518
 519         spin_lock_irqsave(&gpio_dev->lock, flags);
 520         reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
 521         reg |= EOI_MASK;
 522         writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
 523         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 524
 525         chained_irq_exit(chip, desc);
 526 }
 527
 528 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
 529 {
 530         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 531
 532         return gpio_dev->ngroups;
 533 }
 534
 535 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
 536                                       unsigned group)
 537 {
 538         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 539
 540         return gpio_dev->groups[group].name;
 541 }
 542
 543 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
 544                               unsigned group,
 545                               const unsigned **pins,
 546                               unsigned *num_pins)
 547 {
 548         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 549
 550         *pins = gpio_dev->groups[group].pins;
 551         *num_pins = gpio_dev->groups[group].npins;
 552         return 0;
 553 }
 554
 555 static const struct pinctrl_ops amd_pinctrl_ops = {
 556         .get_groups_count       = amd_get_groups_count,
 557         .get_group_name         = amd_get_group_name,
 558         .get_group_pins         = amd_get_group_pins,
 559 #ifdef CONFIG_OF
 560         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 561         .dt_free_map            = pinctrl_utils_dt_free_map,
 562 #endif
 563 };
 564
 565 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
 566                           unsigned int pin,
 567                           unsigned long *config)
 568 {
 569         u32 pin_reg;
 570         unsigned arg;
 571         unsigned long flags;
 572         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 573         enum pin_config_param param = pinconf_to_config_param(*config);
 574
 575         spin_lock_irqsave(&gpio_dev->lock, flags);
 576         pin_reg = readl(gpio_dev->base + pin*4);
 577         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 578         switch (param) {
 579         case PIN_CONFIG_INPUT_DEBOUNCE:
 580                 arg = pin_reg & DB_TMR_OUT_MASK;
 581                 break;
 582
 583         case PIN_CONFIG_BIAS_PULL_DOWN:
 584                 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
 585                 break;
 586
 587         case PIN_CONFIG_BIAS_PULL_UP:
 588                 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
 589                 break;
 590
 591         case PIN_CONFIG_DRIVE_STRENGTH:
 592                 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
 593                 break;
 594
 595         default:
 596                 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
 597                         param);
 598                 return -ENOTSUPP;
 599         }
 600
 601         *config = pinconf_to_config_packed(param, arg);
 602
 603         return 0;
 604 }
 605
 606 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 607                                 unsigned long *configs, unsigned num_configs)
 608 {
 609         int i;
 610         u32 arg;
 611         int ret = 0;
 612         u32 pin_reg;
 613         unsigned long flags;
 614         enum pin_config_param param;
 615         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 616
 617         spin_lock_irqsave(&gpio_dev->lock, flags);
 618         for (i = 0; i < num_configs; i++) {
 619                 param = pinconf_to_config_param(configs[i]);
 620                 arg = pinconf_to_config_argument(configs[i]);
 621                 pin_reg = readl(gpio_dev->base + pin*4);
 622
 623                 switch (param) {
 624                 case PIN_CONFIG_INPUT_DEBOUNCE:
 625                         pin_reg &= ~DB_TMR_OUT_MASK;
 626                         pin_reg |= arg & DB_TMR_OUT_MASK;
 627                         break;
 628
 629                 case PIN_CONFIG_BIAS_PULL_DOWN:
 630                         pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
 631                         pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
 632                         break;
 633
 634                 case PIN_CONFIG_BIAS_PULL_UP:
 635                         pin_reg &= ~BIT(PULL_UP_SEL_OFF);
 636                         pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
 637                         pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
 638                         pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
 639                         break;
 640
 641                 case PIN_CONFIG_DRIVE_STRENGTH:
 642                         pin_reg &= ~(DRV_STRENGTH_SEL_MASK
 643                                         << DRV_STRENGTH_SEL_OFF);
 644                         pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
 645                                         << DRV_STRENGTH_SEL_OFF;
 646                         break;
 647
 648                 default:
 649                         dev_err(&gpio_dev->pdev->dev,
 650                                 "Invalid config param %04x\n", param);
 651                         ret = -ENOTSUPP;
 652                 }
 653
 654                 writel(pin_reg, gpio_dev->base + pin*4);
 655         }
 656         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 657
 658         return ret;
 659 }
 660
 661 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
 662                                 unsigned int group,
 663                                 unsigned long *config)
 664 {
 665         const unsigned *pins;
 666         unsigned npins;
 667         int ret;
 668
 669         ret = amd_get_group_pins(pctldev, group, &pins, &npins);
 670         if (ret)
 671                 return ret;
 672
 673         if (amd_pinconf_get(pctldev, pins[0], config))
 674                         return -ENOTSUPP;
 675
 676         return 0;
 677 }
 678
 679 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
 680                                 unsigned group, unsigned long *configs,
 681                                 unsigned num_configs)
 682 {
 683         const unsigned *pins;
 684         unsigned npins;
 685         int i, ret;
 686
 687         ret = amd_get_group_pins(pctldev, group, &pins, &npins);
 688         if (ret)
 689                 return ret;
 690         for (i = 0; i < npins; i++) {
 691                 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
 692                         return -ENOTSUPP;
 693         }
 694         return 0;
 695 }
 696
 697 static const struct pinconf_ops amd_pinconf_ops = {
 698         .pin_config_get         = amd_pinconf_get,
 699         .pin_config_set         = amd_pinconf_set,
 700         .pin_config_group_get = amd_pinconf_group_get,
 701         .pin_config_group_set = amd_pinconf_group_set,
 702 };
 703
 704 static struct pinctrl_desc amd_pinctrl_desc = {
 705         .pins   = kerncz_pins,
 706         .npins = ARRAY_SIZE(kerncz_pins),
 707         .pctlops = &amd_pinctrl_ops,
 708         .confops = &amd_pinconf_ops,
 709         .owner = THIS_MODULE,
 710 };
 711
 712 static int amd_gpio_probe(struct platform_device *pdev)
 713 {
 714         int ret = 0;
 715         int irq_base;
 716         struct resource *res;
 717         struct amd_gpio *gpio_dev;
 718
 719         gpio_dev = devm_kzalloc(&pdev->dev,
 720                                 sizeof(struct amd_gpio), GFP_KERNEL);
 721         if (!gpio_dev)
 722                 return -ENOMEM;
 723
 724         spin_lock_init(&gpio_dev->lock);
 725
 726         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 727         if (!res) {
 728                 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
 729                 return -EINVAL;
 730         }
 731
 732         gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
 733                                                 resource_size(res));
 734         if (IS_ERR(gpio_dev->base))
 735                 return PTR_ERR(gpio_dev->base);
 736
 737         irq_base = platform_get_irq(pdev, 0);
 738         if (irq_base < 0) {
 739                 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
 740                 return -EINVAL;
 741         }
 742
 743         gpio_dev->pdev = pdev;
 744         gpio_dev->gc.direction_input    = amd_gpio_direction_input;
 745         gpio_dev->gc.direction_output   = amd_gpio_direction_output;
 746         gpio_dev->gc.get                        = amd_gpio_get_value;
 747         gpio_dev->gc.set                        = amd_gpio_set_value;
 748         gpio_dev->gc.set_debounce       = amd_gpio_set_debounce;
 749         gpio_dev->gc.dbg_show           = amd_gpio_dbg_show;
 750
 751         gpio_dev->gc.base                       = 0;
 752         gpio_dev->gc.label                      = pdev->name;
 753         gpio_dev->gc.owner                      = THIS_MODULE;
 754         gpio_dev->gc.dev                        = &pdev->dev;
 755         gpio_dev->gc.ngpio                      = TOTAL_NUMBER_OF_PINS;
 756 #if defined(CONFIG_OF_GPIO)
 757         gpio_dev->gc.of_node                    = pdev->dev.of_node;
 758 #endif
 759
 760         gpio_dev->groups = kerncz_groups;
 761         gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
 762
 763         amd_pinctrl_desc.name = dev_name(&pdev->dev);
 764         gpio_dev->pctrl = pinctrl_register(&amd_pinctrl_desc,
 765                                         &pdev->dev, gpio_dev);
 766         if (IS_ERR(gpio_dev->pctrl)) {
 767                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 768                 return PTR_ERR(gpio_dev->pctrl);
 769         }
 770
 771         ret = gpiochip_add(&gpio_dev->gc);
 772         if (ret)
 773                 goto out1;
 774
 775         ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
 776                                 0, 0, TOTAL_NUMBER_OF_PINS);
 777         if (ret) {
 778                 dev_err(&pdev->dev, "Failed to add pin range\n");
 779                 goto out2;
 780         }
 781
 782         ret = gpiochip_irqchip_add(&gpio_dev->gc,
 783                                 &amd_gpio_irqchip,
 784                                 0,
 785                                 handle_simple_irq,
 786                                 IRQ_TYPE_NONE);
 787         if (ret) {
 788                 dev_err(&pdev->dev, "could not add irqchip\n");
 789                 ret = -ENODEV;
 790                 goto out2;
 791         }
 792
 793         gpiochip_set_chained_irqchip(&gpio_dev->gc,
 794                                  &amd_gpio_irqchip,
 795                                  irq_base,
 796                                  amd_gpio_irq_handler);
 797
 798         platform_set_drvdata(pdev, gpio_dev);
 799
 800         dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
 801         return ret;
 802
 803 out2:
 804         gpiochip_remove(&gpio_dev->gc);
 805
 806 out1:
 807         pinctrl_unregister(gpio_dev->pctrl);
 808         return ret;
 809 }
 810
 811 static int amd_gpio_remove(struct platform_device *pdev)
 812 {
 813         struct amd_gpio *gpio_dev;
 814
 815         gpio_dev = platform_get_drvdata(pdev);
 816
 817         gpiochip_remove(&gpio_dev->gc);
 818         pinctrl_unregister(gpio_dev->pctrl);
 819
 820         return 0;
 821 }
 822
 823 static const struct acpi_device_id amd_gpio_acpi_match[] = {
 824         { "AMD0030", 0 },
 825         { },
 826 };
 827 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
 828
 829 static struct platform_driver amd_gpio_driver = {
 830         .driver         = {
 831                 .name   = "amd_gpio",
 832                 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
 833         },
 834         .probe          = amd_gpio_probe,
 835         .remove         = amd_gpio_remove,
 836 };
 837
 838 module_platform_driver(amd_gpio_driver);
 839
 840 MODULE_LICENSE("GPL v2");
 841 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
 842 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");