drivers/pinctrl/pinctrl-gemini.c

   1 /*
   2  * Driver for the Gemini pin controller
   3  *
   4  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
   5  *
   6  * This is a group-only pin controller.
   7  */
   8 #include <linux/err.h>
   9 #include <linux/init.h>
  10 #include <linux/io.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/of.h>
  13 #include <linux/pinctrl/machine.h>
  14 #include <linux/pinctrl/pinctrl.h>
  15 #include <linux/pinctrl/pinmux.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/slab.h>
  18 #include <linux/regmap.h>
  19
  20 #include "pinctrl-utils.h"
  21
  22 #define DRIVER_NAME "pinctrl-gemini"
  23
  24 /**
  25  * @dev: a pointer back to containing device
  26  * @virtbase: the offset to the controller in virtual memory
  27  * @map: regmap to access registers
  28  * @is_3512: whether the SoC/package is the 3512 variant
  29  * @is_3516: whether the SoC/package is the 3516 variant
  30  * @flash_pin: whether the flash pin (extended pins for parallel
  31  * flash) is set
  32  */
  33 struct gemini_pmx {
  34         struct device *dev;
  35         struct pinctrl_dev *pctl;
  36         struct regmap *map;
  37         bool is_3512;
  38         bool is_3516;
  39         bool flash_pin;
  40 };
  41
  42 /**
  43  * struct gemini_pin_group - describes a Gemini pin group
  44  * @name: the name of this specific pin group
  45  * @pins: an array of discrete physical pins used in this group, taken
  46  *      from the driver-local pin enumeration space
  47  * @num_pins: the number of pins in this group array, i.e. the number of
  48  *      elements in .pins so we can iterate over that array
  49  * @mask: bits to clear to enable this when doing pin muxing
  50  * @value: bits to set to enable this when doing pin muxing
  51  */
  52 struct gemini_pin_group {
  53         const char *name;
  54         const unsigned int *pins;
  55         const unsigned int num_pins;
  56         u32 mask;
  57         u32 value;
  58 };
  59
  60 /*
  61  * Global Miscellaneous Control Register
  62  * This register controls all Gemini pad/pin multiplexing
  63  *
  64  * It is a tricky register though:
  65  * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
  66  *   be brought back online, so it means permanent disablement of the
  67  *   corresponding pads.
  68  * - For the bits named *_DISABLE, once you enable something, it cannot be
  69  *   DISABLED again. So you select a flash configuration once, and then
  70  *   you are stuck with it.
  71  */
  72 #define GLOBAL_WORD_ID          0x00
  73 #define GLOBAL_STATUS           0x04
  74 #define GLOBAL_STATUS_FLPIN     BIT(20)
  75 #define GLOBAL_MISC_CTRL        0x30
  76 #define TVC_CLK_PAD_ENABLE      BIT(20)
  77 #define PCI_CLK_PAD_ENABLE      BIT(17)
  78 #define LPC_CLK_PAD_ENABLE      BIT(16)
  79 #define TVC_PADS_ENABLE         BIT(9)
  80 #define SSP_PADS_ENABLE         BIT(8)
  81 #define LCD_PADS_ENABLE         BIT(7)
  82 #define LPC_PADS_ENABLE         BIT(6)
  83 #define PCI_PADS_ENABLE         BIT(5)
  84 #define IDE_PADS_ENABLE         BIT(4)
  85 #define DRAM_PADS_POWERDOWN     BIT(3)
  86 #define NAND_PADS_DISABLE       BIT(2)
  87 #define PFLASH_PADS_DISABLE     BIT(1)
  88 #define SFLASH_PADS_DISABLE     BIT(0)
  89 #define PADS_MASK               (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20))
  90 #define PADS_MAXBIT             20
  91
  92 /* Ordered by bit index */
  93 static const char * const gemini_padgroups[] = {
  94         "serial flash",
  95         "parallel flash",
  96         "NAND flash",
  97         "DRAM",
  98         "IDE",
  99         "PCI",
 100         "LPC",
 101         "LCD",
 102         "SSP",
 103         "TVC",
 104         NULL, NULL, NULL, NULL, NULL, NULL,
 105         "LPC CLK",
 106         "PCI CLK",
 107         NULL, NULL,
 108         "TVC CLK",
 109 };
 110
 111 static const struct pinctrl_pin_desc gemini_3512_pins[] = {
 112         /* Row A */
 113         PINCTRL_PIN(0, "A1 VREF CTRL"),
 114         PINCTRL_PIN(1, "A2 VCC2IO CTRL"),
 115         PINCTRL_PIN(2, "A3 DRAM CK"),
 116         PINCTRL_PIN(3, "A4 DRAM CK N"),
 117         PINCTRL_PIN(4, "A5 DRAM A5"),
 118         PINCTRL_PIN(5, "A6 DRAM CKE"),
 119         PINCTRL_PIN(6, "A7 DRAM DQ11"),
 120         PINCTRL_PIN(7, "A8 DRAM DQ0"),
 121         PINCTRL_PIN(8, "A9 DRAM DQ5"),
 122         PINCTRL_PIN(9, "A10 DRAM DQ6"),
 123         PINCTRL_PIN(10, "A11 DRAM DRAM VREF"),
 124         PINCTRL_PIN(11, "A12 DRAM BA1"),
 125         PINCTRL_PIN(12, "A13 DRAM A2"),
 126         PINCTRL_PIN(13, "A14 PCI GNT1 N"),
 127         PINCTRL_PIN(14, "A15 PCI REQ9 N"),
 128         PINCTRL_PIN(15, "A16 PCI REQ2 N"),
 129         PINCTRL_PIN(16, "A17 PCI REQ3 N"),
 130         PINCTRL_PIN(17, "A18 PCI AD31"),
 131         /* Row B */
 132         PINCTRL_PIN(18, "B1 VCCK CTRL"),
 133         PINCTRL_PIN(19, "B2 PWR EN"),
 134         PINCTRL_PIN(20, "B3 RTC CLKI"),
 135         PINCTRL_PIN(21, "B4 DRAM A4"),
 136         PINCTRL_PIN(22, "B5 DRAM A6"),
 137         PINCTRL_PIN(23, "B6 DRAM A12"),
 138         PINCTRL_PIN(24, "B7 DRAM DQS1"),
 139         PINCTRL_PIN(25, "B8 DRAM DQ15"),
 140         PINCTRL_PIN(26, "B9 DRAM DQ4"),
 141         PINCTRL_PIN(27, "B10 DRAM DQS0"),
 142         PINCTRL_PIN(28, "B11 DRAM WE N"),
 143         PINCTRL_PIN(29, "B12 DRAM A10"),
 144         PINCTRL_PIN(30, "B13 DRAM A3"),
 145         PINCTRL_PIN(31, "B14 PCI GNT0 N"),
 146         PINCTRL_PIN(32, "B15 PCI GNT3 N"),
 147         PINCTRL_PIN(33, "B16 PCI REQ1 N"),
 148         PINCTRL_PIN(34, "B17 PCI AD30"),
 149         PINCTRL_PIN(35, "B18 PCI AD29"),
 150         /* Row C */
 151         PINCTRL_PIN(36, "C1 CIR RST N"), /* REALLY? CIR is not in 3512... */
 152         PINCTRL_PIN(37, "C2 XTALI"),
 153         PINCTRL_PIN(38, "C3 PWR BTN"),
 154         PINCTRL_PIN(39, "C4 RTC CLKO"),
 155         PINCTRL_PIN(40, "C5 DRAM A7"),
 156         PINCTRL_PIN(41, "C6 DRAM A11"),
 157         PINCTRL_PIN(42, "C7 DRAM DQ10"),
 158         PINCTRL_PIN(43, "C8 DRAM DQ14"),
 159         PINCTRL_PIN(44, "C9 DRAM DQ3"),
 160         PINCTRL_PIN(45, "C10 DRAM DQ7"),
 161         PINCTRL_PIN(46, "C11 DRAM CAS N"),
 162         PINCTRL_PIN(47, "C12 DRAM A0"),
 163         PINCTRL_PIN(48, "C13 PCI INT0 N"),
 164         PINCTRL_PIN(49, "C14 EXT RESET N"),
 165         PINCTRL_PIN(50, "C15 PCI GNT2 N"),
 166         PINCTRL_PIN(51, "C16 PCI AD28"),
 167         PINCTRL_PIN(52, "C17 PCI AD27"),
 168         PINCTRL_PIN(53, "C18 PCI AD26"),
 169         /* Row D */
 170         PINCTRL_PIN(54, "D1 AVCCKHA"),
 171         PINCTRL_PIN(55, "D2 AGNDIOHA"),
 172         PINCTRL_PIN(56, "D3 XTALO"),
 173         PINCTRL_PIN(57, "D4 AVCC3IOHA"),
 174         PINCTRL_PIN(58, "D5 DRAM A8"),
 175         PINCTRL_PIN(59, "D6 DRAM A9"),
 176         PINCTRL_PIN(60, "D7 DRAM DQ9"),
 177         PINCTRL_PIN(61, "D8 DRAM DQ13"),
 178         PINCTRL_PIN(62, "D9 DRAM DQ2"),
 179         PINCTRL_PIN(63, "D10 DRAM A13"),
 180         PINCTRL_PIN(64, "D11 DRAM RAS N"),
 181         PINCTRL_PIN(65, "D12 DRAM A1"),
 182         PINCTRL_PIN(66, "D13 PCI INTC N"),
 183         PINCTRL_PIN(67, "D14 PCI CLK"),
 184         PINCTRL_PIN(68, "D15 PCI AD25"),
 185         PINCTRL_PIN(69, "D16 PCI AD24"),
 186         PINCTRL_PIN(70, "D17 PCI CBE3 N"),
 187         PINCTRL_PIN(71, "D18 PCI AD23"),
 188         /* Row E */
 189         PINCTRL_PIN(72, "E1 AVCC3IOHA"),
 190         PINCTRL_PIN(73, "E2 EBG"),
 191         PINCTRL_PIN(74, "E3 AVCC3IOHB"),
 192         PINCTRL_PIN(75, "E4 REXT"),
 193         PINCTRL_PIN(76, "E5 GND"),
 194         PINCTRL_PIN(77, "E6 DRAM DQM1"),
 195         PINCTRL_PIN(78, "E7 DRAM DQ8"),
 196         PINCTRL_PIN(79, "E8 DRAM DQ12"),
 197         PINCTRL_PIN(80, "E9 DRAM DQ1"),
 198         PINCTRL_PIN(81, "E10 DRAM DQM0"),
 199         PINCTRL_PIN(82, "E11 DRAM BA0"),
 200         PINCTRL_PIN(83, "E12 PCI INTA N"),
 201         PINCTRL_PIN(84, "E13 PCI INTB N"),
 202         PINCTRL_PIN(85, "E14 GND"),
 203         PINCTRL_PIN(86, "E15 PCI AD22"),
 204         PINCTRL_PIN(87, "E16 PCI AD21"),
 205         PINCTRL_PIN(88, "E17 PCI AD20"),
 206         PINCTRL_PIN(89, "E18 PCI AD19"),
 207         /* Row F */
 208         PINCTRL_PIN(90, "F1 SATA0 RXDP"),
 209         PINCTRL_PIN(91, "F2 SATA0 RXDN"),
 210         PINCTRL_PIN(92, "F3 AGNDK 0"),
 211         PINCTRL_PIN(93, "F4 AVCC3 S"),
 212         PINCTRL_PIN(94, "F5 AVCCK P"),
 213         PINCTRL_PIN(95, "F6 GND"),
 214         PINCTRL_PIN(96, "F7 VCC2IOHA 2"),
 215         PINCTRL_PIN(97, "F8 VCC2IOHA 2"),
 216         PINCTRL_PIN(98, "F9 V1"),
 217         PINCTRL_PIN(99, "F10 V1"),
 218         PINCTRL_PIN(100, "F11 VCC2IOHA 2"),
 219         PINCTRL_PIN(101, "F12 VCC2IOHA 2"),
 220         PINCTRL_PIN(102, "F13 GND"),
 221         PINCTRL_PIN(103, "F14 PCI AD18"),
 222         PINCTRL_PIN(104, "F15 PCI AD17"),
 223         PINCTRL_PIN(105, "F16 PCI AD16"),
 224         PINCTRL_PIN(106, "F17 PCI CBE2 N"),
 225         PINCTRL_PIN(107, "F18 PCI FRAME N"),
 226         /* Row G */
 227         PINCTRL_PIN(108, "G1 SATA0 TXDP"),
 228         PINCTRL_PIN(109, "G2 SATA0 TXDN"),
 229         PINCTRL_PIN(110, "G3 AGNDK 1"),
 230         PINCTRL_PIN(111, "G4 AVCCK 0"),
 231         PINCTRL_PIN(112, "G5 TEST CLKOUT"),
 232         PINCTRL_PIN(113, "G6 AGND"),
 233         PINCTRL_PIN(114, "G7 GND"),
 234         PINCTRL_PIN(115, "G8 VCC2IOHA 2"),
 235         PINCTRL_PIN(116, "G9 V1"),
 236         PINCTRL_PIN(117, "G10 V1"),
 237         PINCTRL_PIN(118, "G11 VCC2IOHA 2"),
 238         PINCTRL_PIN(119, "G12 GND"),
 239         PINCTRL_PIN(120, "G13 VCC3IOHA"),
 240         PINCTRL_PIN(121, "G14 PCI IRDY N"),
 241         PINCTRL_PIN(122, "G15 PCI TRDY N"),
 242         PINCTRL_PIN(123, "G16 PCI DEVSEL N"),
 243         PINCTRL_PIN(124, "G17 PCI STOP N"),
 244         PINCTRL_PIN(125, "G18 PCI PAR"),
 245         /* Row H */
 246         PINCTRL_PIN(126, "H1 SATA1 TXDP"),
 247         PINCTRL_PIN(127, "H2 SATA1 TXDN"),
 248         PINCTRL_PIN(128, "H3 AGNDK 2"),
 249         PINCTRL_PIN(129, "H4 AVCCK 1"),
 250         PINCTRL_PIN(130, "H5 AVCCK S"),
 251         PINCTRL_PIN(131, "H6 AVCCKHB"),
 252         PINCTRL_PIN(132, "H7 AGND"),
 253         PINCTRL_PIN(133, "H8 GND"),
 254         PINCTRL_PIN(134, "H9 GND"),
 255         PINCTRL_PIN(135, "H10 GND"),
 256         PINCTRL_PIN(136, "H11 GND"),
 257         PINCTRL_PIN(137, "H12 VCC3IOHA"),
 258         PINCTRL_PIN(138, "H13 VCC3IOHA"),
 259         PINCTRL_PIN(139, "H14 PCI CBE1 N"),
 260         PINCTRL_PIN(140, "H15 PCI AD15"),
 261         PINCTRL_PIN(141, "H16 PCI AD14"),
 262         PINCTRL_PIN(142, "H17 PCI AD13"),
 263         PINCTRL_PIN(143, "H18 PCI AD12"),
 264         /* Row J (for some reason I is skipped) */
 265         PINCTRL_PIN(144, "J1 SATA1 RXDP"),
 266         PINCTRL_PIN(145, "J2 SATA1 RXDN"),
 267         PINCTRL_PIN(146, "J3 AGNDK 3"),
 268         PINCTRL_PIN(147, "J4 AVCCK 2"),
 269         PINCTRL_PIN(148, "J5 IDE DA1"),
 270         PINCTRL_PIN(149, "J6 V1"),
 271         PINCTRL_PIN(150, "J7 V1"),
 272         PINCTRL_PIN(151, "J8 GND"),
 273         PINCTRL_PIN(152, "J9 GND"),
 274         PINCTRL_PIN(153, "J10 GND"),
 275         PINCTRL_PIN(154, "J11 GND"),
 276         PINCTRL_PIN(155, "J12 V1"),
 277         PINCTRL_PIN(156, "J13 V1"),
 278         PINCTRL_PIN(157, "J14 PCI AD11"),
 279         PINCTRL_PIN(158, "J15 PCI AD10"),
 280         PINCTRL_PIN(159, "J16 PCI AD9"),
 281         PINCTRL_PIN(160, "J17 PCI AD8"),
 282         PINCTRL_PIN(161, "J18 PCI CBE0 N"),
 283         /* Row K */
 284         PINCTRL_PIN(162, "K1 IDE CS1 N"),
 285         PINCTRL_PIN(163, "K2 IDE CS0 N"),
 286         PINCTRL_PIN(164, "K3 AVCCK 3"),
 287         PINCTRL_PIN(165, "K4 IDE DA2"),
 288         PINCTRL_PIN(166, "K5 IDE DA0"),
 289         PINCTRL_PIN(167, "K6 V1"),
 290         PINCTRL_PIN(168, "K7 V1"),
 291         PINCTRL_PIN(169, "K8 GND"),
 292         PINCTRL_PIN(170, "K9 GND"),
 293         PINCTRL_PIN(171, "K10 GND"),
 294         PINCTRL_PIN(172, "K11 GND"),
 295         PINCTRL_PIN(173, "K12 V1"),
 296         PINCTRL_PIN(174, "K13 V1"),
 297         PINCTRL_PIN(175, "K14 PCI AD3"),
 298         PINCTRL_PIN(176, "K15 PCI AD4"),
 299         PINCTRL_PIN(177, "K16 PCI AD5"),
 300         PINCTRL_PIN(178, "K17 PCI AD6"),
 301         PINCTRL_PIN(179, "K18 PCI AD7"),
 302         /* Row L */
 303         PINCTRL_PIN(180, "L1 IDE INTRQ"),
 304         PINCTRL_PIN(181, "L2 IDE DMACK N"),
 305         PINCTRL_PIN(182, "L3 IDE IORDY"),
 306         PINCTRL_PIN(183, "L4 IDE DIOR N"),
 307         PINCTRL_PIN(184, "L5 IDE DIOW N"),
 308         PINCTRL_PIN(185, "L6 VCC3IOHA"),
 309         PINCTRL_PIN(186, "L7 VCC3IOHA"),
 310         PINCTRL_PIN(187, "L8 GND"),
 311         PINCTRL_PIN(188, "L9 GND"),
 312         PINCTRL_PIN(189, "L10 GND"),
 313         PINCTRL_PIN(190, "L11 GND"),
 314         PINCTRL_PIN(191, "L12 VCC3IOHA"),
 315         PINCTRL_PIN(192, "L13 VCC3IOHA"),
 316         PINCTRL_PIN(193, "L14 GPIO0 30"),
 317         PINCTRL_PIN(194, "L15 GPIO0 31"),
 318         PINCTRL_PIN(195, "L16 PCI AD0"),
 319         PINCTRL_PIN(196, "L17 PCI AD1"),
 320         PINCTRL_PIN(197, "L18 PCI AD2"),
 321         /* Row M */
 322         PINCTRL_PIN(198, "M1 IDE DMARQ"),
 323         PINCTRL_PIN(199, "M2 IDE DD15"),
 324         PINCTRL_PIN(200, "M3 IDE DD0"),
 325         PINCTRL_PIN(201, "M4 IDE DD14"),
 326         PINCTRL_PIN(202, "M5 IDE DD1"),
 327         PINCTRL_PIN(203, "M6 VCC3IOHA"),
 328         PINCTRL_PIN(204, "M7 GND"),
 329         PINCTRL_PIN(205, "M8 VCC2IOHA 1"),
 330         PINCTRL_PIN(206, "M9 V1"),
 331         PINCTRL_PIN(207, "M10 V1"),
 332         PINCTRL_PIN(208, "M11 VCC3IOHA"),
 333         PINCTRL_PIN(209, "M12 GND"),
 334         PINCTRL_PIN(210, "M13 VCC3IOHA"),
 335         PINCTRL_PIN(211, "M14 GPIO0 25"),
 336         PINCTRL_PIN(212, "M15 GPIO0 26"),
 337         PINCTRL_PIN(213, "M16 GPIO0 27"),
 338         PINCTRL_PIN(214, "M17 GPIO0 28"),
 339         PINCTRL_PIN(215, "M18 GPIO0 29"),
 340         /* Row N */
 341         PINCTRL_PIN(216, "N1 IDE DD13"),
 342         PINCTRL_PIN(217, "N2 IDE DD2"),
 343         PINCTRL_PIN(218, "N3 IDE DD12"),
 344         PINCTRL_PIN(219, "N4 IDE DD3"),
 345         PINCTRL_PIN(220, "N5 IDE DD11"),
 346         PINCTRL_PIN(221, "N6 GND"),
 347         PINCTRL_PIN(222, "N7 VCC2IOHA 1"),
 348         PINCTRL_PIN(223, "N8 VCC2IOHA 1"),
 349         PINCTRL_PIN(224, "N9 V1"),
 350         PINCTRL_PIN(225, "N10 V1"),
 351         PINCTRL_PIN(226, "N11 VCC3IOHA"),
 352         PINCTRL_PIN(227, "N12 VCC3IOHA"),
 353         PINCTRL_PIN(228, "N13 GND"),
 354         PINCTRL_PIN(229, "N14 GPIO0 20"),
 355         PINCTRL_PIN(230, "N15 GPIO0 21"),
 356         PINCTRL_PIN(231, "N16 GPIO0 22"),
 357         PINCTRL_PIN(232, "N17 GPIO0 23"),
 358         PINCTRL_PIN(233, "N18 GPIO0 24"),
 359         /* Row P (for some reason O is skipped) */
 360         PINCTRL_PIN(234, "P1 IDE DD4"),
 361         PINCTRL_PIN(235, "P2 IDE DD10"),
 362         PINCTRL_PIN(236, "P3 IDE DD5"),
 363         PINCTRL_PIN(237, "P4 IDE DD9"),
 364         PINCTRL_PIN(238, "P5 GND"),
 365         PINCTRL_PIN(239, "P6 USB XSCO"),
 366         PINCTRL_PIN(240, "P7 GMAC0 TXD3"),
 367         PINCTRL_PIN(241, "P8 GMAC0 TXEN"),
 368         PINCTRL_PIN(242, "P9 GMAC0 RXD2"),
 369         PINCTRL_PIN(243, "P10 GMAC1 TXC"),
 370         PINCTRL_PIN(244, "P11 GMAC1 RXD1"),
 371         PINCTRL_PIN(245, "P12 MODE SEL 1"),
 372         PINCTRL_PIN(246, "P13 GPIO1 28"),
 373         PINCTRL_PIN(247, "P14 GND"),
 374         PINCTRL_PIN(248, "P15 GPIO0 5"),
 375         PINCTRL_PIN(249, "P16 GPIO0 17"),
 376         PINCTRL_PIN(250, "P17 GPIO0 18"),
 377         PINCTRL_PIN(251, "P18 GPIO0 19"),
 378         /* Row R (for some reason Q us skipped) */
 379         PINCTRL_PIN(252, "R1 IDE DD6"),
 380         PINCTRL_PIN(253, "R2 IDE DD8"),
 381         PINCTRL_PIN(254, "R3 IDE DD7"),
 382         PINCTRL_PIN(255, "R4 IDE RESET N"),
 383         PINCTRL_PIN(256, "R5 ICE0 DBGACK"),
 384         PINCTRL_PIN(257, "R6 USB XSCI"),
 385         PINCTRL_PIN(258, "R7 GMAC0 TXD2"),
 386         PINCTRL_PIN(259, "R8 GMAC0 RXDV"),
 387         PINCTRL_PIN(260, "R9 GMAC0 RXD3"),
 388         PINCTRL_PIN(261, "R10 GMAC1 TXD0"),
 389         PINCTRL_PIN(262, "R11 GMAC1 RXD0"),
 390         PINCTRL_PIN(263, "R12 MODE SEL 0"),
 391         PINCTRL_PIN(264, "R13 MODE SEL 3"),
 392         PINCTRL_PIN(265, "R14 GPIO0 0"),
 393         PINCTRL_PIN(266, "R15 GPIO0 4"),
 394         PINCTRL_PIN(267, "R16 GPIO0 9"),
 395         PINCTRL_PIN(268, "R17 GPIO0 15"),
 396         PINCTRL_PIN(269, "R18 GPIO0 16"),
 397         /* Row T (for some reason S is skipped) */
 398         PINCTRL_PIN(270, "T1 ICE0 DBGRQ"),
 399         PINCTRL_PIN(271, "T2 ICE0 IDO"),
 400         PINCTRL_PIN(272, "T3 ICE0 ICK"),
 401         PINCTRL_PIN(273, "T4 ICE0 IMS"),
 402         PINCTRL_PIN(274, "T5 ICE0 IDI"),
 403         PINCTRL_PIN(275, "T6 USB RREF"),
 404         PINCTRL_PIN(276, "T7 GMAC0 TXD1"),
 405         PINCTRL_PIN(277, "T8 GMAC0 RXC"),
 406         PINCTRL_PIN(278, "T9 GMAC0 CRS"),
 407         PINCTRL_PIN(279, "T10 GMAC1 TXD1"),
 408         PINCTRL_PIN(280, "T11 GMAC1 RXC"),
 409         PINCTRL_PIN(281, "T12 GMAC1 CRS"),
 410         PINCTRL_PIN(282, "T13 EXT CLK"),
 411         PINCTRL_PIN(283, "T14 GPIO1 31"),
 412         PINCTRL_PIN(284, "T15 GPIO0 3"),
 413         PINCTRL_PIN(285, "T16 GPIO0 8"),
 414         PINCTRL_PIN(286, "T17 GPIO0 12"),
 415         PINCTRL_PIN(287, "T18 GPIO0 14"),
 416         /* Row U */
 417         PINCTRL_PIN(288, "U1 ICE0 IRST N"),
 418         PINCTRL_PIN(289, "U2 USB0 VCCHSRT"),
 419         PINCTRL_PIN(290, "U3 USB0 DP"),
 420         PINCTRL_PIN(291, "U4 USB VCCA U20"),
 421         PINCTRL_PIN(292, "U5 USB1 DP"),
 422         PINCTRL_PIN(293, "U6 USB1 GNDHSRT 1"),
 423         PINCTRL_PIN(294, "U7 GMAC0 TXD0"),
 424         PINCTRL_PIN(295, "U8 GMAC0 RXD0"),
 425         PINCTRL_PIN(296, "U9 GMAC1 COL"),
 426         PINCTRL_PIN(297, "U10 GMAC1 TXD2"),
 427         PINCTRL_PIN(298, "U11 GMAC1 RXDV"),
 428         PINCTRL_PIN(299, "U12 GMAC1 RXD3"),
 429         PINCTRL_PIN(300, "U13 MODE SEL 2"),
 430         PINCTRL_PIN(301, "U14 GPIO1 30"),
 431         PINCTRL_PIN(302, "U15 GPIO0 2"),
 432         PINCTRL_PIN(303, "U16 GPIO0 7"),
 433         PINCTRL_PIN(304, "U17 GPIO0 11"),
 434         PINCTRL_PIN(305, "U18 GPIO0 13"),
 435         /* Row V */
 436         PINCTRL_PIN(306, "V1 USB0 GNDHSRT"),
 437         PINCTRL_PIN(307, "V2 USB0 DM"),
 438         PINCTRL_PIN(308, "V3 USB GNDA U20"),
 439         PINCTRL_PIN(309, "V4 USB1 DM"),
 440         PINCTRL_PIN(310, "V5 USB1 VCCHSRT1"),
 441         PINCTRL_PIN(311, "V6 GMAC0 COL"),
 442         PINCTRL_PIN(312, "V7 GMAC0 TXC"),
 443         PINCTRL_PIN(313, "V8 GMAC0 RXD1"),
 444         PINCTRL_PIN(314, "V9 REF CLK"),
 445         PINCTRL_PIN(315, "V10 GMAC1 TXD3"),
 446         PINCTRL_PIN(316, "V11 GMAC1 TXEN"),
 447         PINCTRL_PIN(317, "V12 GMAC1 RXD2"),
 448         PINCTRL_PIN(318, "V13 M30 CLK"),
 449         PINCTRL_PIN(319, "V14 GPIO1 29"),
 450         PINCTRL_PIN(320, "V15 GPIO0 1"),
 451         PINCTRL_PIN(321, "V16 GPIO0 6"),
 452         PINCTRL_PIN(322, "V17 GPIO0 10"),
 453         PINCTRL_PIN(323, "V18 SYS RESET N"),
 454 };
 455
 456
 457 /* Digital ground */
 458 static const unsigned int gnd_3512_pins[] = {
 459         76, 85, 95, 102, 114, 119, 133, 134, 135, 136, 151, 152, 153, 154, 169,
 460         170, 171, 172, 187, 188, 189, 190, 204, 209, 221, 228, 238, 247
 461 };
 462
 463 static const unsigned int dram_3512_pins[] = {
 464         2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 22, 23, 24, 25, 26, 27, 28, 29,
 465         30, 40, 41, 42, 43, 44, 45, 46, 47, 58, 59, 60, 61, 62, 63, 64, 65, 77,
 466         78, 79, 80, 81, 82
 467 };
 468
 469 static const unsigned int rtc_3512_pins[] = { 57, 20, 39 };
 470
 471 static const unsigned int power_3512_pins[] = { 19, 38, 36, 55, 37, 56, 54, 72 };
 472
 473 static const unsigned int system_3512_pins[] = {
 474         318, 264, 300, 245, 263, 282, 314, 323, 49,
 475 };
 476
 477 static const unsigned int vcontrol_3512_pins[] = { 18, 0, 1 };
 478
 479 static const unsigned int ice_3512_pins[] = { 256, 270, 271, 272, 273, 274, 288 };
 480
 481 static const unsigned int ide_3512_pins[] = {
 482         162, 163, 165, 166, 148, 180, 181, 182, 183, 184, 198, 199, 200, 201, 202,
 483         216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 253, 254, 255
 484 };
 485
 486 static const unsigned int sata_3512_pins[] = {
 487         75, 74, 73, 93, 94, 131, 112, 130, 92, 91, 90, 111, 110, 109, 108, 129,
 488         128, 127, 126, 147, 146, 145, 144, 164
 489 };
 490
 491 static const unsigned int usb_3512_pins[] = {
 492         306, 289, 307, 290, 239, 257, 275, 308, 291, 309, 292, 310, 293
 493 };
 494
 495 /* GMII, ethernet pins */
 496 static const unsigned int gmii_3512_pins[] = {
 497         311, 240, 258, 276, 294, 312, 241, 259, 277, 295, 313, 242, 260, 278, 296,
 498         315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281
 499 };
 500
 501 static const unsigned int pci_3512_pins[] = {
 502         13, 14, 15, 16, 17, 31, 32, 33, 34, 35, 48, 50, 51, 52, 53, 66, 67, 68, 69,
 503         70, 71, 83, 84, 86, 87, 88, 89, 103, 104, 105, 106, 107, 121, 122, 123,
 504         124, 125, 139, 140, 141, 142, 143, 157, 158, 159, 160, 161, 175, 176, 177,
 505         178, 179, 195, 196, 197
 506 };
 507
 508 /*
 509  * Apparently the LPC interface is using the PCICLK for the clocking so
 510  * PCI needs to be active at the same time.
 511  */
 512 static const unsigned int lpc_3512_pins[] = {
 513         285, /* LPC_LAD[0] */
 514         304, /* LPC_SERIRQ */
 515         286, /* LPC_LAD[2] */
 516         305, /* LPC_LFRAME# */
 517         287, /* LPC_LAD[3] */
 518         268, /* LPC_LAD[1] */
 519 };
 520
 521 /* Character LCD */
 522 static const unsigned int lcd_3512_pins[] = {
 523         262, 244, 317, 299, 246, 319, 301, 283, 269, 233, 211
 524 };
 525
 526 static const unsigned int ssp_3512_pins[] = {
 527         285, /* SSP_97RST# SSP AC97 Reset, active low */
 528         304, /* SSP_FSC */
 529         286, /* SSP_ECLK */
 530         305, /* SSP_TXD */
 531         287, /* SSP_RXD */
 532         268, /* SSP_SCLK */
 533 };
 534
 535 static const unsigned int uart_rxtx_3512_pins[] = {
 536         267, /* UART_SIN serial input, RX */
 537         322, /* UART_SOUT serial output, TX */
 538 };
 539
 540 static const unsigned int uart_modem_3512_pins[] = {
 541         285, /* UART_NDCD DCD carrier detect */
 542         304, /* UART_NDTR DTR data terminal ready */
 543         286, /* UART_NDSR DSR data set ready */
 544         305, /* UART_NRTS RTS request to send */
 545         287, /* UART_NCTS CTS clear to send */
 546         268, /* UART_NRI RI ring indicator */
 547 };
 548
 549 static const unsigned int tvc_3512_pins[] = {
 550         246, /* TVC_DATA[0] */
 551         319, /* TVC_DATA[1] */
 552         301, /* TVC_DATA[2] */
 553         283, /* TVC_DATA[3] */
 554         320, /* TVC_DATA[4] */
 555         302, /* TVC_DATA[5] */
 556         284, /* TVC_DATA[6] */
 557         266, /* TVC_DATA[7] */
 558 };
 559
 560 static const unsigned int tvc_clk_3512_pins[] = {
 561         265, /* TVC_CLK */
 562 };
 563
 564 /* NAND flash pins */
 565 static const unsigned int nflash_3512_pins[] = {
 566         199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252,
 567         253, 254, 249, 250, 232, 233, 211, 193, 194
 568 };
 569
 570 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
 571 static const unsigned int pflash_3512_pins[] = {
 572         162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
 573         234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
 574         214, 215, 193, 194
 575 };
 576
 577 /*
 578  * The parallel flash can be set up in a 26-bit address bus mode exposing
 579  * A[0-15] (A[15] takes the place of ALE), but it has the
 580  * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
 581  * used at the same time.
 582  */
 583 static const unsigned int pflash_3512_pins_extended[] = {
 584         162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
 585         234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
 586         214, 215, 193, 194,
 587         /* The extra pins */
 588         296, 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281,
 589         265,
 590 };
 591
 592 /* Serial flash pins CE0, CE1, DI, DO, CK */
 593 static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 };
 594
 595 /* The GPIO0A (0) pin overlap with TVC CLK and extended parallel flash */
 596 static const unsigned int gpio0a_3512_pins[] = { 265 };
 597
 598 /* The GPIO0B (1-4) pins overlap with TVC and ICE */
 599 static const unsigned int gpio0b_3512_pins[] = { 320, 302, 284, 266 };
 600
 601 /* The GPIO0C (5-7) pins overlap with ICE */
 602 static const unsigned int gpio0c_3512_pins[] = { 248, 321, 303 };
 603
 604 /* The GPIO0D (9,10) pins overlap with UART RX/TX */
 605 static const unsigned int gpio0d_3512_pins[] = { 267, 322 };
 606
 607 /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */
 608 static const unsigned int gpio0e_3512_pins[] = { 285, 304, 286, 305, 287, 268 };
 609
 610 /* The GPIO0F (16) pins overlap with LCD */
 611 static const unsigned int gpio0f_3512_pins[] = { 269 };
 612
 613 /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */
 614 static const unsigned int gpio0g_3512_pins[] = { 249, 250 };
 615
 616 /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */
 617 static const unsigned int gpio0h_3512_pins[] = { 251, 229 };
 618
 619 /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */
 620 static const unsigned int gpio0i_3512_pins[] = { 230, 231 };
 621
 622 /* The GPIO0J (23) pins overlap with all flash */
 623 static const unsigned int gpio0j_3512_pins[] = { 232 };
 624
 625 /* The GPIO0K (24,25) pins overlap with all flash and LCD */
 626 static const unsigned int gpio0k_3512_pins[] = { 233, 211 };
 627
 628 /* The GPIO0L (26-29) pins overlap with parallel flash */
 629 static const unsigned int gpio0l_3512_pins[] = { 212, 213, 214, 215 };
 630
 631 /* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */
 632 static const unsigned int gpio0m_3512_pins[] = { 193, 194 };
 633
 634 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
 635 static const unsigned int gpio1a_3512_pins[] = { 162, 163, 165, 166, 148 };
 636
 637 /* The GPIO1B (5-10, 27) pins overlap with just IDE */
 638 static const unsigned int gpio1b_3512_pins[] = {
 639         180, 181, 182, 183, 184, 198, 255
 640 };
 641
 642 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
 643 static const unsigned int gpio1c_3512_pins[] = {
 644         199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237,
 645         252, 253, 254
 646 };
 647
 648 /* The GPIO1D (28-31) pins overlap with LCD and TVC */
 649 static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 };
 650
 651 /* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */
 652 static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 };
 653
 654 /* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */
 655 static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 };
 656
 657 /* The GPIO2C (8-31) pins overlap with PCI */
 658 static const unsigned int gpio2c_3512_pins[] = {
 659         17, 34, 35, 51, 52, 53, 68, 69, 71, 86, 87, 88, 89, 103, 104, 105,
 660         140, 141, 142, 143, 157, 158, 159, 160
 661 };
 662
 663 /* Groups for the 3512 SoC/package */
 664 static const struct gemini_pin_group gemini_3512_pin_groups[] = {
 665         {
 666                 .name = "gndgrp",
 667                 .pins = gnd_3512_pins,
 668                 .num_pins = ARRAY_SIZE(gnd_3512_pins),
 669         },
 670         {
 671                 .name = "dramgrp",
 672                 .pins = dram_3512_pins,
 673                 .num_pins = ARRAY_SIZE(dram_3512_pins),
 674                 .mask = DRAM_PADS_POWERDOWN,
 675         },
 676         {
 677                 .name = "rtcgrp",
 678                 .pins = rtc_3512_pins,
 679                 .num_pins = ARRAY_SIZE(rtc_3512_pins),
 680         },
 681         {
 682                 .name = "powergrp",
 683                 .pins = power_3512_pins,
 684                 .num_pins = ARRAY_SIZE(power_3512_pins),
 685         },
 686         {
 687                 .name = "systemgrp",
 688                 .pins = system_3512_pins,
 689                 .num_pins = ARRAY_SIZE(system_3512_pins),
 690         },
 691         {
 692                 .name = "vcontrolgrp",
 693                 .pins = vcontrol_3512_pins,
 694                 .num_pins = ARRAY_SIZE(vcontrol_3512_pins),
 695         },
 696         {
 697                 .name = "icegrp",
 698                 .pins = ice_3512_pins,
 699                 .num_pins = ARRAY_SIZE(ice_3512_pins),
 700                 /* Conflict with some GPIO groups */
 701         },
 702         {
 703                 .name = "idegrp",
 704                 .pins = ide_3512_pins,
 705                 .num_pins = ARRAY_SIZE(ide_3512_pins),
 706                 /* Conflict with all flash usage */
 707                 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
 708                         PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
 709         },
 710         {
 711                 .name = "satagrp",
 712                 .pins = sata_3512_pins,
 713                 .num_pins = ARRAY_SIZE(sata_3512_pins),
 714         },
 715         {
 716                 .name = "usbgrp",
 717                 .pins = usb_3512_pins,
 718                 .num_pins = ARRAY_SIZE(usb_3512_pins),
 719         },
 720         {
 721                 .name = "gmiigrp",
 722                 .pins = gmii_3512_pins,
 723                 .num_pins = ARRAY_SIZE(gmii_3512_pins),
 724         },
 725         {
 726                 .name = "pcigrp",
 727                 .pins = pci_3512_pins,
 728                 .num_pins = ARRAY_SIZE(pci_3512_pins),
 729                 /* Conflict only with GPIO2 */
 730                 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
 731         },
 732         {
 733                 .name = "lpcgrp",
 734                 .pins = lpc_3512_pins,
 735                 .num_pins = ARRAY_SIZE(lpc_3512_pins),
 736                 /* Conflict with SSP and UART modem pins */
 737                 .mask = SSP_PADS_ENABLE,
 738                 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,
 739         },
 740         {
 741                 .name = "lcdgrp",
 742                 .pins = lcd_3512_pins,
 743                 .num_pins = ARRAY_SIZE(lcd_3512_pins),
 744                 /* Conflict with TVC and ICE */
 745                 .mask = TVC_PADS_ENABLE,
 746                 .value = LCD_PADS_ENABLE,
 747         },
 748         {
 749                 .name = "sspgrp",
 750                 .pins = ssp_3512_pins,
 751                 .num_pins = ARRAY_SIZE(ssp_3512_pins),
 752                 /* Conflict with LPC and UART modem pins */
 753                 .mask = LPC_PADS_ENABLE,
 754                 .value = SSP_PADS_ENABLE,
 755         },
 756         {
 757                 .name = "uartrxtxgrp",
 758                 .pins = uart_rxtx_3512_pins,
 759                 .num_pins = ARRAY_SIZE(uart_rxtx_3512_pins),
 760                 /* No conflicts except GPIO */
 761         },
 762         {
 763                 .name = "uartmodemgrp",
 764                 .pins = uart_modem_3512_pins,
 765                 .num_pins = ARRAY_SIZE(uart_modem_3512_pins),
 766                 /*
 767                  * Conflict with LPC and SSP,
 768                  * so when those are both disabled, modem UART can thrive.
 769                  */
 770                 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
 771         },
 772         {
 773                 .name = "tvcgrp",
 774                 .pins = tvc_3512_pins,
 775                 .num_pins = ARRAY_SIZE(tvc_3512_pins),
 776                 /* Conflict with character LCD and ICE */
 777                 .mask = LCD_PADS_ENABLE,
 778                 .value = TVC_PADS_ENABLE,
 779         },
 780         {
 781                 .name = "tvcclkgrp",
 782                 .pins = tvc_clk_3512_pins,
 783                 .num_pins = ARRAY_SIZE(tvc_clk_3512_pins),
 784                 .value = TVC_CLK_PAD_ENABLE,
 785         },
 786         /*
 787          * The construction is done such that it is possible to use a serial
 788          * flash together with a NAND or parallel (NOR) flash, but it is not
 789          * possible to use NAND and parallel flash together. To use serial
 790          * flash with one of the two others, the muxbits need to be flipped
 791          * around before any access.
 792          */
 793         {
 794                 .name = "nflashgrp",
 795                 .pins = nflash_3512_pins,
 796                 .num_pins = ARRAY_SIZE(nflash_3512_pins),
 797                 /* Conflict with IDE, parallel and serial flash */
 798                 .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE,
 799                 .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
 800         },
 801         {
 802                 .name = "pflashgrp",
 803                 .pins = pflash_3512_pins,
 804                 .num_pins = ARRAY_SIZE(pflash_3512_pins),
 805                 /* Conflict with IDE, NAND and serial flash */
 806                 .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
 807                 .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE,
 808         },
 809         {
 810                 .name = "sflashgrp",
 811                 .pins = sflash_3512_pins,
 812                 .num_pins = ARRAY_SIZE(sflash_3512_pins),
 813                 /* Conflict with IDE, NAND and parallel flash */
 814                 .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
 815                 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
 816         },
 817         {
 818                 .name = "gpio0agrp",
 819                 .pins = gpio0a_3512_pins,
 820                 .num_pins = ARRAY_SIZE(gpio0a_3512_pins),
 821                 /* Conflict with TVC CLK */
 822                 .mask = TVC_CLK_PAD_ENABLE,
 823         },
 824         {
 825                 .name = "gpio0bgrp",
 826                 .pins = gpio0b_3512_pins,
 827                 .num_pins = ARRAY_SIZE(gpio0b_3512_pins),
 828                 /* Conflict with TVC and ICE */
 829                 .mask = TVC_PADS_ENABLE,
 830         },
 831         {
 832                 .name = "gpio0cgrp",
 833                 .pins = gpio0c_3512_pins,
 834                 .num_pins = ARRAY_SIZE(gpio0c_3512_pins),
 835                 /* Conflict with ICE */
 836         },
 837         {
 838                 .name = "gpio0dgrp",
 839                 .pins = gpio0d_3512_pins,
 840                 .num_pins = ARRAY_SIZE(gpio0d_3512_pins),
 841                 /* Conflict with UART RX/TX */
 842         },
 843         {
 844                 .name = "gpio0egrp",
 845                 .pins = gpio0e_3512_pins,
 846                 .num_pins = ARRAY_SIZE(gpio0e_3512_pins),
 847                 /* Conflict with LPC, UART modem pins, SSP */
 848                 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
 849         },
 850         {
 851                 .name = "gpio0fgrp",
 852                 .pins = gpio0f_3512_pins,
 853                 .num_pins = ARRAY_SIZE(gpio0f_3512_pins),
 854                 /* Conflict with LCD */
 855                 .mask = LCD_PADS_ENABLE,
 856         },
 857         {
 858                 .name = "gpio0ggrp",
 859                 .pins = gpio0g_3512_pins,
 860                 .num_pins = ARRAY_SIZE(gpio0g_3512_pins),
 861                 /* Conflict with NAND flash */
 862                 .value = NAND_PADS_DISABLE,
 863         },
 864         {
 865                 .name = "gpio0hgrp",
 866                 .pins = gpio0h_3512_pins,
 867                 .num_pins = ARRAY_SIZE(gpio0h_3512_pins),
 868                 /* Conflict with parallel flash */
 869                 .value = PFLASH_PADS_DISABLE,
 870         },
 871         {
 872                 .name = "gpio0igrp",
 873                 .pins = gpio0i_3512_pins,
 874                 .num_pins = ARRAY_SIZE(gpio0i_3512_pins),
 875                 /* Conflict with serial flash */
 876                 .value = SFLASH_PADS_DISABLE,
 877         },
 878         {
 879                 .name = "gpio0jgrp",
 880                 .pins = gpio0j_3512_pins,
 881                 .num_pins = ARRAY_SIZE(gpio0j_3512_pins),
 882                 /* Conflict with all flash */
 883                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
 884                         SFLASH_PADS_DISABLE,
 885         },
 886         {
 887                 .name = "gpio0kgrp",
 888                 .pins = gpio0k_3512_pins,
 889                 .num_pins = ARRAY_SIZE(gpio0k_3512_pins),
 890                 /* Conflict with all flash and LCD */
 891                 .mask = LCD_PADS_ENABLE,
 892                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
 893                         SFLASH_PADS_DISABLE,
 894         },
 895         {
 896                 .name = "gpio0lgrp",
 897                 .pins = gpio0l_3512_pins,
 898                 .num_pins = ARRAY_SIZE(gpio0l_3512_pins),
 899                 /* Conflict with parallel flash */
 900                 .value = PFLASH_PADS_DISABLE,
 901         },
 902         {
 903                 .name = "gpio0mgrp",
 904                 .pins = gpio0m_3512_pins,
 905                 .num_pins = ARRAY_SIZE(gpio0m_3512_pins),
 906                 /* Conflict with parallel and NAND flash */
 907                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
 908         },
 909         {
 910                 .name = "gpio1agrp",
 911                 .pins = gpio1a_3512_pins,
 912                 .num_pins = ARRAY_SIZE(gpio1a_3512_pins),
 913                 /* Conflict with IDE and parallel flash */
 914                 .mask = IDE_PADS_ENABLE,
 915                 .value = PFLASH_PADS_DISABLE,
 916         },
 917         {
 918                 .name = "gpio1bgrp",
 919                 .pins = gpio1b_3512_pins,
 920                 .num_pins = ARRAY_SIZE(gpio1b_3512_pins),
 921                 /* Conflict with IDE only */
 922                 .mask = IDE_PADS_ENABLE,
 923         },
 924         {
 925                 .name = "gpio1cgrp",
 926                 .pins = gpio1c_3512_pins,
 927                 .num_pins = ARRAY_SIZE(gpio1c_3512_pins),
 928                 /* Conflict with IDE, parallel and NAND flash */
 929                 .mask = IDE_PADS_ENABLE,
 930                 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
 931         },
 932         {
 933                 .name = "gpio1dgrp",
 934                 .pins = gpio1d_3512_pins,
 935                 .num_pins = ARRAY_SIZE(gpio1d_3512_pins),
 936                 /* Conflict with LCD and TVC */
 937                 .mask = LCD_PADS_ENABLE | TVC_PADS_ENABLE,
 938         },
 939         {
 940                 .name = "gpio2agrp",
 941                 .pins = gpio2a_3512_pins,
 942                 .num_pins = ARRAY_SIZE(gpio2a_3512_pins),
 943                 /* Conflict with GMII and extended parallel flash */
 944         },
 945         {
 946                 .name = "gpio2bgrp",
 947                 .pins = gpio2b_3512_pins,
 948                 .num_pins = ARRAY_SIZE(gpio2b_3512_pins),
 949                 /* Conflict with GMII, extended parallel flash and LCD */
 950                 .mask = LCD_PADS_ENABLE,
 951         },
 952         {
 953                 .name = "gpio2cgrp",
 954                 .pins = gpio2c_3512_pins,
 955                 .num_pins = ARRAY_SIZE(gpio2c_3512_pins),
 956                 /* Conflict with PCI */
 957                 .mask = PCI_PADS_ENABLE,
 958         },
 959 };
 960
 961 /* Pin names for the pinmux subsystem, 3516 variant */
 962 static const struct pinctrl_pin_desc gemini_3516_pins[] = {
 963         /* Row A */
 964         PINCTRL_PIN(0, "A1 AVCC3IOHA"),
 965         PINCTRL_PIN(1, "A2 DRAM CK N"),
 966         PINCTRL_PIN(2, "A3 DRAM CK"),
 967         PINCTRL_PIN(3, "A4 DRAM DQM1"),
 968         PINCTRL_PIN(4, "A5 DRAM DQ9"),
 969         PINCTRL_PIN(5, "A6 DRAM DQ13"),
 970         PINCTRL_PIN(6, "A7 DRAM DQ1"),
 971         PINCTRL_PIN(7, "A8 DRAM DQ2"),
 972         PINCTRL_PIN(8, "A9 DRAM DQ4"),
 973         PINCTRL_PIN(9, "A10 DRAM VREF"),
 974         PINCTRL_PIN(10, "A11 DRAM DQ24"),
 975         PINCTRL_PIN(11, "A12 DRAM DQ28"),
 976         PINCTRL_PIN(12, "A13 DRAM DQ30"),
 977         PINCTRL_PIN(13, "A14 DRAM DQ18"),
 978         PINCTRL_PIN(14, "A15 DRAM DQ21"),
 979         PINCTRL_PIN(15, "A16 DRAM CAS_N"),
 980         PINCTRL_PIN(16, "A17 DRAM BA1"),
 981         PINCTRL_PIN(17, "A18 PCI INTA N"),
 982         PINCTRL_PIN(18, "A19 PCI INTB N"),
 983         PINCTRL_PIN(19, "A20 PCI INTC N"),
 984         /* Row B */
 985         PINCTRL_PIN(20, "B1 PWR EN"),
 986         PINCTRL_PIN(21, "B2 GND"),
 987         PINCTRL_PIN(22, "B3 RTC CLKO"),
 988         PINCTRL_PIN(23, "B4 DRAM A5"),
 989         PINCTRL_PIN(24, "B5 DRAM A6"),
 990         PINCTRL_PIN(25, "B6 DRAM DQS1"),
 991         PINCTRL_PIN(26, "B7 DRAM DQ11"),
 992         PINCTRL_PIN(27, "B8 DRAM DQ0"),
 993         PINCTRL_PIN(28, "B9 DRAM DQS0"),
 994         PINCTRL_PIN(29, "B10 DRAM DQ7"),
 995         PINCTRL_PIN(30, "B11 DRAM DQS3"),
 996         PINCTRL_PIN(31, "B12 DRAM DQ27"),
 997         PINCTRL_PIN(32, "B13 DRAM DQ31"),
 998         PINCTRL_PIN(33, "B14 DRAM DQ20"),
 999         PINCTRL_PIN(34, "B15 DRAM DQS2"),
1000         PINCTRL_PIN(35, "B16 DRAM WE N"),
1001         PINCTRL_PIN(36, "B17 DRAM A10"),
1002         PINCTRL_PIN(37, "B18 DRAM A2"),
1003         PINCTRL_PIN(38, "B19 GND"),
1004         PINCTRL_PIN(39, "B20 PCI GNT0 N"),
1005         /* Row C */
1006         PINCTRL_PIN(40, "C1 AGNDIOHA"),
1007         PINCTRL_PIN(41, "C2 XTALI"),
1008         PINCTRL_PIN(42, "C3 GND"),
1009         PINCTRL_PIN(43, "C4 RTC CLKI"),
1010         PINCTRL_PIN(44, "C5 DRAM A12"),
1011         PINCTRL_PIN(45, "C6 DRAM A11"),
1012         PINCTRL_PIN(46, "C7 DRAM DQ8"),
1013         PINCTRL_PIN(47, "C8 DRAM DQ10"),
1014         PINCTRL_PIN(48, "C9 DRAM DQ3"),
1015         PINCTRL_PIN(49, "C10 DRAM DQ6"),
1016         PINCTRL_PIN(50, "C11 DRAM DQM0"),
1017         PINCTRL_PIN(51, "C12 DRAM DQ26"),
1018         PINCTRL_PIN(52, "C13 DRAM DQ16"),
1019         PINCTRL_PIN(53, "C14 DRAM DQ22"),
1020         PINCTRL_PIN(54, "C15 DRAM DQM2"),
1021         PINCTRL_PIN(55, "C16 DRAM BA0"),
1022         PINCTRL_PIN(56, "C17 DRAM A3"),
1023         PINCTRL_PIN(57, "C18 GND"),
1024         PINCTRL_PIN(58, "C19 PCI GNT1 N"),
1025         PINCTRL_PIN(59, "C20 PCI REQ2 N"),
1026         /* Row D */
1027         PINCTRL_PIN(60, "D1 AVCC3IOAHA"),
1028         PINCTRL_PIN(61, "D2 AVCCKHA"),
1029         PINCTRL_PIN(62, "D3 XTALO"),
1030         PINCTRL_PIN(63, "D4 GND"),
1031         PINCTRL_PIN(64, "D5 CIR RXD"),
1032         PINCTRL_PIN(65, "D6 DRAM A7"),
1033         PINCTRL_PIN(66, "D7 DRAM A4"),
1034         PINCTRL_PIN(67, "D8 DRAM A8"),
1035         PINCTRL_PIN(68, "D9 DRAM CKE"),
1036         PINCTRL_PIN(69, "D10 DRAM DQ14"),
1037         PINCTRL_PIN(70, "D11 DRAM DQ5"),
1038         PINCTRL_PIN(71, "D12 DRAM DQ25"),
1039         PINCTRL_PIN(72, "D13 DRAM DQ17"),
1040         PINCTRL_PIN(73, "D14 DRAM DQ23"),
1041         PINCTRL_PIN(74, "D15 DRAM RAS N"),
1042         PINCTRL_PIN(75, "D16 DRAM A1"),
1043         PINCTRL_PIN(76, "D17 GND"),
1044         PINCTRL_PIN(77, "D18 EXT RESET N"),
1045         PINCTRL_PIN(78, "D19 PCI REQ1 N"),
1046         PINCTRL_PIN(79, "D20 PCI REQ3 N"),
1047         /* Row E */
1048         PINCTRL_PIN(80, "E1 VCC2IO CTRL"),
1049         PINCTRL_PIN(81, "E2 VREF CTRL"),
1050         PINCTRL_PIN(82, "E3 CIR RST N"),
1051         PINCTRL_PIN(83, "E4 PWR BTN"),
1052         PINCTRL_PIN(84, "E5 GND"),
1053         PINCTRL_PIN(85, "E6 CIR TXD"),
1054         PINCTRL_PIN(86, "E7 VCCK CTRL"),
1055         PINCTRL_PIN(87, "E8 DRAM A9"),
1056         PINCTRL_PIN(88, "E9 DRAM DQ12"),
1057         PINCTRL_PIN(89, "E10 DRAM DQ15"),
1058         PINCTRL_PIN(90, "E11 DRAM DQM3"),
1059         PINCTRL_PIN(91, "E12 DRAM DQ29"),
1060         PINCTRL_PIN(92, "E13 DRAM DQ19"),
1061         PINCTRL_PIN(93, "E14 DRAM A13"),
1062         PINCTRL_PIN(94, "E15 DRAM A0"),
1063         PINCTRL_PIN(95, "E16 GND"),
1064         PINCTRL_PIN(96, "E17 PCI INTD N"),
1065         PINCTRL_PIN(97, "E18 PCI GNT3 N"),
1066         PINCTRL_PIN(98, "E19 PCI AD29"),
1067         PINCTRL_PIN(99, "E20 PCI AD28"),
1068         /* Row F */
1069         PINCTRL_PIN(100, "F1 AVCCKHB"),
1070         PINCTRL_PIN(101, "F2 AVCCK P"),
1071         PINCTRL_PIN(102, "F3 EBG"),
1072         PINCTRL_PIN(103, "F4 REXT"),
1073         PINCTRL_PIN(104, "F5 AVCC3IOHB"),
1074         PINCTRL_PIN(105, "F6 GND"),
1075         PINCTRL_PIN(106, "F7 VCC2IOHA 2"),
1076         PINCTRL_PIN(107, "F8 VCC2IOHA 2"),
1077         PINCTRL_PIN(108, "F9 VCC2IOHA 2"),
1078         PINCTRL_PIN(109, "F10 V1"),
1079         PINCTRL_PIN(110, "F11 V1"),
1080         PINCTRL_PIN(111, "F12 VCC2IOHA 2"),
1081         PINCTRL_PIN(112, "F13 VCC2IOHA 2"),
1082         PINCTRL_PIN(113, "F14 VCC2IOHA 2"),
1083         PINCTRL_PIN(114, "F15 GND"),
1084         PINCTRL_PIN(115, "F16 PCI CLK"),
1085         PINCTRL_PIN(116, "F17 PCI GNT2 N"),
1086         PINCTRL_PIN(117, "F18 PCI AD31"),
1087         PINCTRL_PIN(118, "F19 PCI AD26"),
1088         PINCTRL_PIN(119, "F20 PCI CBE3 N"),
1089         /* Row G */
1090         PINCTRL_PIN(120, "G1 SATA0 RXDP"),
1091         PINCTRL_PIN(121, "G2 SATA0 RXDN"),
1092         PINCTRL_PIN(122, "G3 AGNDK 0"),
1093         PINCTRL_PIN(123, "G4 AVCCK S"),
1094         PINCTRL_PIN(124, "G5 AVCC3 S"),
1095         PINCTRL_PIN(125, "G6 VCC2IOHA 2"),
1096         PINCTRL_PIN(126, "G7 GND"),
1097         PINCTRL_PIN(127, "G8 VCC2IOHA 2"),
1098         PINCTRL_PIN(128, "G9 V1"),
1099         PINCTRL_PIN(129, "G10 V1"),
1100         PINCTRL_PIN(130, "G11 V1"),
1101         PINCTRL_PIN(131, "G12 V1"),
1102         PINCTRL_PIN(132, "G13 VCC2IOHA 2"),
1103         PINCTRL_PIN(133, "G14 GND"),
1104         PINCTRL_PIN(134, "G15 VCC3IOHA"),
1105         PINCTRL_PIN(135, "G16 PCI REQ0 N"),
1106         PINCTRL_PIN(136, "G17 PCI AD30"),
1107         PINCTRL_PIN(137, "G18 PCI AD24"),
1108         PINCTRL_PIN(138, "G19 PCI AD23"),
1109         PINCTRL_PIN(139, "G20 PCI AD21"),
1110         /* Row H */
1111         PINCTRL_PIN(140, "H1 SATA0 TXDP"),
1112         PINCTRL_PIN(141, "H2 SATA0 TXDN"),
1113         PINCTRL_PIN(142, "H3 AGNDK 1"),
1114         PINCTRL_PIN(143, "H4 AVCCK 0"),
1115         PINCTRL_PIN(144, "H5 TEST CLKOUT"),
1116         PINCTRL_PIN(145, "H6 AGND"),
1117         PINCTRL_PIN(146, "H7 VCC2IOHA 2"),
1118         PINCTRL_PIN(147, "H8 GND"),
1119         PINCTRL_PIN(148, "H9 GND"),
1120         PINCTRL_PIN(149, "H10 GDN"),
1121         PINCTRL_PIN(150, "H11 GND"),
1122         PINCTRL_PIN(151, "H12 GND"),
1123         PINCTRL_PIN(152, "H13 GND"),
1124         PINCTRL_PIN(153, "H14 VCC3IOHA"),
1125         PINCTRL_PIN(154, "H15 VCC3IOHA"),
1126         PINCTRL_PIN(155, "H16 PCI AD27"),
1127         PINCTRL_PIN(156, "H17 PCI AD25"),
1128         PINCTRL_PIN(157, "H18 PCI AD22"),
1129         PINCTRL_PIN(158, "H19 PCI AD18"),
1130         PINCTRL_PIN(159, "H20 PCI AD17"),
1131         /* Row J (for some reason I is skipped) */
1132         PINCTRL_PIN(160, "J1 SATA1 TXDP"),
1133         PINCTRL_PIN(161, "J2 SATA1 TXDN"),
1134         PINCTRL_PIN(162, "J3 AGNDK 2"),
1135         PINCTRL_PIN(163, "J4 AVCCK 1"),
1136         PINCTRL_PIN(164, "J5 AGND"),
1137         PINCTRL_PIN(165, "J6 AGND"),
1138         PINCTRL_PIN(166, "J7 V1"),
1139         PINCTRL_PIN(167, "J8 GND"),
1140         PINCTRL_PIN(168, "J9 GND"),
1141         PINCTRL_PIN(169, "J10 GND"),
1142         PINCTRL_PIN(170, "J11 GND"),
1143         PINCTRL_PIN(171, "J12 GND"),
1144         PINCTRL_PIN(172, "J13 GND"),
1145         PINCTRL_PIN(173, "J14 V1"),
1146         PINCTRL_PIN(174, "J15 VCC3IOHA"),
1147         PINCTRL_PIN(175, "J16 PCI AD19"),
1148         PINCTRL_PIN(176, "J17 PCI AD20"),
1149         PINCTRL_PIN(177, "J18 PCI AD16"),
1150         PINCTRL_PIN(178, "J19 PCI CBE2 N"),
1151         PINCTRL_PIN(179, "J20 PCI FRAME N"),
1152         /* Row K */
1153         PINCTRL_PIN(180, "K1 SATA1 RXDP"),
1154         PINCTRL_PIN(181, "K2 SATA1 RXDN"),
1155         PINCTRL_PIN(182, "K3 AGNDK 3"),
1156         PINCTRL_PIN(183, "K4 AVCCK 2"),
1157         PINCTRL_PIN(184, "K5 AGND"),
1158         PINCTRL_PIN(185, "K6 V1"),
1159         PINCTRL_PIN(186, "K7 V1"),
1160         PINCTRL_PIN(187, "K8 GND"),
1161         PINCTRL_PIN(188, "K9 GND"),
1162         PINCTRL_PIN(189, "K10 GND"),
1163         PINCTRL_PIN(190, "K11 GND"),
1164         PINCTRL_PIN(191, "K12 GND"),
1165         PINCTRL_PIN(192, "K13 GND"),
1166         PINCTRL_PIN(193, "K14 V1"),
1167         PINCTRL_PIN(194, "K15 V1"),
1168         PINCTRL_PIN(195, "K16 PCI TRDY N"),
1169         PINCTRL_PIN(196, "K17 PCI IRDY N"),
1170         PINCTRL_PIN(197, "K18 PCI DEVSEL N"),
1171         PINCTRL_PIN(198, "K19 PCI STOP N"),
1172         PINCTRL_PIN(199, "K20 PCI PAR"),
1173         /* Row L */
1174         PINCTRL_PIN(200, "L1 IDE CS0 N"),
1175         PINCTRL_PIN(201, "L2 IDE DA0"),
1176         PINCTRL_PIN(202, "L3 AVCCK 3"),
1177         PINCTRL_PIN(203, "L4 AGND"),
1178         PINCTRL_PIN(204, "L5 IDE DIOR N"),
1179         PINCTRL_PIN(205, "L6 V1"),
1180         PINCTRL_PIN(206, "L7 V1"),
1181         PINCTRL_PIN(207, "L8 GND"),
1182         PINCTRL_PIN(208, "L9 GND"),
1183         PINCTRL_PIN(209, "L10 GND"),
1184         PINCTRL_PIN(210, "L11 GND"),
1185         PINCTRL_PIN(211, "L12 GND"),
1186         PINCTRL_PIN(212, "L13 GND"),
1187         PINCTRL_PIN(213, "L14 V1"),
1188         PINCTRL_PIN(214, "L15 V1"),
1189         PINCTRL_PIN(215, "L16 PCI AD12"),
1190         PINCTRL_PIN(216, "L17 PCI AD13"),
1191         PINCTRL_PIN(217, "L18 PCI AD14"),
1192         PINCTRL_PIN(218, "L19 PCI AD15"),
1193         PINCTRL_PIN(219, "L20 PCI CBE1 N"),
1194         /* Row M */
1195         PINCTRL_PIN(220, "M1 IDE DA1"),
1196         PINCTRL_PIN(221, "M2 IDE CS1 N"),
1197         PINCTRL_PIN(222, "M3 IDE DA2"),
1198         PINCTRL_PIN(223, "M4 IDE DMACK N"),
1199         PINCTRL_PIN(224, "M5 IDE DD1"),
1200         PINCTRL_PIN(225, "M6 VCC3IOHA"),
1201         PINCTRL_PIN(226, "M7 V1"),
1202         PINCTRL_PIN(227, "M8 GND"),
1203         PINCTRL_PIN(228, "M9 GND"),
1204         PINCTRL_PIN(229, "M10 GND"),
1205         PINCTRL_PIN(230, "M11 GND"),
1206         PINCTRL_PIN(231, "M12 GND"),
1207         PINCTRL_PIN(232, "M13 GND"),
1208         PINCTRL_PIN(233, "M14 V1"),
1209         PINCTRL_PIN(234, "M15 VCC3IOHA"),
1210         PINCTRL_PIN(235, "M16 PCI AD7"),
1211         PINCTRL_PIN(236, "M17 PCI AD6"),
1212         PINCTRL_PIN(237, "M18 PCI AD9"),
1213         PINCTRL_PIN(238, "M19 PCI AD10"),
1214         PINCTRL_PIN(239, "M20 PCI AD11"),
1215         /* Row N */
1216         PINCTRL_PIN(240, "N1 IDE IORDY"),
1217         PINCTRL_PIN(241, "N2 IDE INTRQ"),
1218         PINCTRL_PIN(242, "N3 IDE DIOW N"),
1219         PINCTRL_PIN(243, "N4 IDE DD15"),
1220         PINCTRL_PIN(244, "N5 IDE DMARQ"),
1221         PINCTRL_PIN(245, "N6 VCC3IOHA"),
1222         PINCTRL_PIN(246, "N7 VCC3IOHA"),
1223         PINCTRL_PIN(247, "N8 GND"),
1224         PINCTRL_PIN(248, "N9 GND"),
1225         PINCTRL_PIN(249, "N10 GND"),
1226         PINCTRL_PIN(250, "N11 GND"),
1227         PINCTRL_PIN(251, "N12 GND"),
1228         PINCTRL_PIN(252, "N13 GND"),
1229         PINCTRL_PIN(253, "N14 VCC3IOHA"),
1230         PINCTRL_PIN(254, "N15 VCC3IOHA"),
1231         PINCTRL_PIN(255, "N16 PCI CLKRUN N"),
1232         PINCTRL_PIN(256, "N17 PCI AD0"),
1233         PINCTRL_PIN(257, "N18 PCI AD4"),
1234         PINCTRL_PIN(258, "N19 PCI CBE0 N"),
1235         PINCTRL_PIN(259, "N20 PCI AD8"),
1236         /* Row P (for some reason O is skipped) */
1237         PINCTRL_PIN(260, "P1 IDE DD0"),
1238         PINCTRL_PIN(261, "P2 IDE DD14"),
1239         PINCTRL_PIN(262, "P3 IDE DD2"),
1240         PINCTRL_PIN(263, "P4 IDE DD4"),
1241         PINCTRL_PIN(264, "P5 IDE DD3"),
1242         PINCTRL_PIN(265, "P6 VCC3IOHA"),
1243         PINCTRL_PIN(266, "P7 GND"),
1244         PINCTRL_PIN(267, "P8 VCC2IOHA 1"),
1245         PINCTRL_PIN(268, "P9 V1"),
1246         PINCTRL_PIN(269, "P10 V1"),
1247         PINCTRL_PIN(270, "P11 V1"),
1248         PINCTRL_PIN(271, "P12 V1"),
1249         PINCTRL_PIN(272, "P13 VCC3IOHA"),
1250         PINCTRL_PIN(273, "P14 GND"),
1251         PINCTRL_PIN(274, "P15 VCC3IOHA"),
1252         PINCTRL_PIN(275, "P16 GPIO0 30"),
1253         PINCTRL_PIN(276, "P17 GPIO0 28"),
1254         PINCTRL_PIN(277, "P18 PCI AD1"),
1255         PINCTRL_PIN(278, "P19 PCI AD3"),
1256         PINCTRL_PIN(279, "P20 PCI AD5"),
1257         /* Row R (for some reason Q us skipped) */
1258         PINCTRL_PIN(280, "R1 IDE DD13"),
1259         PINCTRL_PIN(281, "R2 IDE DD12"),
1260         PINCTRL_PIN(282, "R3 IDE DD10"),
1261         PINCTRL_PIN(283, "R4 IDE DD6"),
1262         PINCTRL_PIN(284, "R5 ICE0 IDI"),
1263         PINCTRL_PIN(285, "R6 GND"),
1264         PINCTRL_PIN(286, "R7 VCC2IOHA 1"),
1265         PINCTRL_PIN(287, "R8 VCC2IOHA 1"),
1266         PINCTRL_PIN(288, "R9 VCC2IOHA 1"),
1267         PINCTRL_PIN(289, "R10 V1"),
1268         PINCTRL_PIN(290, "R11 V1"),
1269         PINCTRL_PIN(291, "R12 VCC3IOHA"),
1270         PINCTRL_PIN(292, "R13 VCC3IOHA"),
1271         PINCTRL_PIN(293, "R14 VCC3IOHA"),
1272         PINCTRL_PIN(294, "R15 GND"),
1273         PINCTRL_PIN(295, "R16 GPIO0 23"),
1274         PINCTRL_PIN(296, "R17 GPIO0 21"),
1275         PINCTRL_PIN(297, "R18 GPIO0 26"),
1276         PINCTRL_PIN(298, "R19 GPIO0 31"),
1277         PINCTRL_PIN(299, "R20 PCI AD2"),
1278         /* Row T (for some reason S is skipped) */
1279         PINCTRL_PIN(300, "T1 IDE DD11"),
1280         PINCTRL_PIN(301, "T2 IDE DD5"),
1281         PINCTRL_PIN(302, "T3 IDE DD8"),
1282         PINCTRL_PIN(303, "T4 ICE0 IDO"),
1283         PINCTRL_PIN(304, "T5 GND"),
1284         PINCTRL_PIN(305, "T6 USB GNDA U20"),
1285         PINCTRL_PIN(306, "T7 GMAC0 TXD0"),
1286         PINCTRL_PIN(307, "T8 GMAC0 TXEN"),
1287         PINCTRL_PIN(308, "T9 GMAC1 TXD3"),
1288         PINCTRL_PIN(309, "T10 GMAC1 RXDV"),
1289         PINCTRL_PIN(310, "T11 GMAC1 RXD2"),
1290         PINCTRL_PIN(311, "T12 GPIO1 29"),
1291         PINCTRL_PIN(312, "T13 GPIO0 3"),
1292         PINCTRL_PIN(313, "T14 GPIO0 9"),
1293         PINCTRL_PIN(314, "T15 GPIO0 16"),
1294         PINCTRL_PIN(315, "T16 GND"),
1295         PINCTRL_PIN(316, "T17 GPIO0 14"),
1296         PINCTRL_PIN(317, "T18 GPIO0 19"),
1297         PINCTRL_PIN(318, "T19 GPIO0 27"),
1298         PINCTRL_PIN(319, "T20 GPIO0 29"),
1299         /* Row U */
1300         PINCTRL_PIN(320, "U1 IDE DD9"),
1301         PINCTRL_PIN(321, "U2 IDE DD7"),
1302         PINCTRL_PIN(322, "U3 ICE0 ICK"),
1303         PINCTRL_PIN(323, "U4 GND"),
1304         PINCTRL_PIN(324, "U5 USB XSCO"),
1305         PINCTRL_PIN(325, "U6 GMAC0 TXD1"),
1306         PINCTRL_PIN(326, "U7 GMAC0 TXD3"),
1307         PINCTRL_PIN(327, "U8 GMAC0 TXC"),
1308         PINCTRL_PIN(328, "U9 GMAC0 RXD3"),
1309         PINCTRL_PIN(329, "U10 GMAC1 TXD0"),
1310         PINCTRL_PIN(330, "U11 GMAC1 CRS"),
1311         PINCTRL_PIN(331, "U12 EXT CLK"),
1312         PINCTRL_PIN(332, "U13 DEV DEF"),
1313         PINCTRL_PIN(333, "U14 GPIO0 0"),
1314         PINCTRL_PIN(334, "U15 GPIO0 4"),
1315         PINCTRL_PIN(335, "U16 GPIO0 10"),
1316         PINCTRL_PIN(336, "U17 GND"),
1317         PINCTRL_PIN(337, "U18 GPIO0 17"),
1318         PINCTRL_PIN(338, "U19 GPIO0 22"),
1319         PINCTRL_PIN(339, "U20 GPIO0 25"),
1320         /* Row V */
1321         PINCTRL_PIN(340, "V1 ICE0 DBGACK"),
1322         PINCTRL_PIN(341, "V2 ICE0 DBGRQ"),
1323         PINCTRL_PIN(342, "V3 GND"),
1324         PINCTRL_PIN(343, "V4 ICE0 IRST N"),
1325         PINCTRL_PIN(344, "V5 USB XSCI"),
1326         PINCTRL_PIN(345, "V6 GMAC0 COL"),
1327         PINCTRL_PIN(346, "V7 GMAC0 TXD2"),
1328         PINCTRL_PIN(347, "V8 GMAC0 RXDV"),
1329         PINCTRL_PIN(348, "V9 GMAC0 RXD1"),
1330         PINCTRL_PIN(349, "V10 GMAC1 COL"),
1331         PINCTRL_PIN(350, "V11 GMAC1 TXC"),
1332         PINCTRL_PIN(351, "V12 GMAC1 RXD1"),
1333         PINCTRL_PIN(352, "V13 MODE SEL1"),
1334         PINCTRL_PIN(353, "V14 GPIO1 28"),
1335         PINCTRL_PIN(354, "V15 GPIO0 1"),
1336         PINCTRL_PIN(355, "V16 GPIO0 8"),
1337         PINCTRL_PIN(356, "V17 GPIO0 11"),
1338         PINCTRL_PIN(357, "V18 GND"),
1339         PINCTRL_PIN(358, "V19 GPIO0 18"),
1340         PINCTRL_PIN(359, "V20 GPIO0 24"),
1341         /* Row W */
1342         PINCTRL_PIN(360, "W1 IDE RESET N"),
1343         PINCTRL_PIN(361, "W2 GND"),
1344         PINCTRL_PIN(362, "W3 USB0 VCCHSRT"),
1345         PINCTRL_PIN(363, "W4 USB0 DP"),
1346         PINCTRL_PIN(364, "W5 USB VCCA U20"),
1347         PINCTRL_PIN(365, "W6 USB1 DP"),
1348         PINCTRL_PIN(366, "W7 USB1 GNDHSRT"),
1349         PINCTRL_PIN(367, "W8 GMAC0 RXD0"),
1350         PINCTRL_PIN(368, "W9 GMAC0 CRS"),
1351         PINCTRL_PIN(369, "W10 GMAC1 TXD2"),
1352         PINCTRL_PIN(370, "W11 GMAC1 TXEN"),
1353         PINCTRL_PIN(371, "W12 GMAC1 RXD3"),
1354         PINCTRL_PIN(372, "W13 MODE SEL0"),
1355         PINCTRL_PIN(373, "W14 MODE SEL3"),
1356         PINCTRL_PIN(374, "W15 GPIO1 31"),
1357         PINCTRL_PIN(375, "W16 GPIO0 5"),
1358         PINCTRL_PIN(376, "W17 GPIO0 7"),
1359         PINCTRL_PIN(377, "W18 GPIO0 12"),
1360         PINCTRL_PIN(378, "W19 GND"),
1361         PINCTRL_PIN(379, "W20 GPIO0 20"),
1362         /* Row Y */
1363         PINCTRL_PIN(380, "Y1 ICE0 IMS"),
1364         PINCTRL_PIN(381, "Y2 USB0 GNDHSRT"),
1365         PINCTRL_PIN(382, "Y3 USB0 DM"),
1366         PINCTRL_PIN(383, "Y4 USB RREF"),
1367         PINCTRL_PIN(384, "Y5 USB1 DM"),
1368         PINCTRL_PIN(385, "Y6 USB1 VCCHSRT"),
1369         PINCTRL_PIN(386, "Y7 GMAC0 RXC"),
1370         PINCTRL_PIN(387, "Y8 GMAC0 RXD2"),
1371         PINCTRL_PIN(388, "Y9 REF CLK"),
1372         PINCTRL_PIN(389, "Y10 GMAC1 TXD1"),
1373         PINCTRL_PIN(390, "Y11 GMAC1 RXC"),
1374         PINCTRL_PIN(391, "Y12 GMAC1 RXD0"),
1375         PINCTRL_PIN(392, "Y13 M30 CLK"),
1376         PINCTRL_PIN(393, "Y14 MODE SEL2"),
1377         PINCTRL_PIN(394, "Y15 GPIO1 30"),
1378         PINCTRL_PIN(395, "Y16 GPIO0 2"),
1379         PINCTRL_PIN(396, "Y17 GPIO0 6"),
1380         PINCTRL_PIN(397, "Y18 SYS RESET N"),
1381         PINCTRL_PIN(398, "Y19 GPIO0 13"),
1382         PINCTRL_PIN(399, "Y20 GPIO0 15"),
1383 };
1384
1385 /* Digital ground */
1386 static const unsigned int gnd_3516_pins[] = {
1387         21, 38, 42, 57, 63, 76, 84, 95, 105, 114, 126, 133, 147, 148, 149, 150,
1388         151, 152, 167, 168, 169, 170, 171, 172, 187, 188, 189, 190, 191, 192,
1389         207, 208, 209, 210, 211, 212, 227, 228, 229, 230, 231, 232, 247, 248,
1390         249, 250, 251, 252, 266, 273, 285, 294, 304, 315, 323, 336, 342, 357,
1391         361, 378
1392 };
1393
1394 static const unsigned int dram_3516_pins[] = {
1395         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 23, 24, 25, 26,
1396         27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 44, 45, 46, 47, 48, 49, 50,
1397         51, 52, 53, 54, 55, 56, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
1398         87, 88, 89, 90, 91, 92, 93, 94
1399 };
1400
1401 static const unsigned int rtc_3516_pins[] = { 0, 43, 22 };
1402
1403 static const unsigned int power_3516_pins[] = { 20, 83, 40, 41, 60, 61, 62 };
1404
1405 static const unsigned int cir_3516_pins[] = { 85, 64, 82 };
1406
1407 static const unsigned int system_3516_pins[] = {
1408         332, 392, 372, 373, 393, 352, 331, 388, 397, 77
1409 };
1410
1411 static const unsigned int vcontrol_3516_pins[] = { 86, 81, 80 };
1412
1413 static const unsigned int ice_3516_pins[] = { 340, 341, 303, 322, 380, 284, 343 };
1414
1415 static const unsigned int ide_3516_pins[] = {
1416         200, 201, 204, 220, 221, 222, 223, 224, 240, 241, 242, 243, 244, 260,
1417         261, 262, 263, 264, 280, 281, 282, 283, 300, 301, 302, 320, 321, 360
1418 };
1419
1420 static const unsigned int sata_3516_pins[] = {
1421         100, 101, 102, 103, 104, 120, 121, 122, 123, 124, 140, 141, 142, 143,
1422         144, 160, 161, 162, 163, 180, 181, 182, 183, 202
1423 };
1424
1425 static const unsigned int usb_3516_pins[] = {
1426         305, 324, 344, 362, 363, 364, 365, 366, 381, 382, 383, 384, 385
1427 };
1428
1429 /* GMII, ethernet pins */
1430 static const unsigned int gmii_3516_pins[] = {
1431         306, 307, 308, 309, 310, 325, 326, 327, 328, 329, 330, 345, 346, 347,
1432         348, 349, 350, 351, 367, 368, 369, 370, 371, 386, 387, 389, 390, 391
1433 };
1434
1435 static const unsigned int pci_3516_pins[] = {
1436         17, 18, 19, 39, 58, 59, 78, 79, 96, 97, 98, 99, 115, 116, 117, 118,
1437         119, 135, 136, 137, 138, 139, 155, 156, 157, 158, 159, 175, 176, 177,
1438         178, 179, 195, 196, 197, 198, 199, 215, 216, 217, 218, 219, 235, 236,
1439         237, 238, 239, 255, 256, 257, 258, 259, 277, 278, 279, 299
1440 };
1441
1442 /*
1443  * Apparently the LPC interface is using the PCICLK for the clocking so
1444  * PCI needs to be active at the same time.
1445  */
1446 static const unsigned int lpc_3516_pins[] = {
1447         355, /* LPC_LAD[0] */
1448         356, /* LPC_SERIRQ */
1449         377, /* LPC_LAD[2] */
1450         398, /* LPC_LFRAME# */
1451         316, /* LPC_LAD[3] */
1452         399, /* LPC_LAD[1] */
1453 };
1454
1455 /* Character LCD */
1456 static const unsigned int lcd_3516_pins[] = {
1457         391, 351, 310, 371, 353, 311, 394, 374, 314, 359, 339
1458 };
1459
1460 static const unsigned int ssp_3516_pins[] = {
1461         355, /* SSP_97RST# SSP AC97 Reset, active low */
1462         356, /* SSP_FSC */
1463         377, /* SSP_ECLK */
1464         398, /* SSP_TXD */
1465         316, /* SSP_RXD */
1466         399, /* SSP_SCLK */
1467 };
1468
1469 static const unsigned int uart_rxtx_3516_pins[] = {
1470         313, /* UART_SIN serial input, RX */
1471         335, /* UART_SOUT serial output, TX */
1472 };
1473
1474 static const unsigned int uart_modem_3516_pins[] = {
1475         355, /* UART_NDCD DCD carrier detect */
1476         356, /* UART_NDTR DTR data terminal ready */
1477         377, /* UART_NDSR DSR data set ready */
1478         398, /* UART_NRTS RTS request to send */
1479         316, /* UART_NCTS CTS clear to send */
1480         399, /* UART_NRI RI ring indicator */
1481 };
1482
1483 static const unsigned int tvc_3516_pins[] = {
1484         353, /* TVC_DATA[0] */
1485         311, /* TVC_DATA[1] */
1486         394, /* TVC_DATA[2] */
1487         374, /* TVC_DATA[3] */
1488         354, /* TVC_DATA[4] */
1489         395, /* TVC_DATA[5] */
1490         312, /* TVC_DATA[6] */
1491         334, /* TVC_DATA[7] */
1492 };
1493
1494 static const unsigned int tvc_clk_3516_pins[] = {
1495         333, /* TVC_CLK */
1496 };
1497
1498 /* NAND flash pins */
1499 static const unsigned int nflash_3516_pins[] = {
1500         243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283,
1501         302, 321, 337, 358, 295, 359, 339, 275, 298
1502 };
1503
1504 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1505 static const unsigned int pflash_3516_pins[] = {
1506         221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300,
1507         263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318,
1508         276, 319, 275, 298
1509 };
1510
1511 /*
1512  * The parallel flash can be set up in a 26-bit address bus mode exposing
1513  * A[0-15] (A[15] takes the place of ALE), but it has the
1514  * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
1515  * used at the same time.
1516  */
1517 static const unsigned int pflash_3516_pins_extended[] = {
1518         221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300,
1519         263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318,
1520         276, 319, 275, 298,
1521         /* The extra pins */
1522         349, 308, 369, 389, 329, 350, 370, 309, 390, 391, 351, 310, 371, 330,
1523         333
1524 };
1525
1526 /* Serial flash pins CE0, CE1, DI, DO, CK */
1527 static const unsigned int sflash_3516_pins[] = { 296, 338, 295, 359, 339 };
1528
1529 /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */
1530 static const unsigned int gpio0a_3516_pins[] = { 354, 395, 312, 334 };
1531
1532 /* The GPIO0B (5-7) pins overlap with ICE */
1533 static const unsigned int gpio0b_3516_pins[] = { 375, 396, 376 };
1534
1535 /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */
1536 static const unsigned int gpio0c_3516_pins[] = { 355, 356, 377, 398, 316, 399 };
1537
1538 /* The GPIO0D (9,10) pins overlap with UART RX/TX */
1539 static const unsigned int gpio0d_3516_pins[] = { 313, 335 };
1540
1541 /* The GPIO0E (16) pins overlap with LCD */
1542 static const unsigned int gpio0e_3516_pins[] = { 314 };
1543
1544 /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */
1545 static const unsigned int gpio0f_3516_pins[] = { 337, 358 };
1546
1547 /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */
1548 static const unsigned int gpio0g_3516_pins[] = { 317, 379, 297, 318, 276, 319 };
1549
1550 /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */
1551 static const unsigned int gpio0h_3516_pins[] = { 296, 338 };
1552
1553 /* The GPIO0I (23) pins overlap with all flash */
1554 static const unsigned int gpio0i_3516_pins[] = { 295 };
1555
1556 /* The GPIO0J (24,25) pins overlap with all flash and LCD */
1557 static const unsigned int gpio0j_3516_pins[] = { 359, 339 };
1558
1559 /* The GPIO0K (30,31) pins overlap with NAND flash */
1560 static const unsigned int gpio0k_3516_pins[] = { 275, 298 };
1561
1562 /* The GPIO0L (0) pins overlap with TVC_CLK */
1563 static const unsigned int gpio0l_3516_pins[] = { 333 };
1564
1565 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
1566 static const unsigned int gpio1a_3516_pins[] = { 221, 200, 222, 201, 220 };
1567
1568 /* The GPIO1B (5-10,27) pins overlap with just IDE */
1569 static const unsigned int gpio1b_3516_pins[] = { 241, 223, 240, 204, 242, 244, 360 };
1570
1571 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
1572 static const unsigned int gpio1c_3516_pins[] = {
1573         243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283,
1574         302, 321
1575 };
1576
1577 /* The GPIO1D (28-31) pins overlap with TVC */
1578 static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 };
1579
1580 /* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */
1581 static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 };
1582
1583 /* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */
1584 static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 };
1585
1586 /* The GPIO2C (8-31) pins overlap with PCI */
1587 static const unsigned int gpio2c_3516_pins[] = {
1588         259, 237, 238, 239, 215, 216, 217, 218, 177, 159, 158, 175, 176, 139,
1589         157, 138, 137, 156, 118, 155, 99, 98, 136, 117
1590 };
1591
1592 /* Groups for the 3516 SoC/package */
1593 static const struct gemini_pin_group gemini_3516_pin_groups[] = {
1594         {
1595                 .name = "gndgrp",
1596                 .pins = gnd_3516_pins,
1597                 .num_pins = ARRAY_SIZE(gnd_3516_pins),
1598         },
1599         {
1600                 .name = "dramgrp",
1601                 .pins = dram_3516_pins,
1602                 .num_pins = ARRAY_SIZE(dram_3516_pins),
1603                 .mask = DRAM_PADS_POWERDOWN,
1604         },
1605         {
1606                 .name = "rtcgrp",
1607                 .pins = rtc_3516_pins,
1608                 .num_pins = ARRAY_SIZE(rtc_3516_pins),
1609         },
1610         {
1611                 .name = "powergrp",
1612                 .pins = power_3516_pins,
1613                 .num_pins = ARRAY_SIZE(power_3516_pins),
1614         },
1615         {
1616                 .name = "cirgrp",
1617                 .pins = cir_3516_pins,
1618                 .num_pins = ARRAY_SIZE(cir_3516_pins),
1619         },
1620         {
1621                 .name = "systemgrp",
1622                 .pins = system_3516_pins,
1623                 .num_pins = ARRAY_SIZE(system_3516_pins),
1624         },
1625         {
1626                 .name = "vcontrolgrp",
1627                 .pins = vcontrol_3516_pins,
1628                 .num_pins = ARRAY_SIZE(vcontrol_3516_pins),
1629         },
1630         {
1631                 .name = "icegrp",
1632                 .pins = ice_3516_pins,
1633                 .num_pins = ARRAY_SIZE(ice_3516_pins),
1634                 /* Conflict with some GPIO groups */
1635         },
1636         {
1637                 .name = "idegrp",
1638                 .pins = ide_3516_pins,
1639                 .num_pins = ARRAY_SIZE(ide_3516_pins),
1640                 /* Conflict with all flash usage */
1641                 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
1642                         PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
1643         },
1644         {
1645                 .name = "satagrp",
1646                 .pins = sata_3516_pins,
1647                 .num_pins = ARRAY_SIZE(sata_3516_pins),
1648         },
1649         {
1650                 .name = "usbgrp",
1651                 .pins = usb_3516_pins,
1652                 .num_pins = ARRAY_SIZE(usb_3516_pins),
1653         },
1654         {
1655                 .name = "gmiigrp",
1656                 .pins = gmii_3516_pins,
1657                 .num_pins = ARRAY_SIZE(gmii_3516_pins),
1658         },
1659         {
1660                 .name = "pcigrp",
1661                 .pins = pci_3516_pins,
1662                 .num_pins = ARRAY_SIZE(pci_3516_pins),
1663                 /* Conflict only with GPIO2 */
1664                 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
1665         },
1666         {
1667                 .name = "lpcgrp",
1668                 .pins = lpc_3516_pins,
1669                 .num_pins = ARRAY_SIZE(lpc_3516_pins),
1670                 /* Conflict with SSP */
1671                 .mask = SSP_PADS_ENABLE,
1672                 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,
1673         },
1674         {
1675                 .name = "lcdgrp",
1676                 .pins = lcd_3516_pins,
1677                 .num_pins = ARRAY_SIZE(lcd_3516_pins),
1678                 .mask = TVC_PADS_ENABLE,
1679                 .value = LCD_PADS_ENABLE,
1680         },
1681         {
1682                 .name = "sspgrp",
1683                 .pins = ssp_3516_pins,
1684                 .num_pins = ARRAY_SIZE(ssp_3516_pins),
1685                 /* Conflict with LPC */
1686                 .mask = LPC_PADS_ENABLE,
1687                 .value = SSP_PADS_ENABLE,
1688         },
1689         {
1690                 .name = "uartrxtxgrp",
1691                 .pins = uart_rxtx_3516_pins,
1692                 .num_pins = ARRAY_SIZE(uart_rxtx_3516_pins),
1693                 /* No conflicts except GPIO */
1694         },
1695         {
1696                 .name = "uartmodemgrp",
1697                 .pins = uart_modem_3516_pins,
1698                 .num_pins = ARRAY_SIZE(uart_modem_3516_pins),
1699                 /*
1700                  * Conflict with LPC and SSP,
1701                  * so when those are both disabled, modem UART can thrive.
1702                  */
1703                 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
1704         },
1705         {
1706                 .name = "tvcgrp",
1707                 .pins = tvc_3516_pins,
1708                 .num_pins = ARRAY_SIZE(tvc_3516_pins),
1709                 /* Conflict with character LCD */
1710                 .mask = LCD_PADS_ENABLE,
1711                 .value = TVC_PADS_ENABLE,
1712         },
1713         {
1714                 .name = "tvcclkgrp",
1715                 .pins = tvc_clk_3516_pins,
1716                 .num_pins = ARRAY_SIZE(tvc_clk_3516_pins),
1717                 .value = TVC_CLK_PAD_ENABLE,
1718         },
1719         /*
1720          * The construction is done such that it is possible to use a serial
1721          * flash together with a NAND or parallel (NOR) flash, but it is not
1722          * possible to use NAND and parallel flash together. To use serial
1723          * flash with one of the two others, the muxbits need to be flipped
1724          * around before any access.
1725          */
1726         {
1727                 .name = "nflashgrp",
1728                 .pins = nflash_3516_pins,
1729                 .num_pins = ARRAY_SIZE(nflash_3516_pins),
1730                 /* Conflict with IDE, parallel and serial flash */
1731                 .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE,
1732                 .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
1733         },
1734         {
1735                 .name = "pflashgrp",
1736                 .pins = pflash_3516_pins,
1737                 .num_pins = ARRAY_SIZE(pflash_3516_pins),
1738                 /* Conflict with IDE, NAND and serial flash */
1739                 .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
1740                 .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE,
1741         },
1742         {
1743                 .name = "sflashgrp",
1744                 .pins = sflash_3516_pins,
1745                 .num_pins = ARRAY_SIZE(sflash_3516_pins),
1746                 /* Conflict with IDE, NAND and parallel flash */
1747                 .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
1748                 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
1749         },
1750         {
1751                 .name = "gpio0agrp",
1752                 .pins = gpio0a_3516_pins,
1753                 .num_pins = ARRAY_SIZE(gpio0a_3516_pins),
1754                 /* Conflict with TVC and ICE */
1755                 .mask = TVC_PADS_ENABLE,
1756         },
1757         {
1758                 .name = "gpio0bgrp",
1759                 .pins = gpio0b_3516_pins,
1760                 .num_pins = ARRAY_SIZE(gpio0b_3516_pins),
1761                 /* Conflict with ICE */
1762         },
1763         {
1764                 .name = "gpio0cgrp",
1765                 .pins = gpio0c_3516_pins,
1766                 .num_pins = ARRAY_SIZE(gpio0c_3516_pins),
1767                 /* Conflict with LPC, UART and SSP */
1768                 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
1769         },
1770         {
1771                 .name = "gpio0dgrp",
1772                 .pins = gpio0d_3516_pins,
1773                 .num_pins = ARRAY_SIZE(gpio0d_3516_pins),
1774                 /* Conflict with UART */
1775         },
1776         {
1777                 .name = "gpio0egrp",
1778                 .pins = gpio0e_3516_pins,
1779                 .num_pins = ARRAY_SIZE(gpio0e_3516_pins),
1780                 /* Conflict with LCD */
1781                 .mask = LCD_PADS_ENABLE,
1782         },
1783         {
1784                 .name = "gpio0fgrp",
1785                 .pins = gpio0f_3516_pins,
1786                 .num_pins = ARRAY_SIZE(gpio0f_3516_pins),
1787                 /* Conflict with NAND flash */
1788                 .value = NAND_PADS_DISABLE,
1789         },
1790         {
1791                 .name = "gpio0ggrp",
1792                 .pins = gpio0g_3516_pins,
1793                 .num_pins = ARRAY_SIZE(gpio0g_3516_pins),
1794                 /* Conflict with parallel flash */
1795                 .value = PFLASH_PADS_DISABLE,
1796         },
1797         {
1798                 .name = "gpio0hgrp",
1799                 .pins = gpio0h_3516_pins,
1800                 .num_pins = ARRAY_SIZE(gpio0h_3516_pins),
1801                 /* Conflict with serial flash */
1802                 .value = SFLASH_PADS_DISABLE,
1803         },
1804         {
1805                 .name = "gpio0igrp",
1806                 .pins = gpio0i_3516_pins,
1807                 .num_pins = ARRAY_SIZE(gpio0i_3516_pins),
1808                 /* Conflict with all flash */
1809                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
1810                         SFLASH_PADS_DISABLE,
1811         },
1812         {
1813                 .name = "gpio0jgrp",
1814                 .pins = gpio0j_3516_pins,
1815                 .num_pins = ARRAY_SIZE(gpio0j_3516_pins),
1816                 /* Conflict with all flash and LCD */
1817                 .mask = LCD_PADS_ENABLE,
1818                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
1819                         SFLASH_PADS_DISABLE,
1820         },
1821         {
1822                 .name = "gpio0kgrp",
1823                 .pins = gpio0k_3516_pins,
1824                 .num_pins = ARRAY_SIZE(gpio0k_3516_pins),
1825                 /* Conflict with parallel and NAND flash */
1826                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
1827         },
1828         {
1829                 .name = "gpio0lgrp",
1830                 .pins = gpio0l_3516_pins,
1831                 .num_pins = ARRAY_SIZE(gpio0l_3516_pins),
1832                 /* Conflict with TVE CLK */
1833                 .mask = TVC_CLK_PAD_ENABLE,
1834         },
1835         {
1836                 .name = "gpio1agrp",
1837                 .pins = gpio1a_3516_pins,
1838                 .num_pins = ARRAY_SIZE(gpio1a_3516_pins),
1839                 /* Conflict with IDE and parallel flash */
1840                 .mask = IDE_PADS_ENABLE,
1841                 .value = PFLASH_PADS_DISABLE,
1842         },
1843         {
1844                 .name = "gpio1bgrp",
1845                 .pins = gpio1b_3516_pins,
1846                 .num_pins = ARRAY_SIZE(gpio1b_3516_pins),
1847                 /* Conflict with IDE only */
1848                 .mask = IDE_PADS_ENABLE,
1849         },
1850         {
1851                 .name = "gpio1cgrp",
1852                 .pins = gpio1c_3516_pins,
1853                 .num_pins = ARRAY_SIZE(gpio1c_3516_pins),
1854                 /* Conflict with IDE, parallel and NAND flash */
1855                 .mask = IDE_PADS_ENABLE,
1856                 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
1857         },
1858         {
1859                 .name = "gpio1dgrp",
1860                 .pins = gpio1d_3516_pins,
1861                 .num_pins = ARRAY_SIZE(gpio1d_3516_pins),
1862                 /* Conflict with TVC */
1863                 .mask = TVC_PADS_ENABLE,
1864         },
1865         {
1866                 .name = "gpio2agrp",
1867                 .pins = gpio2a_3516_pins,
1868                 .num_pins = ARRAY_SIZE(gpio2a_3516_pins),
1869                 /* Conflict with GMII and extended parallel flash */
1870         },
1871         {
1872                 .name = "gpio2bgrp",
1873                 .pins = gpio2b_3516_pins,
1874                 .num_pins = ARRAY_SIZE(gpio2b_3516_pins),
1875                 /* Conflict with GMII, extended parallel flash and LCD */
1876                 .mask = LCD_PADS_ENABLE,
1877         },
1878         {
1879                 .name = "gpio2cgrp",
1880                 .pins = gpio2c_3516_pins,
1881                 .num_pins = ARRAY_SIZE(gpio2c_3516_pins),
1882                 /* Conflict with PCI */
1883                 .mask = PCI_PADS_ENABLE,
1884         },
1885 };
1886
1887 static int gemini_get_groups_count(struct pinctrl_dev *pctldev)
1888 {
1889         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1890
1891         if (pmx->is_3512)
1892                 return ARRAY_SIZE(gemini_3512_pin_groups);
1893         if (pmx->is_3516)
1894                 return ARRAY_SIZE(gemini_3516_pin_groups);
1895         return 0;
1896 }
1897
1898 static const char *gemini_get_group_name(struct pinctrl_dev *pctldev,
1899                                          unsigned int selector)
1900 {
1901         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1902
1903         if (pmx->is_3512)
1904                 return gemini_3512_pin_groups[selector].name;
1905         if (pmx->is_3516)
1906                 return gemini_3516_pin_groups[selector].name;
1907         return NULL;
1908 }
1909
1910 static int gemini_get_group_pins(struct pinctrl_dev *pctldev,
1911                                  unsigned int selector,
1912                                  const unsigned int **pins,
1913                                  unsigned int *num_pins)
1914 {
1915         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1916
1917         /* The special case with the 3516 flash pin */
1918         if (pmx->flash_pin &&
1919             pmx->is_3512 &&
1920             !strcmp(gemini_3512_pin_groups[selector].name, "pflashgrp")) {
1921                 *pins = pflash_3512_pins_extended;
1922                 *num_pins = ARRAY_SIZE(pflash_3512_pins_extended);
1923                 return 0;
1924         }
1925         if (pmx->flash_pin &&
1926             pmx->is_3516 &&
1927             !strcmp(gemini_3516_pin_groups[selector].name, "pflashgrp")) {
1928                 *pins = pflash_3516_pins_extended;
1929                 *num_pins = ARRAY_SIZE(pflash_3516_pins_extended);
1930                 return 0;
1931         }
1932         if (pmx->is_3512) {
1933                 *pins = gemini_3512_pin_groups[selector].pins;
1934                 *num_pins = gemini_3512_pin_groups[selector].num_pins;
1935         }
1936         if (pmx->is_3516) {
1937                 *pins = gemini_3516_pin_groups[selector].pins;
1938                 *num_pins = gemini_3516_pin_groups[selector].num_pins;
1939         }
1940         return 0;
1941 }
1942
1943 static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1944                                 unsigned int offset)
1945 {
1946         seq_printf(s, " " DRIVER_NAME);
1947 }
1948
1949 static int gemini_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1950                                             struct device_node *np,
1951                                             struct pinctrl_map **map,
1952                                             unsigned int *reserved_maps,
1953                                             unsigned int *num_maps)
1954 {
1955         int ret;
1956         const char *function = NULL;
1957         const char *group;
1958         struct property *prop;
1959
1960         ret = of_property_read_string(np, "function", &function);
1961         if (ret < 0)
1962                 return ret;
1963
1964         ret = of_property_count_strings(np, "groups");
1965         if (ret < 0)
1966                 return ret;
1967
1968         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
1969                                         num_maps, ret);
1970         if (ret < 0)
1971                 return ret;
1972
1973         of_property_for_each_string(np, "groups", prop, group) {
1974                 ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps,
1975                                                 num_maps, group, function);
1976                 if (ret < 0)
1977                         return ret;
1978                 pr_debug("ADDED FUNCTION %s <-> GROUP %s\n",
1979                          function, group);
1980         }
1981
1982         return 0;
1983 }
1984
1985 static int gemini_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1986                                 struct device_node *np_config,
1987                                 struct pinctrl_map **map,
1988                                 unsigned int *num_maps)
1989 {
1990         unsigned int reserved_maps = 0;
1991         struct device_node *np;
1992         int ret;
1993
1994         *map = NULL;
1995         *num_maps = 0;
1996
1997         for_each_child_of_node(np_config, np) {
1998                 ret = gemini_pinctrl_dt_subnode_to_map(pctldev, np, map,
1999                                         &reserved_maps, num_maps);
2000                 if (ret < 0) {
2001                         pinctrl_utils_free_map(pctldev, *map, *num_maps);
2002                         return ret;
2003                 }
2004         }
2005
2006         return 0;
2007 };
2008
2009 static const struct pinctrl_ops gemini_pctrl_ops = {
2010         .get_groups_count = gemini_get_groups_count,
2011         .get_group_name = gemini_get_group_name,
2012         .get_group_pins = gemini_get_group_pins,
2013         .pin_dbg_show = gemini_pin_dbg_show,
2014         .dt_node_to_map = gemini_pinctrl_dt_node_to_map,
2015         .dt_free_map = pinctrl_utils_free_map,
2016 };
2017
2018 /**
2019  * struct gemini_pmx_func - describes Gemini pinmux functions
2020  * @name: the name of this specific function
2021  * @groups: corresponding pin groups
2022  */
2023 struct gemini_pmx_func {
2024         const char *name;
2025         const char * const *groups;
2026         const unsigned int num_groups;
2027 };
2028
2029 static const char * const dramgrps[] = { "dramgrp" };
2030 static const char * const rtcgrps[] = { "rtcgrp" };
2031 static const char * const powergrps[] = { "powergrp" };
2032 static const char * const cirgrps[] = { "cirgrp" };
2033 static const char * const systemgrps[] = { "systemgrp" };
2034 static const char * const vcontrolgrps[] = { "vcontrolgrp" };
2035 static const char * const icegrps[] = { "icegrp" };
2036 static const char * const idegrps[] = { "idegrp" };
2037 static const char * const satagrps[] = { "satagrp" };
2038 static const char * const usbgrps[] = { "usbgrp" };
2039 static const char * const gmiigrps[] = { "gmiigrp" };
2040 static const char * const pcigrps[] = { "pcigrp" };
2041 static const char * const lpcgrps[] = { "lpcgrp" };
2042 static const char * const lcdgrps[] = { "lcdgrp" };
2043 static const char * const sspgrps[] = { "sspgrp" };
2044 static const char * const uartgrps[] = { "uartrxtxgrp", "uartmodemgrp" };
2045 static const char * const tvcgrps[] = { "tvcgrp" };
2046 static const char * const nflashgrps[] = { "nflashgrp" };
2047 static const char * const pflashgrps[] = { "pflashgrp", "pflashextgrp" };
2048 static const char * const sflashgrps[] = { "sflashgrp" };
2049 static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp",
2050                                           "gpio0dgrp", "gpio0egrp", "gpio0fgrp",
2051                                           "gpio0ggrp", "gpio0hgrp", "gpio0igrp",
2052                                           "gpio0jgrp", "gpio0kgrp" };
2053 static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp",
2054                                           "gpio1dgrp" };
2055 static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" };
2056
2057 static const struct gemini_pmx_func gemini_pmx_functions[] = {
2058         {
2059                 .name = "dram",
2060                 .groups = dramgrps,
2061                 .num_groups = ARRAY_SIZE(idegrps),
2062         },
2063         {
2064                 .name = "rtc",
2065                 .groups = rtcgrps,
2066                 .num_groups = ARRAY_SIZE(rtcgrps),
2067         },
2068         {
2069                 .name = "power",
2070                 .groups = powergrps,
2071                 .num_groups = ARRAY_SIZE(powergrps),
2072         },
2073         {
2074                 /* This function is strictly unavailable on 3512 */
2075                 .name = "cir",
2076                 .groups = cirgrps,
2077                 .num_groups = ARRAY_SIZE(cirgrps),
2078         },
2079         {
2080                 .name = "system",
2081                 .groups = systemgrps,
2082                 .num_groups = ARRAY_SIZE(systemgrps),
2083         },
2084         {
2085                 .name = "vcontrol",
2086                 .groups = vcontrolgrps,
2087                 .num_groups = ARRAY_SIZE(vcontrolgrps),
2088         },
2089         {
2090                 .name = "ice",
2091                 .groups = icegrps,
2092                 .num_groups = ARRAY_SIZE(icegrps),
2093         },
2094         {
2095                 .name = "ide",
2096                 .groups = idegrps,
2097                 .num_groups = ARRAY_SIZE(idegrps),
2098         },
2099         {
2100                 .name = "sata",
2101                 .groups = satagrps,
2102                 .num_groups = ARRAY_SIZE(satagrps),
2103         },
2104         {
2105                 .name = "pci",
2106                 .groups = pcigrps,
2107                 .num_groups = ARRAY_SIZE(pcigrps),
2108         },
2109         {
2110                 .name = "lpc",
2111                 .groups = lpcgrps,
2112                 .num_groups = ARRAY_SIZE(lpcgrps),
2113         },
2114         {
2115                 .name = "lcd",
2116                 .groups = lcdgrps,
2117                 .num_groups = ARRAY_SIZE(lcdgrps),
2118         },
2119         {
2120                 .name = "ssp",
2121                 .groups = sspgrps,
2122                 .num_groups = ARRAY_SIZE(sspgrps),
2123         },
2124         {
2125                 .name = "uart",
2126                 .groups = uartgrps,
2127                 .num_groups = ARRAY_SIZE(uartgrps),
2128         },
2129         {
2130                 .name = "tvc",
2131                 .groups = tvcgrps,
2132                 .num_groups = ARRAY_SIZE(tvcgrps),
2133         },
2134         {
2135                 .name = "nflash",
2136                 .groups = nflashgrps,
2137                 .num_groups = ARRAY_SIZE(nflashgrps),
2138         },
2139         {
2140                 .name = "pflash",
2141                 .groups = pflashgrps,
2142                 .num_groups = ARRAY_SIZE(pflashgrps),
2143         },
2144         {
2145                 .name = "sflash",
2146                 .groups = sflashgrps,
2147                 .num_groups = ARRAY_SIZE(sflashgrps),
2148         },
2149         {
2150                 .name = "gpio0",
2151                 .groups = gpio0grps,
2152                 .num_groups = ARRAY_SIZE(gpio0grps),
2153         },
2154         {
2155                 .name = "gpio1",
2156                 .groups = gpio1grps,
2157                 .num_groups = ARRAY_SIZE(gpio1grps),
2158         },
2159         {
2160                 .name = "gpio2",
2161                 .groups = gpio2grps,
2162                 .num_groups = ARRAY_SIZE(gpio2grps),
2163         },
2164 };
2165
2166
2167 static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev,
2168                               unsigned int selector,
2169                               unsigned int group)
2170 {
2171         struct gemini_pmx *pmx;
2172         const struct gemini_pmx_func *func;
2173         const struct gemini_pin_group *grp;
2174         u32 before, after, expected;
2175         unsigned long tmp;
2176         int i;
2177
2178         pmx = pinctrl_dev_get_drvdata(pctldev);
2179
2180         func = &gemini_pmx_functions[selector];
2181         if (pmx->is_3512)
2182                 grp = &gemini_3512_pin_groups[group];
2183         else if (pmx->is_3516)
2184                 grp = &gemini_3516_pin_groups[group];
2185         else {
2186                 dev_err(pmx->dev, "invalid SoC type\n");
2187                 return -ENODEV;
2188         }
2189
2190         dev_info(pmx->dev,
2191                  "ACTIVATE function \"%s\" with group \"%s\"\n",
2192                  func->name, grp->name);
2193
2194         regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before);
2195         regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL,
2196                            grp->mask | grp->value,
2197                            grp->value);
2198         regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after);
2199
2200         /* Which bits changed */
2201         before &= PADS_MASK;
2202         after &= PADS_MASK;
2203         expected = before &= ~grp->mask;
2204         expected |= grp->value;
2205         expected &= PADS_MASK;
2206
2207         /* Print changed states */
2208         tmp = grp->mask;
2209         for_each_set_bit(i, &tmp, PADS_MAXBIT) {
2210                 bool enabled = !(i > 3);
2211
2212                 /* Did not go low though it should */
2213                 if (after & BIT(i)) {
2214                         dev_err(pmx->dev,
2215                                 "pin group %s could not be %s: "
2216                                 "probably a hardware limitation\n",
2217                                 gemini_padgroups[i],
2218                                 enabled ? "enabled" : "disabled");
2219                         dev_err(pmx->dev,
2220                                 "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
2221                                 before, after, expected);
2222                 } else {
2223                         dev_info(pmx->dev,
2224                                  "padgroup %s %s\n",
2225                                  gemini_padgroups[i],
2226                                  enabled ? "enabled" : "disabled");
2227                 }
2228         }
2229
2230         tmp = grp->value;
2231         for_each_set_bit(i, &tmp, PADS_MAXBIT) {
2232                 bool enabled = (i > 3);
2233
2234                 /* Did not go high though it should */
2235                 if (!(after & BIT(i))) {
2236                         dev_err(pmx->dev,
2237                                 "pin group %s could not be %s: "
2238                                 "probably a hardware limitation\n",
2239                                 gemini_padgroups[i],
2240                                 enabled ? "enabled" : "disabled");
2241                         dev_err(pmx->dev,
2242                                 "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
2243                                 before, after, expected);
2244                 } else {
2245                         dev_info(pmx->dev,
2246                                  "padgroup %s %s\n",
2247                                  gemini_padgroups[i],
2248                                  enabled ? "enabled" : "disabled");
2249                 }
2250         }
2251
2252         return 0;
2253 }
2254
2255 static int gemini_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2256 {
2257         return ARRAY_SIZE(gemini_pmx_functions);
2258 }
2259
2260 static const char *gemini_pmx_get_func_name(struct pinctrl_dev *pctldev,
2261                                             unsigned int selector)
2262 {
2263         return gemini_pmx_functions[selector].name;
2264 }
2265
2266 static int gemini_pmx_get_groups(struct pinctrl_dev *pctldev,
2267                                  unsigned int selector,
2268                                  const char * const **groups,
2269                                  unsigned int * const num_groups)
2270 {
2271         *groups = gemini_pmx_functions[selector].groups;
2272         *num_groups = gemini_pmx_functions[selector].num_groups;
2273         return 0;
2274 }
2275
2276 static const struct pinmux_ops gemini_pmx_ops = {
2277         .get_functions_count = gemini_pmx_get_funcs_count,
2278         .get_function_name = gemini_pmx_get_func_name,
2279         .get_function_groups = gemini_pmx_get_groups,
2280         .set_mux = gemini_pmx_set_mux,
2281 };
2282
2283 static struct pinctrl_desc gemini_pmx_desc = {
2284         .name = DRIVER_NAME,
2285         .pctlops = &gemini_pctrl_ops,
2286         .pmxops = &gemini_pmx_ops,
2287         .owner = THIS_MODULE,
2288 };
2289
2290 static int gemini_pmx_probe(struct platform_device *pdev)
2291 {
2292         struct gemini_pmx *pmx;
2293         struct regmap *map;
2294         struct device *dev = &pdev->dev;
2295         struct device *parent;
2296         unsigned long tmp;
2297         u32 val;
2298         int ret;
2299         int i;
2300
2301         /* Create state holders etc for this driver */
2302         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
2303         if (!pmx)
2304                 return -ENOMEM;
2305
2306         pmx->dev = &pdev->dev;
2307         parent = dev->parent;
2308         if (!parent) {
2309                 dev_err(dev, "no parent to pin controller\n");
2310                 return -ENODEV;
2311         }
2312         map = syscon_node_to_regmap(parent->of_node);
2313         if (IS_ERR(map)) {
2314                 dev_err(dev, "no syscon regmap\n");
2315                 return PTR_ERR(map);
2316         }
2317         pmx->map = map;
2318
2319         /* Check that regmap works at first call, then no more */
2320         ret = regmap_read(map, GLOBAL_WORD_ID, &val);
2321         if (ret) {
2322                 dev_err(dev, "cannot access regmap\n");
2323                 return ret;
2324         }
2325         val >>= 8;
2326         val &= 0xffff;
2327         if (val == 0x3512) {
2328                 pmx->is_3512 = true;
2329                 gemini_pmx_desc.pins = gemini_3512_pins;
2330                 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins);
2331                 dev_info(dev, "detected 3512 chip variant\n");
2332         } else if (val == 0x3516) {
2333                 pmx->is_3516 = true;
2334                 gemini_pmx_desc.pins = gemini_3516_pins;
2335                 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins);
2336                 dev_info(dev, "detected 3516 chip variant\n");
2337         } else {
2338                 dev_err(dev, "unknown chip ID: %04x\n", val);
2339                 return -ENODEV;
2340         }
2341
2342         ret = regmap_read(map, GLOBAL_MISC_CTRL, &val);
2343         dev_info(dev, "GLOBAL MISC CTRL at boot: 0x%08x\n", val);
2344         /* Mask off relevant pads */
2345         val &= PADS_MASK;
2346         /* Invert the meaning of the DRAM+flash pads */
2347         val ^= 0x0f;
2348         /* Print initial state */
2349         tmp = val;
2350         for_each_set_bit(i, &tmp, PADS_MAXBIT) {
2351                 dev_info(dev, "pad group %s %s\n", gemini_padgroups[i],
2352                          (val & BIT(i)) ? "enabled" : "disabled");
2353         }
2354
2355         /* Check if flash pin is set */
2356         regmap_read(map, GLOBAL_STATUS, &val);
2357         pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN);
2358         dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set");
2359
2360         pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx);
2361         if (IS_ERR(pmx->pctl)) {
2362                 dev_err(dev, "could not register pinmux driver\n");
2363                 return PTR_ERR(pmx->pctl);
2364         }
2365
2366         dev_info(dev, "initialized Gemini pin control driver\n");
2367
2368         return 0;
2369 }
2370
2371 static const struct of_device_id gemini_pinctrl_match[] = {
2372         { .compatible = "cortina,gemini-pinctrl" },
2373         {},
2374 };
2375
2376 static struct platform_driver gemini_pmx_driver = {
2377         .driver = {
2378                 .name = DRIVER_NAME,
2379                 .of_match_table = gemini_pinctrl_match,
2380         },
2381         .probe = gemini_pmx_probe,
2382 };
2383
2384 static int __init gemini_pmx_init(void)
2385 {
2386         return platform_driver_register(&gemini_pmx_driver);
2387 }
2388 arch_initcall(gemini_pmx_init);