drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/init.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43
  44 #include "core.h"
  45 #include "pinconf.h"
  46
  47 /* GPIO control registers */
  48 #define GPIO_SWPORT_DR          0x00
  49 #define GPIO_SWPORT_DDR         0x04
  50 #define GPIO_INTEN              0x30
  51 #define GPIO_INTMASK            0x34
  52 #define GPIO_INTTYPE_LEVEL      0x38
  53 #define GPIO_INT_POLARITY       0x3c
  54 #define GPIO_INT_STATUS         0x40
  55 #define GPIO_INT_RAWSTATUS      0x44
  56 #define GPIO_DEBOUNCE           0x48
  57 #define GPIO_PORTS_EOI          0x4c
  58 #define GPIO_EXT_PORT           0x50
  59 #define GPIO_LS_SYNC            0x60
  60
  61 enum rockchip_pinctrl_type {
  62         PX30,
  63         RV1108,
  64         RK2928,
  65         RK3066B,
  66         RK3128,
  67         RK3188,
  68         RK3288,
  69         RK3368,
  70         RK3399,
  71 };
  72
  73 /**
  74  * Encode variants of iomux registers into a type variable
  75  */
  76 #define IOMUX_GPIO_ONLY         BIT(0)
  77 #define IOMUX_WIDTH_4BIT        BIT(1)
  78 #define IOMUX_SOURCE_PMU        BIT(2)
  79 #define IOMUX_UNROUTED          BIT(3)
  80 #define IOMUX_WIDTH_3BIT        BIT(4)
  81
  82 /**
  83  * @type: iomux variant using IOMUX_* constants
  84  * @offset: if initialized to -1 it will be autocalculated, by specifying
  85  *          an initial offset value the relevant source offset can be reset
  86  *          to a new value for autocalculating the following iomux registers.
  87  */
  88 struct rockchip_iomux {
  89         int                             type;
  90         int                             offset;
  91 };
  92
  93 /**
  94  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  95  */
  96 enum rockchip_pin_drv_type {
  97         DRV_TYPE_IO_DEFAULT = 0,
  98         DRV_TYPE_IO_1V8_OR_3V0,
  99         DRV_TYPE_IO_1V8_ONLY,
 100         DRV_TYPE_IO_1V8_3V0_AUTO,
 101         DRV_TYPE_IO_3V3_ONLY,
 102         DRV_TYPE_MAX
 103 };
 104
 105 /**
 106  * enum type index corresponding to rockchip_pull_list arrays index.
 107  */
 108 enum rockchip_pin_pull_type {
 109         PULL_TYPE_IO_DEFAULT = 0,
 110         PULL_TYPE_IO_1V8_ONLY,
 111         PULL_TYPE_MAX
 112 };
 113
 114 /**
 115  * @drv_type: drive strength variant using rockchip_perpin_drv_type
 116  * @offset: if initialized to -1 it will be autocalculated, by specifying
 117  *          an initial offset value the relevant source offset can be reset
 118  *          to a new value for autocalculating the following drive strength
 119  *          registers. if used chips own cal_drv func instead to calculate
 120  *          registers offset, the variant could be ignored.
 121  */
 122 struct rockchip_drv {
 123         enum rockchip_pin_drv_type      drv_type;
 124         int                             offset;
 125 };
 126
 127 /**
 128  * @reg_base: register base of the gpio bank
 129  * @reg_pull: optional separate register for additional pull settings
 130  * @clk: clock of the gpio bank
 131  * @irq: interrupt of the gpio bank
 132  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 133  * @pin_base: first pin number
 134  * @nr_pins: number of pins in this bank
 135  * @name: name of the bank
 136  * @bank_num: number of the bank, to account for holes
 137  * @iomux: array describing the 4 iomux sources of the bank
 138  * @drv: array describing the 4 drive strength sources of the bank
 139  * @pull_type: array describing the 4 pull type sources of the bank
 140  * @valid: is all necessary information present
 141  * @of_node: dt node of this bank
 142  * @drvdata: common pinctrl basedata
 143  * @domain: irqdomain of the gpio bank
 144  * @gpio_chip: gpiolib chip
 145  * @grange: gpio range
 146  * @slock: spinlock for the gpio bank
 147  * @route_mask: bits describing the routing pins of per bank
 148  */
 149 struct rockchip_pin_bank {
 150         void __iomem                    *reg_base;
 151         struct regmap                   *regmap_pull;
 152         struct clk                      *clk;
 153         int                             irq;
 154         u32                             saved_masks;
 155         u32                             pin_base;
 156         u8                              nr_pins;
 157         char                            *name;
 158         u8                              bank_num;
 159         struct rockchip_iomux           iomux[4];
 160         struct rockchip_drv             drv[4];
 161         enum rockchip_pin_pull_type     pull_type[4];
 162         bool                            valid;
 163         struct device_node              *of_node;
 164         struct rockchip_pinctrl         *drvdata;
 165         struct irq_domain               *domain;
 166         struct gpio_chip                gpio_chip;
 167         struct pinctrl_gpio_range       grange;
 168         raw_spinlock_t                  slock;
 169         u32                             toggle_edge_mode;
 170         u32                             recalced_mask;
 171         u32                             route_mask;
 172 };
 173
 174 #define PIN_BANK(id, pins, label)                       \
 175         {                                               \
 176                 .bank_num       = id,                   \
 177                 .nr_pins        = pins,                 \
 178                 .name           = label,                \
 179                 .iomux          = {                     \
 180                         { .offset = -1 },               \
 181                         { .offset = -1 },               \
 182                         { .offset = -1 },               \
 183                         { .offset = -1 },               \
 184                 },                                      \
 185         }
 186
 187 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 188         {                                                               \
 189                 .bank_num       = id,                                   \
 190                 .nr_pins        = pins,                                 \
 191                 .name           = label,                                \
 192                 .iomux          = {                                     \
 193                         { .type = iom0, .offset = -1 },                 \
 194                         { .type = iom1, .offset = -1 },                 \
 195                         { .type = iom2, .offset = -1 },                 \
 196                         { .type = iom3, .offset = -1 },                 \
 197                 },                                                      \
 198         }
 199
 200 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
 201         {                                                               \
 202                 .bank_num       = id,                                   \
 203                 .nr_pins        = pins,                                 \
 204                 .name           = label,                                \
 205                 .iomux          = {                                     \
 206                         { .offset = -1 },                               \
 207                         { .offset = -1 },                               \
 208                         { .offset = -1 },                               \
 209                         { .offset = -1 },                               \
 210                 },                                                      \
 211                 .drv            = {                                     \
 212                         { .drv_type = type0, .offset = -1 },            \
 213                         { .drv_type = type1, .offset = -1 },            \
 214                         { .drv_type = type2, .offset = -1 },            \
 215                         { .drv_type = type3, .offset = -1 },            \
 216                 },                                                      \
 217         }
 218
 219 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,      \
 220                                       drv2, drv3, pull0, pull1,         \
 221                                       pull2, pull3)                     \
 222         {                                                               \
 223                 .bank_num       = id,                                   \
 224                 .nr_pins        = pins,                                 \
 225                 .name           = label,                                \
 226                 .iomux          = {                                     \
 227                         { .offset = -1 },                               \
 228                         { .offset = -1 },                               \
 229                         { .offset = -1 },                               \
 230                         { .offset = -1 },                               \
 231                 },                                                      \
 232                 .drv            = {                                     \
 233                         { .drv_type = drv0, .offset = -1 },             \
 234                         { .drv_type = drv1, .offset = -1 },             \
 235                         { .drv_type = drv2, .offset = -1 },             \
 236                         { .drv_type = drv3, .offset = -1 },             \
 237                 },                                                      \
 238                 .pull_type[0] = pull0,                                  \
 239                 .pull_type[1] = pull1,                                  \
 240                 .pull_type[2] = pull2,                                  \
 241                 .pull_type[3] = pull3,                                  \
 242         }
 243
 244 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 245                                         iom2, iom3, drv0, drv1, drv2,   \
 246                                         drv3, offset0, offset1,         \
 247                                         offset2, offset3)               \
 248         {                                                               \
 249                 .bank_num       = id,                                   \
 250                 .nr_pins        = pins,                                 \
 251                 .name           = label,                                \
 252                 .iomux          = {                                     \
 253                         { .type = iom0, .offset = -1 },                 \
 254                         { .type = iom1, .offset = -1 },                 \
 255                         { .type = iom2, .offset = -1 },                 \
 256                         { .type = iom3, .offset = -1 },                 \
 257                 },                                                      \
 258                 .drv            = {                                     \
 259                         { .drv_type = drv0, .offset = offset0 },        \
 260                         { .drv_type = drv1, .offset = offset1 },        \
 261                         { .drv_type = drv2, .offset = offset2 },        \
 262                         { .drv_type = drv3, .offset = offset3 },        \
 263                 },                                                      \
 264         }
 265
 266 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 267                                               label, iom0, iom1, iom2,  \
 268                                               iom3, drv0, drv1, drv2,   \
 269                                               drv3, offset0, offset1,   \
 270                                               offset2, offset3, pull0,  \
 271                                               pull1, pull2, pull3)      \
 272         {                                                               \
 273                 .bank_num       = id,                                   \
 274                 .nr_pins        = pins,                                 \
 275                 .name           = label,                                \
 276                 .iomux          = {                                     \
 277                         { .type = iom0, .offset = -1 },                 \
 278                         { .type = iom1, .offset = -1 },                 \
 279                         { .type = iom2, .offset = -1 },                 \
 280                         { .type = iom3, .offset = -1 },                 \
 281                 },                                                      \
 282                 .drv            = {                                     \
 283                         { .drv_type = drv0, .offset = offset0 },        \
 284                         { .drv_type = drv1, .offset = offset1 },        \
 285                         { .drv_type = drv2, .offset = offset2 },        \
 286                         { .drv_type = drv3, .offset = offset3 },        \
 287                 },                                                      \
 288                 .pull_type[0] = pull0,                                  \
 289                 .pull_type[1] = pull1,                                  \
 290                 .pull_type[2] = pull2,                                  \
 291                 .pull_type[3] = pull3,                                  \
 292         }
 293
 294 /**
 295  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 296  * @num: bank number.
 297  * @pin: pin number.
 298  * @bit: index at register.
 299  * @reg: register offset.
 300  * @mask: mask bit
 301  */
 302 struct rockchip_mux_recalced_data {
 303         u8 num;
 304         u8 pin;
 305         u32 reg;
 306         u8 bit;
 307         u8 mask;
 308 };
 309
 310 /**
 311  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 312  * @bank_num: bank number.
 313  * @pin: index at register or used to calc index.
 314  * @func: the min pin.
 315  * @route_offset: the max pin.
 316  * @route_val: the register offset.
 317  */
 318 struct rockchip_mux_route_data {
 319         u8 bank_num;
 320         u8 pin;
 321         u8 func;
 322         u32 route_offset;
 323         u32 route_val;
 324 };
 325
 326 /**
 327  */
 328 struct rockchip_pin_ctrl {
 329         struct rockchip_pin_bank        *pin_banks;
 330         u32                             nr_banks;
 331         u32                             nr_pins;
 332         char                            *label;
 333         enum rockchip_pinctrl_type      type;
 334         int                             grf_mux_offset;
 335         int                             pmu_mux_offset;
 336         int                             grf_drv_offset;
 337         int                             pmu_drv_offset;
 338         struct rockchip_mux_recalced_data *iomux_recalced;
 339         u32                             niomux_recalced;
 340         struct rockchip_mux_route_data *iomux_routes;
 341         u32                             niomux_routes;
 342
 343         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 344                                     int pin_num, struct regmap **regmap,
 345                                     int *reg, u8 *bit);
 346         void    (*drv_calc_reg)(struct rockchip_pin_bank *bank,
 347                                     int pin_num, struct regmap **regmap,
 348                                     int *reg, u8 *bit);
 349         int     (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
 350                                     int pin_num, struct regmap **regmap,
 351                                     int *reg, u8 *bit);
 352 };
 353
 354 struct rockchip_pin_config {
 355         unsigned int            func;
 356         unsigned long           *configs;
 357         unsigned int            nconfigs;
 358 };
 359
 360 /**
 361  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 362  * @name: name of the pin group, used to lookup the group.
 363  * @pins: the pins included in this group.
 364  * @npins: number of pins included in this group.
 365  * @func: the mux function number to be programmed when selected.
 366  * @configs: the config values to be set for each pin
 367  * @nconfigs: number of configs for each pin
 368  */
 369 struct rockchip_pin_group {
 370         const char                      *name;
 371         unsigned int                    npins;
 372         unsigned int                    *pins;
 373         struct rockchip_pin_config      *data;
 374 };
 375
 376 /**
 377  * struct rockchip_pmx_func: represent a pin function.
 378  * @name: name of the pin function, used to lookup the function.
 379  * @groups: one or more names of pin groups that provide this function.
 380  * @num_groups: number of groups included in @groups.
 381  */
 382 struct rockchip_pmx_func {
 383         const char              *name;
 384         const char              **groups;
 385         u8                      ngroups;
 386 };
 387
 388 struct rockchip_pinctrl {
 389         struct regmap                   *regmap_base;
 390         int                             reg_size;
 391         struct regmap                   *regmap_pull;
 392         struct regmap                   *regmap_pmu;
 393         struct device                   *dev;
 394         struct rockchip_pin_ctrl        *ctrl;
 395         struct pinctrl_desc             pctl;
 396         struct pinctrl_dev              *pctl_dev;
 397         struct rockchip_pin_group       *groups;
 398         unsigned int                    ngroups;
 399         struct rockchip_pmx_func        *functions;
 400         unsigned int                    nfunctions;
 401 };
 402
 403 static struct regmap_config rockchip_regmap_config = {
 404         .reg_bits = 32,
 405         .val_bits = 32,
 406         .reg_stride = 4,
 407 };
 408
 409 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
 410                                         const struct rockchip_pinctrl *info,
 411                                         const char *name)
 412 {
 413         int i;
 414
 415         for (i = 0; i < info->ngroups; i++) {
 416                 if (!strcmp(info->groups[i].name, name))
 417                         return &info->groups[i];
 418         }
 419
 420         return NULL;
 421 }
 422
 423 /*
 424  * given a pin number that is local to a pin controller, find out the pin bank
 425  * and the register base of the pin bank.
 426  */
 427 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 428                                                                 unsigned pin)
 429 {
 430         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 431
 432         while (pin >= (b->pin_base + b->nr_pins))
 433                 b++;
 434
 435         return b;
 436 }
 437
 438 static struct rockchip_pin_bank *bank_num_to_bank(
 439                                         struct rockchip_pinctrl *info,
 440                                         unsigned num)
 441 {
 442         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 443         int i;
 444
 445         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 446                 if (b->bank_num == num)
 447                         return b;
 448         }
 449
 450         return ERR_PTR(-EINVAL);
 451 }
 452
 453 /*
 454  * Pinctrl_ops handling
 455  */
 456
 457 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 458 {
 459         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 460
 461         return info->ngroups;
 462 }
 463
 464 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 465                                                         unsigned selector)
 466 {
 467         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 468
 469         return info->groups[selector].name;
 470 }
 471
 472 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 473                                       unsigned selector, const unsigned **pins,
 474                                       unsigned *npins)
 475 {
 476         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 477
 478         if (selector >= info->ngroups)
 479                 return -EINVAL;
 480
 481         *pins = info->groups[selector].pins;
 482         *npins = info->groups[selector].npins;
 483
 484         return 0;
 485 }
 486
 487 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 488                                  struct device_node *np,
 489                                  struct pinctrl_map **map, unsigned *num_maps)
 490 {
 491         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 492         const struct rockchip_pin_group *grp;
 493         struct pinctrl_map *new_map;
 494         struct device_node *parent;
 495         int map_num = 1;
 496         int i;
 497
 498         /*
 499          * first find the group of this node and check if we need to create
 500          * config maps for pins
 501          */
 502         grp = pinctrl_name_to_group(info, np->name);
 503         if (!grp) {
 504                 dev_err(info->dev, "unable to find group for node %s\n",
 505                         np->name);
 506                 return -EINVAL;
 507         }
 508
 509         map_num += grp->npins;
 510
 511         new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
 512         if (!new_map)
 513                 return -ENOMEM;
 514
 515         *map = new_map;
 516         *num_maps = map_num;
 517
 518         /* create mux map */
 519         parent = of_get_parent(np);
 520         if (!parent) {
 521                 kfree(new_map);
 522                 return -EINVAL;
 523         }
 524         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 525         new_map[0].data.mux.function = parent->name;
 526         new_map[0].data.mux.group = np->name;
 527         of_node_put(parent);
 528
 529         /* create config map */
 530         new_map++;
 531         for (i = 0; i < grp->npins; i++) {
 532                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 533                 new_map[i].data.configs.group_or_pin =
 534                                 pin_get_name(pctldev, grp->pins[i]);
 535                 new_map[i].data.configs.configs = grp->data[i].configs;
 536                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 537         }
 538
 539         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 540                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 541
 542         return 0;
 543 }
 544
 545 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 546                                     struct pinctrl_map *map, unsigned num_maps)
 547 {
 548         kfree(map);
 549 }
 550
 551 static const struct pinctrl_ops rockchip_pctrl_ops = {
 552         .get_groups_count       = rockchip_get_groups_count,
 553         .get_group_name         = rockchip_get_group_name,
 554         .get_group_pins         = rockchip_get_group_pins,
 555         .dt_node_to_map         = rockchip_dt_node_to_map,
 556         .dt_free_map            = rockchip_dt_free_map,
 557 };
 558
 559 /*
 560  * Hardware access
 561  */
 562
 563 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
 564         {
 565                 .num = 1,
 566                 .pin = 0,
 567                 .reg = 0x418,
 568                 .bit = 0,
 569                 .mask = 0x3
 570         }, {
 571                 .num = 1,
 572                 .pin = 1,
 573                 .reg = 0x418,
 574                 .bit = 2,
 575                 .mask = 0x3
 576         }, {
 577                 .num = 1,
 578                 .pin = 2,
 579                 .reg = 0x418,
 580                 .bit = 4,
 581                 .mask = 0x3
 582         }, {
 583                 .num = 1,
 584                 .pin = 3,
 585                 .reg = 0x418,
 586                 .bit = 6,
 587                 .mask = 0x3
 588         }, {
 589                 .num = 1,
 590                 .pin = 4,
 591                 .reg = 0x418,
 592                 .bit = 8,
 593                 .mask = 0x3
 594         }, {
 595                 .num = 1,
 596                 .pin = 5,
 597                 .reg = 0x418,
 598                 .bit = 10,
 599                 .mask = 0x3
 600         }, {
 601                 .num = 1,
 602                 .pin = 6,
 603                 .reg = 0x418,
 604                 .bit = 12,
 605                 .mask = 0x3
 606         }, {
 607                 .num = 1,
 608                 .pin = 7,
 609                 .reg = 0x418,
 610                 .bit = 14,
 611                 .mask = 0x3
 612         }, {
 613                 .num = 1,
 614                 .pin = 8,
 615                 .reg = 0x41c,
 616                 .bit = 0,
 617                 .mask = 0x3
 618         }, {
 619                 .num = 1,
 620                 .pin = 9,
 621                 .reg = 0x41c,
 622                 .bit = 2,
 623                 .mask = 0x3
 624         },
 625 };
 626
 627 static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
 628         {
 629                 .num = 2,
 630                 .pin = 20,
 631                 .reg = 0xe8,
 632                 .bit = 0,
 633                 .mask = 0x7
 634         }, {
 635                 .num = 2,
 636                 .pin = 21,
 637                 .reg = 0xe8,
 638                 .bit = 4,
 639                 .mask = 0x7
 640         }, {
 641                 .num = 2,
 642                 .pin = 22,
 643                 .reg = 0xe8,
 644                 .bit = 8,
 645                 .mask = 0x7
 646         }, {
 647                 .num = 2,
 648                 .pin = 23,
 649                 .reg = 0xe8,
 650                 .bit = 12,
 651                 .mask = 0x7
 652         }, {
 653                 .num = 2,
 654                 .pin = 24,
 655                 .reg = 0xd4,
 656                 .bit = 12,
 657                 .mask = 0x7
 658         },
 659 };
 660
 661 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 662         {
 663                 .num = 2,
 664                 .pin = 12,
 665                 .reg = 0x24,
 666                 .bit = 8,
 667                 .mask = 0x3
 668         }, {
 669                 .num = 2,
 670                 .pin = 15,
 671                 .reg = 0x28,
 672                 .bit = 0,
 673                 .mask = 0x7
 674         }, {
 675                 .num = 2,
 676                 .pin = 23,
 677                 .reg = 0x30,
 678                 .bit = 14,
 679                 .mask = 0x3
 680         },
 681 };
 682
 683 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
 684                                       int *reg, u8 *bit, int *mask)
 685 {
 686         struct rockchip_pinctrl *info = bank->drvdata;
 687         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 688         struct rockchip_mux_recalced_data *data;
 689         int i;
 690
 691         for (i = 0; i < ctrl->niomux_recalced; i++) {
 692                 data = &ctrl->iomux_recalced[i];
 693                 if (data->num == bank->bank_num &&
 694                     data->pin == pin)
 695                         break;
 696         }
 697
 698         if (i >= ctrl->niomux_recalced)
 699                 return;
 700
 701         *reg = data->reg;
 702         *mask = data->mask;
 703         *bit = data->bit;
 704 }
 705
 706 static struct rockchip_mux_route_data px30_mux_route_data[] = {
 707         {
 708                 /* cif-d2m0 */
 709                 .bank_num = 2,
 710                 .pin = 0,
 711                 .func = 1,
 712                 .route_offset = 0x184,
 713                 .route_val = BIT(16 + 7),
 714         }, {
 715                 /* cif-d2m1 */
 716                 .bank_num = 3,
 717                 .pin = 3,
 718                 .func = 3,
 719                 .route_offset = 0x184,
 720                 .route_val = BIT(16 + 7) | BIT(7),
 721         }, {
 722                 /* pdm-m0 */
 723                 .bank_num = 3,
 724                 .pin = 22,
 725                 .func = 2,
 726                 .route_offset = 0x184,
 727                 .route_val = BIT(16 + 8),
 728         }, {
 729                 /* pdm-m1 */
 730                 .bank_num = 2,
 731                 .pin = 22,
 732                 .func = 1,
 733                 .route_offset = 0x184,
 734                 .route_val = BIT(16 + 8) | BIT(8),
 735         }, {
 736                 /* uart2-rxm0 */
 737                 .bank_num = 1,
 738                 .pin = 27,
 739                 .func = 2,
 740                 .route_offset = 0x184,
 741                 .route_val = BIT(16 + 10),
 742         }, {
 743                 /* uart2-rxm1 */
 744                 .bank_num = 2,
 745                 .pin = 14,
 746                 .func = 2,
 747                 .route_offset = 0x184,
 748                 .route_val = BIT(16 + 10) | BIT(10),
 749         }, {
 750                 /* uart3-rxm0 */
 751                 .bank_num = 0,
 752                 .pin = 17,
 753                 .func = 2,
 754                 .route_offset = 0x184,
 755                 .route_val = BIT(16 + 9),
 756         }, {
 757                 /* uart3-rxm1 */
 758                 .bank_num = 1,
 759                 .pin = 15,
 760                 .func = 2,
 761                 .route_offset = 0x184,
 762                 .route_val = BIT(16 + 9) | BIT(9),
 763         },
 764 };
 765
 766 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
 767         {
 768                 /* spi-0 */
 769                 .bank_num = 1,
 770                 .pin = 10,
 771                 .func = 1,
 772                 .route_offset = 0x144,
 773                 .route_val = BIT(16 + 3) | BIT(16 + 4),
 774         }, {
 775                 /* spi-1 */
 776                 .bank_num = 1,
 777                 .pin = 27,
 778                 .func = 3,
 779                 .route_offset = 0x144,
 780                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
 781         }, {
 782                 /* spi-2 */
 783                 .bank_num = 0,
 784                 .pin = 13,
 785                 .func = 2,
 786                 .route_offset = 0x144,
 787                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
 788         }, {
 789                 /* i2s-0 */
 790                 .bank_num = 1,
 791                 .pin = 5,
 792                 .func = 1,
 793                 .route_offset = 0x144,
 794                 .route_val = BIT(16 + 5),
 795         }, {
 796                 /* i2s-1 */
 797                 .bank_num = 0,
 798                 .pin = 14,
 799                 .func = 1,
 800                 .route_offset = 0x144,
 801                 .route_val = BIT(16 + 5) | BIT(5),
 802         }, {
 803                 /* emmc-0 */
 804                 .bank_num = 1,
 805                 .pin = 22,
 806                 .func = 2,
 807                 .route_offset = 0x144,
 808                 .route_val = BIT(16 + 6),
 809         }, {
 810                 /* emmc-1 */
 811                 .bank_num = 2,
 812                 .pin = 4,
 813                 .func = 2,
 814                 .route_offset = 0x144,
 815                 .route_val = BIT(16 + 6) | BIT(6),
 816         },
 817 };
 818
 819 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
 820         {
 821                 /* pwm0-0 */
 822                 .bank_num = 0,
 823                 .pin = 26,
 824                 .func = 1,
 825                 .route_offset = 0x50,
 826                 .route_val = BIT(16),
 827         }, {
 828                 /* pwm0-1 */
 829                 .bank_num = 3,
 830                 .pin = 21,
 831                 .func = 1,
 832                 .route_offset = 0x50,
 833                 .route_val = BIT(16) | BIT(0),
 834         }, {
 835                 /* pwm1-0 */
 836                 .bank_num = 0,
 837                 .pin = 27,
 838                 .func = 1,
 839                 .route_offset = 0x50,
 840                 .route_val = BIT(16 + 1),
 841         }, {
 842                 /* pwm1-1 */
 843                 .bank_num = 0,
 844                 .pin = 30,
 845                 .func = 2,
 846                 .route_offset = 0x50,
 847                 .route_val = BIT(16 + 1) | BIT(1),
 848         }, {
 849                 /* pwm2-0 */
 850                 .bank_num = 0,
 851                 .pin = 28,
 852                 .func = 1,
 853                 .route_offset = 0x50,
 854                 .route_val = BIT(16 + 2),
 855         }, {
 856                 /* pwm2-1 */
 857                 .bank_num = 1,
 858                 .pin = 12,
 859                 .func = 2,
 860                 .route_offset = 0x50,
 861                 .route_val = BIT(16 + 2) | BIT(2),
 862         }, {
 863                 /* pwm3-0 */
 864                 .bank_num = 3,
 865                 .pin = 26,
 866                 .func = 1,
 867                 .route_offset = 0x50,
 868                 .route_val = BIT(16 + 3),
 869         }, {
 870                 /* pwm3-1 */
 871                 .bank_num = 1,
 872                 .pin = 11,
 873                 .func = 2,
 874                 .route_offset = 0x50,
 875                 .route_val = BIT(16 + 3) | BIT(3),
 876         }, {
 877                 /* sdio-0_d0 */
 878                 .bank_num = 1,
 879                 .pin = 1,
 880                 .func = 1,
 881                 .route_offset = 0x50,
 882                 .route_val = BIT(16 + 4),
 883         }, {
 884                 /* sdio-1_d0 */
 885                 .bank_num = 3,
 886                 .pin = 2,
 887                 .func = 1,
 888                 .route_offset = 0x50,
 889                 .route_val = BIT(16 + 4) | BIT(4),
 890         }, {
 891                 /* spi-0_rx */
 892                 .bank_num = 0,
 893                 .pin = 13,
 894                 .func = 2,
 895                 .route_offset = 0x50,
 896                 .route_val = BIT(16 + 5),
 897         }, {
 898                 /* spi-1_rx */
 899                 .bank_num = 2,
 900                 .pin = 0,
 901                 .func = 2,
 902                 .route_offset = 0x50,
 903                 .route_val = BIT(16 + 5) | BIT(5),
 904         }, {
 905                 /* emmc-0_cmd */
 906                 .bank_num = 1,
 907                 .pin = 22,
 908                 .func = 2,
 909                 .route_offset = 0x50,
 910                 .route_val = BIT(16 + 7),
 911         }, {
 912                 /* emmc-1_cmd */
 913                 .bank_num = 2,
 914                 .pin = 4,
 915                 .func = 2,
 916                 .route_offset = 0x50,
 917                 .route_val = BIT(16 + 7) | BIT(7),
 918         }, {
 919                 /* uart2-0_rx */
 920                 .bank_num = 1,
 921                 .pin = 19,
 922                 .func = 2,
 923                 .route_offset = 0x50,
 924                 .route_val = BIT(16 + 8),
 925         }, {
 926                 /* uart2-1_rx */
 927                 .bank_num = 1,
 928                 .pin = 10,
 929                 .func = 2,
 930                 .route_offset = 0x50,
 931                 .route_val = BIT(16 + 8) | BIT(8),
 932         }, {
 933                 /* uart1-0_rx */
 934                 .bank_num = 1,
 935                 .pin = 10,
 936                 .func = 1,
 937                 .route_offset = 0x50,
 938                 .route_val = BIT(16 + 11),
 939         }, {
 940                 /* uart1-1_rx */
 941                 .bank_num = 3,
 942                 .pin = 13,
 943                 .func = 1,
 944                 .route_offset = 0x50,
 945                 .route_val = BIT(16 + 11) | BIT(11),
 946         },
 947 };
 948
 949 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
 950         {
 951                 /* edphdmi_cecinoutt1 */
 952                 .bank_num = 7,
 953                 .pin = 16,
 954                 .func = 2,
 955                 .route_offset = 0x264,
 956                 .route_val = BIT(16 + 12) | BIT(12),
 957         }, {
 958                 /* edphdmi_cecinout */
 959                 .bank_num = 7,
 960                 .pin = 23,
 961                 .func = 4,
 962                 .route_offset = 0x264,
 963                 .route_val = BIT(16 + 12),
 964         },
 965 };
 966
 967 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
 968         {
 969                 /* uart2dbg_rxm0 */
 970                 .bank_num = 1,
 971                 .pin = 1,
 972                 .func = 2,
 973                 .route_offset = 0x50,
 974                 .route_val = BIT(16) | BIT(16 + 1),
 975         }, {
 976                 /* uart2dbg_rxm1 */
 977                 .bank_num = 2,
 978                 .pin = 1,
 979                 .func = 1,
 980                 .route_offset = 0x50,
 981                 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
 982         }, {
 983                 /* gmac-m1_rxd0 */
 984                 .bank_num = 1,
 985                 .pin = 11,
 986                 .func = 2,
 987                 .route_offset = 0x50,
 988                 .route_val = BIT(16 + 2) | BIT(2),
 989         }, {
 990                 /* gmac-m1-optimized_rxd3 */
 991                 .bank_num = 1,
 992                 .pin = 14,
 993                 .func = 2,
 994                 .route_offset = 0x50,
 995                 .route_val = BIT(16 + 10) | BIT(10),
 996         }, {
 997                 /* pdm_sdi0m0 */
 998                 .bank_num = 2,
 999                 .pin = 19,
1000                 .func = 2,
1001                 .route_offset = 0x50,
1002                 .route_val = BIT(16 + 3),
1003         }, {
1004                 /* pdm_sdi0m1 */
1005                 .bank_num = 1,
1006                 .pin = 23,
1007                 .func = 3,
1008                 .route_offset = 0x50,
1009                 .route_val =  BIT(16 + 3) | BIT(3),
1010         }, {
1011                 /* spi_rxdm2 */
1012                 .bank_num = 3,
1013                 .pin = 2,
1014                 .func = 4,
1015                 .route_offset = 0x50,
1016                 .route_val =  BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1017         }, {
1018                 /* i2s2_sdim0 */
1019                 .bank_num = 1,
1020                 .pin = 24,
1021                 .func = 1,
1022                 .route_offset = 0x50,
1023                 .route_val = BIT(16 + 6),
1024         }, {
1025                 /* i2s2_sdim1 */
1026                 .bank_num = 3,
1027                 .pin = 2,
1028                 .func = 6,
1029                 .route_offset = 0x50,
1030                 .route_val =  BIT(16 + 6) | BIT(6),
1031         }, {
1032                 /* card_iom1 */
1033                 .bank_num = 2,
1034                 .pin = 22,
1035                 .func = 3,
1036                 .route_offset = 0x50,
1037                 .route_val =  BIT(16 + 7) | BIT(7),
1038         }, {
1039                 /* tsp_d5m1 */
1040                 .bank_num = 2,
1041                 .pin = 16,
1042                 .func = 3,
1043                 .route_offset = 0x50,
1044                 .route_val =  BIT(16 + 8) | BIT(8),
1045         }, {
1046                 /* cif_data5m1 */
1047                 .bank_num = 2,
1048                 .pin = 16,
1049                 .func = 4,
1050                 .route_offset = 0x50,
1051                 .route_val =  BIT(16 + 9) | BIT(9),
1052         },
1053 };
1054
1055 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1056         {
1057                 /* uart2dbga_rx */
1058                 .bank_num = 4,
1059                 .pin = 8,
1060                 .func = 2,
1061                 .route_offset = 0xe21c,
1062                 .route_val = BIT(16 + 10) | BIT(16 + 11),
1063         }, {
1064                 /* uart2dbgb_rx */
1065                 .bank_num = 4,
1066                 .pin = 16,
1067                 .func = 2,
1068                 .route_offset = 0xe21c,
1069                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1070         }, {
1071                 /* uart2dbgc_rx */
1072                 .bank_num = 4,
1073                 .pin = 19,
1074                 .func = 1,
1075                 .route_offset = 0xe21c,
1076                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1077         }, {
1078                 /* pcie_clkreqn */
1079                 .bank_num = 2,
1080                 .pin = 26,
1081                 .func = 2,
1082                 .route_offset = 0xe21c,
1083                 .route_val = BIT(16 + 14),
1084         }, {
1085                 /* pcie_clkreqnb */
1086                 .bank_num = 4,
1087                 .pin = 24,
1088                 .func = 1,
1089                 .route_offset = 0xe21c,
1090                 .route_val = BIT(16 + 14) | BIT(14),
1091         },
1092 };
1093
1094 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1095                                    int mux, u32 *reg, u32 *value)
1096 {
1097         struct rockchip_pinctrl *info = bank->drvdata;
1098         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1099         struct rockchip_mux_route_data *data;
1100         int i;
1101
1102         for (i = 0; i < ctrl->niomux_routes; i++) {
1103                 data = &ctrl->iomux_routes[i];
1104                 if ((data->bank_num == bank->bank_num) &&
1105                     (data->pin == pin) && (data->func == mux))
1106                         break;
1107         }
1108
1109         if (i >= ctrl->niomux_routes)
1110                 return false;
1111
1112         *reg = data->route_offset;
1113         *value = data->route_val;
1114
1115         return true;
1116 }
1117
1118 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1119 {
1120         struct rockchip_pinctrl *info = bank->drvdata;
1121         int iomux_num = (pin / 8);
1122         struct regmap *regmap;
1123         unsigned int val;
1124         int reg, ret, mask, mux_type;
1125         u8 bit;
1126
1127         if (iomux_num > 3)
1128                 return -EINVAL;
1129
1130         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1131                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1132                 return -EINVAL;
1133         }
1134
1135         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1136                 return RK_FUNC_GPIO;
1137
1138         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1139                                 ? info->regmap_pmu : info->regmap_base;
1140
1141         /* get basic quadrupel of mux registers and the correct reg inside */
1142         mux_type = bank->iomux[iomux_num].type;
1143         reg = bank->iomux[iomux_num].offset;
1144         if (mux_type & IOMUX_WIDTH_4BIT) {
1145                 if ((pin % 8) >= 4)
1146                         reg += 0x4;
1147                 bit = (pin % 4) * 4;
1148                 mask = 0xf;
1149         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1150                 if ((pin % 8) >= 5)
1151                         reg += 0x4;
1152                 bit = (pin % 8 % 5) * 3;
1153                 mask = 0x7;
1154         } else {
1155                 bit = (pin % 8) * 2;
1156                 mask = 0x3;
1157         }
1158
1159         if (bank->recalced_mask & BIT(pin))
1160                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1161
1162         ret = regmap_read(regmap, reg, &val);
1163         if (ret)
1164                 return ret;
1165
1166         return ((val >> bit) & mask);
1167 }
1168
1169 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1170                                int pin, int mux)
1171 {
1172         struct rockchip_pinctrl *info = bank->drvdata;
1173         int iomux_num = (pin / 8);
1174
1175         if (iomux_num > 3)
1176                 return -EINVAL;
1177
1178         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1179                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1180                 return -EINVAL;
1181         }
1182
1183         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1184                 if (mux != RK_FUNC_GPIO) {
1185                         dev_err(info->dev,
1186                                 "pin %d only supports a gpio mux\n", pin);
1187                         return -ENOTSUPP;
1188                 }
1189         }
1190
1191         return 0;
1192 }
1193
1194 /*
1195  * Set a new mux function for a pin.
1196  *
1197  * The register is divided into the upper and lower 16 bit. When changing
1198  * a value, the previous register value is not read and changed. Instead
1199  * it seems the changed bits are marked in the upper 16 bit, while the
1200  * changed value gets set in the same offset in the lower 16 bit.
1201  * All pin settings seem to be 2 bit wide in both the upper and lower
1202  * parts.
1203  * @bank: pin bank to change
1204  * @pin: pin to change
1205  * @mux: new mux function to set
1206  */
1207 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1208 {
1209         struct rockchip_pinctrl *info = bank->drvdata;
1210         int iomux_num = (pin / 8);
1211         struct regmap *regmap;
1212         int reg, ret, mask, mux_type;
1213         u8 bit;
1214         u32 data, rmask, route_reg, route_val;
1215
1216         ret = rockchip_verify_mux(bank, pin, mux);
1217         if (ret < 0)
1218                 return ret;
1219
1220         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1221                 return 0;
1222
1223         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1224                                                 bank->bank_num, pin, mux);
1225
1226         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1227                                 ? info->regmap_pmu : info->regmap_base;
1228
1229         /* get basic quadrupel of mux registers and the correct reg inside */
1230         mux_type = bank->iomux[iomux_num].type;
1231         reg = bank->iomux[iomux_num].offset;
1232         if (mux_type & IOMUX_WIDTH_4BIT) {
1233                 if ((pin % 8) >= 4)
1234                         reg += 0x4;
1235                 bit = (pin % 4) * 4;
1236                 mask = 0xf;
1237         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1238                 if ((pin % 8) >= 5)
1239                         reg += 0x4;
1240                 bit = (pin % 8 % 5) * 3;
1241                 mask = 0x7;
1242         } else {
1243                 bit = (pin % 8) * 2;
1244                 mask = 0x3;
1245         }
1246
1247         if (bank->recalced_mask & BIT(pin))
1248                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1249
1250         if (bank->route_mask & BIT(pin)) {
1251                 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
1252                                            &route_val)) {
1253                         ret = regmap_write(regmap, route_reg, route_val);
1254                         if (ret)
1255                                 return ret;
1256                 }
1257         }
1258
1259         data = (mask << (bit + 16));
1260         rmask = data | (data >> 16);
1261         data |= (mux & mask) << bit;
1262         ret = regmap_update_bits(regmap, reg, rmask, data);
1263
1264         return ret;
1265 }
1266
1267 #define PX30_PULL_PMU_OFFSET            0x10
1268 #define PX30_PULL_GRF_OFFSET            0x60
1269 #define PX30_PULL_BITS_PER_PIN          2
1270 #define PX30_PULL_PINS_PER_REG          8
1271 #define PX30_PULL_BANK_STRIDE           16
1272
1273 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1274                                        int pin_num, struct regmap **regmap,
1275                                        int *reg, u8 *bit)
1276 {
1277         struct rockchip_pinctrl *info = bank->drvdata;
1278
1279         /* The first 32 pins of the first bank are located in PMU */
1280         if (bank->bank_num == 0) {
1281                 *regmap = info->regmap_pmu;
1282                 *reg = PX30_PULL_PMU_OFFSET;
1283         } else {
1284                 *regmap = info->regmap_base;
1285                 *reg = PX30_PULL_GRF_OFFSET;
1286
1287                 /* correct the offset, as we're starting with the 2nd bank */
1288                 *reg -= 0x10;
1289                 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1290         }
1291
1292         *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1293         *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1294         *bit *= PX30_PULL_BITS_PER_PIN;
1295 }
1296
1297 #define PX30_DRV_PMU_OFFSET             0x20
1298 #define PX30_DRV_GRF_OFFSET             0xf0
1299 #define PX30_DRV_BITS_PER_PIN           2
1300 #define PX30_DRV_PINS_PER_REG           8
1301 #define PX30_DRV_BANK_STRIDE            16
1302
1303 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1304                                       int pin_num, struct regmap **regmap,
1305                                       int *reg, u8 *bit)
1306 {
1307         struct rockchip_pinctrl *info = bank->drvdata;
1308
1309         /* The first 32 pins of the first bank are located in PMU */
1310         if (bank->bank_num == 0) {
1311                 *regmap = info->regmap_pmu;
1312                 *reg = PX30_DRV_PMU_OFFSET;
1313         } else {
1314                 *regmap = info->regmap_base;
1315                 *reg = PX30_DRV_GRF_OFFSET;
1316
1317                 /* correct the offset, as we're starting with the 2nd bank */
1318                 *reg -= 0x10;
1319                 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1320         }
1321
1322         *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1323         *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1324         *bit *= PX30_DRV_BITS_PER_PIN;
1325 }
1326
1327 #define PX30_SCHMITT_PMU_OFFSET                 0x38
1328 #define PX30_SCHMITT_GRF_OFFSET                 0xc0
1329 #define PX30_SCHMITT_PINS_PER_PMU_REG           16
1330 #define PX30_SCHMITT_BANK_STRIDE                16
1331 #define PX30_SCHMITT_PINS_PER_GRF_REG           8
1332
1333 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1334                                          int pin_num,
1335                                          struct regmap **regmap,
1336                                          int *reg, u8 *bit)
1337 {
1338         struct rockchip_pinctrl *info = bank->drvdata;
1339         int pins_per_reg;
1340
1341         if (bank->bank_num == 0) {
1342                 *regmap = info->regmap_pmu;
1343                 *reg = PX30_SCHMITT_PMU_OFFSET;
1344                 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1345         } else {
1346                 *regmap = info->regmap_base;
1347                 *reg = PX30_SCHMITT_GRF_OFFSET;
1348                 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1349                 *reg += (bank->bank_num  - 1) * PX30_SCHMITT_BANK_STRIDE;
1350         }
1351
1352         *reg += ((pin_num / pins_per_reg) * 4);
1353         *bit = pin_num % pins_per_reg;
1354
1355         return 0;
1356 }
1357
1358 #define RV1108_PULL_PMU_OFFSET          0x10
1359 #define RV1108_PULL_OFFSET              0x110
1360 #define RV1108_PULL_PINS_PER_REG        8
1361 #define RV1108_PULL_BITS_PER_PIN        2
1362 #define RV1108_PULL_BANK_STRIDE         16
1363
1364 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1365                                          int pin_num, struct regmap **regmap,
1366                                          int *reg, u8 *bit)
1367 {
1368         struct rockchip_pinctrl *info = bank->drvdata;
1369
1370         /* The first 24 pins of the first bank are located in PMU */
1371         if (bank->bank_num == 0) {
1372                 *regmap = info->regmap_pmu;
1373                 *reg = RV1108_PULL_PMU_OFFSET;
1374         } else {
1375                 *reg = RV1108_PULL_OFFSET;
1376                 *regmap = info->regmap_base;
1377                 /* correct the offset, as we're starting with the 2nd bank */
1378                 *reg -= 0x10;
1379                 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1380         }
1381
1382         *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1383         *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1384         *bit *= RV1108_PULL_BITS_PER_PIN;
1385 }
1386
1387 #define RV1108_DRV_PMU_OFFSET           0x20
1388 #define RV1108_DRV_GRF_OFFSET           0x210
1389 #define RV1108_DRV_BITS_PER_PIN         2
1390 #define RV1108_DRV_PINS_PER_REG         8
1391 #define RV1108_DRV_BANK_STRIDE          16
1392
1393 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1394                                         int pin_num, struct regmap **regmap,
1395                                         int *reg, u8 *bit)
1396 {
1397         struct rockchip_pinctrl *info = bank->drvdata;
1398
1399         /* The first 24 pins of the first bank are located in PMU */
1400         if (bank->bank_num == 0) {
1401                 *regmap = info->regmap_pmu;
1402                 *reg = RV1108_DRV_PMU_OFFSET;
1403         } else {
1404                 *regmap = info->regmap_base;
1405                 *reg = RV1108_DRV_GRF_OFFSET;
1406
1407                 /* correct the offset, as we're starting with the 2nd bank */
1408                 *reg -= 0x10;
1409                 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1410         }
1411
1412         *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1413         *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1414         *bit *= RV1108_DRV_BITS_PER_PIN;
1415 }
1416
1417 #define RV1108_SCHMITT_PMU_OFFSET               0x30
1418 #define RV1108_SCHMITT_GRF_OFFSET               0x388
1419 #define RV1108_SCHMITT_BANK_STRIDE              8
1420 #define RV1108_SCHMITT_PINS_PER_GRF_REG         16
1421 #define RV1108_SCHMITT_PINS_PER_PMU_REG         8
1422
1423 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1424                                            int pin_num,
1425                                            struct regmap **regmap,
1426                                            int *reg, u8 *bit)
1427 {
1428         struct rockchip_pinctrl *info = bank->drvdata;
1429         int pins_per_reg;
1430
1431         if (bank->bank_num == 0) {
1432                 *regmap = info->regmap_pmu;
1433                 *reg = RV1108_SCHMITT_PMU_OFFSET;
1434                 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1435         } else {
1436                 *regmap = info->regmap_base;
1437                 *reg = RV1108_SCHMITT_GRF_OFFSET;
1438                 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1439                 *reg += (bank->bank_num  - 1) * RV1108_SCHMITT_BANK_STRIDE;
1440         }
1441         *reg += ((pin_num / pins_per_reg) * 4);
1442         *bit = pin_num % pins_per_reg;
1443
1444         return 0;
1445 }
1446
1447 #define RK2928_PULL_OFFSET              0x118
1448 #define RK2928_PULL_PINS_PER_REG        16
1449 #define RK2928_PULL_BANK_STRIDE         8
1450
1451 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1452                                     int pin_num, struct regmap **regmap,
1453                                     int *reg, u8 *bit)
1454 {
1455         struct rockchip_pinctrl *info = bank->drvdata;
1456
1457         *regmap = info->regmap_base;
1458         *reg = RK2928_PULL_OFFSET;
1459         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1460         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1461
1462         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1463 };
1464
1465 #define RK3128_PULL_OFFSET      0x118
1466
1467 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1468                                          int pin_num, struct regmap **regmap,
1469                                          int *reg, u8 *bit)
1470 {
1471         struct rockchip_pinctrl *info = bank->drvdata;
1472
1473         *regmap = info->regmap_base;
1474         *reg = RK3128_PULL_OFFSET;
1475         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1476         *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1477
1478         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1479 }
1480
1481 #define RK3188_PULL_OFFSET              0x164
1482 #define RK3188_PULL_BITS_PER_PIN        2
1483 #define RK3188_PULL_PINS_PER_REG        8
1484 #define RK3188_PULL_BANK_STRIDE         16
1485 #define RK3188_PULL_PMU_OFFSET          0x64
1486
1487 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1488                                     int pin_num, struct regmap **regmap,
1489                                     int *reg, u8 *bit)
1490 {
1491         struct rockchip_pinctrl *info = bank->drvdata;
1492
1493         /* The first 12 pins of the first bank are located elsewhere */
1494         if (bank->bank_num == 0 && pin_num < 12) {
1495                 *regmap = info->regmap_pmu ? info->regmap_pmu
1496                                            : bank->regmap_pull;
1497                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1498                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1499                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1500                 *bit *= RK3188_PULL_BITS_PER_PIN;
1501         } else {
1502                 *regmap = info->regmap_pull ? info->regmap_pull
1503                                             : info->regmap_base;
1504                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1505
1506                 /* correct the offset, as it is the 2nd pull register */
1507                 *reg -= 4;
1508                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1509                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1510
1511                 /*
1512                  * The bits in these registers have an inverse ordering
1513                  * with the lowest pin being in bits 15:14 and the highest
1514                  * pin in bits 1:0
1515                  */
1516                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1517                 *bit *= RK3188_PULL_BITS_PER_PIN;
1518         }
1519 }
1520
1521 #define RK3288_PULL_OFFSET              0x140
1522 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1523                                     int pin_num, struct regmap **regmap,
1524                                     int *reg, u8 *bit)
1525 {
1526         struct rockchip_pinctrl *info = bank->drvdata;
1527
1528         /* The first 24 pins of the first bank are located in PMU */
1529         if (bank->bank_num == 0) {
1530                 *regmap = info->regmap_pmu;
1531                 *reg = RK3188_PULL_PMU_OFFSET;
1532
1533                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1534                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1535                 *bit *= RK3188_PULL_BITS_PER_PIN;
1536         } else {
1537                 *regmap = info->regmap_base;
1538                 *reg = RK3288_PULL_OFFSET;
1539
1540                 /* correct the offset, as we're starting with the 2nd bank */
1541                 *reg -= 0x10;
1542                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1543                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1544
1545                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1546                 *bit *= RK3188_PULL_BITS_PER_PIN;
1547         }
1548 }
1549
1550 #define RK3288_DRV_PMU_OFFSET           0x70
1551 #define RK3288_DRV_GRF_OFFSET           0x1c0
1552 #define RK3288_DRV_BITS_PER_PIN         2
1553 #define RK3288_DRV_PINS_PER_REG         8
1554 #define RK3288_DRV_BANK_STRIDE          16
1555
1556 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1557                                     int pin_num, struct regmap **regmap,
1558                                     int *reg, u8 *bit)
1559 {
1560         struct rockchip_pinctrl *info = bank->drvdata;
1561
1562         /* The first 24 pins of the first bank are located in PMU */
1563         if (bank->bank_num == 0) {
1564                 *regmap = info->regmap_pmu;
1565                 *reg = RK3288_DRV_PMU_OFFSET;
1566
1567                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1568                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1569                 *bit *= RK3288_DRV_BITS_PER_PIN;
1570         } else {
1571                 *regmap = info->regmap_base;
1572                 *reg = RK3288_DRV_GRF_OFFSET;
1573
1574                 /* correct the offset, as we're starting with the 2nd bank */
1575                 *reg -= 0x10;
1576                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1577                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1578
1579                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1580                 *bit *= RK3288_DRV_BITS_PER_PIN;
1581         }
1582 }
1583
1584 #define RK3228_PULL_OFFSET              0x100
1585
1586 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1587                                     int pin_num, struct regmap **regmap,
1588                                     int *reg, u8 *bit)
1589 {
1590         struct rockchip_pinctrl *info = bank->drvdata;
1591
1592         *regmap = info->regmap_base;
1593         *reg = RK3228_PULL_OFFSET;
1594         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1595         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1596
1597         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1598         *bit *= RK3188_PULL_BITS_PER_PIN;
1599 }
1600
1601 #define RK3228_DRV_GRF_OFFSET           0x200
1602
1603 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1604                                     int pin_num, struct regmap **regmap,
1605                                     int *reg, u8 *bit)
1606 {
1607         struct rockchip_pinctrl *info = bank->drvdata;
1608
1609         *regmap = info->regmap_base;
1610         *reg = RK3228_DRV_GRF_OFFSET;
1611         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1612         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1613
1614         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1615         *bit *= RK3288_DRV_BITS_PER_PIN;
1616 }
1617
1618 #define RK3368_PULL_GRF_OFFSET          0x100
1619 #define RK3368_PULL_PMU_OFFSET          0x10
1620
1621 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1622                                     int pin_num, struct regmap **regmap,
1623                                     int *reg, u8 *bit)
1624 {
1625         struct rockchip_pinctrl *info = bank->drvdata;
1626
1627         /* The first 32 pins of the first bank are located in PMU */
1628         if (bank->bank_num == 0) {
1629                 *regmap = info->regmap_pmu;
1630                 *reg = RK3368_PULL_PMU_OFFSET;
1631
1632                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1633                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1634                 *bit *= RK3188_PULL_BITS_PER_PIN;
1635         } else {
1636                 *regmap = info->regmap_base;
1637                 *reg = RK3368_PULL_GRF_OFFSET;
1638
1639                 /* correct the offset, as we're starting with the 2nd bank */
1640                 *reg -= 0x10;
1641                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1642                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1643
1644                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1645                 *bit *= RK3188_PULL_BITS_PER_PIN;
1646         }
1647 }
1648
1649 #define RK3368_DRV_PMU_OFFSET           0x20
1650 #define RK3368_DRV_GRF_OFFSET           0x200
1651
1652 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1653                                     int pin_num, struct regmap **regmap,
1654                                     int *reg, u8 *bit)
1655 {
1656         struct rockchip_pinctrl *info = bank->drvdata;
1657
1658         /* The first 32 pins of the first bank are located in PMU */
1659         if (bank->bank_num == 0) {
1660                 *regmap = info->regmap_pmu;
1661                 *reg = RK3368_DRV_PMU_OFFSET;
1662
1663                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1664                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1665                 *bit *= RK3288_DRV_BITS_PER_PIN;
1666         } else {
1667                 *regmap = info->regmap_base;
1668                 *reg = RK3368_DRV_GRF_OFFSET;
1669
1670                 /* correct the offset, as we're starting with the 2nd bank */
1671                 *reg -= 0x10;
1672                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1673                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1674
1675                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1676                 *bit *= RK3288_DRV_BITS_PER_PIN;
1677         }
1678 }
1679
1680 #define RK3399_PULL_GRF_OFFSET          0xe040
1681 #define RK3399_PULL_PMU_OFFSET          0x40
1682 #define RK3399_DRV_3BITS_PER_PIN        3
1683
1684 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1685                                          int pin_num, struct regmap **regmap,
1686                                          int *reg, u8 *bit)
1687 {
1688         struct rockchip_pinctrl *info = bank->drvdata;
1689
1690         /* The bank0:16 and bank1:32 pins are located in PMU */
1691         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1692                 *regmap = info->regmap_pmu;
1693                 *reg = RK3399_PULL_PMU_OFFSET;
1694
1695                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1696
1697                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1698                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1699                 *bit *= RK3188_PULL_BITS_PER_PIN;
1700         } else {
1701                 *regmap = info->regmap_base;
1702                 *reg = RK3399_PULL_GRF_OFFSET;
1703
1704                 /* correct the offset, as we're starting with the 3rd bank */
1705                 *reg -= 0x20;
1706                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1707                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1708
1709                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1710                 *bit *= RK3188_PULL_BITS_PER_PIN;
1711         }
1712 }
1713
1714 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1715                                         int pin_num, struct regmap **regmap,
1716                                         int *reg, u8 *bit)
1717 {
1718         struct rockchip_pinctrl *info = bank->drvdata;
1719         int drv_num = (pin_num / 8);
1720
1721         /*  The bank0:16 and bank1:32 pins are located in PMU */
1722         if ((bank->bank_num == 0) || (bank->bank_num == 1))
1723                 *regmap = info->regmap_pmu;
1724         else
1725                 *regmap = info->regmap_base;
1726
1727         *reg = bank->drv[drv_num].offset;
1728         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1729             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1730                 *bit = (pin_num % 8) * 3;
1731         else
1732                 *bit = (pin_num % 8) * 2;
1733 }
1734
1735 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1736         { 2, 4, 8, 12, -1, -1, -1, -1 },
1737         { 3, 6, 9, 12, -1, -1, -1, -1 },
1738         { 5, 10, 15, 20, -1, -1, -1, -1 },
1739         { 4, 6, 8, 10, 12, 14, 16, 18 },
1740         { 4, 7, 10, 13, 16, 19, 22, 26 }
1741 };
1742
1743 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1744                                      int pin_num)
1745 {
1746         struct rockchip_pinctrl *info = bank->drvdata;
1747         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1748         struct regmap *regmap;
1749         int reg, ret;
1750         u32 data, temp, rmask_bits;
1751         u8 bit;
1752         int drv_type = bank->drv[pin_num / 8].drv_type;
1753
1754         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1755
1756         switch (drv_type) {
1757         case DRV_TYPE_IO_1V8_3V0_AUTO:
1758         case DRV_TYPE_IO_3V3_ONLY:
1759                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1760                 switch (bit) {
1761                 case 0 ... 12:
1762                         /* regular case, nothing to do */
1763                         break;
1764                 case 15:
1765                         /*
1766                          * drive-strength offset is special, as it is
1767                          * spread over 2 registers
1768                          */
1769                         ret = regmap_read(regmap, reg, &data);
1770                         if (ret)
1771                                 return ret;
1772
1773                         ret = regmap_read(regmap, reg + 0x4, &temp);
1774                         if (ret)
1775                                 return ret;
1776
1777                         /*
1778                          * the bit data[15] contains bit 0 of the value
1779                          * while temp[1:0] contains bits 2 and 1
1780                          */
1781                         data >>= 15;
1782                         temp &= 0x3;
1783                         temp <<= 1;
1784                         data |= temp;
1785
1786                         return rockchip_perpin_drv_list[drv_type][data];
1787                 case 18 ... 21:
1788                         /* setting fully enclosed in the second register */
1789                         reg += 4;
1790                         bit -= 16;
1791                         break;
1792                 default:
1793                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1794                                 bit, drv_type);
1795                         return -EINVAL;
1796                 }
1797
1798                 break;
1799         case DRV_TYPE_IO_DEFAULT:
1800         case DRV_TYPE_IO_1V8_OR_3V0:
1801         case DRV_TYPE_IO_1V8_ONLY:
1802                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1803                 break;
1804         default:
1805                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1806                         drv_type);
1807                 return -EINVAL;
1808         }
1809
1810         ret = regmap_read(regmap, reg, &data);
1811         if (ret)
1812                 return ret;
1813
1814         data >>= bit;
1815         data &= (1 << rmask_bits) - 1;
1816
1817         return rockchip_perpin_drv_list[drv_type][data];
1818 }
1819
1820 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1821                                      int pin_num, int strength)
1822 {
1823         struct rockchip_pinctrl *info = bank->drvdata;
1824         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1825         struct regmap *regmap;
1826         int reg, ret, i;
1827         u32 data, rmask, rmask_bits, temp;
1828         u8 bit;
1829         int drv_type = bank->drv[pin_num / 8].drv_type;
1830
1831         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1832                 bank->bank_num, pin_num, strength);
1833
1834         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1835
1836         ret = -EINVAL;
1837         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1838                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1839                         ret = i;
1840                         break;
1841                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1842                         ret = rockchip_perpin_drv_list[drv_type][i];
1843                         break;
1844                 }
1845         }
1846
1847         if (ret < 0) {
1848                 dev_err(info->dev, "unsupported driver strength %d\n",
1849                         strength);
1850                 return ret;
1851         }
1852
1853         switch (drv_type) {
1854         case DRV_TYPE_IO_1V8_3V0_AUTO:
1855         case DRV_TYPE_IO_3V3_ONLY:
1856                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1857                 switch (bit) {
1858                 case 0 ... 12:
1859                         /* regular case, nothing to do */
1860                         break;
1861                 case 15:
1862                         /*
1863                          * drive-strength offset is special, as it is spread
1864                          * over 2 registers, the bit data[15] contains bit 0
1865                          * of the value while temp[1:0] contains bits 2 and 1
1866                          */
1867                         data = (ret & 0x1) << 15;
1868                         temp = (ret >> 0x1) & 0x3;
1869
1870                         rmask = BIT(15) | BIT(31);
1871                         data |= BIT(31);
1872                         ret = regmap_update_bits(regmap, reg, rmask, data);
1873                         if (ret)
1874                                 return ret;
1875
1876                         rmask = 0x3 | (0x3 << 16);
1877                         temp |= (0x3 << 16);
1878                         reg += 0x4;
1879                         ret = regmap_update_bits(regmap, reg, rmask, temp);
1880
1881                         return ret;
1882                 case 18 ... 21:
1883                         /* setting fully enclosed in the second register */
1884                         reg += 4;
1885                         bit -= 16;
1886                         break;
1887                 default:
1888                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1889                                 bit, drv_type);
1890                         return -EINVAL;
1891                 }
1892                 break;
1893         case DRV_TYPE_IO_DEFAULT:
1894         case DRV_TYPE_IO_1V8_OR_3V0:
1895         case DRV_TYPE_IO_1V8_ONLY:
1896                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1897                 break;
1898         default:
1899                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1900                         drv_type);
1901                 return -EINVAL;
1902         }
1903
1904         /* enable the write to the equivalent lower bits */
1905         data = ((1 << rmask_bits) - 1) << (bit + 16);
1906         rmask = data | (data >> 16);
1907         data |= (ret << bit);
1908
1909         ret = regmap_update_bits(regmap, reg, rmask, data);
1910
1911         return ret;
1912 }
1913
1914 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1915         {
1916                 PIN_CONFIG_BIAS_DISABLE,
1917                 PIN_CONFIG_BIAS_PULL_UP,
1918                 PIN_CONFIG_BIAS_PULL_DOWN,
1919                 PIN_CONFIG_BIAS_BUS_HOLD
1920         },
1921         {
1922                 PIN_CONFIG_BIAS_DISABLE,
1923                 PIN_CONFIG_BIAS_PULL_DOWN,
1924                 PIN_CONFIG_BIAS_DISABLE,
1925                 PIN_CONFIG_BIAS_PULL_UP
1926         },
1927 };
1928
1929 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1930 {
1931         struct rockchip_pinctrl *info = bank->drvdata;
1932         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1933         struct regmap *regmap;
1934         int reg, ret, pull_type;
1935         u8 bit;
1936         u32 data;
1937
1938         /* rk3066b does support any pulls */
1939         if (ctrl->type == RK3066B)
1940                 return PIN_CONFIG_BIAS_DISABLE;
1941
1942         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1943
1944         ret = regmap_read(regmap, reg, &data);
1945         if (ret)
1946                 return ret;
1947
1948         switch (ctrl->type) {
1949         case RK2928:
1950         case RK3128:
1951                 return !(data & BIT(bit))
1952                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1953                                 : PIN_CONFIG_BIAS_DISABLE;
1954         case PX30:
1955         case RV1108:
1956         case RK3188:
1957         case RK3288:
1958         case RK3368:
1959         case RK3399:
1960                 pull_type = bank->pull_type[pin_num / 8];
1961                 data >>= bit;
1962                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1963
1964                 return rockchip_pull_list[pull_type][data];
1965         default:
1966                 dev_err(info->dev, "unsupported pinctrl type\n");
1967                 return -EINVAL;
1968         };
1969 }
1970
1971 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1972                                         int pin_num, int pull)
1973 {
1974         struct rockchip_pinctrl *info = bank->drvdata;
1975         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1976         struct regmap *regmap;
1977         int reg, ret, i, pull_type;
1978         u8 bit;
1979         u32 data, rmask;
1980
1981         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1982                  bank->bank_num, pin_num, pull);
1983
1984         /* rk3066b does support any pulls */
1985         if (ctrl->type == RK3066B)
1986                 return pull ? -EINVAL : 0;
1987
1988         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1989
1990         switch (ctrl->type) {
1991         case RK2928:
1992         case RK3128:
1993                 data = BIT(bit + 16);
1994                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1995                         data |= BIT(bit);
1996                 ret = regmap_write(regmap, reg, data);
1997                 break;
1998         case PX30:
1999         case RV1108:
2000         case RK3188:
2001         case RK3288:
2002         case RK3368:
2003         case RK3399:
2004                 pull_type = bank->pull_type[pin_num / 8];
2005                 ret = -EINVAL;
2006                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2007                         i++) {
2008                         if (rockchip_pull_list[pull_type][i] == pull) {
2009                                 ret = i;
2010                                 break;
2011                         }
2012                 }
2013
2014                 if (ret < 0) {
2015                         dev_err(info->dev, "unsupported pull setting %d\n",
2016                                 pull);
2017                         return ret;
2018                 }
2019
2020                 /* enable the write to the equivalent lower bits */
2021                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2022                 rmask = data | (data >> 16);
2023                 data |= (ret << bit);
2024
2025                 ret = regmap_update_bits(regmap, reg, rmask, data);
2026                 break;
2027         default:
2028                 dev_err(info->dev, "unsupported pinctrl type\n");
2029                 return -EINVAL;
2030         }
2031
2032         return ret;
2033 }
2034
2035 #define RK3328_SCHMITT_BITS_PER_PIN             1
2036 #define RK3328_SCHMITT_PINS_PER_REG             16
2037 #define RK3328_SCHMITT_BANK_STRIDE              8
2038 #define RK3328_SCHMITT_GRF_OFFSET               0x380
2039
2040 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2041                                            int pin_num,
2042                                            struct regmap **regmap,
2043                                            int *reg, u8 *bit)
2044 {
2045         struct rockchip_pinctrl *info = bank->drvdata;
2046
2047         *regmap = info->regmap_base;
2048         *reg = RK3328_SCHMITT_GRF_OFFSET;
2049
2050         *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2051         *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2052         *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2053
2054         return 0;
2055 }
2056
2057 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2058 {
2059         struct rockchip_pinctrl *info = bank->drvdata;
2060         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2061         struct regmap *regmap;
2062         int reg, ret;
2063         u8 bit;
2064         u32 data;
2065
2066         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2067         if (ret)
2068                 return ret;
2069
2070         ret = regmap_read(regmap, reg, &data);
2071         if (ret)
2072                 return ret;
2073
2074         data >>= bit;
2075         return data & 0x1;
2076 }
2077
2078 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2079                                 int pin_num, int enable)
2080 {
2081         struct rockchip_pinctrl *info = bank->drvdata;
2082         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2083         struct regmap *regmap;
2084         int reg, ret;
2085         u8 bit;
2086         u32 data, rmask;
2087
2088         dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2089                 bank->bank_num, pin_num, enable);
2090
2091         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2092         if (ret)
2093                 return ret;
2094
2095         /* enable the write to the equivalent lower bits */
2096         data = BIT(bit + 16) | (enable << bit);
2097         rmask = BIT(bit + 16) | BIT(bit);
2098
2099         return regmap_update_bits(regmap, reg, rmask, data);
2100 }
2101
2102 /*
2103  * Pinmux_ops handling
2104  */
2105
2106 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2107 {
2108         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2109
2110         return info->nfunctions;
2111 }
2112
2113 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2114                                           unsigned selector)
2115 {
2116         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2117
2118         return info->functions[selector].name;
2119 }
2120
2121 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2122                                 unsigned selector, const char * const **groups,
2123                                 unsigned * const num_groups)
2124 {
2125         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2126
2127         *groups = info->functions[selector].groups;
2128         *num_groups = info->functions[selector].ngroups;
2129
2130         return 0;
2131 }
2132
2133 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2134                             unsigned group)
2135 {
2136         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2137         const unsigned int *pins = info->groups[group].pins;
2138         const struct rockchip_pin_config *data = info->groups[group].data;
2139         struct rockchip_pin_bank *bank;
2140         int cnt, ret = 0;
2141
2142         dev_dbg(info->dev, "enable function %s group %s\n",
2143                 info->functions[selector].name, info->groups[group].name);
2144
2145         /*
2146          * for each pin in the pin group selected, program the corresponding
2147          * pin function number in the config register.
2148          */
2149         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2150                 bank = pin_to_bank(info, pins[cnt]);
2151                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2152                                        data[cnt].func);
2153                 if (ret)
2154                         break;
2155         }
2156
2157         if (ret) {
2158                 /* revert the already done pin settings */
2159                 for (cnt--; cnt >= 0; cnt--)
2160                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2161
2162                 return ret;
2163         }
2164
2165         return 0;
2166 }
2167
2168 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2169 {
2170         struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2171         u32 data;
2172         int ret;
2173
2174         ret = clk_enable(bank->clk);
2175         if (ret < 0) {
2176                 dev_err(bank->drvdata->dev,
2177                         "failed to enable clock for bank %s\n", bank->name);
2178                 return ret;
2179         }
2180         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2181         clk_disable(bank->clk);
2182
2183         return !(data & BIT(offset));
2184 }
2185
2186 /*
2187  * The calls to gpio_direction_output() and gpio_direction_input()
2188  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2189  * function called from the gpiolib interface).
2190  */
2191 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2192                                             int pin, bool input)
2193 {
2194         struct rockchip_pin_bank *bank;
2195         int ret;
2196         unsigned long flags;
2197         u32 data;
2198
2199         bank = gpiochip_get_data(chip);
2200
2201         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2202         if (ret < 0)
2203                 return ret;
2204
2205         clk_enable(bank->clk);
2206         raw_spin_lock_irqsave(&bank->slock, flags);
2207
2208         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2209         /* set bit to 1 for output, 0 for input */
2210         if (!input)
2211                 data |= BIT(pin);
2212         else
2213                 data &= ~BIT(pin);
2214         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2215
2216         raw_spin_unlock_irqrestore(&bank->slock, flags);
2217         clk_disable(bank->clk);
2218
2219         return 0;
2220 }
2221
2222 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2223                                               struct pinctrl_gpio_range *range,
2224                                               unsigned offset, bool input)
2225 {
2226         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2227         struct gpio_chip *chip;
2228         int pin;
2229
2230         chip = range->gc;
2231         pin = offset - chip->base;
2232         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2233                  offset, range->name, pin, input ? "input" : "output");
2234
2235         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2236                                                 input);
2237 }
2238
2239 static const struct pinmux_ops rockchip_pmx_ops = {
2240         .get_functions_count    = rockchip_pmx_get_funcs_count,
2241         .get_function_name      = rockchip_pmx_get_func_name,
2242         .get_function_groups    = rockchip_pmx_get_groups,
2243         .set_mux                = rockchip_pmx_set,
2244         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
2245 };
2246
2247 /*
2248  * Pinconf_ops handling
2249  */
2250
2251 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2252                                         enum pin_config_param pull)
2253 {
2254         switch (ctrl->type) {
2255         case RK2928:
2256         case RK3128:
2257                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2258                                         pull == PIN_CONFIG_BIAS_DISABLE);
2259         case RK3066B:
2260                 return pull ? false : true;
2261         case PX30:
2262         case RV1108:
2263         case RK3188:
2264         case RK3288:
2265         case RK3368:
2266         case RK3399:
2267                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2268         }
2269
2270         return false;
2271 }
2272
2273 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2274 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2275
2276 /* set the pin config settings for a specified pin */
2277 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2278                                 unsigned long *configs, unsigned num_configs)
2279 {
2280         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2281         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2282         enum pin_config_param param;
2283         u32 arg;
2284         int i;
2285         int rc;
2286
2287         for (i = 0; i < num_configs; i++) {
2288                 param = pinconf_to_config_param(configs[i]);
2289                 arg = pinconf_to_config_argument(configs[i]);
2290
2291                 switch (param) {
2292                 case PIN_CONFIG_BIAS_DISABLE:
2293                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
2294                                 param);
2295                         if (rc)
2296                                 return rc;
2297                         break;
2298                 case PIN_CONFIG_BIAS_PULL_UP:
2299                 case PIN_CONFIG_BIAS_PULL_DOWN:
2300                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2301                 case PIN_CONFIG_BIAS_BUS_HOLD:
2302                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2303                                 return -ENOTSUPP;
2304
2305                         if (!arg)
2306                                 return -EINVAL;
2307
2308                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
2309                                 param);
2310                         if (rc)
2311                                 return rc;
2312                         break;
2313                 case PIN_CONFIG_OUTPUT:
2314                         rockchip_gpio_set(&bank->gpio_chip,
2315                                           pin - bank->pin_base, arg);
2316                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2317                                           pin - bank->pin_base, false);
2318                         if (rc)
2319                                 return rc;
2320                         break;
2321                 case PIN_CONFIG_DRIVE_STRENGTH:
2322                         /* rk3288 is the first with per-pin drive-strength */
2323                         if (!info->ctrl->drv_calc_reg)
2324                                 return -ENOTSUPP;
2325
2326                         rc = rockchip_set_drive_perpin(bank,
2327                                                 pin - bank->pin_base, arg);
2328                         if (rc < 0)
2329                                 return rc;
2330                         break;
2331                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2332                         if (!info->ctrl->schmitt_calc_reg)
2333                                 return -ENOTSUPP;
2334
2335                         rc = rockchip_set_schmitt(bank,
2336                                                   pin - bank->pin_base, arg);
2337                         if (rc < 0)
2338                                 return rc;
2339                         break;
2340                 default:
2341                         return -ENOTSUPP;
2342                         break;
2343                 }
2344         } /* for each config */
2345
2346         return 0;
2347 }
2348
2349 /* get the pin config settings for a specified pin */
2350 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2351                                                         unsigned long *config)
2352 {
2353         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2354         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2355         enum pin_config_param param = pinconf_to_config_param(*config);
2356         u16 arg;
2357         int rc;
2358
2359         switch (param) {
2360         case PIN_CONFIG_BIAS_DISABLE:
2361                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2362                         return -EINVAL;
2363
2364                 arg = 0;
2365                 break;
2366         case PIN_CONFIG_BIAS_PULL_UP:
2367         case PIN_CONFIG_BIAS_PULL_DOWN:
2368         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2369         case PIN_CONFIG_BIAS_BUS_HOLD:
2370                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2371                         return -ENOTSUPP;
2372
2373                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2374                         return -EINVAL;
2375
2376                 arg = 1;
2377                 break;
2378         case PIN_CONFIG_OUTPUT:
2379                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2380                 if (rc != RK_FUNC_GPIO)
2381                         return -EINVAL;
2382
2383                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2384                 if (rc < 0)
2385                         return rc;
2386
2387                 arg = rc ? 1 : 0;
2388                 break;
2389         case PIN_CONFIG_DRIVE_STRENGTH:
2390                 /* rk3288 is the first with per-pin drive-strength */
2391                 if (!info->ctrl->drv_calc_reg)
2392                         return -ENOTSUPP;
2393
2394                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2395                 if (rc < 0)
2396                         return rc;
2397
2398                 arg = rc;
2399                 break;
2400         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2401                 if (!info->ctrl->schmitt_calc_reg)
2402                         return -ENOTSUPP;
2403
2404                 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2405                 if (rc < 0)
2406                         return rc;
2407
2408                 arg = rc;
2409                 break;
2410         default:
2411                 return -ENOTSUPP;
2412                 break;
2413         }
2414
2415         *config = pinconf_to_config_packed(param, arg);
2416
2417         return 0;
2418 }
2419
2420 static const struct pinconf_ops rockchip_pinconf_ops = {
2421         .pin_config_get                 = rockchip_pinconf_get,
2422         .pin_config_set                 = rockchip_pinconf_set,
2423         .is_generic                     = true,
2424 };
2425
2426 static const struct of_device_id rockchip_bank_match[] = {
2427         { .compatible = "rockchip,gpio-bank" },
2428         { .compatible = "rockchip,rk3188-gpio-bank0" },
2429         {},
2430 };
2431
2432 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2433                                                 struct device_node *np)
2434 {
2435         struct device_node *child;
2436
2437         for_each_child_of_node(np, child) {
2438                 if (of_match_node(rockchip_bank_match, child))
2439                         continue;
2440
2441                 info->nfunctions++;
2442                 info->ngroups += of_get_child_count(child);
2443         }
2444 }
2445
2446 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2447                                               struct rockchip_pin_group *grp,
2448                                               struct rockchip_pinctrl *info,
2449                                               u32 index)
2450 {
2451         struct rockchip_pin_bank *bank;
2452         int size;
2453         const __be32 *list;
2454         int num;
2455         int i, j;
2456         int ret;
2457
2458         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
2459
2460         /* Initialise group */
2461         grp->name = np->name;
2462
2463         /*
2464          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2465          * do sanity check and calculate pins number
2466          */
2467         list = of_get_property(np, "rockchip,pins", &size);
2468         /* we do not check return since it's safe node passed down */
2469         size /= sizeof(*list);
2470         if (!size || size % 4) {
2471                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2472                 return -EINVAL;
2473         }
2474
2475         grp->npins = size / 4;
2476
2477         grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2478                                                 GFP_KERNEL);
2479         grp->data = devm_kcalloc(info->dev,
2480                                         grp->npins,
2481                                         sizeof(struct rockchip_pin_config),
2482                                         GFP_KERNEL);
2483         if (!grp->pins || !grp->data)
2484                 return -ENOMEM;
2485
2486         for (i = 0, j = 0; i < size; i += 4, j++) {
2487                 const __be32 *phandle;
2488                 struct device_node *np_config;
2489
2490                 num = be32_to_cpu(*list++);
2491                 bank = bank_num_to_bank(info, num);
2492                 if (IS_ERR(bank))
2493                         return PTR_ERR(bank);
2494
2495                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2496                 grp->data[j].func = be32_to_cpu(*list++);
2497
2498                 phandle = list++;
2499                 if (!phandle)
2500                         return -EINVAL;
2501
2502                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2503                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2504                                 &grp->data[j].configs, &grp->data[j].nconfigs);
2505                 if (ret)
2506                         return ret;
2507         }
2508
2509         return 0;
2510 }
2511
2512 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2513                                                 struct rockchip_pinctrl *info,
2514                                                 u32 index)
2515 {
2516         struct device_node *child;
2517         struct rockchip_pmx_func *func;
2518         struct rockchip_pin_group *grp;
2519         int ret;
2520         static u32 grp_index;
2521         u32 i = 0;
2522
2523         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
2524
2525         func = &info->functions[index];
2526
2527         /* Initialise function */
2528         func->name = np->name;
2529         func->ngroups = of_get_child_count(np);
2530         if (func->ngroups <= 0)
2531                 return 0;
2532
2533         func->groups = devm_kcalloc(info->dev,
2534                         func->ngroups, sizeof(char *), GFP_KERNEL);
2535         if (!func->groups)
2536                 return -ENOMEM;
2537
2538         for_each_child_of_node(np, child) {
2539                 func->groups[i] = child->name;
2540                 grp = &info->groups[grp_index++];
2541                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2542                 if (ret) {
2543                         of_node_put(child);
2544                         return ret;
2545                 }
2546         }
2547
2548         return 0;
2549 }
2550
2551 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2552                                               struct rockchip_pinctrl *info)
2553 {
2554         struct device *dev = &pdev->dev;
2555         struct device_node *np = dev->of_node;
2556         struct device_node *child;
2557         int ret;
2558         int i;
2559
2560         rockchip_pinctrl_child_count(info, np);
2561
2562         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2563         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2564
2565         info->functions = devm_kcalloc(dev,
2566                                               info->nfunctions,
2567                                               sizeof(struct rockchip_pmx_func),
2568                                               GFP_KERNEL);
2569         if (!info->functions)
2570                 return -EINVAL;
2571
2572         info->groups = devm_kcalloc(dev,
2573                                             info->ngroups,
2574                                             sizeof(struct rockchip_pin_group),
2575                                             GFP_KERNEL);
2576         if (!info->groups)
2577                 return -EINVAL;
2578
2579         i = 0;
2580
2581         for_each_child_of_node(np, child) {
2582                 if (of_match_node(rockchip_bank_match, child))
2583                         continue;
2584
2585                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2586                 if (ret) {
2587                         dev_err(&pdev->dev, "failed to parse function\n");
2588                         of_node_put(child);
2589                         return ret;
2590                 }
2591         }
2592
2593         return 0;
2594 }
2595
2596 static int rockchip_pinctrl_register(struct platform_device *pdev,
2597                                         struct rockchip_pinctrl *info)
2598 {
2599         struct pinctrl_desc *ctrldesc = &info->pctl;
2600         struct pinctrl_pin_desc *pindesc, *pdesc;
2601         struct rockchip_pin_bank *pin_bank;
2602         int pin, bank, ret;
2603         int k;
2604
2605         ctrldesc->name = "rockchip-pinctrl";
2606         ctrldesc->owner = THIS_MODULE;
2607         ctrldesc->pctlops = &rockchip_pctrl_ops;
2608         ctrldesc->pmxops = &rockchip_pmx_ops;
2609         ctrldesc->confops = &rockchip_pinconf_ops;
2610
2611         pindesc = devm_kcalloc(&pdev->dev,
2612                                info->ctrl->nr_pins, sizeof(*pindesc),
2613                                GFP_KERNEL);
2614         if (!pindesc)
2615                 return -ENOMEM;
2616
2617         ctrldesc->pins = pindesc;
2618         ctrldesc->npins = info->ctrl->nr_pins;
2619
2620         pdesc = pindesc;
2621         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2622                 pin_bank = &info->ctrl->pin_banks[bank];
2623                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2624                         pdesc->number = k;
2625                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2626                                                 pin_bank->name, pin);
2627                         pdesc++;
2628                 }
2629         }
2630
2631         ret = rockchip_pinctrl_parse_dt(pdev, info);
2632         if (ret)
2633                 return ret;
2634
2635         info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
2636         if (IS_ERR(info->pctl_dev)) {
2637                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2638                 return PTR_ERR(info->pctl_dev);
2639         }
2640
2641         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2642                 pin_bank = &info->ctrl->pin_banks[bank];
2643                 pin_bank->grange.name = pin_bank->name;
2644                 pin_bank->grange.id = bank;
2645                 pin_bank->grange.pin_base = pin_bank->pin_base;
2646                 pin_bank->grange.base = pin_bank->gpio_chip.base;
2647                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2648                 pin_bank->grange.gc = &pin_bank->gpio_chip;
2649                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2650         }
2651
2652         return 0;
2653 }
2654
2655 /*
2656  * GPIO handling
2657  */
2658
2659 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2660 {
2661         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2662         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2663         unsigned long flags;
2664         u32 data;
2665
2666         clk_enable(bank->clk);
2667         raw_spin_lock_irqsave(&bank->slock, flags);
2668
2669         data = readl(reg);
2670         data &= ~BIT(offset);
2671         if (value)
2672                 data |= BIT(offset);
2673         writel(data, reg);
2674
2675         raw_spin_unlock_irqrestore(&bank->slock, flags);
2676         clk_disable(bank->clk);
2677 }
2678
2679 /*
2680  * Returns the level of the pin for input direction and setting of the DR
2681  * register for output gpios.
2682  */
2683 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2684 {
2685         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2686         u32 data;
2687
2688         clk_enable(bank->clk);
2689         data = readl(bank->reg_base + GPIO_EXT_PORT);
2690         clk_disable(bank->clk);
2691         data >>= offset;
2692         data &= 1;
2693         return data;
2694 }
2695
2696 /*
2697  * gpiolib gpio_direction_input callback function. The setting of the pin
2698  * mux function as 'gpio input' will be handled by the pinctrl subsystem
2699  * interface.
2700  */
2701 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2702 {
2703         return pinctrl_gpio_direction_input(gc->base + offset);
2704 }
2705
2706 /*
2707  * gpiolib gpio_direction_output callback function. The setting of the pin
2708  * mux function as 'gpio output' will be handled by the pinctrl subsystem
2709  * interface.
2710  */
2711 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2712                                           unsigned offset, int value)
2713 {
2714         rockchip_gpio_set(gc, offset, value);
2715         return pinctrl_gpio_direction_output(gc->base + offset);
2716 }
2717
2718 static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
2719                                        unsigned int offset, bool enable)
2720 {
2721         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2722         void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
2723         unsigned long flags;
2724         u32 data;
2725
2726         clk_enable(bank->clk);
2727         raw_spin_lock_irqsave(&bank->slock, flags);
2728
2729         data = readl(reg);
2730         if (enable)
2731                 data |= BIT(offset);
2732         else
2733                 data &= ~BIT(offset);
2734         writel(data, reg);
2735
2736         raw_spin_unlock_irqrestore(&bank->slock, flags);
2737         clk_disable(bank->clk);
2738 }
2739
2740 /*
2741  * gpiolib set_config callback function. The setting of the pin
2742  * mux function as 'gpio output' will be handled by the pinctrl subsystem
2743  * interface.
2744  */
2745 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
2746                                   unsigned long config)
2747 {
2748         enum pin_config_param param = pinconf_to_config_param(config);
2749
2750         switch (param) {
2751         case PIN_CONFIG_INPUT_DEBOUNCE:
2752                 rockchip_gpio_set_debounce(gc, offset, true);
2753                 /*
2754                  * Rockchip's gpio could only support up to one period
2755                  * of the debounce clock(pclk), which is far away from
2756                  * satisftying the requirement, as pclk is usually near
2757                  * 100MHz shared by all peripherals. So the fact is it
2758                  * has crippled debounce capability could only be useful
2759                  * to prevent any spurious glitches from waking up the system
2760                  * if the gpio is conguired as wakeup interrupt source. Let's
2761                  * still return -ENOTSUPP as before, to make sure the caller
2762                  * of gpiod_set_debounce won't change its behaviour.
2763                  */
2764         default:
2765                 return -ENOTSUPP;
2766         }
2767 }
2768
2769 /*
2770  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2771  * and a virtual IRQ, if not already present.
2772  */
2773 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2774 {
2775         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2776         unsigned int virq;
2777
2778         if (!bank->domain)
2779                 return -ENXIO;
2780
2781         clk_enable(bank->clk);
2782         virq = irq_create_mapping(bank->domain, offset);
2783         clk_disable(bank->clk);
2784
2785         return (virq) ? : -ENXIO;
2786 }
2787
2788 static const struct gpio_chip rockchip_gpiolib_chip = {
2789         .request = gpiochip_generic_request,
2790         .free = gpiochip_generic_free,
2791         .set = rockchip_gpio_set,
2792         .get = rockchip_gpio_get,
2793         .get_direction  = rockchip_gpio_get_direction,
2794         .direction_input = rockchip_gpio_direction_input,
2795         .direction_output = rockchip_gpio_direction_output,
2796         .set_config = rockchip_gpio_set_config,
2797         .to_irq = rockchip_gpio_to_irq,
2798         .owner = THIS_MODULE,
2799 };
2800
2801 /*
2802  * Interrupt handling
2803  */
2804
2805 static void rockchip_irq_demux(struct irq_desc *desc)
2806 {
2807         struct irq_chip *chip = irq_desc_get_chip(desc);
2808         struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2809         u32 pend;
2810
2811         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2812
2813         chained_irq_enter(chip, desc);
2814
2815         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2816
2817         while (pend) {
2818                 unsigned int irq, virq;
2819
2820                 irq = __ffs(pend);
2821                 pend &= ~BIT(irq);
2822                 virq = irq_linear_revmap(bank->domain, irq);
2823
2824                 if (!virq) {
2825                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2826                         continue;
2827                 }
2828
2829                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2830
2831                 /*
2832                  * Triggering IRQ on both rising and falling edge
2833                  * needs manual intervention.
2834                  */
2835                 if (bank->toggle_edge_mode & BIT(irq)) {
2836                         u32 data, data_old, polarity;
2837                         unsigned long flags;
2838
2839                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2840                         do {
2841                                 raw_spin_lock_irqsave(&bank->slock, flags);
2842
2843                                 polarity = readl_relaxed(bank->reg_base +
2844                                                          GPIO_INT_POLARITY);
2845                                 if (data & BIT(irq))
2846                                         polarity &= ~BIT(irq);
2847                                 else
2848                                         polarity |= BIT(irq);
2849                                 writel(polarity,
2850                                        bank->reg_base + GPIO_INT_POLARITY);
2851
2852                                 raw_spin_unlock_irqrestore(&bank->slock, flags);
2853
2854                                 data_old = data;
2855                                 data = readl_relaxed(bank->reg_base +
2856                                                      GPIO_EXT_PORT);
2857                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2858                 }
2859
2860                 generic_handle_irq(virq);
2861         }
2862
2863         chained_irq_exit(chip, desc);
2864 }
2865
2866 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2867 {
2868         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2869         struct rockchip_pin_bank *bank = gc->private;
2870         u32 mask = BIT(d->hwirq);
2871         u32 polarity;
2872         u32 level;
2873         u32 data;
2874         unsigned long flags;
2875         int ret;
2876
2877         /* make sure the pin is configured as gpio input */
2878         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2879         if (ret < 0)
2880                 return ret;
2881
2882         clk_enable(bank->clk);
2883         raw_spin_lock_irqsave(&bank->slock, flags);
2884
2885         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2886         data &= ~mask;
2887         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2888
2889         raw_spin_unlock_irqrestore(&bank->slock, flags);
2890
2891         if (type & IRQ_TYPE_EDGE_BOTH)
2892                 irq_set_handler_locked(d, handle_edge_irq);
2893         else
2894                 irq_set_handler_locked(d, handle_level_irq);
2895
2896         raw_spin_lock_irqsave(&bank->slock, flags);
2897         irq_gc_lock(gc);
2898
2899         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2900         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2901
2902         switch (type) {
2903         case IRQ_TYPE_EDGE_BOTH:
2904                 bank->toggle_edge_mode |= mask;
2905                 level |= mask;
2906
2907                 /*
2908                  * Determine gpio state. If 1 next interrupt should be falling
2909                  * otherwise rising.
2910                  */
2911                 data = readl(bank->reg_base + GPIO_EXT_PORT);
2912                 if (data & mask)
2913                         polarity &= ~mask;
2914                 else
2915                         polarity |= mask;
2916                 break;
2917         case IRQ_TYPE_EDGE_RISING:
2918                 bank->toggle_edge_mode &= ~mask;
2919                 level |= mask;
2920                 polarity |= mask;
2921                 break;
2922         case IRQ_TYPE_EDGE_FALLING:
2923                 bank->toggle_edge_mode &= ~mask;
2924                 level |= mask;
2925                 polarity &= ~mask;
2926                 break;
2927         case IRQ_TYPE_LEVEL_HIGH:
2928                 bank->toggle_edge_mode &= ~mask;
2929                 level &= ~mask;
2930                 polarity |= mask;
2931                 break;
2932         case IRQ_TYPE_LEVEL_LOW:
2933                 bank->toggle_edge_mode &= ~mask;
2934                 level &= ~mask;
2935                 polarity &= ~mask;
2936                 break;
2937         default:
2938                 irq_gc_unlock(gc);
2939                 raw_spin_unlock_irqrestore(&bank->slock, flags);
2940                 clk_disable(bank->clk);
2941                 return -EINVAL;
2942         }
2943
2944         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2945         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2946
2947         irq_gc_unlock(gc);
2948         raw_spin_unlock_irqrestore(&bank->slock, flags);
2949         clk_disable(bank->clk);
2950
2951         return 0;
2952 }
2953
2954 static void rockchip_irq_suspend(struct irq_data *d)
2955 {
2956         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2957         struct rockchip_pin_bank *bank = gc->private;
2958
2959         clk_enable(bank->clk);
2960         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2961         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2962         clk_disable(bank->clk);
2963 }
2964
2965 static void rockchip_irq_resume(struct irq_data *d)
2966 {
2967         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2968         struct rockchip_pin_bank *bank = gc->private;
2969
2970         clk_enable(bank->clk);
2971         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2972         clk_disable(bank->clk);
2973 }
2974
2975 static void rockchip_irq_enable(struct irq_data *d)
2976 {
2977         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2978         struct rockchip_pin_bank *bank = gc->private;
2979
2980         clk_enable(bank->clk);
2981         irq_gc_mask_clr_bit(d);
2982 }
2983
2984 static void rockchip_irq_disable(struct irq_data *d)
2985 {
2986         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2987         struct rockchip_pin_bank *bank = gc->private;
2988
2989         irq_gc_mask_set_bit(d);
2990         clk_disable(bank->clk);
2991 }
2992
2993 static int rockchip_interrupts_register(struct platform_device *pdev,
2994                                                 struct rockchip_pinctrl *info)
2995 {
2996         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2997         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2998         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2999         struct irq_chip_generic *gc;
3000         int ret;
3001         int i, j;
3002
3003         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3004                 if (!bank->valid) {
3005                         dev_warn(&pdev->dev, "bank %s is not valid\n",
3006                                  bank->name);
3007                         continue;
3008                 }
3009
3010                 ret = clk_enable(bank->clk);
3011                 if (ret) {
3012                         dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3013                                 bank->name);
3014                         continue;
3015                 }
3016
3017                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3018                                                 &irq_generic_chip_ops, NULL);
3019                 if (!bank->domain) {
3020                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3021                                  bank->name);
3022                         clk_disable(bank->clk);
3023                         continue;
3024                 }
3025
3026                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3027                                          "rockchip_gpio_irq", handle_level_irq,
3028                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
3029                 if (ret) {
3030                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3031                                 bank->name);
3032                         irq_domain_remove(bank->domain);
3033                         clk_disable(bank->clk);
3034                         continue;
3035                 }
3036
3037                 /*
3038                  * Linux assumes that all interrupts start out disabled/masked.
3039                  * Our driver only uses the concept of masked and always keeps
3040                  * things enabled, so for us that's all masked and all enabled.
3041                  */
3042                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3043                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3044
3045                 gc = irq_get_domain_generic_chip(bank->domain, 0);
3046                 gc->reg_base = bank->reg_base;
3047                 gc->private = bank;
3048                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
3049                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3050                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3051                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3052                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3053                 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3054                 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3055                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3056                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3057                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3058                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3059                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3060
3061                 irq_set_chained_handler_and_data(bank->irq,
3062                                                  rockchip_irq_demux, bank);
3063
3064                 /* map the gpio irqs here, when the clock is still running */
3065                 for (j = 0 ; j < 32 ; j++)
3066                         irq_create_mapping(bank->domain, j);
3067
3068                 clk_disable(bank->clk);
3069         }
3070
3071         return 0;
3072 }
3073
3074 static int rockchip_gpiolib_register(struct platform_device *pdev,
3075                                                 struct rockchip_pinctrl *info)
3076 {
3077         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3078         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3079         struct gpio_chip *gc;
3080         int ret;
3081         int i;
3082
3083         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3084                 if (!bank->valid) {
3085                         dev_warn(&pdev->dev, "bank %s is not valid\n",
3086                                  bank->name);
3087                         continue;
3088                 }
3089
3090                 bank->gpio_chip = rockchip_gpiolib_chip;
3091
3092                 gc = &bank->gpio_chip;
3093                 gc->base = bank->pin_base;
3094                 gc->ngpio = bank->nr_pins;
3095                 gc->parent = &pdev->dev;
3096                 gc->of_node = bank->of_node;
3097                 gc->label = bank->name;
3098
3099                 ret = gpiochip_add_data(gc, bank);
3100                 if (ret) {
3101                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3102                                                         gc->label, ret);
3103                         goto fail;
3104                 }
3105         }
3106
3107         rockchip_interrupts_register(pdev, info);
3108
3109         return 0;
3110
3111 fail:
3112         for (--i, --bank; i >= 0; --i, --bank) {
3113                 if (!bank->valid)
3114                         continue;
3115                 gpiochip_remove(&bank->gpio_chip);
3116         }
3117         return ret;
3118 }
3119
3120 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3121                                                 struct rockchip_pinctrl *info)
3122 {
3123         struct rockchip_pin_ctrl *ctrl = info->ctrl;
3124         struct rockchip_pin_bank *bank = ctrl->pin_banks;
3125         int i;
3126
3127         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3128                 if (!bank->valid)
3129                         continue;
3130                 gpiochip_remove(&bank->gpio_chip);
3131         }
3132
3133         return 0;
3134 }
3135
3136 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3137                                   struct rockchip_pinctrl *info)
3138 {
3139         struct resource res;
3140         void __iomem *base;
3141
3142         if (of_address_to_resource(bank->of_node, 0, &res)) {
3143                 dev_err(info->dev, "cannot find IO resource for bank\n");
3144                 return -ENOENT;
3145         }
3146
3147         bank->reg_base = devm_ioremap_resource(info->dev, &res);
3148         if (IS_ERR(bank->reg_base))
3149                 return PTR_ERR(bank->reg_base);
3150
3151         /*
3152          * special case, where parts of the pull setting-registers are
3153          * part of the PMU register space
3154          */
3155         if (of_device_is_compatible(bank->of_node,
3156                                     "rockchip,rk3188-gpio-bank0")) {
3157                 struct device_node *node;
3158
3159                 node = of_parse_phandle(bank->of_node->parent,
3160                                         "rockchip,pmu", 0);
3161                 if (!node) {
3162                         if (of_address_to_resource(bank->of_node, 1, &res)) {
3163                                 dev_err(info->dev, "cannot find IO resource for bank\n");
3164                                 return -ENOENT;
3165                         }
3166
3167                         base = devm_ioremap_resource(info->dev, &res);
3168                         if (IS_ERR(base))
3169                                 return PTR_ERR(base);
3170                         rockchip_regmap_config.max_register =
3171                                                     resource_size(&res) - 4;
3172                         rockchip_regmap_config.name =
3173                                             "rockchip,rk3188-gpio-bank0-pull";
3174                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3175                                                     base,
3176                                                     &rockchip_regmap_config);
3177                 }
3178                 of_node_put(node);
3179         }
3180
3181         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3182
3183         bank->clk = of_clk_get(bank->of_node, 0);
3184         if (IS_ERR(bank->clk))
3185                 return PTR_ERR(bank->clk);
3186
3187         return clk_prepare(bank->clk);
3188 }
3189
3190 static const struct of_device_id rockchip_pinctrl_dt_match[];
3191
3192 /* retrieve the soc specific data */
3193 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3194                                                 struct rockchip_pinctrl *d,
3195                                                 struct platform_device *pdev)
3196 {
3197         const struct of_device_id *match;
3198         struct device_node *node = pdev->dev.of_node;
3199         struct device_node *np;
3200         struct rockchip_pin_ctrl *ctrl;
3201         struct rockchip_pin_bank *bank;
3202         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3203
3204         match = of_match_node(rockchip_pinctrl_dt_match, node);
3205         ctrl = (struct rockchip_pin_ctrl *)match->data;
3206
3207         for_each_child_of_node(node, np) {
3208                 if (!of_find_property(np, "gpio-controller", NULL))
3209                         continue;
3210
3211                 bank = ctrl->pin_banks;
3212                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3213                         if (!strcmp(bank->name, np->name)) {
3214                                 bank->of_node = np;
3215
3216                                 if (!rockchip_get_bank_data(bank, d))
3217                                         bank->valid = true;
3218
3219                                 break;
3220                         }
3221                 }
3222         }
3223
3224         grf_offs = ctrl->grf_mux_offset;
3225         pmu_offs = ctrl->pmu_mux_offset;
3226         drv_pmu_offs = ctrl->pmu_drv_offset;
3227         drv_grf_offs = ctrl->grf_drv_offset;
3228         bank = ctrl->pin_banks;
3229         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3230                 int bank_pins = 0;
3231
3232                 raw_spin_lock_init(&bank->slock);
3233                 bank->drvdata = d;
3234                 bank->pin_base = ctrl->nr_pins;
3235                 ctrl->nr_pins += bank->nr_pins;
3236
3237                 /* calculate iomux and drv offsets */
3238                 for (j = 0; j < 4; j++) {
3239                         struct rockchip_iomux *iom = &bank->iomux[j];
3240                         struct rockchip_drv *drv = &bank->drv[j];
3241                         int inc;
3242
3243                         if (bank_pins >= bank->nr_pins)
3244                                 break;
3245
3246                         /* preset iomux offset value, set new start value */
3247                         if (iom->offset >= 0) {
3248                                 if (iom->type & IOMUX_SOURCE_PMU)
3249                                         pmu_offs = iom->offset;
3250                                 else
3251                                         grf_offs = iom->offset;
3252                         } else { /* set current iomux offset */
3253                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3254                                                         pmu_offs : grf_offs;
3255                         }
3256
3257                         /* preset drv offset value, set new start value */
3258                         if (drv->offset >= 0) {
3259                                 if (iom->type & IOMUX_SOURCE_PMU)
3260                                         drv_pmu_offs = drv->offset;
3261                                 else
3262                                         drv_grf_offs = drv->offset;
3263                         } else { /* set current drv offset */
3264                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3265                                                 drv_pmu_offs : drv_grf_offs;
3266                         }
3267
3268                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3269                                 i, j, iom->offset, drv->offset);
3270
3271                         /*
3272                          * Increase offset according to iomux width.
3273                          * 4bit iomux'es are spread over two registers.
3274                          */
3275                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
3276                                             IOMUX_WIDTH_3BIT)) ? 8 : 4;
3277                         if (iom->type & IOMUX_SOURCE_PMU)
3278                                 pmu_offs += inc;
3279                         else
3280                                 grf_offs += inc;
3281
3282                         /*
3283                          * Increase offset according to drv width.
3284                          * 3bit drive-strenth'es are spread over two registers.
3285                          */
3286                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3287                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3288                                 inc = 8;
3289                         else
3290                                 inc = 4;
3291
3292                         if (iom->type & IOMUX_SOURCE_PMU)
3293                                 drv_pmu_offs += inc;
3294                         else
3295                                 drv_grf_offs += inc;
3296
3297                         bank_pins += 8;
3298                 }
3299
3300                 /* calculate the per-bank recalced_mask */
3301                 for (j = 0; j < ctrl->niomux_recalced; j++) {
3302                         int pin = 0;
3303
3304                         if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3305                                 pin = ctrl->iomux_recalced[j].pin;
3306                                 bank->recalced_mask |= BIT(pin);
3307                         }
3308                 }
3309
3310                 /* calculate the per-bank route_mask */
3311                 for (j = 0; j < ctrl->niomux_routes; j++) {
3312                         int pin = 0;
3313
3314                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3315                                 pin = ctrl->iomux_routes[j].pin;
3316                                 bank->route_mask |= BIT(pin);
3317                         }
3318                 }
3319         }
3320
3321         return ctrl;
3322 }
3323
3324 #define RK3288_GRF_GPIO6C_IOMUX         0x64
3325 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
3326
3327 static u32 rk3288_grf_gpio6c_iomux;
3328
3329 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3330 {
3331         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3332         int ret = pinctrl_force_sleep(info->pctl_dev);
3333
3334         if (ret)
3335                 return ret;
3336
3337         /*
3338          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3339          * the setting here, and restore it at resume.
3340          */
3341         if (info->ctrl->type == RK3288) {
3342                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3343                                   &rk3288_grf_gpio6c_iomux);
3344                 if (ret) {
3345                         pinctrl_force_default(info->pctl_dev);
3346                         return ret;
3347                 }
3348         }
3349
3350         return 0;
3351 }
3352
3353 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3354 {
3355         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3356         int ret;
3357
3358         if (info->ctrl->type == RK3288) {
3359                 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3360                                    rk3288_grf_gpio6c_iomux |
3361                                    GPIO6C6_SEL_WRITE_ENABLE);
3362                 if (ret)
3363                         return ret;
3364         }
3365
3366         return pinctrl_force_default(info->pctl_dev);
3367 }
3368
3369 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3370                          rockchip_pinctrl_resume);
3371
3372 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3373 {
3374         struct rockchip_pinctrl *info;
3375         struct device *dev = &pdev->dev;
3376         struct rockchip_pin_ctrl *ctrl;
3377         struct device_node *np = pdev->dev.of_node, *node;
3378         struct resource *res;
3379         void __iomem *base;
3380         int ret;
3381
3382         if (!dev->of_node) {
3383                 dev_err(dev, "device tree node not found\n");
3384                 return -ENODEV;
3385         }
3386
3387         info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3388         if (!info)
3389                 return -ENOMEM;
3390
3391         info->dev = dev;
3392
3393         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3394         if (!ctrl) {
3395                 dev_err(dev, "driver data not available\n");
3396                 return -EINVAL;
3397         }
3398         info->ctrl = ctrl;
3399
3400         node = of_parse_phandle(np, "rockchip,grf", 0);
3401         if (node) {
3402                 info->regmap_base = syscon_node_to_regmap(node);
3403                 of_node_put(node);
3404                 if (IS_ERR(info->regmap_base))
3405                         return PTR_ERR(info->regmap_base);
3406         } else {
3407                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3408                 base = devm_ioremap_resource(&pdev->dev, res);
3409                 if (IS_ERR(base))
3410                         return PTR_ERR(base);
3411
3412                 rockchip_regmap_config.max_register = resource_size(res) - 4;
3413                 rockchip_regmap_config.name = "rockchip,pinctrl";
3414                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3415                                                     &rockchip_regmap_config);
3416
3417                 /* to check for the old dt-bindings */
3418                 info->reg_size = resource_size(res);
3419
3420                 /* Honor the old binding, with pull registers as 2nd resource */
3421                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3422                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3423                         base = devm_ioremap_resource(&pdev->dev, res);
3424                         if (IS_ERR(base))
3425                                 return PTR_ERR(base);
3426
3427                         rockchip_regmap_config.max_register =
3428                                                         resource_size(res) - 4;
3429                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3430                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3431                                                     base,
3432                                                     &rockchip_regmap_config);
3433                 }
3434         }
3435
3436         /* try to find the optional reference to the pmu syscon */
3437         node = of_parse_phandle(np, "rockchip,pmu", 0);
3438         if (node) {
3439                 info->regmap_pmu = syscon_node_to_regmap(node);
3440                 of_node_put(node);
3441                 if (IS_ERR(info->regmap_pmu))
3442                         return PTR_ERR(info->regmap_pmu);
3443         }
3444
3445         ret = rockchip_gpiolib_register(pdev, info);
3446         if (ret)
3447                 return ret;
3448
3449         ret = rockchip_pinctrl_register(pdev, info);
3450         if (ret) {
3451                 rockchip_gpiolib_unregister(pdev, info);
3452                 return ret;
3453         }
3454
3455         platform_set_drvdata(pdev, info);
3456
3457         return 0;
3458 }
3459
3460 static struct rockchip_pin_bank px30_pin_banks[] = {
3461         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3462                                              IOMUX_SOURCE_PMU,
3463                                              IOMUX_SOURCE_PMU,
3464                                              IOMUX_SOURCE_PMU
3465                             ),
3466         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3467                                              IOMUX_WIDTH_4BIT,
3468                                              IOMUX_WIDTH_4BIT,
3469                                              IOMUX_WIDTH_4BIT
3470                             ),
3471         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3472                                              IOMUX_WIDTH_4BIT,
3473                                              IOMUX_WIDTH_4BIT,
3474                                              IOMUX_WIDTH_4BIT
3475                             ),
3476         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3477                                              IOMUX_WIDTH_4BIT,
3478                                              IOMUX_WIDTH_4BIT,
3479                                              IOMUX_WIDTH_4BIT
3480                             ),
3481 };
3482
3483 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3484                 .pin_banks              = px30_pin_banks,
3485                 .nr_banks               = ARRAY_SIZE(px30_pin_banks),
3486                 .label                  = "PX30-GPIO",
3487                 .type                   = PX30,
3488                 .grf_mux_offset         = 0x0,
3489                 .pmu_mux_offset         = 0x0,
3490                 .iomux_routes           = px30_mux_route_data,
3491                 .niomux_routes          = ARRAY_SIZE(px30_mux_route_data),
3492                 .pull_calc_reg          = px30_calc_pull_reg_and_bit,
3493                 .drv_calc_reg           = px30_calc_drv_reg_and_bit,
3494                 .schmitt_calc_reg       = px30_calc_schmitt_reg_and_bit,
3495 };
3496
3497 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3498         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3499                                              IOMUX_SOURCE_PMU,
3500                                              IOMUX_SOURCE_PMU,
3501                                              IOMUX_SOURCE_PMU),
3502         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3503         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3504         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3505 };
3506
3507 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3508         .pin_banks              = rv1108_pin_banks,
3509         .nr_banks               = ARRAY_SIZE(rv1108_pin_banks),
3510         .label                  = "RV1108-GPIO",
3511         .type                   = RV1108,
3512         .grf_mux_offset         = 0x10,
3513         .pmu_mux_offset         = 0x0,
3514         .iomux_recalced         = rv1108_mux_recalced_data,
3515         .niomux_recalced        = ARRAY_SIZE(rv1108_mux_recalced_data),
3516         .pull_calc_reg          = rv1108_calc_pull_reg_and_bit,
3517         .drv_calc_reg           = rv1108_calc_drv_reg_and_bit,
3518         .schmitt_calc_reg       = rv1108_calc_schmitt_reg_and_bit,
3519 };
3520
3521 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3522         PIN_BANK(0, 32, "gpio0"),
3523         PIN_BANK(1, 32, "gpio1"),
3524         PIN_BANK(2, 32, "gpio2"),
3525         PIN_BANK(3, 32, "gpio3"),
3526 };
3527
3528 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3529                 .pin_banks              = rk2928_pin_banks,
3530                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
3531                 .label                  = "RK2928-GPIO",
3532                 .type                   = RK2928,
3533                 .grf_mux_offset         = 0xa8,
3534                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3535 };
3536
3537 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3538         PIN_BANK(0, 32, "gpio0"),
3539         PIN_BANK(1, 32, "gpio1"),
3540         PIN_BANK(2, 32, "gpio2"),
3541 };
3542
3543 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3544                 .pin_banks              = rk3036_pin_banks,
3545                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
3546                 .label                  = "RK3036-GPIO",
3547                 .type                   = RK2928,
3548                 .grf_mux_offset         = 0xa8,
3549                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3550 };
3551
3552 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3553         PIN_BANK(0, 32, "gpio0"),
3554         PIN_BANK(1, 32, "gpio1"),
3555         PIN_BANK(2, 32, "gpio2"),
3556         PIN_BANK(3, 32, "gpio3"),
3557         PIN_BANK(4, 32, "gpio4"),
3558         PIN_BANK(6, 16, "gpio6"),
3559 };
3560
3561 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3562                 .pin_banks              = rk3066a_pin_banks,
3563                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
3564                 .label                  = "RK3066a-GPIO",
3565                 .type                   = RK2928,
3566                 .grf_mux_offset         = 0xa8,
3567                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3568 };
3569
3570 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3571         PIN_BANK(0, 32, "gpio0"),
3572         PIN_BANK(1, 32, "gpio1"),
3573         PIN_BANK(2, 32, "gpio2"),
3574         PIN_BANK(3, 32, "gpio3"),
3575 };
3576
3577 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3578                 .pin_banks      = rk3066b_pin_banks,
3579                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
3580                 .label          = "RK3066b-GPIO",
3581                 .type           = RK3066B,
3582                 .grf_mux_offset = 0x60,
3583 };
3584
3585 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3586         PIN_BANK(0, 32, "gpio0"),
3587         PIN_BANK(1, 32, "gpio1"),
3588         PIN_BANK(2, 32, "gpio2"),
3589         PIN_BANK(3, 32, "gpio3"),
3590 };
3591
3592 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3593                 .pin_banks              = rk3128_pin_banks,
3594                 .nr_banks               = ARRAY_SIZE(rk3128_pin_banks),
3595                 .label                  = "RK3128-GPIO",
3596                 .type                   = RK3128,
3597                 .grf_mux_offset         = 0xa8,
3598                 .iomux_recalced         = rk3128_mux_recalced_data,
3599                 .niomux_recalced        = ARRAY_SIZE(rk3128_mux_recalced_data),
3600                 .iomux_routes           = rk3128_mux_route_data,
3601                 .niomux_routes          = ARRAY_SIZE(rk3128_mux_route_data),
3602                 .pull_calc_reg          = rk3128_calc_pull_reg_and_bit,
3603 };
3604
3605 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3606         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3607         PIN_BANK(1, 32, "gpio1"),
3608         PIN_BANK(2, 32, "gpio2"),
3609         PIN_BANK(3, 32, "gpio3"),
3610 };
3611
3612 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3613                 .pin_banks              = rk3188_pin_banks,
3614                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
3615                 .label                  = "RK3188-GPIO",
3616                 .type                   = RK3188,
3617                 .grf_mux_offset         = 0x60,
3618                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
3619 };
3620
3621 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3622         PIN_BANK(0, 32, "gpio0"),
3623         PIN_BANK(1, 32, "gpio1"),
3624         PIN_BANK(2, 32, "gpio2"),
3625         PIN_BANK(3, 32, "gpio3"),
3626 };
3627
3628 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3629                 .pin_banks              = rk3228_pin_banks,
3630                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
3631                 .label                  = "RK3228-GPIO",
3632                 .type                   = RK3288,
3633                 .grf_mux_offset         = 0x0,
3634                 .iomux_routes           = rk3228_mux_route_data,
3635                 .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
3636                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3637                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3638 };
3639
3640 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3641         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3642                                              IOMUX_SOURCE_PMU,
3643                                              IOMUX_SOURCE_PMU,
3644                                              IOMUX_UNROUTED
3645                             ),
3646         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3647                                              IOMUX_UNROUTED,
3648                                              IOMUX_UNROUTED,
3649                                              0
3650                             ),
3651         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3652         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3653         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3654                                              IOMUX_WIDTH_4BIT,
3655                                              0,
3656                                              0
3657                             ),
3658         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3659                                              0,
3660                                              0,
3661                                              IOMUX_UNROUTED
3662                             ),
3663         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3664         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3665                                              0,
3666                                              IOMUX_WIDTH_4BIT,
3667                                              IOMUX_UNROUTED
3668                             ),
3669         PIN_BANK(8, 16, "gpio8"),
3670 };
3671
3672 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3673                 .pin_banks              = rk3288_pin_banks,
3674                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
3675                 .label                  = "RK3288-GPIO",
3676                 .type                   = RK3288,
3677                 .grf_mux_offset         = 0x0,
3678                 .pmu_mux_offset         = 0x84,
3679                 .iomux_routes           = rk3288_mux_route_data,
3680                 .niomux_routes          = ARRAY_SIZE(rk3288_mux_route_data),
3681                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
3682                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
3683 };
3684
3685 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3686         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3687         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3688         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3689                              IOMUX_WIDTH_3BIT,
3690                              IOMUX_WIDTH_3BIT,
3691                              0),
3692         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3693                              IOMUX_WIDTH_3BIT,
3694                              IOMUX_WIDTH_3BIT,
3695                              0,
3696                              0),
3697 };
3698
3699 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3700                 .pin_banks              = rk3328_pin_banks,
3701                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
3702                 .label                  = "RK3328-GPIO",
3703                 .type                   = RK3288,
3704                 .grf_mux_offset         = 0x0,
3705                 .iomux_recalced         = rk3328_mux_recalced_data,
3706                 .niomux_recalced        = ARRAY_SIZE(rk3328_mux_recalced_data),
3707                 .iomux_routes           = rk3328_mux_route_data,
3708                 .niomux_routes          = ARRAY_SIZE(rk3328_mux_route_data),
3709                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3710                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3711                 .schmitt_calc_reg       = rk3328_calc_schmitt_reg_and_bit,
3712 };
3713
3714 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3715         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3716                                              IOMUX_SOURCE_PMU,
3717                                              IOMUX_SOURCE_PMU,
3718                                              IOMUX_SOURCE_PMU
3719                             ),
3720         PIN_BANK(1, 32, "gpio1"),
3721         PIN_BANK(2, 32, "gpio2"),
3722         PIN_BANK(3, 32, "gpio3"),
3723 };
3724
3725 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3726                 .pin_banks              = rk3368_pin_banks,
3727                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
3728                 .label                  = "RK3368-GPIO",
3729                 .type                   = RK3368,
3730                 .grf_mux_offset         = 0x0,
3731                 .pmu_mux_offset         = 0x0,
3732                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
3733                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
3734 };
3735
3736 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3737         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3738                                                          IOMUX_SOURCE_PMU,
3739                                                          IOMUX_SOURCE_PMU,
3740                                                          IOMUX_SOURCE_PMU,
3741                                                          IOMUX_SOURCE_PMU,
3742                                                          DRV_TYPE_IO_1V8_ONLY,
3743                                                          DRV_TYPE_IO_1V8_ONLY,
3744                                                          DRV_TYPE_IO_DEFAULT,
3745                                                          DRV_TYPE_IO_DEFAULT,
3746                                                          0x80,
3747                                                          0x88,
3748                                                          -1,
3749                                                          -1,
3750                                                          PULL_TYPE_IO_1V8_ONLY,
3751                                                          PULL_TYPE_IO_1V8_ONLY,
3752                                                          PULL_TYPE_IO_DEFAULT,
3753                                                          PULL_TYPE_IO_DEFAULT
3754                                                         ),
3755         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3756                                         IOMUX_SOURCE_PMU,
3757                                         IOMUX_SOURCE_PMU,
3758                                         IOMUX_SOURCE_PMU,
3759                                         DRV_TYPE_IO_1V8_OR_3V0,
3760                                         DRV_TYPE_IO_1V8_OR_3V0,
3761                                         DRV_TYPE_IO_1V8_OR_3V0,
3762                                         DRV_TYPE_IO_1V8_OR_3V0,
3763                                         0xa0,
3764                                         0xa8,
3765                                         0xb0,
3766                                         0xb8
3767                                         ),
3768         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3769                                       DRV_TYPE_IO_1V8_OR_3V0,
3770                                       DRV_TYPE_IO_1V8_ONLY,
3771                                       DRV_TYPE_IO_1V8_ONLY,
3772                                       PULL_TYPE_IO_DEFAULT,
3773                                       PULL_TYPE_IO_DEFAULT,
3774                                       PULL_TYPE_IO_1V8_ONLY,
3775                                       PULL_TYPE_IO_1V8_ONLY
3776                                       ),
3777         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3778                            DRV_TYPE_IO_3V3_ONLY,
3779                            DRV_TYPE_IO_3V3_ONLY,
3780                            DRV_TYPE_IO_1V8_OR_3V0
3781                            ),
3782         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3783                            DRV_TYPE_IO_1V8_3V0_AUTO,
3784                            DRV_TYPE_IO_1V8_OR_3V0,
3785                            DRV_TYPE_IO_1V8_OR_3V0
3786                            ),
3787 };
3788
3789 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3790                 .pin_banks              = rk3399_pin_banks,
3791                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
3792                 .label                  = "RK3399-GPIO",
3793                 .type                   = RK3399,
3794                 .grf_mux_offset         = 0xe000,
3795                 .pmu_mux_offset         = 0x0,
3796                 .grf_drv_offset         = 0xe100,
3797                 .pmu_drv_offset         = 0x80,
3798                 .iomux_routes           = rk3399_mux_route_data,
3799                 .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
3800                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
3801                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
3802 };
3803
3804 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3805         { .compatible = "rockchip,px30-pinctrl",
3806                 .data = &px30_pin_ctrl },
3807         { .compatible = "rockchip,rv1108-pinctrl",
3808                 .data = &rv1108_pin_ctrl },
3809         { .compatible = "rockchip,rk2928-pinctrl",
3810                 .data = &rk2928_pin_ctrl },
3811         { .compatible = "rockchip,rk3036-pinctrl",
3812                 .data = &rk3036_pin_ctrl },
3813         { .compatible = "rockchip,rk3066a-pinctrl",
3814                 .data = &rk3066a_pin_ctrl },
3815         { .compatible = "rockchip,rk3066b-pinctrl",
3816                 .data = &rk3066b_pin_ctrl },
3817         { .compatible = "rockchip,rk3128-pinctrl",
3818                 .data = (void *)&rk3128_pin_ctrl },
3819         { .compatible = "rockchip,rk3188-pinctrl",
3820                 .data = &rk3188_pin_ctrl },
3821         { .compatible = "rockchip,rk3228-pinctrl",
3822                 .data = &rk3228_pin_ctrl },
3823         { .compatible = "rockchip,rk3288-pinctrl",
3824                 .data = &rk3288_pin_ctrl },
3825         { .compatible = "rockchip,rk3328-pinctrl",
3826                 .data = &rk3328_pin_ctrl },
3827         { .compatible = "rockchip,rk3368-pinctrl",
3828                 .data = &rk3368_pin_ctrl },
3829         { .compatible = "rockchip,rk3399-pinctrl",
3830                 .data = &rk3399_pin_ctrl },
3831         {},
3832 };
3833
3834 static struct platform_driver rockchip_pinctrl_driver = {
3835         .probe          = rockchip_pinctrl_probe,
3836         .driver = {
3837                 .name   = "rockchip-pinctrl",
3838                 .pm = &rockchip_pinctrl_dev_pm_ops,
3839                 .of_match_table = rockchip_pinctrl_dt_match,
3840         },
3841 };
3842
3843 static int __init rockchip_pinctrl_drv_register(void)
3844 {
3845         return platform_driver_register(&rockchip_pinctrl_driver);
3846 }
3847 postcore_initcall(rockchip_pinctrl_drv_register);