drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

   1 /*
   2  * Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver
   3  * with eint support.
   4  *
   5  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  * Copyright (c) 2012 Linaro Ltd
   8  *              http://www.linaro.org
   9  * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This file contains the Samsung Exynos specific information required by the
  17  * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
  18  * external gpio and wakeup interrupt support.
  19  */
  20
  21 #include <linux/slab.h>
  22 #include <linux/soc/samsung/exynos-regs-pmu.h>
  23
  24 #include "pinctrl-samsung.h"
  25 #include "pinctrl-exynos.h"
  26
  27 static const struct samsung_pin_bank_type bank_type_off = {
  28         .fld_width = { 4, 1, 2, 2, 2, 2, },
  29         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
  30 };
  31
  32 static const struct samsung_pin_bank_type bank_type_alive = {
  33         .fld_width = { 4, 1, 2, 2, },
  34         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
  35 };
  36
  37 /* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */
  38 static const struct samsung_pin_bank_type exynos5433_bank_type_off = {
  39         .fld_width = { 4, 1, 2, 4, 2, 2, },
  40         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
  41 };
  42
  43 static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
  44         .fld_width = { 4, 1, 2, 4, },
  45         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
  46 };
  47
  48 /* Pad retention control code for accessing PMU regmap */
  49 static atomic_t exynos_shared_retention_refcnt;
  50
  51 /* pin banks of exynos5433 pin-controller - ALIVE */
  52 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = {
  53         EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
  54         EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
  55         EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
  56         EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
  57         EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
  58         EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
  59         EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
  60         EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
  61         EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
  62 };
  63
  64 /* pin banks of exynos5433 pin-controller - AUD */
  65 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = {
  66         EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
  67         EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
  68 };
  69
  70 /* pin banks of exynos5433 pin-controller - CPIF */
  71 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = {
  72         EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
  73 };
  74
  75 /* pin banks of exynos5433 pin-controller - eSE */
  76 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = {
  77         EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
  78 };
  79
  80 /* pin banks of exynos5433 pin-controller - FINGER */
  81 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = {
  82         EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
  83 };
  84
  85 /* pin banks of exynos5433 pin-controller - FSYS */
  86 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = {
  87         EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
  88         EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
  89         EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
  90         EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
  91         EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
  92         EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
  93 };
  94
  95 /* pin banks of exynos5433 pin-controller - IMEM */
  96 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = {
  97         EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
  98 };
  99
 100 /* pin banks of exynos5433 pin-controller - NFC */
 101 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = {
 102         EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
 103 };
 104
 105 /* pin banks of exynos5433 pin-controller - PERIC */
 106 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = {
 107         EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
 108         EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
 109         EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
 110         EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
 111         EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
 112         EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
 113         EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
 114         EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
 115         EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
 116         EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
 117         EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
 118         EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
 119         EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
 120         EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
 121         EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
 122         EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
 123         EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
 124 };
 125
 126 /* pin banks of exynos5433 pin-controller - TOUCH */
 127 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = {
 128         EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
 129 };
 130
 131 /* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */
 132 static const u32 exynos5433_retention_regs[] = {
 133         EXYNOS5433_PAD_RETENTION_TOP_OPTION,
 134         EXYNOS5433_PAD_RETENTION_UART_OPTION,
 135         EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
 136         EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
 137         EXYNOS5433_PAD_RETENTION_SPI_OPTION,
 138         EXYNOS5433_PAD_RETENTION_MIF_OPTION,
 139         EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
 140         EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
 141         EXYNOS5433_PAD_RETENTION_UFS_OPTION,
 142         EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,
 143 };
 144
 145 static const struct samsung_retention_data exynos5433_retention_data __initconst = {
 146         .regs    = exynos5433_retention_regs,
 147         .nr_regs = ARRAY_SIZE(exynos5433_retention_regs),
 148         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 149         .refcnt  = &exynos_shared_retention_refcnt,
 150         .init    = exynos_retention_init,
 151 };
 152
 153 /* PMU retention control for audio pins can be tied to audio pin bank */
 154 static const u32 exynos5433_audio_retention_regs[] = {
 155         EXYNOS5433_PAD_RETENTION_AUD_OPTION,
 156 };
 157
 158 static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = {
 159         .regs    = exynos5433_audio_retention_regs,
 160         .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs),
 161         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 162         .init    = exynos_retention_init,
 163 };
 164
 165 /* PMU retention control for mmc pins can be tied to fsys pin bank */
 166 static const u32 exynos5433_fsys_retention_regs[] = {
 167         EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
 168         EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
 169         EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
 170 };
 171
 172 static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = {
 173         .regs    = exynos5433_fsys_retention_regs,
 174         .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs),
 175         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 176         .init    = exynos_retention_init,
 177 };
 178
 179 /*
 180  * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
 181  * ten gpio/pin-mux/pinconfig controllers.
 182  */
 183 static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
 184         {
 185                 /* pin-controller instance 0 data */
 186                 .pin_banks      = exynos5433_pin_banks0,
 187                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks0),
 188                 .eint_wkup_init = exynos_eint_wkup_init,
 189                 .suspend        = exynos_pinctrl_suspend,
 190                 .resume         = exynos_pinctrl_resume,
 191                 .nr_ext_resources = 1,
 192                 .retention_data = &exynos5433_retention_data,
 193         }, {
 194                 /* pin-controller instance 1 data */
 195                 .pin_banks      = exynos5433_pin_banks1,
 196                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks1),
 197                 .eint_gpio_init = exynos_eint_gpio_init,
 198                 .suspend        = exynos_pinctrl_suspend,
 199                 .resume         = exynos_pinctrl_resume,
 200                 .retention_data = &exynos5433_audio_retention_data,
 201         }, {
 202                 /* pin-controller instance 2 data */
 203                 .pin_banks      = exynos5433_pin_banks2,
 204                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks2),
 205                 .eint_gpio_init = exynos_eint_gpio_init,
 206                 .suspend        = exynos_pinctrl_suspend,
 207                 .resume         = exynos_pinctrl_resume,
 208                 .retention_data = &exynos5433_retention_data,
 209         }, {
 210                 /* pin-controller instance 3 data */
 211                 .pin_banks      = exynos5433_pin_banks3,
 212                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks3),
 213                 .eint_gpio_init = exynos_eint_gpio_init,
 214                 .suspend        = exynos_pinctrl_suspend,
 215                 .resume         = exynos_pinctrl_resume,
 216                 .retention_data = &exynos5433_retention_data,
 217         }, {
 218                 /* pin-controller instance 4 data */
 219                 .pin_banks      = exynos5433_pin_banks4,
 220                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks4),
 221                 .eint_gpio_init = exynos_eint_gpio_init,
 222                 .suspend        = exynos_pinctrl_suspend,
 223                 .resume         = exynos_pinctrl_resume,
 224                 .retention_data = &exynos5433_retention_data,
 225         }, {
 226                 /* pin-controller instance 5 data */
 227                 .pin_banks      = exynos5433_pin_banks5,
 228                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks5),
 229                 .eint_gpio_init = exynos_eint_gpio_init,
 230                 .suspend        = exynos_pinctrl_suspend,
 231                 .resume         = exynos_pinctrl_resume,
 232                 .retention_data = &exynos5433_fsys_retention_data,
 233         }, {
 234                 /* pin-controller instance 6 data */
 235                 .pin_banks      = exynos5433_pin_banks6,
 236                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks6),
 237                 .eint_gpio_init = exynos_eint_gpio_init,
 238                 .suspend        = exynos_pinctrl_suspend,
 239                 .resume         = exynos_pinctrl_resume,
 240                 .retention_data = &exynos5433_retention_data,
 241         }, {
 242                 /* pin-controller instance 7 data */
 243                 .pin_banks      = exynos5433_pin_banks7,
 244                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks7),
 245                 .eint_gpio_init = exynos_eint_gpio_init,
 246                 .suspend        = exynos_pinctrl_suspend,
 247                 .resume         = exynos_pinctrl_resume,
 248                 .retention_data = &exynos5433_retention_data,
 249         }, {
 250                 /* pin-controller instance 8 data */
 251                 .pin_banks      = exynos5433_pin_banks8,
 252                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks8),
 253                 .eint_gpio_init = exynos_eint_gpio_init,
 254                 .suspend        = exynos_pinctrl_suspend,
 255                 .resume         = exynos_pinctrl_resume,
 256                 .retention_data = &exynos5433_retention_data,
 257         }, {
 258                 /* pin-controller instance 9 data */
 259                 .pin_banks      = exynos5433_pin_banks9,
 260                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks9),
 261                 .eint_gpio_init = exynos_eint_gpio_init,
 262                 .suspend        = exynos_pinctrl_suspend,
 263                 .resume         = exynos_pinctrl_resume,
 264                 .retention_data = &exynos5433_retention_data,
 265         },
 266 };
 267
 268 const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = {
 269         .ctrl           = exynos5433_pin_ctrl,
 270         .num_ctrl       = ARRAY_SIZE(exynos5433_pin_ctrl),
 271 };
 272
 273 /* pin banks of exynos7 pin-controller - ALIVE */
 274 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
 275         EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
 276         EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
 277         EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
 278         EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
 279 };
 280
 281 /* pin banks of exynos7 pin-controller - BUS0 */
 282 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
 283         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
 284         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
 285         EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
 286         EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
 287         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
 288         EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
 289         EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
 290         EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
 291         EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
 292         EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
 293         EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
 294         EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
 295         EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
 296         EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
 297         EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
 298 };
 299
 300 /* pin banks of exynos7 pin-controller - NFC */
 301 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
 302         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
 303 };
 304
 305 /* pin banks of exynos7 pin-controller - TOUCH */
 306 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
 307         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
 308 };
 309
 310 /* pin banks of exynos7 pin-controller - FF */
 311 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
 312         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
 313 };
 314
 315 /* pin banks of exynos7 pin-controller - ESE */
 316 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
 317         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
 318 };
 319
 320 /* pin banks of exynos7 pin-controller - FSYS0 */
 321 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
 322         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
 323 };
 324
 325 /* pin banks of exynos7 pin-controller - FSYS1 */
 326 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
 327         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
 328         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
 329         EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
 330         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
 331 };
 332
 333 /* pin banks of exynos7 pin-controller - BUS1 */
 334 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
 335         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
 336         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
 337         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
 338         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
 339         EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
 340         EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
 341         EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
 342         EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
 343         EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
 344         EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
 345 };
 346
 347 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
 348         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
 349         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
 350 };
 351
 352 static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
 353         {
 354                 /* pin-controller instance 0 Alive data */
 355                 .pin_banks      = exynos7_pin_banks0,
 356                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks0),
 357                 .eint_wkup_init = exynos_eint_wkup_init,
 358         }, {
 359                 /* pin-controller instance 1 BUS0 data */
 360                 .pin_banks      = exynos7_pin_banks1,
 361                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks1),
 362                 .eint_gpio_init = exynos_eint_gpio_init,
 363         }, {
 364                 /* pin-controller instance 2 NFC data */
 365                 .pin_banks      = exynos7_pin_banks2,
 366                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks2),
 367                 .eint_gpio_init = exynos_eint_gpio_init,
 368         }, {
 369                 /* pin-controller instance 3 TOUCH data */
 370                 .pin_banks      = exynos7_pin_banks3,
 371                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks3),
 372                 .eint_gpio_init = exynos_eint_gpio_init,
 373         }, {
 374                 /* pin-controller instance 4 FF data */
 375                 .pin_banks      = exynos7_pin_banks4,
 376                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks4),
 377                 .eint_gpio_init = exynos_eint_gpio_init,
 378         }, {
 379                 /* pin-controller instance 5 ESE data */
 380                 .pin_banks      = exynos7_pin_banks5,
 381                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks5),
 382                 .eint_gpio_init = exynos_eint_gpio_init,
 383         }, {
 384                 /* pin-controller instance 6 FSYS0 data */
 385                 .pin_banks      = exynos7_pin_banks6,
 386                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks6),
 387                 .eint_gpio_init = exynos_eint_gpio_init,
 388         }, {
 389                 /* pin-controller instance 7 FSYS1 data */
 390                 .pin_banks      = exynos7_pin_banks7,
 391                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
 392                 .eint_gpio_init = exynos_eint_gpio_init,
 393         }, {
 394                 /* pin-controller instance 8 BUS1 data */
 395                 .pin_banks      = exynos7_pin_banks8,
 396                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
 397                 .eint_gpio_init = exynos_eint_gpio_init,
 398         }, {
 399                 /* pin-controller instance 9 AUD data */
 400                 .pin_banks      = exynos7_pin_banks9,
 401                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks9),
 402                 .eint_gpio_init = exynos_eint_gpio_init,
 403         },
 404 };
 405
 406 const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
 407         .ctrl           = exynos7_pin_ctrl,
 408         .num_ctrl       = ARRAY_SIZE(exynos7_pin_ctrl),
 409 };