drivers/pinctrl/sh-pfc/pfc-r8a7778.c

   1 /*
   2  * r8a7778 processor support - PFC hardware block
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  * Copyright (C) 2015  Ulrich Hecht
   8  *
   9  * based on
  10  * Copyright (C) 2011  Renesas Solutions Corp.
  11  * Copyright (C) 2011  Magnus Damm
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; version 2 of the License.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  */
  22
  23 #include <linux/io.h>
  24 #include <linux/kernel.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26
  27 #include "core.h"
  28 #include "sh_pfc.h"
  29
  30 #define PORT_GP_PUP_1(bank, pin, fn, sfx)       \
  31         PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
  32
  33 #define PORT_GP_PUP_27(bank, fn, sfx)                                   \
  34         PORT_GP_PUP_1(bank, 0,  fn, sfx), PORT_GP_PUP_1(bank, 1,  fn, sfx),     \
  35         PORT_GP_PUP_1(bank, 2,  fn, sfx), PORT_GP_PUP_1(bank, 3,  fn, sfx),     \
  36         PORT_GP_PUP_1(bank, 4,  fn, sfx), PORT_GP_PUP_1(bank, 5,  fn, sfx),     \
  37         PORT_GP_PUP_1(bank, 6,  fn, sfx), PORT_GP_PUP_1(bank, 7,  fn, sfx),     \
  38         PORT_GP_PUP_1(bank, 8,  fn, sfx), PORT_GP_PUP_1(bank, 9,  fn, sfx),     \
  39         PORT_GP_PUP_1(bank, 10, fn, sfx), PORT_GP_PUP_1(bank, 11, fn, sfx),     \
  40         PORT_GP_PUP_1(bank, 12, fn, sfx), PORT_GP_PUP_1(bank, 13, fn, sfx),     \
  41         PORT_GP_PUP_1(bank, 14, fn, sfx), PORT_GP_PUP_1(bank, 15, fn, sfx),     \
  42         PORT_GP_PUP_1(bank, 16, fn, sfx), PORT_GP_PUP_1(bank, 17, fn, sfx),     \
  43         PORT_GP_PUP_1(bank, 18, fn, sfx), PORT_GP_PUP_1(bank, 19, fn, sfx),     \
  44         PORT_GP_PUP_1(bank, 20, fn, sfx), PORT_GP_PUP_1(bank, 21, fn, sfx),     \
  45         PORT_GP_PUP_1(bank, 22, fn, sfx), PORT_GP_PUP_1(bank, 23, fn, sfx),     \
  46         PORT_GP_PUP_1(bank, 24, fn, sfx), PORT_GP_PUP_1(bank, 25, fn, sfx),     \
  47         PORT_GP_PUP_1(bank, 26, fn, sfx)
  48
  49 #define CPU_ALL_PORT(fn, sfx)           \
  50         PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  51         PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  52         PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  53         PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  54         PORT_GP_PUP_27(4, fn, sfx)
  55
  56 enum {
  57         PINMUX_RESERVED = 0,
  58
  59         PINMUX_DATA_BEGIN,
  60         GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
  61         PINMUX_DATA_END,
  62
  63         PINMUX_FUNCTION_BEGIN,
  64         GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
  65
  66         /* GPSR0 */
  67         FN_IP0_1_0,     FN_PENC0,       FN_PENC1,       FN_IP0_4_2,
  68         FN_IP0_7_5,     FN_IP0_11_8,    FN_IP0_14_12,   FN_A1,
  69         FN_A2,          FN_A3,          FN_IP0_15,      FN_IP0_16,
  70         FN_IP0_17,      FN_IP0_18,      FN_IP0_19,      FN_IP0_20,
  71         FN_IP0_21,      FN_IP0_22,      FN_IP0_23,      FN_IP0_24,
  72         FN_IP0_25,      FN_IP0_26,      FN_IP0_27,      FN_IP0_28,
  73         FN_IP0_29,      FN_IP0_30,      FN_IP1_0,       FN_IP1_1,
  74         FN_IP1_4_2,     FN_IP1_7_5,     FN_IP1_10_8,    FN_IP1_14_11,
  75
  76         /* GPSR1 */
  77         FN_IP1_23_21,   FN_WE0,         FN_IP1_24,      FN_IP1_27_25,
  78         FN_IP1_29_28,   FN_IP2_2_0,     FN_IP2_5_3,     FN_IP2_8_6,
  79         FN_IP2_11_9,    FN_IP2_13_12,   FN_IP2_16_14,   FN_IP2_17,
  80         FN_IP2_30,      FN_IP2_31,      FN_IP3_1_0,     FN_IP3_4_2,
  81         FN_IP3_7_5,     FN_IP3_9_8,     FN_IP3_12_10,   FN_IP3_15_13,
  82         FN_IP3_18_16,   FN_IP3_20_19,   FN_IP3_23_21,   FN_IP3_26_24,
  83         FN_IP3_27,      FN_IP3_28,      FN_IP3_29,      FN_IP3_30,
  84         FN_IP3_31,      FN_IP4_0,       FN_IP4_3_1,     FN_IP4_6_4,
  85
  86         /* GPSR2 */
  87         FN_IP4_7,       FN_IP4_8,       FN_IP4_10_9,    FN_IP4_12_11,
  88         FN_IP4_14_13,   FN_IP4_16_15,   FN_IP4_20_17,   FN_IP4_24_21,
  89         FN_IP4_26_25,   FN_IP4_28_27,   FN_IP4_30_29,   FN_IP5_1_0,
  90         FN_IP5_3_2,     FN_IP5_5_4,     FN_IP5_6,       FN_IP5_7,
  91         FN_IP5_9_8,     FN_IP5_11_10,   FN_IP5_12,      FN_IP5_14_13,
  92         FN_IP5_17_15,   FN_IP5_20_18,   FN_AUDIO_CLKA,  FN_AUDIO_CLKB,
  93         FN_IP5_22_21,   FN_IP5_25_23,   FN_IP5_28_26,   FN_IP5_30_29,
  94         FN_IP6_1_0,     FN_IP6_4_2,     FN_IP6_6_5,     FN_IP6_7,
  95
  96         /* GPSR3 */
  97         FN_IP6_8,       FN_IP6_9,       FN_SSI_SCK34,   FN_IP6_10,
  98         FN_IP6_12_11,   FN_IP6_13,      FN_IP6_15_14,   FN_IP6_16,
  99         FN_IP6_18_17,   FN_IP6_20_19,   FN_IP6_21,      FN_IP6_23_22,
 100         FN_IP6_25_24,   FN_IP6_27_26,   FN_IP6_29_28,   FN_IP6_31_30,
 101         FN_IP7_1_0,     FN_IP7_3_2,     FN_IP7_5_4,     FN_IP7_8_6,
 102         FN_IP7_11_9,    FN_IP7_14_12,   FN_IP7_17_15,   FN_IP7_20_18,
 103         FN_IP7_21,      FN_IP7_24_22,   FN_IP7_28_25,   FN_IP7_31_29,
 104         FN_IP8_2_0,     FN_IP8_5_3,     FN_IP8_8_6,     FN_IP8_10_9,
 105
 106         /* GPSR4 */
 107         FN_IP8_13_11,   FN_IP8_15_14,   FN_IP8_18_16,   FN_IP8_21_19,
 108         FN_IP8_23_22,   FN_IP8_26_24,   FN_IP8_29_27,   FN_IP9_2_0,
 109         FN_IP9_5_3,     FN_IP9_8_6,     FN_IP9_11_9,    FN_IP9_14_12,
 110         FN_IP9_17_15,   FN_IP9_20_18,   FN_IP9_23_21,   FN_IP9_26_24,
 111         FN_IP9_29_27,   FN_IP10_2_0,    FN_IP10_5_3,    FN_IP10_8_6,
 112         FN_IP10_12_9,   FN_IP10_15_13,  FN_IP10_18_16,  FN_IP10_21_19,
 113         FN_IP10_24_22,  FN_AVS1,        FN_AVS2,
 114
 115         /* IPSR0 */
 116         FN_PRESETOUT,   FN_PWM1,        FN_AUDATA0,     FN_ARM_TRACEDATA_0,
 117         FN_GPSCLK_C,    FN_USB_OVC0,    FN_TX2_E,       FN_SDA2_B,
 118         FN_AUDATA1,     FN_ARM_TRACEDATA_1,             FN_GPSIN_C,
 119         FN_USB_OVC1,    FN_RX2_E,       FN_SCL2_B,      FN_SD1_DAT2_A,
 120         FN_MMC_D2,      FN_BS,          FN_ATADIR0_A,   FN_SDSELF_A,
 121         FN_PWM4_B,      FN_SD1_DAT3_A,  FN_MMC_D3,      FN_A0,
 122         FN_ATAG0_A,     FN_REMOCON_B,   FN_A4,          FN_A5,
 123         FN_A6,          FN_A7,          FN_A8,          FN_A9,
 124         FN_A10,         FN_A11,         FN_A12,         FN_A13,
 125         FN_A14,         FN_A15,         FN_A16,         FN_A17,
 126         FN_A18,         FN_A19,
 127
 128         /* IPSR1 */
 129         FN_A20,         FN_HSPI_CS1_B,  FN_A21,         FN_HSPI_CLK1_B,
 130         FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
 131         FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
 132         FN_TS_SDEN0_A,  FN_SD1_CD_A,    FN_MMC_D6,      FN_A24,
 133         FN_DREQ1_A,     FN_HRX0_B,      FN_TS_SPSYNC0_A,
 134         FN_SD1_WP_A,    FN_MMC_D7,      FN_A25, FN_DACK1_A,
 135         FN_HCTS0_B,     FN_RX3_C,       FN_TS_SDAT0_A,  FN_CLKOUT,
 136         FN_HSPI_TX1_B,  FN_PWM0_B,      FN_CS0,         FN_HSPI_RX1_B,
 137         FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
 138         FN_SCK2_B,      FN_MMC_D5,      FN_ATADIR0_B,   FN_RD_WR,
 139         FN_WE1,         FN_ATAWR0_B,    FN_SSI_WS1_B,   FN_EX_CS0,
 140         FN_SCL2_A,      FN_TX3_C,       FN_TS_SCK0_A,   FN_EX_CS1,
 141         FN_MMC_D4,
 142
 143         /* IPSR2 */
 144         FN_SD1_CLK_A,   FN_MMC_CLK,     FN_ATACS00,     FN_EX_CS2,
 145         FN_SD1_CMD_A,   FN_MMC_CMD,     FN_ATACS10,     FN_EX_CS3,
 146         FN_SD1_DAT0_A,  FN_MMC_D0,      FN_ATARD0,      FN_EX_CS4,
 147         FN_EX_WAIT1_A,  FN_SD1_DAT1_A,  FN_MMC_D1,      FN_ATAWR0_A,
 148         FN_EX_CS5,      FN_EX_WAIT2_A,  FN_DREQ0_A,     FN_RX3_A,
 149         FN_DACK0,       FN_TX3_A,       FN_DRACK0,      FN_EX_WAIT0,
 150         FN_PWM0_C,      FN_D0,          FN_D1,          FN_D2,
 151         FN_D3,          FN_D4,          FN_D5,          FN_D6,
 152         FN_D7,          FN_D8,          FN_D9,          FN_D10,
 153         FN_D11,         FN_RD_WR_B,     FN_IRQ0,        FN_MLB_CLK,
 154         FN_IRQ1_A,
 155
 156         /* IPSR3 */
 157         FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
 158         FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
 159         FN_SDSELF_B,    FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,
 160         FN_CAN_CLK_B,   FN_SDA3_B,      FN_SD1_CLK_B,   FN_HTX0_A,
 161         FN_TX0_A,       FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,
 162         FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
 163         FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        FN_SD1_DAT3_B,
 164         FN_HRTS0_A,     FN_RTS0,        FN_SSI_SCK4,    FN_DU0_DR0,
 165         FN_LCDOUT0,     FN_AUDATA2,     FN_ARM_TRACEDATA_2,
 166         FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,  FN_SSI_WS4,
 167         FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,     FN_ARM_TRACEDATA_3,
 168         FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
 169         FN_DU0_DR2,     FN_LCDOUT2,     FN_DU0_DR3,     FN_LCDOUT3,
 170         FN_DU0_DR4,     FN_LCDOUT4,     FN_DU0_DR5,     FN_LCDOUT5,
 171         FN_DU0_DR6,     FN_LCDOUT6,
 172
 173         /* IPSR4 */
 174         FN_DU0_DR7,     FN_LCDOUT7,     FN_DU0_DG0,     FN_LCDOUT8,
 175         FN_AUDATA4,     FN_ARM_TRACEDATA_4,             FN_TX1_D,
 176         FN_CAN0_TX_A,   FN_ADICHS0,     FN_DU0_DG1,     FN_LCDOUT9,
 177         FN_AUDATA5,     FN_ARM_TRACEDATA_5,             FN_RX1_D,
 178         FN_CAN0_RX_A,   FN_ADIDATA,     FN_DU0_DG2,     FN_LCDOUT10,
 179         FN_DU0_DG3,     FN_LCDOUT11,    FN_DU0_DG4,     FN_LCDOUT12,
 180         FN_RX0_B,       FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,
 181         FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       FN_DU0_DG7,
 182         FN_LCDOUT15,    FN_TX4_A,       FN_SSI_SCK2_B,  FN_VI0_R0_B,
 183         FN_DU0_DB0,     FN_LCDOUT16,    FN_AUDATA6,     FN_ARM_TRACEDATA_6,
 184         FN_GPSCLK_A,    FN_PWM0_A,      FN_ADICLK,      FN_TS_SDAT0_B,
 185         FN_AUDIO_CLKC,  FN_VI0_R1_B,    FN_DU0_DB1,     FN_LCDOUT17,
 186         FN_AUDATA7,     FN_ARM_TRACEDATA_7,             FN_GPSIN_A,
 187         FN_ADICS_SAMP,  FN_TS_SCK0_B,   FN_VI0_R2_B,    FN_DU0_DB2,
 188         FN_LCDOUT18,    FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,
 189         FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,
 190
 191         /* IPSR5 */
 192         FN_VI0_R5_B,    FN_DU0_DB5,     FN_LCDOUT21,    FN_VI1_DATA10_B,
 193         FN_DU0_DB6,     FN_LCDOUT22,    FN_VI1_DATA11_B,
 194         FN_DU0_DB7,     FN_LCDOUT23,    FN_DU0_DOTCLKIN,
 195         FN_QSTVA_QVS,   FN_DU0_DOTCLKO_UT0,             FN_QCLK,
 196         FN_DU0_DOTCLKO_UT1,             FN_QSTVB_QVE,   FN_AUDIO_CLKOUT_A,
 197         FN_REMOCON_C,   FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
 198         FN_QSTH_QHS,    FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
 199         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
 200         FN_QCPV_QDE,    FN_FMCLK_D,     FN_SSI_SCK1_A,  FN_DU0_DISP,
 201         FN_QPOLA,       FN_AUDCK,       FN_ARM_TRACECLK,
 202         FN_BPFCLK_D,    FN_SSI_WS1_A,   FN_DU0_CDE,     FN_QPOLB,
 203         FN_AUDSYNC,     FN_ARM_TRACECTL,                FN_FMIN_D,
 204         FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
 205         FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
 206         FN_CAN_CLK_D,   FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,
 207         FN_TX2_A,       FN_CAN0_TX_B,   FN_SSI_SDATA7,  FN_HSPI_TX0_B,
 208         FN_RX2_A,       FN_CAN0_RX_B,
 209
 210         /* IPSR6 */
 211         FN_SSI_SCK6,    FN_HSPI_RX2_A,  FN_FMCLK_B,     FN_CAN1_TX_B,
 212         FN_SSI_WS6,     FN_HSPI_CLK2_A, FN_BPFCLK_B,    FN_CAN1_RX_B,
 213         FN_SSI_SDATA6,  FN_HSPI_TX2_A,  FN_FMIN_B,      FN_SSI_SCK5,
 214         FN_RX4_C,       FN_SSI_WS5,     FN_TX4_C,       FN_SSI_SDATA5,
 215         FN_RX0_D,       FN_SSI_WS34,    FN_ARM_TRACEDATA_8,
 216         FN_SSI_SDATA4,  FN_SSI_WS2_A,   FN_ARM_TRACEDATA_9,
 217         FN_SSI_SDATA3,  FN_ARM_TRACEDATA_10,
 218         FN_SSI_SCK012,  FN_ARM_TRACEDATA_11,
 219         FN_TX0_D,       FN_SSI_WS012,   FN_ARM_TRACEDATA_12,
 220         FN_SSI_SDATA2,  FN_HSPI_CS2_A,  FN_ARM_TRACEDATA_13,
 221         FN_SDA1_A,      FN_SSI_SDATA1,  FN_ARM_TRACEDATA_14,
 222         FN_SCL1_A,      FN_SCK2_A,      FN_SSI_SDATA0,
 223         FN_ARM_TRACEDATA_15,
 224         FN_SD0_CLK,     FN_SUB_TDO,     FN_SD0_CMD,     FN_SUB_TRST,
 225         FN_SD0_DAT0,    FN_SUB_TMS,     FN_SD0_DAT1,    FN_SUB_TCK,
 226         FN_SD0_DAT2,    FN_SUB_TDI,
 227
 228         /* IPSR7 */
 229         FN_SD0_DAT3,    FN_IRQ1_B,      FN_SD0_CD,      FN_TX5_A,
 230         FN_SD0_WP,      FN_RX5_A,       FN_VI1_CLKENB,  FN_HSPI_CLK0_A,
 231         FN_HTX1_A,      FN_RTS1_C,      FN_VI1_FIELD,   FN_HSPI_CS0_A,
 232         FN_HRX1_A,      FN_SCK1_C,      FN_VI1_HSYNC,   FN_HSPI_RX0_A,
 233         FN_HRTS1_A,     FN_FMCLK_A,     FN_RX1_C,       FN_VI1_VSYNC,
 234         FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,    FN_TX1_C,
 235         FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      FN_IRQ2_C,
 236         FN_CTS1_C,      FN_SPEEDIN,     FN_VI0_CLK,     FN_CAN_CLK_A,
 237         FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
 238         FN_HSPI_RX1_A,  FN_RX4_B,       FN_VI0_FIELD,   FN_SD2_DAT3_B,
 239         FN_VI0_R3_C,    FN_VI1_DATA1,   FN_DU1_DG7,     FN_HSPI_CLK1_A,
 240         FN_TX4_B,       FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,
 241         FN_DU1_DR2,     FN_HSPI_CS1_A,  FN_RX3_B,
 242
 243         /* IPSR8 */
 244         FN_VI0_VSYNC,   FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
 245         FN_HSPI_TX1_A,  FN_TX3_B,       FN_VI0_DATA0_VI0_B0,
 246         FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,       FN_VI0_DATA1_VI0_B1,
 247         FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,       FN_VI0_DATA2_VI0_B2,
 248         FN_DU1_DG4,     FN_RX0_C,       FN_VI0_DATA3_VI0_B3,
 249         FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,       FN_VI0_DATA4_VI0_B4,
 250         FN_DU1_DB2,     FN_RX1_A,       FN_VI0_DATA5_VI0_B5,
 251         FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,        FN_HSCK1_B,
 252         FN_VI0_DATA6_VI0_G0,            FN_DU1_DB4,     FN_CTS1_A,
 253         FN_PWM5,        FN_VI0_DATA7_VI0_G1,            FN_DU1_DB5,
 254         FN_RTS1_A,      FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,
 255         FN_DU1_DR4,     FN_HTX1_B,      FN_VI0_G3,      FN_SD2_CMD_B,
 256         FN_VI1_DATA5,   FN_DU1_DR5,     FN_HRX1_B,
 257
 258         /* IPSR9 */
 259         FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
 260         FN_HRTS1_B,     FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,
 261         FN_DU1_DR7,     FN_HCTS1_B,     FN_VI0_R0_A,    FN_VI1_CLK,
 262         FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,                FN_VI0_R1_A,
 263         FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,    FN_PWM2,
 264         FN_TCLK1,       FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,
 265         FN_ETH_TXD1,    FN_PWM3,        FN_VI0_R3_A,    FN_ETH_CRS_DV,
 266         FN_IECLK,       FN_SCK2_C,      FN_VI0_R4_A,    FN_ETH_TX_EN,
 267         FN_IETX,        FN_TX2_C,       FN_VI0_R5_A,    FN_ETH_RX_ER,
 268         FN_FMCLK_C,     FN_IERX,        FN_RX2_C,       FN_VI1_DATA10_A,
 269         FN_DU1_DOTCLKOUT,               FN_ETH_RXD0,    FN_BPFCLK_C,
 270         FN_TX2_D,       FN_SDA2_C,      FN_VI1_DATA11_A,
 271         FN_DU1_EXHSYNC_DU1_HSYNC,       FN_ETH_RXD1,    FN_FMIN_C,
 272         FN_RX2_D,       FN_SCL2_C,
 273
 274         /* IPSR10 */
 275         FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,       FN_ATARD1,
 276         FN_ETH_MDC,     FN_SDA1_B,      FN_SD2_CMD_A,
 277         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,                FN_ATAWR1,
 278         FN_ETH_MDIO,    FN_SCL1_B,      FN_SD2_DAT0_A,  FN_DU1_DISP,
 279         FN_ATACS01,     FN_DREQ1_B,     FN_ETH_LINK,    FN_CAN1_RX_A,
 280         FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
 281         FN_ETH_MAGIC,   FN_CAN1_TX_A,   FN_PWM6,        FN_SD2_DAT2_A,
 282         FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,     FN_HSPI_CLK2_B,
 283         FN_GPSCLK_B,    FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,
 284         FN_ATAG1,       FN_HSPI_CS2_B,  FN_GPSIN_B,     FN_SD2_CD_A,
 285         FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,     FN_HSPI_RX2_B,
 286         FN_REMOCON_A,   FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,
 287         FN_DACK0_B,     FN_HSPI_TX2_B,  FN_CAN_CLK_C,
 288
 289         /* SEL */
 290         FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
 291         FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C,
 292         FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
 293         FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E,
 294         FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
 295         FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
 296         FN_SEL_SSI2_A,  FN_SEL_SSI2_B,
 297         FN_SEL_SSI1_A,  FN_SEL_SSI1_B,
 298         FN_SEL_VI1_A,   FN_SEL_VI1_B,
 299         FN_SEL_VI0_A,   FN_SEL_VI0_B,   FN_SEL_VI0_C,   FN_SEL_VI0_D,
 300         FN_SEL_SD2_A,   FN_SEL_SD2_B,
 301         FN_SEL_SD1_A,   FN_SEL_SD1_B,
 302         FN_SEL_IRQ3_A,  FN_SEL_IRQ3_B,
 303         FN_SEL_IRQ2_A,  FN_SEL_IRQ2_B,  FN_SEL_IRQ2_C,
 304         FN_SEL_IRQ1_A,  FN_SEL_IRQ1_B,
 305         FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
 306         FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
 307         FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
 308         FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
 309         FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
 310         FN_SEL_CAN1_A,  FN_SEL_CAN1_B,
 311         FN_SEL_CAN0_A,  FN_SEL_CAN0_B,
 312         FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
 313         FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
 314         FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
 315         FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
 316         FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,       FN_SEL_REMOCON_C,
 317         FN_SEL_FM_A,    FN_SEL_FM_B,    FN_SEL_FM_C,    FN_SEL_FM_D,
 318         FN_SEL_GPS_A,   FN_SEL_GPS_B,   FN_SEL_GPS_C,
 319         FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
 320         FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
 321         FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
 322         FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
 323         FN_SEL_I2C3_A,  FN_SEL_I2C3_B,  FN_SEL_I2C3_C,
 324         FN_SEL_I2C2_A,  FN_SEL_I2C2_B,  FN_SEL_I2C2_C,
 325         FN_SEL_I2C1_A,  FN_SEL_I2C1_B,
 326         PINMUX_FUNCTION_END,
 327
 328         PINMUX_MARK_BEGIN,
 329
 330         /* GPSR0 */
 331         PENC0_MARK,     PENC1_MARK,     A1_MARK,        A2_MARK,        A3_MARK,
 332
 333         /* GPSR1 */
 334         WE0_MARK,
 335
 336         /* GPSR2 */
 337         AUDIO_CLKA_MARK,
 338         AUDIO_CLKB_MARK,
 339
 340         /* GPSR3 */
 341         SSI_SCK34_MARK,
 342
 343         /* GPSR4 */
 344         AVS1_MARK,
 345         AVS2_MARK,
 346
 347         VI0_R0_C_MARK,          /* see sel_vi0 */
 348         VI0_R1_C_MARK,          /* see sel_vi0 */
 349         VI0_R2_C_MARK,          /* see sel_vi0 */
 350         /* VI0_R3_C_MARK, */
 351         VI0_R4_C_MARK,          /* see sel_vi0 */
 352         VI0_R5_C_MARK,          /* see sel_vi0 */
 353
 354         VI0_R0_D_MARK,          /* see sel_vi0 */
 355         VI0_R1_D_MARK,          /* see sel_vi0 */
 356         VI0_R2_D_MARK,          /* see sel_vi0 */
 357         VI0_R3_D_MARK,          /* see sel_vi0 */
 358         VI0_R4_D_MARK,          /* see sel_vi0 */
 359         VI0_R5_D_MARK,          /* see sel_vi0 */
 360
 361         /* IPSR0 */
 362         PRESETOUT_MARK, PWM1_MARK,      AUDATA0_MARK,
 363         ARM_TRACEDATA_0_MARK,           GPSCLK_C_MARK,  USB_OVC0_MARK,
 364         TX2_E_MARK,     SDA2_B_MARK,    AUDATA1_MARK,   ARM_TRACEDATA_1_MARK,
 365         GPSIN_C_MARK,   USB_OVC1_MARK,  RX2_E_MARK,     SCL2_B_MARK,
 366         SD1_DAT2_A_MARK,                MMC_D2_MARK,    BS_MARK,
 367         ATADIR0_A_MARK, SDSELF_A_MARK,  PWM4_B_MARK,    SD1_DAT3_A_MARK,
 368         MMC_D3_MARK,    A0_MARK,        ATAG0_A_MARK,   REMOCON_B_MARK,
 369         A4_MARK,        A5_MARK,        A6_MARK,        A7_MARK,
 370         A8_MARK,        A9_MARK,        A10_MARK,       A11_MARK,
 371         A12_MARK,       A13_MARK,       A14_MARK,       A15_MARK,
 372         A16_MARK,       A17_MARK,       A18_MARK,       A19_MARK,
 373
 374         /* IPSR1 */
 375         A20_MARK,       HSPI_CS1_B_MARK,                A21_MARK,
 376         HSPI_CLK1_B_MARK,               A22_MARK,       HRTS0_B_MARK,
 377         RX2_B_MARK,     DREQ2_A_MARK,   A23_MARK,       HTX0_B_MARK,
 378         TX2_B_MARK,     DACK2_A_MARK,   TS_SDEN0_A_MARK,
 379         SD1_CD_A_MARK,  MMC_D6_MARK,    A24_MARK,       DREQ1_A_MARK,
 380         HRX0_B_MARK,    TS_SPSYNC0_A_MARK,              SD1_WP_A_MARK,
 381         MMC_D7_MARK,    A25_MARK,       DACK1_A_MARK,   HCTS0_B_MARK,
 382         RX3_C_MARK,     TS_SDAT0_A_MARK,                CLKOUT_MARK,
 383         HSPI_TX1_B_MARK,                PWM0_B_MARK,    CS0_MARK,
 384         HSPI_RX1_B_MARK,                SSI_SCK1_B_MARK,
 385         ATAG0_B_MARK,   CS1_A26_MARK,   SDA2_A_MARK,    SCK2_B_MARK,
 386         MMC_D5_MARK,    ATADIR0_B_MARK, RD_WR_MARK,     WE1_MARK,
 387         ATAWR0_B_MARK,  SSI_WS1_B_MARK, EX_CS0_MARK,    SCL2_A_MARK,
 388         TX3_C_MARK,     TS_SCK0_A_MARK, EX_CS1_MARK,    MMC_D4_MARK,
 389
 390         /* IPSR2 */
 391         SD1_CLK_A_MARK, MMC_CLK_MARK,   ATACS00_MARK,   EX_CS2_MARK,
 392         SD1_CMD_A_MARK, MMC_CMD_MARK,   ATACS10_MARK,   EX_CS3_MARK,
 393         SD1_DAT0_A_MARK,                MMC_D0_MARK,    ATARD0_MARK,
 394         EX_CS4_MARK,    EX_WAIT1_A_MARK,                SD1_DAT1_A_MARK,
 395         MMC_D1_MARK,    ATAWR0_A_MARK,  EX_CS5_MARK,    EX_WAIT2_A_MARK,
 396         DREQ0_A_MARK,   RX3_A_MARK,     DACK0_MARK,     TX3_A_MARK,
 397         DRACK0_MARK,    EX_WAIT0_MARK,  PWM0_C_MARK,    D0_MARK,
 398         D1_MARK,        D2_MARK,        D3_MARK,        D4_MARK,
 399         D5_MARK,        D6_MARK,        D7_MARK,        D8_MARK,
 400         D9_MARK,        D10_MARK,       D11_MARK,       RD_WR_B_MARK,
 401         IRQ0_MARK,      MLB_CLK_MARK,   IRQ1_A_MARK,
 402
 403         /* IPSR3 */
 404         MLB_SIG_MARK,   RX5_B_MARK,     SDA3_A_MARK,    IRQ2_A_MARK,
 405         MLB_DAT_MARK,   TX5_B_MARK,     SCL3_A_MARK,    IRQ3_A_MARK,
 406         SDSELF_B_MARK,  SD1_CMD_B_MARK, SCIF_CLK_MARK,  AUDIO_CLKOUT_B_MARK,
 407         CAN_CLK_B_MARK, SDA3_B_MARK,    SD1_CLK_B_MARK, HTX0_A_MARK,
 408         TX0_A_MARK,     SD1_DAT0_B_MARK,                HRX0_A_MARK,
 409         RX0_A_MARK,     SD1_DAT1_B_MARK,                HSCK0_MARK,
 410         SCK0_MARK,      SCL3_B_MARK,    SD1_DAT2_B_MARK,
 411         HCTS0_A_MARK,   CTS0_MARK,      SD1_DAT3_B_MARK,
 412         HRTS0_A_MARK,   RTS0_MARK,      SSI_SCK4_MARK,
 413         DU0_DR0_MARK,   LCDOUT0_MARK,   AUDATA2_MARK,   ARM_TRACEDATA_2_MARK,
 414         SDA3_C_MARK,    ADICHS1_MARK,   TS_SDEN0_B_MARK,
 415         SSI_WS4_MARK,   DU0_DR1_MARK,   LCDOUT1_MARK,   AUDATA3_MARK,
 416         ARM_TRACEDATA_3_MARK,           SCL3_C_MARK,    ADICHS2_MARK,
 417         TS_SPSYNC0_B_MARK,              DU0_DR2_MARK,   LCDOUT2_MARK,
 418         DU0_DR3_MARK,   LCDOUT3_MARK,   DU0_DR4_MARK,   LCDOUT4_MARK,
 419         DU0_DR5_MARK,   LCDOUT5_MARK,   DU0_DR6_MARK,   LCDOUT6_MARK,
 420
 421         /* IPSR4 */
 422         DU0_DR7_MARK,   LCDOUT7_MARK,   DU0_DG0_MARK,   LCDOUT8_MARK,
 423         AUDATA4_MARK,   ARM_TRACEDATA_4_MARK,
 424         TX1_D_MARK,     CAN0_TX_A_MARK, ADICHS0_MARK,   DU0_DG1_MARK,
 425         LCDOUT9_MARK,   AUDATA5_MARK,   ARM_TRACEDATA_5_MARK,
 426         RX1_D_MARK,     CAN0_RX_A_MARK, ADIDATA_MARK,   DU0_DG2_MARK,
 427         LCDOUT10_MARK,  DU0_DG3_MARK,   LCDOUT11_MARK,  DU0_DG4_MARK,
 428         LCDOUT12_MARK,  RX0_B_MARK,     DU0_DG5_MARK,   LCDOUT13_MARK,
 429         TX0_B_MARK,     DU0_DG6_MARK,   LCDOUT14_MARK,  RX4_A_MARK,
 430         DU0_DG7_MARK,   LCDOUT15_MARK,  TX4_A_MARK,     SSI_SCK2_B_MARK,
 431         VI0_R0_B_MARK,  DU0_DB0_MARK,   LCDOUT16_MARK,  AUDATA6_MARK,
 432         ARM_TRACEDATA_6_MARK,           GPSCLK_A_MARK,  PWM0_A_MARK,
 433         ADICLK_MARK,    TS_SDAT0_B_MARK,                AUDIO_CLKC_MARK,
 434         VI0_R1_B_MARK,  DU0_DB1_MARK,   LCDOUT17_MARK,  AUDATA7_MARK,
 435         ARM_TRACEDATA_7_MARK,           GPSIN_A_MARK,   ADICS_SAMP_MARK,
 436         TS_SCK0_B_MARK, VI0_R2_B_MARK,  DU0_DB2_MARK,   LCDOUT18_MARK,
 437         VI0_R3_B_MARK,  DU0_DB3_MARK,   LCDOUT19_MARK,  VI0_R4_B_MARK,
 438         DU0_DB4_MARK,   LCDOUT20_MARK,
 439
 440         /* IPSR5 */
 441         VI0_R5_B_MARK,  DU0_DB5_MARK,   LCDOUT21_MARK,  VI1_DATA10_B_MARK,
 442         DU0_DB6_MARK,   LCDOUT22_MARK,  VI1_DATA11_B_MARK,
 443         DU0_DB7_MARK,   LCDOUT23_MARK,  DU0_DOTCLKIN_MARK,
 444         QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK,
 445         QCLK_MARK,      DU0_DOTCLKO_UT1_MARK,           QSTVB_QVE_MARK,
 446         AUDIO_CLKOUT_A_MARK,            REMOCON_C_MARK, SSI_WS2_B_MARK,
 447         DU0_EXHSYNC_DU0_HSYNC_MARK,     QSTH_QHS_MARK,
 448         DU0_EXVSYNC_DU0_VSYNC_MARK,     QSTB_QHE_MARK,
 449         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
 450         QCPV_QDE_MARK,  FMCLK_D_MARK,   SSI_SCK1_A_MARK,
 451         DU0_DISP_MARK,  QPOLA_MARK,     AUDCK_MARK,     ARM_TRACECLK_MARK,
 452         BPFCLK_D_MARK,  SSI_WS1_A_MARK, DU0_CDE_MARK,   QPOLB_MARK,
 453         AUDSYNC_MARK,   ARM_TRACECTL_MARK,              FMIN_D_MARK,
 454         SD1_CD_B_MARK,  SSI_SCK78_MARK, HSPI_RX0_B_MARK,
 455         TX1_B_MARK,     SD1_WP_B_MARK,  SSI_WS78_MARK,  HSPI_CLK0_B_MARK,
 456         RX1_B_MARK,     CAN_CLK_D_MARK, SSI_SDATA8_MARK,
 457         SSI_SCK2_A_MARK,                HSPI_CS0_B_MARK,
 458         TX2_A_MARK,     CAN0_TX_B_MARK, SSI_SDATA7_MARK,
 459         HSPI_TX0_B_MARK,                RX2_A_MARK,     CAN0_RX_B_MARK,
 460
 461         /* IPSR6 */
 462         SSI_SCK6_MARK,  HSPI_RX2_A_MARK,                FMCLK_B_MARK,
 463         CAN1_TX_B_MARK, SSI_WS6_MARK,   HSPI_CLK2_A_MARK,
 464         BPFCLK_B_MARK,  CAN1_RX_B_MARK, SSI_SDATA6_MARK,
 465         HSPI_TX2_A_MARK,                FMIN_B_MARK,    SSI_SCK5_MARK,
 466         RX4_C_MARK,     SSI_WS5_MARK,   TX4_C_MARK,     SSI_SDATA5_MARK,
 467         RX0_D_MARK,     SSI_WS34_MARK,  ARM_TRACEDATA_8_MARK,
 468         SSI_SDATA4_MARK,                SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK,
 469         SSI_SDATA3_MARK,                ARM_TRACEDATA_10_MARK,
 470         SSI_SCK012_MARK,                ARM_TRACEDATA_11_MARK,
 471         TX0_D_MARK,     SSI_WS012_MARK, ARM_TRACEDATA_12_MARK,
 472         SSI_SDATA2_MARK,                HSPI_CS2_A_MARK,
 473         ARM_TRACEDATA_13_MARK,          SDA1_A_MARK,    SSI_SDATA1_MARK,
 474         ARM_TRACEDATA_14_MARK,          SCL1_A_MARK,    SCK2_A_MARK,
 475         SSI_SDATA0_MARK,                ARM_TRACEDATA_15_MARK,
 476         SD0_CLK_MARK,   SUB_TDO_MARK,   SD0_CMD_MARK,   SUB_TRST_MARK,
 477         SD0_DAT0_MARK,  SUB_TMS_MARK,   SD0_DAT1_MARK,  SUB_TCK_MARK,
 478         SD0_DAT2_MARK,  SUB_TDI_MARK,
 479
 480         /* IPSR7 */
 481         SD0_DAT3_MARK,  IRQ1_B_MARK,    SD0_CD_MARK,    TX5_A_MARK,
 482         SD0_WP_MARK,    RX5_A_MARK,     VI1_CLKENB_MARK,
 483         HSPI_CLK0_A_MARK,       HTX1_A_MARK,    RTS1_C_MARK,    VI1_FIELD_MARK,
 484         HSPI_CS0_A_MARK,        HRX1_A_MARK,    SCK1_C_MARK,    VI1_HSYNC_MARK,
 485         HSPI_RX0_A_MARK,        HRTS1_A_MARK,   FMCLK_A_MARK,   RX1_C_MARK,
 486         VI1_VSYNC_MARK, HSPI_TX0_MARK,  HCTS1_A_MARK,   BPFCLK_A_MARK,
 487         TX1_C_MARK,     TCLK0_MARK,     HSCK1_A_MARK,   FMIN_A_MARK,
 488         IRQ2_C_MARK,    CTS1_C_MARK,    SPEEDIN_MARK,   VI0_CLK_MARK,
 489         CAN_CLK_A_MARK, VI0_CLKENB_MARK,                SD2_DAT2_B_MARK,
 490         VI1_DATA0_MARK, DU1_DG6_MARK,   HSPI_RX1_A_MARK,
 491         RX4_B_MARK,     VI0_FIELD_MARK, SD2_DAT3_B_MARK,
 492         VI0_R3_C_MARK,  VI1_DATA1_MARK, DU1_DG7_MARK,   HSPI_CLK1_A_MARK,
 493         TX4_B_MARK,     VI0_HSYNC_MARK, SD2_CD_B_MARK,  VI1_DATA2_MARK,
 494         DU1_DR2_MARK,   HSPI_CS1_A_MARK,                RX3_B_MARK,
 495
 496         /* IPSR8 */
 497         VI0_VSYNC_MARK, SD2_WP_B_MARK,  VI1_DATA3_MARK, DU1_DR3_MARK,
 498         HSPI_TX1_A_MARK,                TX3_B_MARK,     VI0_DATA0_VI0_B0_MARK,
 499         DU1_DG2_MARK,   IRQ2_B_MARK,    RX3_D_MARK,     VI0_DATA1_VI0_B1_MARK,
 500         DU1_DG3_MARK,   IRQ3_B_MARK,    TX3_D_MARK,     VI0_DATA2_VI0_B2_MARK,
 501         DU1_DG4_MARK,   RX0_C_MARK,     VI0_DATA3_VI0_B3_MARK,
 502         DU1_DG5_MARK,   TX1_A_MARK,     TX0_C_MARK,     VI0_DATA4_VI0_B4_MARK,
 503         DU1_DB2_MARK,   RX1_A_MARK,     VI0_DATA5_VI0_B5_MARK,
 504         DU1_DB3_MARK,   SCK1_A_MARK,    PWM4_MARK,      HSCK1_B_MARK,
 505         VI0_DATA6_VI0_G0_MARK,          DU1_DB4_MARK,   CTS1_A_MARK,
 506         PWM5_MARK,      VI0_DATA7_VI0_G1_MARK,          DU1_DB5_MARK,
 507         RTS1_A_MARK,    VI0_G2_MARK,    SD2_CLK_B_MARK, VI1_DATA4_MARK,
 508         DU1_DR4_MARK,   HTX1_B_MARK,    VI0_G3_MARK,    SD2_CMD_B_MARK,
 509         VI1_DATA5_MARK, DU1_DR5_MARK,   HRX1_B_MARK,
 510
 511         /* IPSR9 */
 512         VI0_G4_MARK,    SD2_DAT0_B_MARK,                VI1_DATA6_MARK,
 513         DU1_DR6_MARK,   HRTS1_B_MARK,   VI0_G5_MARK,    SD2_DAT1_B_MARK,
 514         VI1_DATA7_MARK, DU1_DR7_MARK,   HCTS1_B_MARK,   VI0_R0_A_MARK,
 515         VI1_CLK_MARK,   ETH_REF_CLK_MARK,               DU1_DOTCLKIN_MARK,
 516         VI0_R1_A_MARK,  VI1_DATA8_MARK, DU1_DB6_MARK,   ETH_TXD0_MARK,
 517         PWM2_MARK,      TCLK1_MARK,     VI0_R2_A_MARK,  VI1_DATA9_MARK,
 518         DU1_DB7_MARK,   ETH_TXD1_MARK,  PWM3_MARK,      VI0_R3_A_MARK,
 519         ETH_CRS_DV_MARK,                IECLK_MARK,     SCK2_C_MARK,
 520         VI0_R4_A_MARK,                  ETH_TX_EN_MARK, IETX_MARK,
 521         TX2_C_MARK,     VI0_R5_A_MARK,  ETH_RX_ER_MARK, FMCLK_C_MARK,
 522         IERX_MARK,      RX2_C_MARK,     VI1_DATA10_A_MARK,
 523         DU1_DOTCLKOUT_MARK,             ETH_RXD0_MARK,
 524         BPFCLK_C_MARK,  TX2_D_MARK,     SDA2_C_MARK,    VI1_DATA11_A_MARK,
 525         DU1_EXHSYNC_DU1_HSYNC_MARK,     ETH_RXD1_MARK,  FMIN_C_MARK,
 526         RX2_D_MARK,     SCL2_C_MARK,
 527
 528         /* IPSR10 */
 529         SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,     ATARD1_MARK,
 530         ETH_MDC_MARK,   SDA1_B_MARK,    SD2_CMD_A_MARK,
 531         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,              ATAWR1_MARK,
 532         ETH_MDIO_MARK,  SCL1_B_MARK,    SD2_DAT0_A_MARK,
 533         DU1_DISP_MARK,  ATACS01_MARK,   DREQ1_B_MARK,   ETH_LINK_MARK,
 534         CAN1_RX_A_MARK, SD2_DAT1_A_MARK,                DU1_CDE_MARK,
 535         ATACS11_MARK,   DACK1_B_MARK,   ETH_MAGIC_MARK, CAN1_TX_A_MARK,
 536         PWM6_MARK,      SD2_DAT2_A_MARK,                VI1_DATA12_MARK,
 537         DREQ2_B_MARK,   ATADIR1_MARK,   HSPI_CLK2_B_MARK,
 538         GPSCLK_B_MARK,  SD2_DAT3_A_MARK,                VI1_DATA13_MARK,
 539         DACK2_B_MARK,   ATAG1_MARK,     HSPI_CS2_B_MARK,
 540         GPSIN_B_MARK,   SD2_CD_A_MARK,  VI1_DATA14_MARK,
 541         EX_WAIT1_B_MARK,                DREQ0_B_MARK,   HSPI_RX2_B_MARK,
 542         REMOCON_A_MARK, SD2_WP_A_MARK,  VI1_DATA15_MARK,
 543         EX_WAIT2_B_MARK,                DACK0_B_MARK,
 544         HSPI_TX2_B_MARK,                CAN_CLK_C_MARK,
 545
 546         PINMUX_MARK_END,
 547 };
 548
 549 static const u16 pinmux_data[] = {
 550         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 551
 552         PINMUX_SINGLE(PENC0),
 553         PINMUX_SINGLE(PENC1),
 554         PINMUX_SINGLE(A1),
 555         PINMUX_SINGLE(A2),
 556         PINMUX_SINGLE(A3),
 557         PINMUX_SINGLE(WE0),
 558         PINMUX_SINGLE(AUDIO_CLKA),
 559         PINMUX_SINGLE(AUDIO_CLKB),
 560         PINMUX_SINGLE(SSI_SCK34),
 561         PINMUX_SINGLE(AVS1),
 562         PINMUX_SINGLE(AVS2),
 563
 564         /* IPSR0 */
 565         PINMUX_IPSR_GPSR(IP0_1_0,       PRESETOUT),
 566         PINMUX_IPSR_GPSR(IP0_1_0,       PWM1),
 567
 568         PINMUX_IPSR_GPSR(IP0_4_2,       AUDATA0),
 569         PINMUX_IPSR_GPSR(IP0_4_2,       ARM_TRACEDATA_0),
 570         PINMUX_IPSR_MSEL(IP0_4_2,       GPSCLK_C,       SEL_GPS_C),
 571         PINMUX_IPSR_GPSR(IP0_4_2,       USB_OVC0),
 572         PINMUX_IPSR_GPSR(IP0_4_2,       TX2_E),
 573         PINMUX_IPSR_MSEL(IP0_4_2,       SDA2_B,         SEL_I2C2_B),
 574
 575         PINMUX_IPSR_GPSR(IP0_7_5,       AUDATA1),
 576         PINMUX_IPSR_GPSR(IP0_7_5,       ARM_TRACEDATA_1),
 577         PINMUX_IPSR_MSEL(IP0_7_5,       GPSIN_C,        SEL_GPS_C),
 578         PINMUX_IPSR_GPSR(IP0_7_5,       USB_OVC1),
 579         PINMUX_IPSR_MSEL(IP0_7_5,       RX2_E,          SEL_SCIF2_E),
 580         PINMUX_IPSR_MSEL(IP0_7_5,       SCL2_B,         SEL_I2C2_B),
 581
 582         PINMUX_IPSR_MSEL(IP0_11_8,      SD1_DAT2_A,     SEL_SD1_A),
 583         PINMUX_IPSR_GPSR(IP0_11_8,      MMC_D2),
 584         PINMUX_IPSR_GPSR(IP0_11_8,      BS),
 585         PINMUX_IPSR_GPSR(IP0_11_8,      ATADIR0_A),
 586         PINMUX_IPSR_GPSR(IP0_11_8,      SDSELF_A),
 587         PINMUX_IPSR_GPSR(IP0_11_8,      PWM4_B),
 588
 589         PINMUX_IPSR_MSEL(IP0_14_12,     SD1_DAT3_A,     SEL_SD1_A),
 590         PINMUX_IPSR_GPSR(IP0_14_12,     MMC_D3),
 591         PINMUX_IPSR_GPSR(IP0_14_12,     A0),
 592         PINMUX_IPSR_GPSR(IP0_14_12,     ATAG0_A),
 593         PINMUX_IPSR_MSEL(IP0_14_12,     REMOCON_B,      SEL_REMOCON_B),
 594
 595         PINMUX_IPSR_GPSR(IP0_15,        A4),
 596         PINMUX_IPSR_GPSR(IP0_16,        A5),
 597         PINMUX_IPSR_GPSR(IP0_17,        A6),
 598         PINMUX_IPSR_GPSR(IP0_18,        A7),
 599         PINMUX_IPSR_GPSR(IP0_19,        A8),
 600         PINMUX_IPSR_GPSR(IP0_20,        A9),
 601         PINMUX_IPSR_GPSR(IP0_21,        A10),
 602         PINMUX_IPSR_GPSR(IP0_22,        A11),
 603         PINMUX_IPSR_GPSR(IP0_23,        A12),
 604         PINMUX_IPSR_GPSR(IP0_24,        A13),
 605         PINMUX_IPSR_GPSR(IP0_25,        A14),
 606         PINMUX_IPSR_GPSR(IP0_26,        A15),
 607         PINMUX_IPSR_GPSR(IP0_27,        A16),
 608         PINMUX_IPSR_GPSR(IP0_28,        A17),
 609         PINMUX_IPSR_GPSR(IP0_29,        A18),
 610         PINMUX_IPSR_GPSR(IP0_30,        A19),
 611
 612         /* IPSR1 */
 613         PINMUX_IPSR_GPSR(IP1_0,         A20),
 614         PINMUX_IPSR_MSEL(IP1_0,         HSPI_CS1_B,     SEL_HSPI1_B),
 615
 616         PINMUX_IPSR_GPSR(IP1_1,         A21),
 617         PINMUX_IPSR_MSEL(IP1_1,         HSPI_CLK1_B,    SEL_HSPI1_B),
 618
 619         PINMUX_IPSR_GPSR(IP1_4_2,       A22),
 620         PINMUX_IPSR_MSEL(IP1_4_2,       HRTS0_B,        SEL_HSCIF0_B),
 621         PINMUX_IPSR_MSEL(IP1_4_2,       RX2_B,          SEL_SCIF2_B),
 622         PINMUX_IPSR_MSEL(IP1_4_2,       DREQ2_A,        SEL_DREQ2_A),
 623
 624         PINMUX_IPSR_GPSR(IP1_7_5,       A23),
 625         PINMUX_IPSR_GPSR(IP1_7_5,       HTX0_B),
 626         PINMUX_IPSR_GPSR(IP1_7_5,       TX2_B),
 627         PINMUX_IPSR_GPSR(IP1_7_5,       DACK2_A),
 628         PINMUX_IPSR_MSEL(IP1_7_5,       TS_SDEN0_A,     SEL_TSIF0_A),
 629
 630         PINMUX_IPSR_MSEL(IP1_10_8,      SD1_CD_A,       SEL_SD1_A),
 631         PINMUX_IPSR_GPSR(IP1_10_8,      MMC_D6),
 632         PINMUX_IPSR_GPSR(IP1_10_8,      A24),
 633         PINMUX_IPSR_MSEL(IP1_10_8,      DREQ1_A,        SEL_DREQ1_A),
 634         PINMUX_IPSR_MSEL(IP1_10_8,      HRX0_B,         SEL_HSCIF0_B),
 635         PINMUX_IPSR_MSEL(IP1_10_8,      TS_SPSYNC0_A,   SEL_TSIF0_A),
 636
 637         PINMUX_IPSR_MSEL(IP1_14_11,     SD1_WP_A,       SEL_SD1_A),
 638         PINMUX_IPSR_GPSR(IP1_14_11,     MMC_D7),
 639         PINMUX_IPSR_GPSR(IP1_14_11,     A25),
 640         PINMUX_IPSR_GPSR(IP1_14_11,     DACK1_A),
 641         PINMUX_IPSR_MSEL(IP1_14_11,     HCTS0_B,        SEL_HSCIF0_B),
 642         PINMUX_IPSR_MSEL(IP1_14_11,     RX3_C,          SEL_SCIF3_C),
 643         PINMUX_IPSR_MSEL(IP1_14_11,     TS_SDAT0_A,     SEL_TSIF0_A),
 644
 645         PINMUX_IPSR_NOGP(IP1_16_15,     CLKOUT),
 646         PINMUX_IPSR_NOGP(IP1_16_15,     HSPI_TX1_B),
 647         PINMUX_IPSR_NOGP(IP1_16_15,     PWM0_B),
 648
 649         PINMUX_IPSR_NOGP(IP1_17,        CS0),
 650         PINMUX_IPSR_NOGM(IP1_17,        HSPI_RX1_B,     SEL_HSPI1_B),
 651
 652         PINMUX_IPSR_NOGM(IP1_20_18,     SSI_SCK1_B,     SEL_SSI1_B),
 653         PINMUX_IPSR_NOGP(IP1_20_18,     ATAG0_B),
 654         PINMUX_IPSR_NOGP(IP1_20_18,     CS1_A26),
 655         PINMUX_IPSR_NOGM(IP1_20_18,     SDA2_A,         SEL_I2C2_A),
 656         PINMUX_IPSR_NOGM(IP1_20_18,     SCK2_B,         SEL_SCIF2_B),
 657
 658         PINMUX_IPSR_GPSR(IP1_23_21,     MMC_D5),
 659         PINMUX_IPSR_GPSR(IP1_23_21,     ATADIR0_B),
 660         PINMUX_IPSR_GPSR(IP1_23_21,     RD_WR),
 661
 662         PINMUX_IPSR_GPSR(IP1_24,        WE1),
 663         PINMUX_IPSR_GPSR(IP1_24,        ATAWR0_B),
 664
 665         PINMUX_IPSR_MSEL(IP1_27_25,     SSI_WS1_B,      SEL_SSI1_B),
 666         PINMUX_IPSR_GPSR(IP1_27_25,     EX_CS0),
 667         PINMUX_IPSR_MSEL(IP1_27_25,     SCL2_A,         SEL_I2C2_A),
 668         PINMUX_IPSR_GPSR(IP1_27_25,     TX3_C),
 669         PINMUX_IPSR_MSEL(IP1_27_25,     TS_SCK0_A,      SEL_TSIF0_A),
 670
 671         PINMUX_IPSR_GPSR(IP1_29_28,     EX_CS1),
 672         PINMUX_IPSR_GPSR(IP1_29_28,     MMC_D4),
 673
 674         /* IPSR2 */
 675         PINMUX_IPSR_GPSR(IP2_2_0,       SD1_CLK_A),
 676         PINMUX_IPSR_GPSR(IP2_2_0,       MMC_CLK),
 677         PINMUX_IPSR_GPSR(IP2_2_0,       ATACS00),
 678         PINMUX_IPSR_GPSR(IP2_2_0,       EX_CS2),
 679
 680         PINMUX_IPSR_MSEL(IP2_5_3,       SD1_CMD_A,      SEL_SD1_A),
 681         PINMUX_IPSR_GPSR(IP2_5_3,       MMC_CMD),
 682         PINMUX_IPSR_GPSR(IP2_5_3,       ATACS10),
 683         PINMUX_IPSR_GPSR(IP2_5_3,       EX_CS3),
 684
 685         PINMUX_IPSR_MSEL(IP2_8_6,       SD1_DAT0_A,     SEL_SD1_A),
 686         PINMUX_IPSR_GPSR(IP2_8_6,       MMC_D0),
 687         PINMUX_IPSR_GPSR(IP2_8_6,       ATARD0),
 688         PINMUX_IPSR_GPSR(IP2_8_6,       EX_CS4),
 689         PINMUX_IPSR_MSEL(IP2_8_6,       EX_WAIT1_A,     SEL_WAIT1_A),
 690
 691         PINMUX_IPSR_MSEL(IP2_11_9,      SD1_DAT1_A,     SEL_SD1_A),
 692         PINMUX_IPSR_GPSR(IP2_11_9,      MMC_D1),
 693         PINMUX_IPSR_GPSR(IP2_11_9,      ATAWR0_A),
 694         PINMUX_IPSR_GPSR(IP2_11_9,      EX_CS5),
 695         PINMUX_IPSR_MSEL(IP2_11_9,      EX_WAIT2_A,     SEL_WAIT2_A),
 696
 697         PINMUX_IPSR_MSEL(IP2_13_12,     DREQ0_A,        SEL_DREQ0_A),
 698         PINMUX_IPSR_MSEL(IP2_13_12,     RX3_A,          SEL_SCIF3_A),
 699
 700         PINMUX_IPSR_GPSR(IP2_16_14,     DACK0),
 701         PINMUX_IPSR_GPSR(IP2_16_14,     TX3_A),
 702         PINMUX_IPSR_GPSR(IP2_16_14,     DRACK0),
 703
 704         PINMUX_IPSR_GPSR(IP2_17,        EX_WAIT0),
 705         PINMUX_IPSR_GPSR(IP2_17,        PWM0_C),
 706
 707         PINMUX_IPSR_NOGP(IP2_18,        D0),
 708         PINMUX_IPSR_NOGP(IP2_19,        D1),
 709         PINMUX_IPSR_NOGP(IP2_20,        D2),
 710         PINMUX_IPSR_NOGP(IP2_21,        D3),
 711         PINMUX_IPSR_NOGP(IP2_22,        D4),
 712         PINMUX_IPSR_NOGP(IP2_23,        D5),
 713         PINMUX_IPSR_NOGP(IP2_24,        D6),
 714         PINMUX_IPSR_NOGP(IP2_25,        D7),
 715         PINMUX_IPSR_NOGP(IP2_26,        D8),
 716         PINMUX_IPSR_NOGP(IP2_27,        D9),
 717         PINMUX_IPSR_NOGP(IP2_28,        D10),
 718         PINMUX_IPSR_NOGP(IP2_29,        D11),
 719
 720         PINMUX_IPSR_GPSR(IP2_30,        RD_WR_B),
 721         PINMUX_IPSR_GPSR(IP2_30,        IRQ0),
 722
 723         PINMUX_IPSR_GPSR(IP2_31,        MLB_CLK),
 724         PINMUX_IPSR_MSEL(IP2_31,        IRQ1_A,         SEL_IRQ1_A),
 725
 726         /* IPSR3 */
 727         PINMUX_IPSR_GPSR(IP3_1_0,       MLB_SIG),
 728         PINMUX_IPSR_MSEL(IP3_1_0,       RX5_B,          SEL_SCIF5_B),
 729         PINMUX_IPSR_MSEL(IP3_1_0,       SDA3_A,         SEL_I2C3_A),
 730         PINMUX_IPSR_MSEL(IP3_1_0,       IRQ2_A,         SEL_IRQ2_A),
 731
 732         PINMUX_IPSR_GPSR(IP3_4_2,       MLB_DAT),
 733         PINMUX_IPSR_GPSR(IP3_4_2,       TX5_B),
 734         PINMUX_IPSR_MSEL(IP3_4_2,       SCL3_A,         SEL_I2C3_A),
 735         PINMUX_IPSR_MSEL(IP3_4_2,       IRQ3_A,         SEL_IRQ3_A),
 736         PINMUX_IPSR_GPSR(IP3_4_2,       SDSELF_B),
 737
 738         PINMUX_IPSR_MSEL(IP3_7_5,       SD1_CMD_B,      SEL_SD1_B),
 739         PINMUX_IPSR_GPSR(IP3_7_5,       SCIF_CLK),
 740         PINMUX_IPSR_GPSR(IP3_7_5,       AUDIO_CLKOUT_B),
 741         PINMUX_IPSR_MSEL(IP3_7_5,       CAN_CLK_B,      SEL_CANCLK_B),
 742         PINMUX_IPSR_MSEL(IP3_7_5,       SDA3_B,         SEL_I2C3_B),
 743
 744         PINMUX_IPSR_GPSR(IP3_9_8,       SD1_CLK_B),
 745         PINMUX_IPSR_GPSR(IP3_9_8,       HTX0_A),
 746         PINMUX_IPSR_GPSR(IP3_9_8,       TX0_A),
 747
 748         PINMUX_IPSR_MSEL(IP3_12_10,     SD1_DAT0_B,     SEL_SD1_B),
 749         PINMUX_IPSR_MSEL(IP3_12_10,     HRX0_A,         SEL_HSCIF0_A),
 750         PINMUX_IPSR_MSEL(IP3_12_10,     RX0_A,          SEL_SCIF0_A),
 751
 752         PINMUX_IPSR_MSEL(IP3_15_13,     SD1_DAT1_B,     SEL_SD1_B),
 753         PINMUX_IPSR_MSEL(IP3_15_13,     HSCK0,          SEL_HSCIF0_A),
 754         PINMUX_IPSR_GPSR(IP3_15_13,     SCK0),
 755         PINMUX_IPSR_MSEL(IP3_15_13,     SCL3_B,         SEL_I2C3_B),
 756
 757         PINMUX_IPSR_MSEL(IP3_18_16,     SD1_DAT2_B,     SEL_SD1_B),
 758         PINMUX_IPSR_MSEL(IP3_18_16,     HCTS0_A,        SEL_HSCIF0_A),
 759         PINMUX_IPSR_GPSR(IP3_18_16,     CTS0),
 760
 761         PINMUX_IPSR_MSEL(IP3_20_19,     SD1_DAT3_B,     SEL_SD1_B),
 762         PINMUX_IPSR_MSEL(IP3_20_19,     HRTS0_A,        SEL_HSCIF0_A),
 763         PINMUX_IPSR_GPSR(IP3_20_19,     RTS0),
 764
 765         PINMUX_IPSR_GPSR(IP3_23_21,     SSI_SCK4),
 766         PINMUX_IPSR_GPSR(IP3_23_21,     DU0_DR0),
 767         PINMUX_IPSR_GPSR(IP3_23_21,     LCDOUT0),
 768         PINMUX_IPSR_GPSR(IP3_23_21,     AUDATA2),
 769         PINMUX_IPSR_GPSR(IP3_23_21,     ARM_TRACEDATA_2),
 770         PINMUX_IPSR_MSEL(IP3_23_21,     SDA3_C,         SEL_I2C3_C),
 771         PINMUX_IPSR_GPSR(IP3_23_21,     ADICHS1),
 772         PINMUX_IPSR_MSEL(IP3_23_21,     TS_SDEN0_B,     SEL_TSIF0_B),
 773
 774         PINMUX_IPSR_GPSR(IP3_26_24,     SSI_WS4),
 775         PINMUX_IPSR_GPSR(IP3_26_24,     DU0_DR1),
 776         PINMUX_IPSR_GPSR(IP3_26_24,     LCDOUT1),
 777         PINMUX_IPSR_GPSR(IP3_26_24,     AUDATA3),
 778         PINMUX_IPSR_GPSR(IP3_26_24,     ARM_TRACEDATA_3),
 779         PINMUX_IPSR_MSEL(IP3_26_24,     SCL3_C,         SEL_I2C3_C),
 780         PINMUX_IPSR_GPSR(IP3_26_24,     ADICHS2),
 781         PINMUX_IPSR_MSEL(IP3_26_24,     TS_SPSYNC0_B,   SEL_TSIF0_B),
 782
 783         PINMUX_IPSR_GPSR(IP3_27,        DU0_DR2),
 784         PINMUX_IPSR_GPSR(IP3_27,        LCDOUT2),
 785
 786         PINMUX_IPSR_GPSR(IP3_28,        DU0_DR3),
 787         PINMUX_IPSR_GPSR(IP3_28,        LCDOUT3),
 788
 789         PINMUX_IPSR_GPSR(IP3_29,        DU0_DR4),
 790         PINMUX_IPSR_GPSR(IP3_29,        LCDOUT4),
 791
 792         PINMUX_IPSR_GPSR(IP3_30,        DU0_DR5),
 793         PINMUX_IPSR_GPSR(IP3_30,        LCDOUT5),
 794
 795         PINMUX_IPSR_GPSR(IP3_31,        DU0_DR6),
 796         PINMUX_IPSR_GPSR(IP3_31,        LCDOUT6),
 797
 798         /* IPSR4 */
 799         PINMUX_IPSR_GPSR(IP4_0,         DU0_DR7),
 800         PINMUX_IPSR_GPSR(IP4_0,         LCDOUT7),
 801
 802         PINMUX_IPSR_GPSR(IP4_3_1,       DU0_DG0),
 803         PINMUX_IPSR_GPSR(IP4_3_1,       LCDOUT8),
 804         PINMUX_IPSR_GPSR(IP4_3_1,       AUDATA4),
 805         PINMUX_IPSR_GPSR(IP4_3_1,       ARM_TRACEDATA_4),
 806         PINMUX_IPSR_GPSR(IP4_3_1,       TX1_D),
 807         PINMUX_IPSR_GPSR(IP4_3_1,       CAN0_TX_A),
 808         PINMUX_IPSR_GPSR(IP4_3_1,       ADICHS0),
 809
 810         PINMUX_IPSR_GPSR(IP4_6_4,       DU0_DG1),
 811         PINMUX_IPSR_GPSR(IP4_6_4,       LCDOUT9),
 812         PINMUX_IPSR_GPSR(IP4_6_4,       AUDATA5),
 813         PINMUX_IPSR_GPSR(IP4_6_4,       ARM_TRACEDATA_5),
 814         PINMUX_IPSR_MSEL(IP4_6_4,       RX1_D,          SEL_SCIF1_D),
 815         PINMUX_IPSR_MSEL(IP4_6_4,       CAN0_RX_A,      SEL_CAN0_A),
 816         PINMUX_IPSR_GPSR(IP4_6_4,       ADIDATA),
 817
 818         PINMUX_IPSR_GPSR(IP4_7,         DU0_DG2),
 819         PINMUX_IPSR_GPSR(IP4_7,         LCDOUT10),
 820
 821         PINMUX_IPSR_GPSR(IP4_8,         DU0_DG3),
 822         PINMUX_IPSR_GPSR(IP4_8,         LCDOUT11),
 823
 824         PINMUX_IPSR_GPSR(IP4_10_9,      DU0_DG4),
 825         PINMUX_IPSR_GPSR(IP4_10_9,      LCDOUT12),
 826         PINMUX_IPSR_MSEL(IP4_10_9,      RX0_B,          SEL_SCIF0_B),
 827
 828         PINMUX_IPSR_GPSR(IP4_12_11,     DU0_DG5),
 829         PINMUX_IPSR_GPSR(IP4_12_11,     LCDOUT13),
 830         PINMUX_IPSR_GPSR(IP4_12_11,     TX0_B),
 831
 832         PINMUX_IPSR_GPSR(IP4_14_13,     DU0_DG6),
 833         PINMUX_IPSR_GPSR(IP4_14_13,     LCDOUT14),
 834         PINMUX_IPSR_MSEL(IP4_14_13,     RX4_A,          SEL_SCIF4_A),
 835
 836         PINMUX_IPSR_GPSR(IP4_16_15,     DU0_DG7),
 837         PINMUX_IPSR_GPSR(IP4_16_15,     LCDOUT15),
 838         PINMUX_IPSR_GPSR(IP4_16_15,     TX4_A),
 839
 840         PINMUX_IPSR_MSEL(IP4_20_17,     SSI_SCK2_B,     SEL_SSI2_B),
 841         PINMUX_DATA(VI0_R0_B_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 842         PINMUX_DATA(VI0_R0_D_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 843         PINMUX_IPSR_GPSR(IP4_20_17,     DU0_DB0),
 844         PINMUX_IPSR_GPSR(IP4_20_17,     LCDOUT16),
 845         PINMUX_IPSR_GPSR(IP4_20_17,     AUDATA6),
 846         PINMUX_IPSR_GPSR(IP4_20_17,     ARM_TRACEDATA_6),
 847         PINMUX_IPSR_MSEL(IP4_20_17,     GPSCLK_A,       SEL_GPS_A),
 848         PINMUX_IPSR_GPSR(IP4_20_17,     PWM0_A),
 849         PINMUX_IPSR_GPSR(IP4_20_17,     ADICLK),
 850         PINMUX_IPSR_MSEL(IP4_20_17,     TS_SDAT0_B,     SEL_TSIF0_B),
 851
 852         PINMUX_IPSR_GPSR(IP4_24_21,     AUDIO_CLKC),
 853         PINMUX_DATA(VI0_R1_B_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 854         PINMUX_DATA(VI0_R1_D_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 855         PINMUX_IPSR_GPSR(IP4_24_21,     DU0_DB1),
 856         PINMUX_IPSR_GPSR(IP4_24_21,     LCDOUT17),
 857         PINMUX_IPSR_GPSR(IP4_24_21,     AUDATA7),
 858         PINMUX_IPSR_GPSR(IP4_24_21,     ARM_TRACEDATA_7),
 859         PINMUX_IPSR_MSEL(IP4_24_21,     GPSIN_A,        SEL_GPS_A),
 860         PINMUX_IPSR_GPSR(IP4_24_21,     ADICS_SAMP),
 861         PINMUX_IPSR_MSEL(IP4_24_21,     TS_SCK0_B,      SEL_TSIF0_B),
 862
 863         PINMUX_DATA(VI0_R2_B_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 864         PINMUX_DATA(VI0_R2_D_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 865         PINMUX_IPSR_GPSR(IP4_26_25,     DU0_DB2),
 866         PINMUX_IPSR_GPSR(IP4_26_25,     LCDOUT18),
 867
 868         PINMUX_IPSR_MSEL(IP4_28_27,     VI0_R3_B,       SEL_VI0_B),
 869         PINMUX_IPSR_GPSR(IP4_28_27,     DU0_DB3),
 870         PINMUX_IPSR_GPSR(IP4_28_27,     LCDOUT19),
 871
 872         PINMUX_DATA(VI0_R4_B_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 873         PINMUX_DATA(VI0_R4_D_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 874         PINMUX_IPSR_GPSR(IP4_30_29,     DU0_DB4),
 875         PINMUX_IPSR_GPSR(IP4_30_29,     LCDOUT20),
 876
 877         /* IPSR5 */
 878         PINMUX_DATA(VI0_R5_B_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 879         PINMUX_DATA(VI0_R5_D_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 880         PINMUX_IPSR_GPSR(IP5_1_0,       DU0_DB5),
 881         PINMUX_IPSR_GPSR(IP5_1_0,       LCDOUT21),
 882
 883         PINMUX_IPSR_MSEL(IP5_3_2,       VI1_DATA10_B,   SEL_VI1_B),
 884         PINMUX_IPSR_GPSR(IP5_3_2,       DU0_DB6),
 885         PINMUX_IPSR_GPSR(IP5_3_2,       LCDOUT22),
 886
 887         PINMUX_IPSR_MSEL(IP5_5_4,       VI1_DATA11_B,   SEL_VI1_B),
 888         PINMUX_IPSR_GPSR(IP5_5_4,       DU0_DB7),
 889         PINMUX_IPSR_GPSR(IP5_5_4,       LCDOUT23),
 890
 891         PINMUX_IPSR_GPSR(IP5_6,         DU0_DOTCLKIN),
 892         PINMUX_IPSR_GPSR(IP5_6,         QSTVA_QVS),
 893
 894         PINMUX_IPSR_GPSR(IP5_7,         DU0_DOTCLKO_UT0),
 895         PINMUX_IPSR_GPSR(IP5_7,         QCLK),
 896
 897         PINMUX_IPSR_GPSR(IP5_9_8,       DU0_DOTCLKO_UT1),
 898         PINMUX_IPSR_GPSR(IP5_9_8,       QSTVB_QVE),
 899         PINMUX_IPSR_GPSR(IP5_9_8,       AUDIO_CLKOUT_A),
 900         PINMUX_IPSR_MSEL(IP5_9_8,       REMOCON_C,      SEL_REMOCON_C),
 901
 902         PINMUX_IPSR_MSEL(IP5_11_10,     SSI_WS2_B,      SEL_SSI2_B),
 903         PINMUX_IPSR_GPSR(IP5_11_10,     DU0_EXHSYNC_DU0_HSYNC),
 904         PINMUX_IPSR_GPSR(IP5_11_10,     QSTH_QHS),
 905
 906         PINMUX_IPSR_GPSR(IP5_12,        DU0_EXVSYNC_DU0_VSYNC),
 907         PINMUX_IPSR_GPSR(IP5_12,        QSTB_QHE),
 908
 909         PINMUX_IPSR_GPSR(IP5_14_13,     DU0_EXODDF_DU0_ODDF_DISP_CDE),
 910         PINMUX_IPSR_GPSR(IP5_14_13,     QCPV_QDE),
 911         PINMUX_IPSR_MSEL(IP5_14_13,     FMCLK_D,        SEL_FM_D),
 912
 913         PINMUX_IPSR_MSEL(IP5_17_15,     SSI_SCK1_A,     SEL_SSI1_A),
 914         PINMUX_IPSR_GPSR(IP5_17_15,     DU0_DISP),
 915         PINMUX_IPSR_GPSR(IP5_17_15,     QPOLA),
 916         PINMUX_IPSR_GPSR(IP5_17_15,     AUDCK),
 917         PINMUX_IPSR_GPSR(IP5_17_15,     ARM_TRACECLK),
 918         PINMUX_IPSR_GPSR(IP5_17_15,     BPFCLK_D),
 919
 920         PINMUX_IPSR_MSEL(IP5_20_18,     SSI_WS1_A,      SEL_SSI1_A),
 921         PINMUX_IPSR_GPSR(IP5_20_18,     DU0_CDE),
 922         PINMUX_IPSR_GPSR(IP5_20_18,     QPOLB),
 923         PINMUX_IPSR_GPSR(IP5_20_18,     AUDSYNC),
 924         PINMUX_IPSR_GPSR(IP5_20_18,     ARM_TRACECTL),
 925         PINMUX_IPSR_MSEL(IP5_20_18,     FMIN_D,         SEL_FM_D),
 926
 927         PINMUX_IPSR_MSEL(IP5_22_21,     SD1_CD_B,       SEL_SD1_B),
 928         PINMUX_IPSR_GPSR(IP5_22_21,     SSI_SCK78),
 929         PINMUX_IPSR_MSEL(IP5_22_21,     HSPI_RX0_B,     SEL_HSPI0_B),
 930         PINMUX_IPSR_GPSR(IP5_22_21,     TX1_B),
 931
 932         PINMUX_IPSR_MSEL(IP5_25_23,     SD1_WP_B,       SEL_SD1_B),
 933         PINMUX_IPSR_GPSR(IP5_25_23,     SSI_WS78),
 934         PINMUX_IPSR_MSEL(IP5_25_23,     HSPI_CLK0_B,    SEL_HSPI0_B),
 935         PINMUX_IPSR_MSEL(IP5_25_23,     RX1_B,          SEL_SCIF1_B),
 936         PINMUX_IPSR_MSEL(IP5_25_23,     CAN_CLK_D,      SEL_CANCLK_D),
 937
 938         PINMUX_IPSR_GPSR(IP5_28_26,     SSI_SDATA8),
 939         PINMUX_IPSR_MSEL(IP5_28_26,     SSI_SCK2_A,     SEL_SSI2_A),
 940         PINMUX_IPSR_MSEL(IP5_28_26,     HSPI_CS0_B,     SEL_HSPI0_B),
 941         PINMUX_IPSR_GPSR(IP5_28_26,     TX2_A),
 942         PINMUX_IPSR_GPSR(IP5_28_26,     CAN0_TX_B),
 943
 944         PINMUX_IPSR_GPSR(IP5_30_29,     SSI_SDATA7),
 945         PINMUX_IPSR_GPSR(IP5_30_29,     HSPI_TX0_B),
 946         PINMUX_IPSR_MSEL(IP5_30_29,     RX2_A,          SEL_SCIF2_A),
 947         PINMUX_IPSR_MSEL(IP5_30_29,     CAN0_RX_B,      SEL_CAN0_B),
 948
 949         /* IPSR6 */
 950         PINMUX_IPSR_GPSR(IP6_1_0,       SSI_SCK6),
 951         PINMUX_IPSR_MSEL(IP6_1_0,       HSPI_RX2_A,     SEL_HSPI2_A),
 952         PINMUX_IPSR_MSEL(IP6_1_0,       FMCLK_B,        SEL_FM_B),
 953         PINMUX_IPSR_GPSR(IP6_1_0,       CAN1_TX_B),
 954
 955         PINMUX_IPSR_GPSR(IP6_4_2,       SSI_WS6),
 956         PINMUX_IPSR_MSEL(IP6_4_2,       HSPI_CLK2_A,    SEL_HSPI2_A),
 957         PINMUX_IPSR_GPSR(IP6_4_2,       BPFCLK_B),
 958         PINMUX_IPSR_MSEL(IP6_4_2,       CAN1_RX_B,      SEL_CAN1_B),
 959
 960         PINMUX_IPSR_GPSR(IP6_6_5,       SSI_SDATA6),
 961         PINMUX_IPSR_GPSR(IP6_6_5,       HSPI_TX2_A),
 962         PINMUX_IPSR_MSEL(IP6_6_5,       FMIN_B,         SEL_FM_B),
 963
 964         PINMUX_IPSR_GPSR(IP6_7,         SSI_SCK5),
 965         PINMUX_IPSR_MSEL(IP6_7,         RX4_C,          SEL_SCIF4_C),
 966
 967         PINMUX_IPSR_GPSR(IP6_8,         SSI_WS5),
 968         PINMUX_IPSR_GPSR(IP6_8,         TX4_C),
 969
 970         PINMUX_IPSR_GPSR(IP6_9,         SSI_SDATA5),
 971         PINMUX_IPSR_MSEL(IP6_9,         RX0_D,          SEL_SCIF0_D),
 972
 973         PINMUX_IPSR_GPSR(IP6_10,        SSI_WS34),
 974         PINMUX_IPSR_GPSR(IP6_10,        ARM_TRACEDATA_8),
 975
 976         PINMUX_IPSR_GPSR(IP6_12_11,     SSI_SDATA4),
 977         PINMUX_IPSR_MSEL(IP6_12_11,     SSI_WS2_A,      SEL_SSI2_A),
 978         PINMUX_IPSR_GPSR(IP6_12_11,     ARM_TRACEDATA_9),
 979
 980         PINMUX_IPSR_GPSR(IP6_13,        SSI_SDATA3),
 981         PINMUX_IPSR_GPSR(IP6_13,        ARM_TRACEDATA_10),
 982
 983         PINMUX_IPSR_GPSR(IP6_15_14,     SSI_SCK012),
 984         PINMUX_IPSR_GPSR(IP6_15_14,     ARM_TRACEDATA_11),
 985         PINMUX_IPSR_GPSR(IP6_15_14,     TX0_D),
 986
 987         PINMUX_IPSR_GPSR(IP6_16,        SSI_WS012),
 988         PINMUX_IPSR_GPSR(IP6_16,        ARM_TRACEDATA_12),
 989
 990         PINMUX_IPSR_GPSR(IP6_18_17,     SSI_SDATA2),
 991         PINMUX_IPSR_MSEL(IP6_18_17,     HSPI_CS2_A,     SEL_HSPI2_A),
 992         PINMUX_IPSR_GPSR(IP6_18_17,     ARM_TRACEDATA_13),
 993         PINMUX_IPSR_MSEL(IP6_18_17,     SDA1_A,         SEL_I2C1_A),
 994
 995         PINMUX_IPSR_GPSR(IP6_20_19,     SSI_SDATA1),
 996         PINMUX_IPSR_GPSR(IP6_20_19,     ARM_TRACEDATA_14),
 997         PINMUX_IPSR_MSEL(IP6_20_19,     SCL1_A,         SEL_I2C1_A),
 998         PINMUX_IPSR_MSEL(IP6_20_19,     SCK2_A,         SEL_SCIF2_A),
 999
1000         PINMUX_IPSR_GPSR(IP6_21,        SSI_SDATA0),
1001         PINMUX_IPSR_GPSR(IP6_21,        ARM_TRACEDATA_15),
1002
1003         PINMUX_IPSR_GPSR(IP6_23_22,     SD0_CLK),
1004         PINMUX_IPSR_GPSR(IP6_23_22,     SUB_TDO),
1005
1006         PINMUX_IPSR_GPSR(IP6_25_24,     SD0_CMD),
1007         PINMUX_IPSR_GPSR(IP6_25_24,     SUB_TRST),
1008
1009         PINMUX_IPSR_GPSR(IP6_27_26,     SD0_DAT0),
1010         PINMUX_IPSR_GPSR(IP6_27_26,     SUB_TMS),
1011
1012         PINMUX_IPSR_GPSR(IP6_29_28,     SD0_DAT1),
1013         PINMUX_IPSR_GPSR(IP6_29_28,     SUB_TCK),
1014
1015         PINMUX_IPSR_GPSR(IP6_31_30,     SD0_DAT2),
1016         PINMUX_IPSR_GPSR(IP6_31_30,     SUB_TDI),
1017
1018         /* IPSR7 */
1019         PINMUX_IPSR_GPSR(IP7_1_0,       SD0_DAT3),
1020         PINMUX_IPSR_MSEL(IP7_1_0,       IRQ1_B,         SEL_IRQ1_B),
1021
1022         PINMUX_IPSR_GPSR(IP7_3_2,       SD0_CD),
1023         PINMUX_IPSR_GPSR(IP7_3_2,       TX5_A),
1024
1025         PINMUX_IPSR_GPSR(IP7_5_4,       SD0_WP),
1026         PINMUX_IPSR_MSEL(IP7_5_4,       RX5_A,          SEL_SCIF5_A),
1027
1028         PINMUX_IPSR_GPSR(IP7_8_6,       VI1_CLKENB),
1029         PINMUX_IPSR_MSEL(IP7_8_6,       HSPI_CLK0_A,    SEL_HSPI0_A),
1030         PINMUX_IPSR_GPSR(IP7_8_6,       HTX1_A),
1031         PINMUX_IPSR_MSEL(IP7_8_6,       RTS1_C,         SEL_SCIF1_C),
1032
1033         PINMUX_IPSR_GPSR(IP7_11_9,      VI1_FIELD),
1034         PINMUX_IPSR_MSEL(IP7_11_9,      HSPI_CS0_A,     SEL_HSPI0_A),
1035         PINMUX_IPSR_MSEL(IP7_11_9,      HRX1_A,         SEL_HSCIF1_A),
1036         PINMUX_IPSR_MSEL(IP7_11_9,      SCK1_C,         SEL_SCIF1_C),
1037
1038         PINMUX_IPSR_GPSR(IP7_14_12,     VI1_HSYNC),
1039         PINMUX_IPSR_MSEL(IP7_14_12,     HSPI_RX0_A,     SEL_HSPI0_A),
1040         PINMUX_IPSR_MSEL(IP7_14_12,     HRTS1_A,        SEL_HSCIF1_A),
1041         PINMUX_IPSR_MSEL(IP7_14_12,     FMCLK_A,        SEL_FM_A),
1042         PINMUX_IPSR_MSEL(IP7_14_12,     RX1_C,          SEL_SCIF1_C),
1043
1044         PINMUX_IPSR_GPSR(IP7_17_15,     VI1_VSYNC),
1045         PINMUX_IPSR_GPSR(IP7_17_15,     HSPI_TX0),
1046         PINMUX_IPSR_MSEL(IP7_17_15,     HCTS1_A,        SEL_HSCIF1_A),
1047         PINMUX_IPSR_GPSR(IP7_17_15,     BPFCLK_A),
1048         PINMUX_IPSR_GPSR(IP7_17_15,     TX1_C),
1049
1050         PINMUX_IPSR_GPSR(IP7_20_18,     TCLK0),
1051         PINMUX_IPSR_MSEL(IP7_20_18,     HSCK1_A,        SEL_HSCIF1_A),
1052         PINMUX_IPSR_MSEL(IP7_20_18,     FMIN_A,         SEL_FM_A),
1053         PINMUX_IPSR_MSEL(IP7_20_18,     IRQ2_C,         SEL_IRQ2_C),
1054         PINMUX_IPSR_MSEL(IP7_20_18,     CTS1_C,         SEL_SCIF1_C),
1055         PINMUX_IPSR_GPSR(IP7_20_18,     SPEEDIN),
1056
1057         PINMUX_IPSR_GPSR(IP7_21,        VI0_CLK),
1058         PINMUX_IPSR_MSEL(IP7_21,        CAN_CLK_A,      SEL_CANCLK_A),
1059
1060         PINMUX_IPSR_GPSR(IP7_24_22,     VI0_CLKENB),
1061         PINMUX_IPSR_MSEL(IP7_24_22,     SD2_DAT2_B,     SEL_SD2_B),
1062         PINMUX_IPSR_GPSR(IP7_24_22,     VI1_DATA0),
1063         PINMUX_IPSR_GPSR(IP7_24_22,     DU1_DG6),
1064         PINMUX_IPSR_MSEL(IP7_24_22,     HSPI_RX1_A,     SEL_HSPI1_A),
1065         PINMUX_IPSR_MSEL(IP7_24_22,     RX4_B,          SEL_SCIF4_B),
1066
1067         PINMUX_IPSR_GPSR(IP7_28_25,     VI0_FIELD),
1068         PINMUX_IPSR_MSEL(IP7_28_25,     SD2_DAT3_B,     SEL_SD2_B),
1069         PINMUX_DATA(VI0_R3_C_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_C), /* see sel_vi0 */
1070         PINMUX_DATA(VI0_R3_D_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_D), /* see sel_vi0 */
1071         PINMUX_IPSR_GPSR(IP7_28_25,     VI1_DATA1),
1072         PINMUX_IPSR_GPSR(IP7_28_25,     DU1_DG7),
1073         PINMUX_IPSR_MSEL(IP7_28_25,     HSPI_CLK1_A,    SEL_HSPI1_A),
1074         PINMUX_IPSR_GPSR(IP7_28_25,     TX4_B),
1075
1076         PINMUX_IPSR_GPSR(IP7_31_29,     VI0_HSYNC),
1077         PINMUX_IPSR_MSEL(IP7_31_29,     SD2_CD_B,       SEL_SD2_B),
1078         PINMUX_IPSR_GPSR(IP7_31_29,     VI1_DATA2),
1079         PINMUX_IPSR_GPSR(IP7_31_29,     DU1_DR2),
1080         PINMUX_IPSR_MSEL(IP7_31_29,     HSPI_CS1_A,     SEL_HSPI1_A),
1081         PINMUX_IPSR_MSEL(IP7_31_29,     RX3_B,          SEL_SCIF3_B),
1082
1083         /* IPSR8 */
1084         PINMUX_IPSR_GPSR(IP8_2_0,       VI0_VSYNC),
1085         PINMUX_IPSR_MSEL(IP8_2_0,       SD2_WP_B,       SEL_SD2_B),
1086         PINMUX_IPSR_GPSR(IP8_2_0,       VI1_DATA3),
1087         PINMUX_IPSR_GPSR(IP8_2_0,       DU1_DR3),
1088         PINMUX_IPSR_GPSR(IP8_2_0,       HSPI_TX1_A),
1089         PINMUX_IPSR_GPSR(IP8_2_0,       TX3_B),
1090
1091         PINMUX_IPSR_GPSR(IP8_5_3,       VI0_DATA0_VI0_B0),
1092         PINMUX_IPSR_GPSR(IP8_5_3,       DU1_DG2),
1093         PINMUX_IPSR_MSEL(IP8_5_3,       IRQ2_B,         SEL_IRQ2_B),
1094         PINMUX_IPSR_MSEL(IP8_5_3,       RX3_D,          SEL_SCIF3_D),
1095
1096         PINMUX_IPSR_GPSR(IP8_8_6,       VI0_DATA1_VI0_B1),
1097         PINMUX_IPSR_GPSR(IP8_8_6,       DU1_DG3),
1098         PINMUX_IPSR_MSEL(IP8_8_6,       IRQ3_B,         SEL_IRQ3_B),
1099         PINMUX_IPSR_GPSR(IP8_8_6,       TX3_D),
1100
1101         PINMUX_IPSR_GPSR(IP8_10_9,      VI0_DATA2_VI0_B2),
1102         PINMUX_IPSR_GPSR(IP8_10_9,      DU1_DG4),
1103         PINMUX_IPSR_MSEL(IP8_10_9,      RX0_C,          SEL_SCIF0_C),
1104
1105         PINMUX_IPSR_GPSR(IP8_13_11,     VI0_DATA3_VI0_B3),
1106         PINMUX_IPSR_GPSR(IP8_13_11,     DU1_DG5),
1107         PINMUX_IPSR_GPSR(IP8_13_11,     TX1_A),
1108         PINMUX_IPSR_GPSR(IP8_13_11,     TX0_C),
1109
1110         PINMUX_IPSR_GPSR(IP8_15_14,     VI0_DATA4_VI0_B4),
1111         PINMUX_IPSR_GPSR(IP8_15_14,     DU1_DB2),
1112         PINMUX_IPSR_MSEL(IP8_15_14,     RX1_A,          SEL_SCIF1_A),
1113
1114         PINMUX_IPSR_GPSR(IP8_18_16,     VI0_DATA5_VI0_B5),
1115         PINMUX_IPSR_GPSR(IP8_18_16,     DU1_DB3),
1116         PINMUX_IPSR_MSEL(IP8_18_16,     SCK1_A,         SEL_SCIF1_A),
1117         PINMUX_IPSR_GPSR(IP8_18_16,     PWM4),
1118         PINMUX_IPSR_MSEL(IP8_18_16,     HSCK1_B,        SEL_HSCIF1_B),
1119
1120         PINMUX_IPSR_GPSR(IP8_21_19,     VI0_DATA6_VI0_G0),
1121         PINMUX_IPSR_GPSR(IP8_21_19,     DU1_DB4),
1122         PINMUX_IPSR_MSEL(IP8_21_19,     CTS1_A,         SEL_SCIF1_A),
1123         PINMUX_IPSR_GPSR(IP8_21_19,     PWM5),
1124
1125         PINMUX_IPSR_GPSR(IP8_23_22,     VI0_DATA7_VI0_G1),
1126         PINMUX_IPSR_GPSR(IP8_23_22,     DU1_DB5),
1127         PINMUX_IPSR_MSEL(IP8_23_22,     RTS1_A,         SEL_SCIF1_A),
1128
1129         PINMUX_IPSR_GPSR(IP8_26_24,     VI0_G2),
1130         PINMUX_IPSR_GPSR(IP8_26_24,     SD2_CLK_B),
1131         PINMUX_IPSR_GPSR(IP8_26_24,     VI1_DATA4),
1132         PINMUX_IPSR_GPSR(IP8_26_24,     DU1_DR4),
1133         PINMUX_IPSR_GPSR(IP8_26_24,     HTX1_B),
1134
1135         PINMUX_IPSR_GPSR(IP8_29_27,     VI0_G3),
1136         PINMUX_IPSR_MSEL(IP8_29_27,     SD2_CMD_B,      SEL_SD2_B),
1137         PINMUX_IPSR_GPSR(IP8_29_27,     VI1_DATA5),
1138         PINMUX_IPSR_GPSR(IP8_29_27,     DU1_DR5),
1139         PINMUX_IPSR_MSEL(IP8_29_27,     HRX1_B,         SEL_HSCIF1_B),
1140
1141         /* IPSR9 */
1142         PINMUX_IPSR_GPSR(IP9_2_0,       VI0_G4),
1143         PINMUX_IPSR_MSEL(IP9_2_0,       SD2_DAT0_B,     SEL_SD2_B),
1144         PINMUX_IPSR_GPSR(IP9_2_0,       VI1_DATA6),
1145         PINMUX_IPSR_GPSR(IP9_2_0,       DU1_DR6),
1146         PINMUX_IPSR_MSEL(IP9_2_0,       HRTS1_B,        SEL_HSCIF1_B),
1147
1148         PINMUX_IPSR_GPSR(IP9_5_3,       VI0_G5),
1149         PINMUX_IPSR_MSEL(IP9_5_3,       SD2_DAT1_B,     SEL_SD2_B),
1150         PINMUX_IPSR_GPSR(IP9_5_3,       VI1_DATA7),
1151         PINMUX_IPSR_GPSR(IP9_5_3,       DU1_DR7),
1152         PINMUX_IPSR_MSEL(IP9_5_3,       HCTS1_B,        SEL_HSCIF1_B),
1153
1154         PINMUX_DATA(VI0_R0_A_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1155         PINMUX_DATA(VI0_R0_C_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1156         PINMUX_IPSR_GPSR(IP9_8_6,       VI1_CLK),
1157         PINMUX_IPSR_GPSR(IP9_8_6,       ETH_REF_CLK),
1158         PINMUX_IPSR_GPSR(IP9_8_6,       DU1_DOTCLKIN),
1159
1160         PINMUX_DATA(VI0_R1_A_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1161         PINMUX_DATA(VI0_R1_C_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1162         PINMUX_IPSR_GPSR(IP9_11_9,      VI1_DATA8),
1163         PINMUX_IPSR_GPSR(IP9_11_9,      DU1_DB6),
1164         PINMUX_IPSR_GPSR(IP9_11_9,      ETH_TXD0),
1165         PINMUX_IPSR_GPSR(IP9_11_9,      PWM2),
1166         PINMUX_IPSR_GPSR(IP9_11_9,      TCLK1),
1167
1168         PINMUX_DATA(VI0_R2_A_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1169         PINMUX_DATA(VI0_R2_C_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1170         PINMUX_IPSR_GPSR(IP9_14_12,     VI1_DATA9),
1171         PINMUX_IPSR_GPSR(IP9_14_12,     DU1_DB7),
1172         PINMUX_IPSR_GPSR(IP9_14_12,     ETH_TXD1),
1173         PINMUX_IPSR_GPSR(IP9_14_12,     PWM3),
1174
1175         PINMUX_IPSR_MSEL(IP9_17_15,     VI0_R3_A,       SEL_VI0_A),
1176         PINMUX_IPSR_GPSR(IP9_17_15,     ETH_CRS_DV),
1177         PINMUX_IPSR_GPSR(IP9_17_15,     IECLK),
1178         PINMUX_IPSR_MSEL(IP9_17_15,     SCK2_C,         SEL_SCIF2_C),
1179
1180         PINMUX_DATA(VI0_R4_A_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1181         PINMUX_DATA(VI0_R3_C_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1182         PINMUX_IPSR_GPSR(IP9_20_18,     ETH_TX_EN),
1183         PINMUX_IPSR_GPSR(IP9_20_18,     IETX),
1184         PINMUX_IPSR_GPSR(IP9_20_18,     TX2_C),
1185
1186         PINMUX_DATA(VI0_R5_A_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1187         PINMUX_DATA(VI0_R5_C_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1188         PINMUX_IPSR_GPSR(IP9_23_21,     ETH_RX_ER),
1189         PINMUX_IPSR_MSEL(IP9_23_21,     FMCLK_C,        SEL_FM_C),
1190         PINMUX_IPSR_GPSR(IP9_23_21,     IERX),
1191         PINMUX_IPSR_MSEL(IP9_23_21,     RX2_C,          SEL_SCIF2_C),
1192
1193         PINMUX_IPSR_MSEL(IP9_26_24,     VI1_DATA10_A,   SEL_VI1_A),
1194         PINMUX_IPSR_GPSR(IP9_26_24,     DU1_DOTCLKOUT),
1195         PINMUX_IPSR_GPSR(IP9_26_24,     ETH_RXD0),
1196         PINMUX_IPSR_GPSR(IP9_26_24,     BPFCLK_C),
1197         PINMUX_IPSR_GPSR(IP9_26_24,     TX2_D),
1198         PINMUX_IPSR_MSEL(IP9_26_24,     SDA2_C,         SEL_I2C2_C),
1199
1200         PINMUX_IPSR_MSEL(IP9_29_27,     VI1_DATA11_A,   SEL_VI1_A),
1201         PINMUX_IPSR_GPSR(IP9_29_27,     DU1_EXHSYNC_DU1_HSYNC),
1202         PINMUX_IPSR_GPSR(IP9_29_27,     ETH_RXD1),
1203         PINMUX_IPSR_MSEL(IP9_29_27,     FMIN_C,         SEL_FM_C),
1204         PINMUX_IPSR_MSEL(IP9_29_27,     RX2_D,          SEL_SCIF2_D),
1205         PINMUX_IPSR_MSEL(IP9_29_27,     SCL2_C,         SEL_I2C2_C),
1206
1207         /* IPSR10 */
1208         PINMUX_IPSR_GPSR(IP10_2_0,      SD2_CLK_A),
1209         PINMUX_IPSR_GPSR(IP10_2_0,      DU1_EXVSYNC_DU1_VSYNC),
1210         PINMUX_IPSR_GPSR(IP10_2_0,      ATARD1),
1211         PINMUX_IPSR_GPSR(IP10_2_0,      ETH_MDC),
1212         PINMUX_IPSR_MSEL(IP10_2_0,      SDA1_B,         SEL_I2C1_B),
1213
1214         PINMUX_IPSR_MSEL(IP10_5_3,      SD2_CMD_A,      SEL_SD2_A),
1215         PINMUX_IPSR_GPSR(IP10_5_3,      DU1_EXODDF_DU1_ODDF_DISP_CDE),
1216         PINMUX_IPSR_GPSR(IP10_5_3,      ATAWR1),
1217         PINMUX_IPSR_GPSR(IP10_5_3,      ETH_MDIO),
1218         PINMUX_IPSR_MSEL(IP10_5_3,      SCL1_B,         SEL_I2C1_B),
1219
1220         PINMUX_IPSR_MSEL(IP10_8_6,      SD2_DAT0_A,     SEL_SD2_A),
1221         PINMUX_IPSR_GPSR(IP10_8_6,      DU1_DISP),
1222         PINMUX_IPSR_GPSR(IP10_8_6,      ATACS01),
1223         PINMUX_IPSR_MSEL(IP10_8_6,      DREQ1_B,        SEL_DREQ1_B),
1224         PINMUX_IPSR_GPSR(IP10_8_6,      ETH_LINK),
1225         PINMUX_IPSR_MSEL(IP10_8_6,      CAN1_RX_A,      SEL_CAN1_A),
1226
1227         PINMUX_IPSR_MSEL(IP10_12_9,     SD2_DAT1_A,     SEL_SD2_A),
1228         PINMUX_IPSR_GPSR(IP10_12_9,     DU1_CDE),
1229         PINMUX_IPSR_GPSR(IP10_12_9,     ATACS11),
1230         PINMUX_IPSR_GPSR(IP10_12_9,     DACK1_B),
1231         PINMUX_IPSR_GPSR(IP10_12_9,     ETH_MAGIC),
1232         PINMUX_IPSR_GPSR(IP10_12_9,     CAN1_TX_A),
1233         PINMUX_IPSR_GPSR(IP10_12_9,     PWM6),
1234
1235         PINMUX_IPSR_MSEL(IP10_15_13,    SD2_DAT2_A,     SEL_SD2_A),
1236         PINMUX_IPSR_GPSR(IP10_15_13,    VI1_DATA12),
1237         PINMUX_IPSR_MSEL(IP10_15_13,    DREQ2_B,        SEL_DREQ2_B),
1238         PINMUX_IPSR_GPSR(IP10_15_13,    ATADIR1),
1239         PINMUX_IPSR_MSEL(IP10_15_13,    HSPI_CLK2_B,    SEL_HSPI2_B),
1240         PINMUX_IPSR_MSEL(IP10_15_13,    GPSCLK_B,       SEL_GPS_B),
1241
1242         PINMUX_IPSR_MSEL(IP10_18_16,    SD2_DAT3_A,     SEL_SD2_A),
1243         PINMUX_IPSR_GPSR(IP10_18_16,    VI1_DATA13),
1244         PINMUX_IPSR_GPSR(IP10_18_16,    DACK2_B),
1245         PINMUX_IPSR_GPSR(IP10_18_16,    ATAG1),
1246         PINMUX_IPSR_MSEL(IP10_18_16,    HSPI_CS2_B,     SEL_HSPI2_B),
1247         PINMUX_IPSR_MSEL(IP10_18_16,    GPSIN_B,        SEL_GPS_B),
1248
1249         PINMUX_IPSR_MSEL(IP10_21_19,    SD2_CD_A,       SEL_SD2_A),
1250         PINMUX_IPSR_GPSR(IP10_21_19,    VI1_DATA14),
1251         PINMUX_IPSR_MSEL(IP10_21_19,    EX_WAIT1_B,     SEL_WAIT1_B),
1252         PINMUX_IPSR_MSEL(IP10_21_19,    DREQ0_B,        SEL_DREQ0_B),
1253         PINMUX_IPSR_MSEL(IP10_21_19,    HSPI_RX2_B,     SEL_HSPI2_B),
1254         PINMUX_IPSR_MSEL(IP10_21_19,    REMOCON_A,      SEL_REMOCON_A),
1255
1256         PINMUX_IPSR_MSEL(IP10_24_22,    SD2_WP_A,       SEL_SD2_A),
1257         PINMUX_IPSR_GPSR(IP10_24_22,    VI1_DATA15),
1258         PINMUX_IPSR_MSEL(IP10_24_22,    EX_WAIT2_B,     SEL_WAIT2_B),
1259         PINMUX_IPSR_GPSR(IP10_24_22,    DACK0_B),
1260         PINMUX_IPSR_GPSR(IP10_24_22,    HSPI_TX2_B),
1261         PINMUX_IPSR_MSEL(IP10_24_22,    CAN_CLK_C,      SEL_CANCLK_C),
1262 };
1263
1264 /* Pin numbers for pins without a corresponding GPIO port number are computed
1265  * from the row and column numbers with a 1000 offset to avoid collisions with
1266  * GPIO port numbers.
1267  */
1268 #define PIN_NUMBER(row, col)            (1000+((row)-1)*25+(col)-1)
1269
1270 static const struct sh_pfc_pin pinmux_pins[] = {
1271         PINMUX_GPIO_GP_ALL(),
1272
1273         /* Pins not associated with a GPIO port */
1274         SH_PFC_PIN_NAMED(3, 20, C20),
1275         SH_PFC_PIN_NAMED(20, 1, T1),
1276         SH_PFC_PIN_NAMED(25, 2, Y2),
1277 };
1278
1279 /* - macro */
1280 #define SH_PFC_PINS(name, args...) \
1281         static const unsigned int name ##_pins[] = { args }
1282 #define SH_PFC_MUX1(name, arg1)                                 \
1283         static const unsigned int name ##_mux[]  = { arg1##_MARK }
1284 #define SH_PFC_MUX2(name, arg1, arg2)                                   \
1285         static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, }
1286 #define SH_PFC_MUX3(name, arg1, arg2, arg3)                                     \
1287         static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK,  \
1288                                                      arg3##_MARK }
1289 #define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4)                       \
1290         static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
1291                                                      arg3##_MARK, arg4##_MARK }
1292 #define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
1293         static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
1294                                                      arg3##_MARK, arg4##_MARK, \
1295                                                      arg5##_MARK, arg6##_MARK, \
1296                                                      arg7##_MARK, arg8##_MARK, }
1297
1298 /* - AUDIO macro -------------------------------------------------------------*/
1299 #define AUDIO_PFC_PIN(name, pin)        SH_PFC_PINS(name, pin)
1300 #define AUDIO_PFC_DAT(name, pin)        SH_PFC_MUX1(name, pin)
1301
1302 /* - AUDIO clock -------------------------------------------------------------*/
1303 AUDIO_PFC_PIN(audio_clk_a,      RCAR_GP_PIN(2, 22));
1304 AUDIO_PFC_DAT(audio_clk_a,      AUDIO_CLKA);
1305 AUDIO_PFC_PIN(audio_clk_b,      RCAR_GP_PIN(2, 23));
1306 AUDIO_PFC_DAT(audio_clk_b,      AUDIO_CLKB);
1307 AUDIO_PFC_PIN(audio_clk_c,      RCAR_GP_PIN(2, 7));
1308 AUDIO_PFC_DAT(audio_clk_c,      AUDIO_CLKC);
1309 AUDIO_PFC_PIN(audio_clkout_a,   RCAR_GP_PIN(2, 16));
1310 AUDIO_PFC_DAT(audio_clkout_a,   AUDIO_CLKOUT_A);
1311 AUDIO_PFC_PIN(audio_clkout_b,   RCAR_GP_PIN(1, 16));
1312 AUDIO_PFC_DAT(audio_clkout_b,   AUDIO_CLKOUT_B);
1313
1314 /* - CAN macro --------_----------------------------------------------------- */
1315 #define CAN_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
1316 #define CAN_PFC_DATA(name, tx, rx)              SH_PFC_MUX2(name, tx, rx)
1317 #define CAN_PFC_CLK(name, clk)                  SH_PFC_MUX1(name, clk)
1318
1319 /* - CAN0 ------------------------------------------------------------------- */
1320 CAN_PFC_PINS(can0_data_a,       RCAR_GP_PIN(1, 30),     RCAR_GP_PIN(1, 31));
1321 CAN_PFC_DATA(can0_data_a,       CAN0_TX_A,              CAN0_RX_A);
1322 CAN_PFC_PINS(can0_data_b,       RCAR_GP_PIN(2, 26),     RCAR_GP_PIN(2, 27));
1323 CAN_PFC_DATA(can0_data_b,       CAN0_TX_B,              CAN0_RX_B);
1324
1325 /* - CAN1 ------------------------------------------------------------------- */
1326 CAN_PFC_PINS(can1_data_a,       RCAR_GP_PIN(4, 20),     RCAR_GP_PIN(4, 19));
1327 CAN_PFC_DATA(can1_data_a,       CAN1_TX_A,              CAN1_RX_A);
1328 CAN_PFC_PINS(can1_data_b,       RCAR_GP_PIN(2, 28),     RCAR_GP_PIN(2, 29));
1329 CAN_PFC_DATA(can1_data_b,       CAN1_TX_B,              CAN1_RX_B);
1330
1331 /* - CAN_CLK  --------------------------------------------------------------- */
1332 CAN_PFC_PINS(can_clk_a,         RCAR_GP_PIN(3, 24));
1333 CAN_PFC_CLK(can_clk_a,          CAN_CLK_A);
1334 CAN_PFC_PINS(can_clk_b,         RCAR_GP_PIN(1, 16));
1335 CAN_PFC_CLK(can_clk_b,          CAN_CLK_B);
1336 CAN_PFC_PINS(can_clk_c,         RCAR_GP_PIN(4, 24));
1337 CAN_PFC_CLK(can_clk_c,          CAN_CLK_C);
1338 CAN_PFC_PINS(can_clk_d,         RCAR_GP_PIN(2, 25));
1339 CAN_PFC_CLK(can_clk_d,          CAN_CLK_D);
1340
1341 /* - Ether ------------------------------------------------------------------ */
1342 SH_PFC_PINS(ether_rmii,         RCAR_GP_PIN(4, 10),     RCAR_GP_PIN(4, 11),
1343                                 RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 9),
1344                                 RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16),
1345                                 RCAR_GP_PIN(4, 12),     RCAR_GP_PIN(4, 14),
1346                                 RCAR_GP_PIN(4, 18),     RCAR_GP_PIN(4, 17));
1347 static const unsigned int ether_rmii_mux[] = {
1348         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REF_CLK_MARK,
1349         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
1350         ETH_MDIO_MARK, ETH_MDC_MARK,
1351 };
1352 SH_PFC_PINS(ether_link,         RCAR_GP_PIN(4, 19));
1353 SH_PFC_MUX1(ether_link,         ETH_LINK);
1354 SH_PFC_PINS(ether_magic,        RCAR_GP_PIN(4, 20));
1355 SH_PFC_MUX1(ether_magic,        ETH_MAGIC);
1356
1357 /* - SCIF macro ------------------------------------------------------------- */
1358 #define SCIF_PFC_PIN(name, args...)     SH_PFC_PINS(name, args)
1359 #define SCIF_PFC_DAT(name, tx, rx)      SH_PFC_MUX2(name, tx, rx)
1360 #define SCIF_PFC_CTR(name, cts, rts)    SH_PFC_MUX2(name, cts, rts)
1361 #define SCIF_PFC_CLK(name, sck)         SH_PFC_MUX1(name, sck)
1362
1363 /* - HSCIF0 ----------------------------------------------------------------- */
1364 SCIF_PFC_PIN(hscif0_data_a,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
1365 SCIF_PFC_DAT(hscif0_data_a,     HTX0_A,                 HRX0_A);
1366 SCIF_PFC_PIN(hscif0_data_b,     RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 30));
1367 SCIF_PFC_DAT(hscif0_data_b,     HTX0_B,                 HRX0_B);
1368 SCIF_PFC_PIN(hscif0_ctrl_a,     RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
1369 SCIF_PFC_CTR(hscif0_ctrl_a,     HCTS0_A,                HRTS0_A);
1370 SCIF_PFC_PIN(hscif0_ctrl_b,     RCAR_GP_PIN(0, 31),     RCAR_GP_PIN(0, 28));
1371 SCIF_PFC_CTR(hscif0_ctrl_b,     HCTS0_B,                HRTS0_B);
1372 SCIF_PFC_PIN(hscif0_clk,        RCAR_GP_PIN(1, 19));
1373 SCIF_PFC_CLK(hscif0_clk,        HSCK0);
1374
1375 /* - HSCIF1 ----------------------------------------------------------------- */
1376 SCIF_PFC_PIN(hscif1_data_a,     RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20));
1377 SCIF_PFC_DAT(hscif1_data_a,     HTX1_A,                 HRX1_A);
1378 SCIF_PFC_PIN(hscif1_data_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
1379 SCIF_PFC_DAT(hscif1_data_b,     HTX1_B,                 HRX1_B);
1380 SCIF_PFC_PIN(hscif1_ctrl_a,     RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
1381 SCIF_PFC_CTR(hscif1_ctrl_a,     HCTS1_A,                HRTS1_A);
1382 SCIF_PFC_PIN(hscif1_ctrl_b,     RCAR_GP_PIN(4, 8),      RCAR_GP_PIN(4, 7));
1383 SCIF_PFC_CTR(hscif1_ctrl_b,     HCTS1_B,                HRTS1_B);
1384 SCIF_PFC_PIN(hscif1_clk_a,      RCAR_GP_PIN(3, 23));
1385 SCIF_PFC_CLK(hscif1_clk_a,      HSCK1_A);
1386 SCIF_PFC_PIN(hscif1_clk_b,      RCAR_GP_PIN(4, 2));
1387 SCIF_PFC_CLK(hscif1_clk_b,      HSCK1_B);
1388
1389 /* - HSPI macro --------------------------------------------------------------*/
1390 #define HSPI_PFC_PIN(name, args...)             SH_PFC_PINS(name, args)
1391 #define HSPI_PFC_DAT(name, clk, cs, rx, tx)     SH_PFC_MUX4(name, clk, cs, rx, tx)
1392
1393 /* - HSPI0 -------------------------------------------------------------------*/
1394 HSPI_PFC_PIN(hspi0_a,   RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20),
1395                         RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
1396 HSPI_PFC_DAT(hspi0_a,   HSPI_CLK0_A,            HSPI_CS0_A,
1397                         HSPI_RX0_A,             HSPI_TX0);
1398
1399 HSPI_PFC_PIN(hspi0_b,   RCAR_GP_PIN(2, 25),     RCAR_GP_PIN(2, 26),
1400                         RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 27));
1401 HSPI_PFC_DAT(hspi0_b,   HSPI_CLK0_B,            HSPI_CS0_B,
1402                         HSPI_RX0_B,             HSPI_TX0_B);
1403
1404 /* - HSPI1 -------------------------------------------------------------------*/
1405 HSPI_PFC_PIN(hspi1_a,   RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 27),
1406                         RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 28));
1407 HSPI_PFC_DAT(hspi1_a,   HSPI_CLK1_A,            HSPI_CS1_A,
1408                         HSPI_RX1_A,             HSPI_TX1_A);
1409
1410 HSPI_PFC_PIN(hspi1_b,   RCAR_GP_PIN(0, 27),     RCAR_GP_PIN(0, 26),
1411                         PIN_NUMBER(20, 1),      PIN_NUMBER(25, 2));
1412 HSPI_PFC_DAT(hspi1_b,   HSPI_CLK1_B,            HSPI_CS1_B,
1413                         HSPI_RX1_B,             HSPI_TX1_B);
1414
1415 /* - HSPI2 -------------------------------------------------------------------*/
1416 HSPI_PFC_PIN(hspi2_a,   RCAR_GP_PIN(2, 29),     RCAR_GP_PIN(3, 8),
1417                         RCAR_GP_PIN(2, 28),     RCAR_GP_PIN(2, 30));
1418 HSPI_PFC_DAT(hspi2_a,   HSPI_CLK2_A,            HSPI_CS2_A,
1419                         HSPI_RX2_A,             HSPI_TX2_A);
1420
1421 HSPI_PFC_PIN(hspi2_b,   RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22),
1422                         RCAR_GP_PIN(4, 23),     RCAR_GP_PIN(4, 24));
1423 HSPI_PFC_DAT(hspi2_b,   HSPI_CLK2_B,            HSPI_CS2_B,
1424                         HSPI_RX2_B,             HSPI_TX2_B);
1425
1426 /* - I2C macro ------------------------------------------------------------- */
1427 #define I2C_PFC_PIN(name, args...)      SH_PFC_PINS(name, args)
1428 #define I2C_PFC_MUX(name, sda, scl)     SH_PFC_MUX2(name, sda, scl)
1429
1430 /* - I2C1 ------------------------------------------------------------------ */
1431 I2C_PFC_PIN(i2c1_a,     RCAR_GP_PIN(3, 8),      RCAR_GP_PIN(3, 9));
1432 I2C_PFC_MUX(i2c1_a,     SDA1_A,                 SCL1_A);
1433 I2C_PFC_PIN(i2c1_b,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
1434 I2C_PFC_MUX(i2c1_b,     SDA1_B,                 SCL1_B);
1435
1436 /* - I2C2 ------------------------------------------------------------------ */
1437 I2C_PFC_PIN(i2c2_a,     PIN_NUMBER(3, 20),      RCAR_GP_PIN(1, 3));
1438 I2C_PFC_MUX(i2c2_a,     SDA2_A,                 SCL2_A);
1439 I2C_PFC_PIN(i2c2_b,     RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
1440 I2C_PFC_MUX(i2c2_b,     SDA2_B,                 SCL2_B);
1441 I2C_PFC_PIN(i2c2_c,     RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
1442 I2C_PFC_MUX(i2c2_c,     SDA2_C,                 SCL2_C);
1443
1444 /* - I2C3 ------------------------------------------------------------------ */
1445 I2C_PFC_PIN(i2c3_a,     RCAR_GP_PIN(1, 14),     RCAR_GP_PIN(1, 15));
1446 I2C_PFC_MUX(i2c3_a,     SDA3_A,                 SCL3_A);
1447 I2C_PFC_PIN(i2c3_b,     RCAR_GP_PIN(1, 16),     RCAR_GP_PIN(1, 19));
1448 I2C_PFC_MUX(i2c3_b,     SDA3_B,                 SCL3_B);
1449 I2C_PFC_PIN(i2c3_c,     RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 23));
1450 I2C_PFC_MUX(i2c3_c,     SDA3_C,                 SCL3_C);
1451
1452 /* - MMC macro -------------------------------------------------------------- */
1453 #define MMC_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
1454 #define MMC_PFC_CTRL(name, clk, cmd)            SH_PFC_MUX2(name, clk, cmd)
1455 #define MMC_PFC_DAT1(name, d0)                  SH_PFC_MUX1(name, d0)
1456 #define MMC_PFC_DAT4(name, d0, d1, d2, d3)      SH_PFC_MUX4(name, d0, d1, d2, d3)
1457 #define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
1458                         SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
1459
1460 /* - MMC -------------------------------------------------------------------- */
1461 MMC_PFC_PINS(mmc_ctrl,          RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
1462 MMC_PFC_CTRL(mmc_ctrl,          MMC_CLK,                MMC_CMD);
1463 MMC_PFC_PINS(mmc_data1,         RCAR_GP_PIN(1, 7));
1464 MMC_PFC_DAT1(mmc_data1,         MMC_D0);
1465 MMC_PFC_PINS(mmc_data4,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(1, 8),
1466                                 RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
1467 MMC_PFC_DAT4(mmc_data4,         MMC_D0,                 MMC_D1,
1468                                 MMC_D2,                 MMC_D3);
1469 MMC_PFC_PINS(mmc_data8,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(1, 8),
1470                                 RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6),
1471                                 RCAR_GP_PIN(1, 4),      RCAR_GP_PIN(1, 0),
1472                                 RCAR_GP_PIN(0, 30),     RCAR_GP_PIN(0, 31));
1473 MMC_PFC_DAT8(mmc_data8,         MMC_D0,                 MMC_D1,
1474                                 MMC_D2,                 MMC_D3,
1475                                 MMC_D4,                 MMC_D5,
1476                                 MMC_D6,                 MMC_D7);
1477
1478 /* - SCIF CLOCK ------------------------------------------------------------- */
1479 SCIF_PFC_PIN(scif_clk,          RCAR_GP_PIN(1, 16));
1480 SCIF_PFC_CLK(scif_clk,          SCIF_CLK);
1481
1482 /* - SCIF0 ------------------------------------------------------------------ */
1483 SCIF_PFC_PIN(scif0_data_a,      RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
1484 SCIF_PFC_DAT(scif0_data_a,      TX0_A,                  RX0_A);
1485 SCIF_PFC_PIN(scif0_data_b,      RCAR_GP_PIN(2, 3),      RCAR_GP_PIN(2, 2));
1486 SCIF_PFC_DAT(scif0_data_b,      TX0_B,                  RX0_B);
1487 SCIF_PFC_PIN(scif0_data_c,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(3, 31));
1488 SCIF_PFC_DAT(scif0_data_c,      TX0_C,                  RX0_C);
1489 SCIF_PFC_PIN(scif0_data_d,      RCAR_GP_PIN(3, 6),      RCAR_GP_PIN(3, 1));
1490 SCIF_PFC_DAT(scif0_data_d,      TX0_D,                  RX0_D);
1491 SCIF_PFC_PIN(scif0_ctrl,        RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
1492 SCIF_PFC_CTR(scif0_ctrl,        CTS0,                   RTS0);
1493 SCIF_PFC_PIN(scif0_clk,         RCAR_GP_PIN(1, 19));
1494 SCIF_PFC_CLK(scif0_clk,         SCK0);
1495
1496 /* - SCIF1 ------------------------------------------------------------------ */
1497 SCIF_PFC_PIN(scif1_data_a,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(4, 1));
1498 SCIF_PFC_DAT(scif1_data_a,      TX1_A,                  RX1_A);
1499 SCIF_PFC_PIN(scif1_data_b,      RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 25));
1500 SCIF_PFC_DAT(scif1_data_b,      TX1_B,                  RX1_B);
1501 SCIF_PFC_PIN(scif1_data_c,      RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
1502 SCIF_PFC_DAT(scif1_data_c,      TX1_C,                  RX1_C);
1503 SCIF_PFC_PIN(scif1_data_d,      RCAR_GP_PIN(1, 30),     RCAR_GP_PIN(1, 31));
1504 SCIF_PFC_DAT(scif1_data_d,      TX1_D,                  RX1_D);
1505 SCIF_PFC_PIN(scif1_ctrl_a,      RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
1506 SCIF_PFC_CTR(scif1_ctrl_a,      CTS1_A,                 RTS1_A);
1507 SCIF_PFC_PIN(scif1_ctrl_c,      RCAR_GP_PIN(3, 23),     RCAR_GP_PIN(3, 19));
1508 SCIF_PFC_CTR(scif1_ctrl_c,      CTS1_C,                 RTS1_C);
1509 SCIF_PFC_PIN(scif1_clk_a,       RCAR_GP_PIN(4, 2));
1510 SCIF_PFC_CLK(scif1_clk_a,       SCK1_A);
1511 SCIF_PFC_PIN(scif1_clk_c,       RCAR_GP_PIN(3, 20));
1512 SCIF_PFC_CLK(scif1_clk_c,       SCK1_C);
1513
1514 /* - SCIF2 ------------------------------------------------------------------ */
1515 SCIF_PFC_PIN(scif2_data_a,      RCAR_GP_PIN(2, 26),     RCAR_GP_PIN(2, 27));
1516 SCIF_PFC_DAT(scif2_data_a,      TX2_A,                  RX2_A);
1517 SCIF_PFC_PIN(scif2_data_b,      RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 28));
1518 SCIF_PFC_DAT(scif2_data_b,      TX2_B,                  RX2_B);
1519 SCIF_PFC_PIN(scif2_data_c,      RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 14));
1520 SCIF_PFC_DAT(scif2_data_c,      TX2_C,                  RX2_C);
1521 SCIF_PFC_PIN(scif2_data_d,      RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
1522 SCIF_PFC_DAT(scif2_data_d,      TX2_D,                  RX2_D);
1523 SCIF_PFC_PIN(scif2_data_e,      RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
1524 SCIF_PFC_DAT(scif2_data_e,      TX2_E,                  RX2_E);
1525 SCIF_PFC_PIN(scif2_clk_a,       RCAR_GP_PIN(3, 9));
1526 SCIF_PFC_CLK(scif2_clk_a,       SCK2_A);
1527 SCIF_PFC_PIN(scif2_clk_b,       PIN_NUMBER(3, 20));
1528 SCIF_PFC_CLK(scif2_clk_b,       SCK2_B);
1529 SCIF_PFC_PIN(scif2_clk_c,       RCAR_GP_PIN(4, 12));
1530 SCIF_PFC_CLK(scif2_clk_c,       SCK2_C);
1531
1532 /* - SCIF3 ------------------------------------------------------------------ */
1533 SCIF_PFC_PIN(scif3_data_a,      RCAR_GP_PIN(1, 10),     RCAR_GP_PIN(1, 9));
1534 SCIF_PFC_DAT(scif3_data_a,      TX3_A,                  RX3_A);
1535 SCIF_PFC_PIN(scif3_data_b,      RCAR_GP_PIN(3, 28),     RCAR_GP_PIN(3, 27));
1536 SCIF_PFC_DAT(scif3_data_b,      TX3_B,                  RX3_B);
1537 SCIF_PFC_PIN(scif3_data_c,      RCAR_GP_PIN(1, 3),      RCAR_GP_PIN(0, 31));
1538 SCIF_PFC_DAT(scif3_data_c,      TX3_C,                  RX3_C);
1539 SCIF_PFC_PIN(scif3_data_d,      RCAR_GP_PIN(3, 30),     RCAR_GP_PIN(3, 29));
1540 SCIF_PFC_DAT(scif3_data_d,      TX3_D,                  RX3_D);
1541
1542 /* - SCIF4 ------------------------------------------------------------------ */
1543 SCIF_PFC_PIN(scif4_data_a,      RCAR_GP_PIN(2, 5),      RCAR_GP_PIN(2, 4));
1544 SCIF_PFC_DAT(scif4_data_a,      TX4_A,                  RX4_A);
1545 SCIF_PFC_PIN(scif4_data_b,      RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 25));
1546 SCIF_PFC_DAT(scif4_data_b,      TX4_B,                  RX4_B);
1547 SCIF_PFC_PIN(scif4_data_c,      RCAR_GP_PIN(3, 0),      RCAR_GP_PIN(2, 31));
1548 SCIF_PFC_DAT(scif4_data_c,      TX4_C,                  RX4_C);
1549
1550 /* - SCIF5 ------------------------------------------------------------------ */
1551 SCIF_PFC_PIN(scif5_data_a,      RCAR_GP_PIN(3, 17),     RCAR_GP_PIN(3, 18));
1552 SCIF_PFC_DAT(scif5_data_a,      TX5_A,                  RX5_A);
1553 SCIF_PFC_PIN(scif5_data_b,      RCAR_GP_PIN(1, 15),     RCAR_GP_PIN(1, 14));
1554 SCIF_PFC_DAT(scif5_data_b,      TX5_B,                  RX5_B);
1555
1556 /* - SDHI macro ------------------------------------------------------------- */
1557 #define SDHI_PFC_PINS(name, args...)            SH_PFC_PINS(name, args)
1558 #define SDHI_PFC_DAT1(name, d0)                 SH_PFC_MUX1(name, d0)
1559 #define SDHI_PFC_DAT4(name, d0, d1, d2, d3)     SH_PFC_MUX4(name, d0, d1, d2, d3)
1560 #define SDHI_PFC_CTRL(name, clk, cmd)           SH_PFC_MUX2(name, clk, cmd)
1561 #define SDHI_PFC_CDPN(name, cd)                 SH_PFC_MUX1(name, cd)
1562 #define SDHI_PFC_WPPN(name, wp)                 SH_PFC_MUX1(name, wp)
1563
1564 /* - SDHI0 ------------------------------------------------------------------ */
1565 SDHI_PFC_PINS(sdhi0_cd,         RCAR_GP_PIN(3, 17));
1566 SDHI_PFC_CDPN(sdhi0_cd,         SD0_CD);
1567 SDHI_PFC_PINS(sdhi0_ctrl,       RCAR_GP_PIN(3, 11),     RCAR_GP_PIN(3, 12));
1568 SDHI_PFC_CTRL(sdhi0_ctrl,       SD0_CLK,                SD0_CMD);
1569 SDHI_PFC_PINS(sdhi0_data1,      RCAR_GP_PIN(3, 13));
1570 SDHI_PFC_DAT1(sdhi0_data1,      SD0_DAT0);
1571 SDHI_PFC_PINS(sdhi0_data4,      RCAR_GP_PIN(3, 13),     RCAR_GP_PIN(3, 14),
1572                                 RCAR_GP_PIN(3, 15),     RCAR_GP_PIN(3, 16));
1573 SDHI_PFC_DAT4(sdhi0_data4,      SD0_DAT0,               SD0_DAT1,
1574                                 SD0_DAT2,               SD0_DAT3);
1575 SDHI_PFC_PINS(sdhi0_wp,         RCAR_GP_PIN(3, 18));
1576 SDHI_PFC_WPPN(sdhi0_wp,         SD0_WP);
1577
1578 /* - SDHI1 ------------------------------------------------------------------ */
1579 SDHI_PFC_PINS(sdhi1_cd_a,       RCAR_GP_PIN(0, 30));
1580 SDHI_PFC_CDPN(sdhi1_cd_a,       SD1_CD_A);
1581 SDHI_PFC_PINS(sdhi1_cd_b,       RCAR_GP_PIN(2, 24));
1582 SDHI_PFC_CDPN(sdhi1_cd_b,       SD1_CD_B);
1583 SDHI_PFC_PINS(sdhi1_ctrl_a,     RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
1584 SDHI_PFC_CTRL(sdhi1_ctrl_a,     SD1_CLK_A,              SD1_CMD_A);
1585 SDHI_PFC_PINS(sdhi1_ctrl_b,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 16));
1586 SDHI_PFC_CTRL(sdhi1_ctrl_b,     SD1_CLK_B,              SD1_CMD_B);
1587 SDHI_PFC_PINS(sdhi1_data1_a,    RCAR_GP_PIN(1, 7));
1588 SDHI_PFC_DAT1(sdhi1_data1_a,    SD1_DAT0_A);
1589 SDHI_PFC_PINS(sdhi1_data1_b,    RCAR_GP_PIN(1, 18));
1590 SDHI_PFC_DAT1(sdhi1_data1_b,    SD1_DAT0_B);
1591 SDHI_PFC_PINS(sdhi1_data4_a,    RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(1, 8),
1592                                 RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
1593 SDHI_PFC_DAT4(sdhi1_data4_a,    SD1_DAT0_A,             SD1_DAT1_A,
1594                                 SD1_DAT2_A,             SD1_DAT3_A);
1595 SDHI_PFC_PINS(sdhi1_data4_b,    RCAR_GP_PIN(1, 18),     RCAR_GP_PIN(1, 19),
1596                                 RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
1597 SDHI_PFC_DAT4(sdhi1_data4_b,    SD1_DAT0_B,             SD1_DAT1_B,
1598                                 SD1_DAT2_B,             SD1_DAT3_B);
1599 SDHI_PFC_PINS(sdhi1_wp_a,       RCAR_GP_PIN(0, 31));
1600 SDHI_PFC_WPPN(sdhi1_wp_a,       SD1_WP_A);
1601 SDHI_PFC_PINS(sdhi1_wp_b,       RCAR_GP_PIN(2, 25));
1602 SDHI_PFC_WPPN(sdhi1_wp_b,       SD1_WP_B);
1603
1604 /* - SDH2 ------------------------------------------------------------------- */
1605 SDHI_PFC_PINS(sdhi2_cd_a,       RCAR_GP_PIN(4, 23));
1606 SDHI_PFC_CDPN(sdhi2_cd_a,       SD2_CD_A);
1607 SDHI_PFC_PINS(sdhi2_cd_b,       RCAR_GP_PIN(3, 27));
1608 SDHI_PFC_CDPN(sdhi2_cd_b,       SD2_CD_B);
1609 SDHI_PFC_PINS(sdhi2_ctrl_a,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
1610 SDHI_PFC_CTRL(sdhi2_ctrl_a,     SD2_CLK_A,              SD2_CMD_A);
1611 SDHI_PFC_PINS(sdhi2_ctrl_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
1612 SDHI_PFC_CTRL(sdhi2_ctrl_b,     SD2_CLK_B,              SD2_CMD_B);
1613 SDHI_PFC_PINS(sdhi2_data1_a,    RCAR_GP_PIN(4, 19));
1614 SDHI_PFC_DAT1(sdhi2_data1_a,    SD2_DAT0_A);
1615 SDHI_PFC_PINS(sdhi2_data1_b,    RCAR_GP_PIN(4, 7));
1616 SDHI_PFC_DAT1(sdhi2_data1_b,    SD2_DAT0_B);
1617 SDHI_PFC_PINS(sdhi2_data4_a,    RCAR_GP_PIN(4, 19),     RCAR_GP_PIN(4, 20),
1618                                 RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22));
1619 SDHI_PFC_DAT4(sdhi2_data4_a,    SD2_DAT0_A,             SD2_DAT1_A,
1620                                 SD2_DAT2_A,             SD2_DAT3_A);
1621 SDHI_PFC_PINS(sdhi2_data4_b,    RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8),
1622                                 RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26));
1623 SDHI_PFC_DAT4(sdhi2_data4_b,    SD2_DAT0_B,             SD2_DAT1_B,
1624                                 SD2_DAT2_B,             SD2_DAT3_B);
1625 SDHI_PFC_PINS(sdhi2_wp_a,       RCAR_GP_PIN(4, 24));
1626 SDHI_PFC_WPPN(sdhi2_wp_a,       SD2_WP_A);
1627 SDHI_PFC_PINS(sdhi2_wp_b,       RCAR_GP_PIN(3, 28));
1628 SDHI_PFC_WPPN(sdhi2_wp_b,       SD2_WP_B);
1629
1630 /* - SSI macro -------------------------------------------------------------- */
1631 #define SSI_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
1632 #define SSI_PFC_CTRL(name, sck, ws)             SH_PFC_MUX2(name, sck, ws)
1633 #define SSI_PFC_DATA(name, d)                   SH_PFC_MUX1(name, d)
1634
1635 /* - SSI 0/1/2 -------------------------------------------------------------- */
1636 SSI_PFC_PINS(ssi012_ctrl,       RCAR_GP_PIN(3, 6),      RCAR_GP_PIN(3, 7));
1637 SSI_PFC_CTRL(ssi012_ctrl,       SSI_SCK012,             SSI_WS012);
1638 SSI_PFC_PINS(ssi0_data,         RCAR_GP_PIN(3, 10));
1639 SSI_PFC_DATA(ssi0_data,         SSI_SDATA0);
1640 SSI_PFC_PINS(ssi1_a_ctrl,       RCAR_GP_PIN(2, 20),     RCAR_GP_PIN(2, 21));
1641 SSI_PFC_CTRL(ssi1_a_ctrl,       SSI_SCK1_A,             SSI_WS1_A);
1642 SSI_PFC_PINS(ssi1_b_ctrl,       PIN_NUMBER(3, 20),      RCAR_GP_PIN(1, 3));
1643 SSI_PFC_CTRL(ssi1_b_ctrl,       SSI_SCK1_B,             SSI_WS1_B);
1644 SSI_PFC_PINS(ssi1_data,         RCAR_GP_PIN(3, 9));
1645 SSI_PFC_DATA(ssi1_data,         SSI_SDATA1);
1646 SSI_PFC_PINS(ssi2_a_ctrl,       RCAR_GP_PIN(2, 26),     RCAR_GP_PIN(3, 4));
1647 SSI_PFC_CTRL(ssi2_a_ctrl,       SSI_SCK2_A,             SSI_WS2_A);
1648 SSI_PFC_PINS(ssi2_b_ctrl,       RCAR_GP_PIN(2, 6),      RCAR_GP_PIN(2, 17));
1649 SSI_PFC_CTRL(ssi2_b_ctrl,       SSI_SCK2_B,             SSI_WS2_B);
1650 SSI_PFC_PINS(ssi2_data,         RCAR_GP_PIN(3, 8));
1651 SSI_PFC_DATA(ssi2_data,         SSI_SDATA2);
1652
1653 /* - SSI 3/4 ---------------------------------------------------------------- */
1654 SSI_PFC_PINS(ssi34_ctrl,        RCAR_GP_PIN(3, 2),      RCAR_GP_PIN(3, 3));
1655 SSI_PFC_CTRL(ssi34_ctrl,        SSI_SCK34,              SSI_WS34);
1656 SSI_PFC_PINS(ssi3_data,         RCAR_GP_PIN(3, 5));
1657 SSI_PFC_DATA(ssi3_data,         SSI_SDATA3);
1658 SSI_PFC_PINS(ssi4_ctrl,         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 23));
1659 SSI_PFC_CTRL(ssi4_ctrl,         SSI_SCK4,               SSI_WS4);
1660 SSI_PFC_PINS(ssi4_data,         RCAR_GP_PIN(3, 4));
1661 SSI_PFC_DATA(ssi4_data,         SSI_SDATA4);
1662
1663 /* - SSI 5 ------------------------------------------------------------------ */
1664 SSI_PFC_PINS(ssi5_ctrl,         RCAR_GP_PIN(2, 31),     RCAR_GP_PIN(3, 0));
1665 SSI_PFC_CTRL(ssi5_ctrl,         SSI_SCK5,               SSI_WS5);
1666 SSI_PFC_PINS(ssi5_data,         RCAR_GP_PIN(3, 1));
1667 SSI_PFC_DATA(ssi5_data,         SSI_SDATA5);
1668
1669 /* - SSI 6 ------------------------------------------------------------------ */
1670 SSI_PFC_PINS(ssi6_ctrl,         RCAR_GP_PIN(2, 28),     RCAR_GP_PIN(2, 29));
1671 SSI_PFC_CTRL(ssi6_ctrl,         SSI_SCK6,               SSI_WS6);
1672 SSI_PFC_PINS(ssi6_data,         RCAR_GP_PIN(2, 30));
1673 SSI_PFC_DATA(ssi6_data,         SSI_SDATA6);
1674
1675 /* - SSI 7/8  --------------------------------------------------------------- */
1676 SSI_PFC_PINS(ssi78_ctrl,        RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 25));
1677 SSI_PFC_CTRL(ssi78_ctrl,        SSI_SCK78,              SSI_WS78);
1678 SSI_PFC_PINS(ssi7_data,         RCAR_GP_PIN(2, 27));
1679 SSI_PFC_DATA(ssi7_data,         SSI_SDATA7);
1680 SSI_PFC_PINS(ssi8_data,         RCAR_GP_PIN(2, 26));
1681 SSI_PFC_DATA(ssi8_data,         SSI_SDATA8);
1682
1683 /* - USB0 ------------------------------------------------------------------- */
1684 SH_PFC_PINS(usb0,               RCAR_GP_PIN(0, 1));
1685 SH_PFC_MUX1(usb0,               PENC0);
1686 SH_PFC_PINS(usb0_ovc,           RCAR_GP_PIN(0, 3));
1687 SH_PFC_MUX1(usb0_ovc,           USB_OVC0);
1688
1689 /* - USB1 ------------------------------------------------------------------- */
1690 SH_PFC_PINS(usb1,               RCAR_GP_PIN(0, 2));
1691 SH_PFC_MUX1(usb1,               PENC1);
1692 SH_PFC_PINS(usb1_ovc,           RCAR_GP_PIN(0, 4));
1693 SH_PFC_MUX1(usb1_ovc,           USB_OVC1);
1694
1695 /* - VIN macros ------------------------------------------------------------- */
1696 #define VIN_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
1697 #define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
1698         SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
1699 #define VIN_PFC_CLK(name, clk)                  SH_PFC_MUX1(name, clk)
1700 #define VIN_PFC_SYNC(name, hsync, vsync)        SH_PFC_MUX2(name, hsync, vsync)
1701
1702 /* - VIN0 ------------------------------------------------------------------- */
1703 VIN_PFC_PINS(vin0_data8,        RCAR_GP_PIN(3, 29),     RCAR_GP_PIN(3, 30),
1704                                 RCAR_GP_PIN(3, 31),     RCAR_GP_PIN(4, 0),
1705                                 RCAR_GP_PIN(4, 1),      RCAR_GP_PIN(4, 2),
1706                                 RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
1707 VIN_PFC_DAT8(vin0_data8,        VI0_DATA0_VI0_B0,       VI0_DATA1_VI0_B1,
1708                                 VI0_DATA2_VI0_B2,       VI0_DATA3_VI0_B3,
1709                                 VI0_DATA4_VI0_B4,       VI0_DATA5_VI0_B5,
1710                                 VI0_DATA6_VI0_G0,       VI0_DATA7_VI0_G1);
1711 VIN_PFC_PINS(vin0_clk,          RCAR_GP_PIN(3, 24));
1712 VIN_PFC_CLK(vin0_clk,           VI0_CLK);
1713 VIN_PFC_PINS(vin0_sync,         RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28));
1714 VIN_PFC_SYNC(vin0_sync,         VI0_HSYNC,              VI0_VSYNC);
1715 /* - VIN1 ------------------------------------------------------------------- */
1716 VIN_PFC_PINS(vin1_data8,        RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26),
1717                                 RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28),
1718                                 RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6),
1719                                 RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8));
1720 VIN_PFC_DAT8(vin1_data8,        VI1_DATA0,              VI1_DATA1,
1721                                 VI1_DATA2,              VI1_DATA3,
1722                                 VI1_DATA4,              VI1_DATA5,
1723                                 VI1_DATA6,              VI1_DATA7);
1724 VIN_PFC_PINS(vin1_clk,          RCAR_GP_PIN(4, 9));
1725 VIN_PFC_CLK(vin1_clk,           VI1_CLK);
1726 VIN_PFC_PINS(vin1_sync,         RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
1727 VIN_PFC_SYNC(vin1_sync,         VI1_HSYNC,              VI1_VSYNC);
1728
1729 static const struct sh_pfc_pin_group pinmux_groups[] = {
1730         SH_PFC_PIN_GROUP(audio_clk_a),
1731         SH_PFC_PIN_GROUP(audio_clk_b),
1732         SH_PFC_PIN_GROUP(audio_clk_c),
1733         SH_PFC_PIN_GROUP(audio_clkout_a),
1734         SH_PFC_PIN_GROUP(audio_clkout_b),
1735         SH_PFC_PIN_GROUP(can0_data_a),
1736         SH_PFC_PIN_GROUP(can0_data_b),
1737         SH_PFC_PIN_GROUP(can1_data_a),
1738         SH_PFC_PIN_GROUP(can1_data_b),
1739         SH_PFC_PIN_GROUP(can_clk_a),
1740         SH_PFC_PIN_GROUP(can_clk_b),
1741         SH_PFC_PIN_GROUP(can_clk_c),
1742         SH_PFC_PIN_GROUP(can_clk_d),
1743         SH_PFC_PIN_GROUP(ether_rmii),
1744         SH_PFC_PIN_GROUP(ether_link),
1745         SH_PFC_PIN_GROUP(ether_magic),
1746         SH_PFC_PIN_GROUP(hscif0_data_a),
1747         SH_PFC_PIN_GROUP(hscif0_data_b),
1748         SH_PFC_PIN_GROUP(hscif0_ctrl_a),
1749         SH_PFC_PIN_GROUP(hscif0_ctrl_b),
1750         SH_PFC_PIN_GROUP(hscif0_clk),
1751         SH_PFC_PIN_GROUP(hscif1_data_a),
1752         SH_PFC_PIN_GROUP(hscif1_data_b),
1753         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
1754         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
1755         SH_PFC_PIN_GROUP(hscif1_clk_a),
1756         SH_PFC_PIN_GROUP(hscif1_clk_b),
1757         SH_PFC_PIN_GROUP(hspi0_a),
1758         SH_PFC_PIN_GROUP(hspi0_b),
1759         SH_PFC_PIN_GROUP(hspi1_a),
1760         SH_PFC_PIN_GROUP(hspi1_b),
1761         SH_PFC_PIN_GROUP(hspi2_a),
1762         SH_PFC_PIN_GROUP(hspi2_b),
1763         SH_PFC_PIN_GROUP(i2c1_a),
1764         SH_PFC_PIN_GROUP(i2c1_b),
1765         SH_PFC_PIN_GROUP(i2c2_a),
1766         SH_PFC_PIN_GROUP(i2c2_b),
1767         SH_PFC_PIN_GROUP(i2c2_c),
1768         SH_PFC_PIN_GROUP(i2c3_a),
1769         SH_PFC_PIN_GROUP(i2c3_b),
1770         SH_PFC_PIN_GROUP(i2c3_c),
1771         SH_PFC_PIN_GROUP(mmc_ctrl),
1772         SH_PFC_PIN_GROUP(mmc_data1),
1773         SH_PFC_PIN_GROUP(mmc_data4),
1774         SH_PFC_PIN_GROUP(mmc_data8),
1775         SH_PFC_PIN_GROUP(scif_clk),
1776         SH_PFC_PIN_GROUP(scif0_data_a),
1777         SH_PFC_PIN_GROUP(scif0_data_b),
1778         SH_PFC_PIN_GROUP(scif0_data_c),
1779         SH_PFC_PIN_GROUP(scif0_data_d),
1780         SH_PFC_PIN_GROUP(scif0_ctrl),
1781         SH_PFC_PIN_GROUP(scif0_clk),
1782         SH_PFC_PIN_GROUP(scif1_data_a),
1783         SH_PFC_PIN_GROUP(scif1_data_b),
1784         SH_PFC_PIN_GROUP(scif1_data_c),
1785         SH_PFC_PIN_GROUP(scif1_data_d),
1786         SH_PFC_PIN_GROUP(scif1_ctrl_a),
1787         SH_PFC_PIN_GROUP(scif1_ctrl_c),
1788         SH_PFC_PIN_GROUP(scif1_clk_a),
1789         SH_PFC_PIN_GROUP(scif1_clk_c),
1790         SH_PFC_PIN_GROUP(scif2_data_a),
1791         SH_PFC_PIN_GROUP(scif2_data_b),
1792         SH_PFC_PIN_GROUP(scif2_data_c),
1793         SH_PFC_PIN_GROUP(scif2_data_d),
1794         SH_PFC_PIN_GROUP(scif2_data_e),
1795         SH_PFC_PIN_GROUP(scif2_clk_a),
1796         SH_PFC_PIN_GROUP(scif2_clk_b),
1797         SH_PFC_PIN_GROUP(scif2_clk_c),
1798         SH_PFC_PIN_GROUP(scif3_data_a),
1799         SH_PFC_PIN_GROUP(scif3_data_b),
1800         SH_PFC_PIN_GROUP(scif3_data_c),
1801         SH_PFC_PIN_GROUP(scif3_data_d),
1802         SH_PFC_PIN_GROUP(scif4_data_a),
1803         SH_PFC_PIN_GROUP(scif4_data_b),
1804         SH_PFC_PIN_GROUP(scif4_data_c),
1805         SH_PFC_PIN_GROUP(scif5_data_a),
1806         SH_PFC_PIN_GROUP(scif5_data_b),
1807         SH_PFC_PIN_GROUP(sdhi0_cd),
1808         SH_PFC_PIN_GROUP(sdhi0_ctrl),
1809         SH_PFC_PIN_GROUP(sdhi0_data1),
1810         SH_PFC_PIN_GROUP(sdhi0_data4),
1811         SH_PFC_PIN_GROUP(sdhi0_wp),
1812         SH_PFC_PIN_GROUP(sdhi1_cd_a),
1813         SH_PFC_PIN_GROUP(sdhi1_cd_b),
1814         SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
1815         SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
1816         SH_PFC_PIN_GROUP(sdhi1_data1_a),
1817         SH_PFC_PIN_GROUP(sdhi1_data1_b),
1818         SH_PFC_PIN_GROUP(sdhi1_data4_a),
1819         SH_PFC_PIN_GROUP(sdhi1_data4_b),
1820         SH_PFC_PIN_GROUP(sdhi1_wp_a),
1821         SH_PFC_PIN_GROUP(sdhi1_wp_b),
1822         SH_PFC_PIN_GROUP(sdhi2_cd_a),
1823         SH_PFC_PIN_GROUP(sdhi2_cd_b),
1824         SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
1825         SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
1826         SH_PFC_PIN_GROUP(sdhi2_data1_a),
1827         SH_PFC_PIN_GROUP(sdhi2_data1_b),
1828         SH_PFC_PIN_GROUP(sdhi2_data4_a),
1829         SH_PFC_PIN_GROUP(sdhi2_data4_b),
1830         SH_PFC_PIN_GROUP(sdhi2_wp_a),
1831         SH_PFC_PIN_GROUP(sdhi2_wp_b),
1832         SH_PFC_PIN_GROUP(ssi012_ctrl),
1833         SH_PFC_PIN_GROUP(ssi0_data),
1834         SH_PFC_PIN_GROUP(ssi1_a_ctrl),
1835         SH_PFC_PIN_GROUP(ssi1_b_ctrl),
1836         SH_PFC_PIN_GROUP(ssi1_data),
1837         SH_PFC_PIN_GROUP(ssi2_a_ctrl),
1838         SH_PFC_PIN_GROUP(ssi2_b_ctrl),
1839         SH_PFC_PIN_GROUP(ssi2_data),
1840         SH_PFC_PIN_GROUP(ssi34_ctrl),
1841         SH_PFC_PIN_GROUP(ssi3_data),
1842         SH_PFC_PIN_GROUP(ssi4_ctrl),
1843         SH_PFC_PIN_GROUP(ssi4_data),
1844         SH_PFC_PIN_GROUP(ssi5_ctrl),
1845         SH_PFC_PIN_GROUP(ssi5_data),
1846         SH_PFC_PIN_GROUP(ssi6_ctrl),
1847         SH_PFC_PIN_GROUP(ssi6_data),
1848         SH_PFC_PIN_GROUP(ssi78_ctrl),
1849         SH_PFC_PIN_GROUP(ssi7_data),
1850         SH_PFC_PIN_GROUP(ssi8_data),
1851         SH_PFC_PIN_GROUP(usb0),
1852         SH_PFC_PIN_GROUP(usb0_ovc),
1853         SH_PFC_PIN_GROUP(usb1),
1854         SH_PFC_PIN_GROUP(usb1_ovc),
1855         SH_PFC_PIN_GROUP(vin0_data8),
1856         SH_PFC_PIN_GROUP(vin0_clk),
1857         SH_PFC_PIN_GROUP(vin0_sync),
1858         SH_PFC_PIN_GROUP(vin1_data8),
1859         SH_PFC_PIN_GROUP(vin1_clk),
1860         SH_PFC_PIN_GROUP(vin1_sync),
1861 };
1862
1863 static const char * const audio_clk_groups[] = {
1864         "audio_clk_a",
1865         "audio_clk_b",
1866         "audio_clk_c",
1867         "audio_clkout_a",
1868         "audio_clkout_b",
1869 };
1870
1871 static const char * const can0_groups[] = {
1872         "can0_data_a",
1873         "can0_data_b",
1874         "can_clk_a",
1875         "can_clk_b",
1876         "can_clk_c",
1877         "can_clk_d",
1878 };
1879
1880 static const char * const can1_groups[] = {
1881         "can1_data_a",
1882         "can1_data_b",
1883         "can_clk_a",
1884         "can_clk_b",
1885         "can_clk_c",
1886         "can_clk_d",
1887 };
1888
1889 static const char * const ether_groups[] = {
1890         "ether_rmii",
1891         "ether_link",
1892         "ether_magic",
1893 };
1894
1895 static const char * const hscif0_groups[] = {
1896         "hscif0_data_a",
1897         "hscif0_data_b",
1898         "hscif0_ctrl_a",
1899         "hscif0_ctrl_b",
1900         "hscif0_clk",
1901 };
1902
1903 static const char * const hscif1_groups[] = {
1904         "hscif1_data_a",
1905         "hscif1_data_b",
1906         "hscif1_ctrl_a",
1907         "hscif1_ctrl_b",
1908         "hscif1_clk_a",
1909         "hscif1_clk_b",
1910 };
1911
1912 static const char * const hspi0_groups[] = {
1913         "hspi0_a",
1914         "hspi0_b",
1915 };
1916
1917 static const char * const hspi1_groups[] = {
1918         "hspi1_a",
1919         "hspi1_b",
1920 };
1921
1922 static const char * const hspi2_groups[] = {
1923         "hspi2_a",
1924         "hspi2_b",
1925 };
1926
1927 static const char * const i2c1_groups[] = {
1928         "i2c1_a",
1929         "i2c1_b",
1930 };
1931
1932 static const char * const i2c2_groups[] = {
1933         "i2c2_a",
1934         "i2c2_b",
1935         "i2c2_c",
1936 };
1937
1938 static const char * const i2c3_groups[] = {
1939         "i2c3_a",
1940         "i2c3_b",
1941         "i2c3_c",
1942 };
1943
1944 static const char * const mmc_groups[] = {
1945         "mmc_ctrl",
1946         "mmc_data1",
1947         "mmc_data4",
1948         "mmc_data8",
1949 };
1950
1951 static const char * const scif_clk_groups[] = {
1952         "scif_clk",
1953 };
1954
1955 static const char * const scif0_groups[] = {
1956         "scif0_data_a",
1957         "scif0_data_b",
1958         "scif0_data_c",
1959         "scif0_data_d",
1960         "scif0_ctrl",
1961         "scif0_clk",
1962 };
1963
1964 static const char * const scif1_groups[] = {
1965         "scif1_data_a",
1966         "scif1_data_b",
1967         "scif1_data_c",
1968         "scif1_data_d",
1969         "scif1_ctrl_a",
1970         "scif1_ctrl_c",
1971         "scif1_clk_a",
1972         "scif1_clk_c",
1973 };
1974
1975 static const char * const scif2_groups[] = {
1976         "scif2_data_a",
1977         "scif2_data_b",
1978         "scif2_data_c",
1979         "scif2_data_d",
1980         "scif2_data_e",
1981         "scif2_clk_a",
1982         "scif2_clk_b",
1983         "scif2_clk_c",
1984 };
1985
1986 static const char * const scif3_groups[] = {
1987         "scif3_data_a",
1988         "scif3_data_b",
1989         "scif3_data_c",
1990         "scif3_data_d",
1991 };
1992
1993 static const char * const scif4_groups[] = {
1994         "scif4_data_a",
1995         "scif4_data_b",
1996         "scif4_data_c",
1997 };
1998
1999 static const char * const scif5_groups[] = {
2000         "scif5_data_a",
2001         "scif5_data_b",
2002 };
2003
2004
2005 static const char * const sdhi0_groups[] = {
2006         "sdhi0_cd",
2007         "sdhi0_ctrl",
2008         "sdhi0_data1",
2009         "sdhi0_data4",
2010         "sdhi0_wp",
2011 };
2012
2013 static const char * const sdhi1_groups[] = {
2014         "sdhi1_cd_a",
2015         "sdhi1_cd_b",
2016         "sdhi1_ctrl_a",
2017         "sdhi1_ctrl_b",
2018         "sdhi1_data1_a",
2019         "sdhi1_data1_b",
2020         "sdhi1_data4_a",
2021         "sdhi1_data4_b",
2022         "sdhi1_wp_a",
2023         "sdhi1_wp_b",
2024 };
2025
2026 static const char * const sdhi2_groups[] = {
2027         "sdhi2_cd_a",
2028         "sdhi2_cd_b",
2029         "sdhi2_ctrl_a",
2030         "sdhi2_ctrl_b",
2031         "sdhi2_data1_a",
2032         "sdhi2_data1_b",
2033         "sdhi2_data4_a",
2034         "sdhi2_data4_b",
2035         "sdhi2_wp_a",
2036         "sdhi2_wp_b",
2037 };
2038
2039 static const char * const ssi_groups[] = {
2040         "ssi012_ctrl",
2041         "ssi0_data",
2042         "ssi1_a_ctrl",
2043         "ssi1_b_ctrl",
2044         "ssi1_data",
2045         "ssi2_a_ctrl",
2046         "ssi2_b_ctrl",
2047         "ssi2_data",
2048         "ssi34_ctrl",
2049         "ssi3_data",
2050         "ssi4_ctrl",
2051         "ssi4_data",
2052         "ssi5_ctrl",
2053         "ssi5_data",
2054         "ssi6_ctrl",
2055         "ssi6_data",
2056         "ssi78_ctrl",
2057         "ssi7_data",
2058         "ssi8_data",
2059 };
2060
2061 static const char * const usb0_groups[] = {
2062         "usb0",
2063         "usb0_ovc",
2064 };
2065
2066 static const char * const usb1_groups[] = {
2067         "usb1",
2068         "usb1_ovc",
2069 };
2070
2071 static const char * const vin0_groups[] = {
2072         "vin0_data8",
2073         "vin0_clk",
2074         "vin0_sync",
2075 };
2076
2077 static const char * const vin1_groups[] = {
2078         "vin1_data8",
2079         "vin1_clk",
2080         "vin1_sync",
2081 };
2082
2083 static const struct sh_pfc_function pinmux_functions[] = {
2084         SH_PFC_FUNCTION(audio_clk),
2085         SH_PFC_FUNCTION(can0),
2086         SH_PFC_FUNCTION(can1),
2087         SH_PFC_FUNCTION(ether),
2088         SH_PFC_FUNCTION(hscif0),
2089         SH_PFC_FUNCTION(hscif1),
2090         SH_PFC_FUNCTION(hspi0),
2091         SH_PFC_FUNCTION(hspi1),
2092         SH_PFC_FUNCTION(hspi2),
2093         SH_PFC_FUNCTION(i2c1),
2094         SH_PFC_FUNCTION(i2c2),
2095         SH_PFC_FUNCTION(i2c3),
2096         SH_PFC_FUNCTION(mmc),
2097         SH_PFC_FUNCTION(scif_clk),
2098         SH_PFC_FUNCTION(scif0),
2099         SH_PFC_FUNCTION(scif1),
2100         SH_PFC_FUNCTION(scif2),
2101         SH_PFC_FUNCTION(scif3),
2102         SH_PFC_FUNCTION(scif4),
2103         SH_PFC_FUNCTION(scif5),
2104         SH_PFC_FUNCTION(sdhi0),
2105         SH_PFC_FUNCTION(sdhi1),
2106         SH_PFC_FUNCTION(sdhi2),
2107         SH_PFC_FUNCTION(ssi),
2108         SH_PFC_FUNCTION(usb0),
2109         SH_PFC_FUNCTION(usb1),
2110         SH_PFC_FUNCTION(vin0),
2111         SH_PFC_FUNCTION(vin1),
2112 };
2113
2114 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2115         { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
2116                 GP_0_31_FN,     FN_IP1_14_11,
2117                 GP_0_30_FN,     FN_IP1_10_8,
2118                 GP_0_29_FN,     FN_IP1_7_5,
2119                 GP_0_28_FN,     FN_IP1_4_2,
2120                 GP_0_27_FN,     FN_IP1_1,
2121                 GP_0_26_FN,     FN_IP1_0,
2122                 GP_0_25_FN,     FN_IP0_30,
2123                 GP_0_24_FN,     FN_IP0_29,
2124                 GP_0_23_FN,     FN_IP0_28,
2125                 GP_0_22_FN,     FN_IP0_27,
2126                 GP_0_21_FN,     FN_IP0_26,
2127                 GP_0_20_FN,     FN_IP0_25,
2128                 GP_0_19_FN,     FN_IP0_24,
2129                 GP_0_18_FN,     FN_IP0_23,
2130                 GP_0_17_FN,     FN_IP0_22,
2131                 GP_0_16_FN,     FN_IP0_21,
2132                 GP_0_15_FN,     FN_IP0_20,
2133                 GP_0_14_FN,     FN_IP0_19,
2134                 GP_0_13_FN,     FN_IP0_18,
2135                 GP_0_12_FN,     FN_IP0_17,
2136                 GP_0_11_FN,     FN_IP0_16,
2137                 GP_0_10_FN,     FN_IP0_15,
2138                 GP_0_9_FN,      FN_A3,
2139                 GP_0_8_FN,      FN_A2,
2140                 GP_0_7_FN,      FN_A1,
2141                 GP_0_6_FN,      FN_IP0_14_12,
2142                 GP_0_5_FN,      FN_IP0_11_8,
2143                 GP_0_4_FN,      FN_IP0_7_5,
2144                 GP_0_3_FN,      FN_IP0_4_2,
2145                 GP_0_2_FN,      FN_PENC1,
2146                 GP_0_1_FN,      FN_PENC0,
2147                 GP_0_0_FN,      FN_IP0_1_0 }
2148         },
2149         { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
2150                 GP_1_31_FN,     FN_IP4_6_4,
2151                 GP_1_30_FN,     FN_IP4_3_1,
2152                 GP_1_29_FN,     FN_IP4_0,
2153                 GP_1_28_FN,     FN_IP3_31,
2154                 GP_1_27_FN,     FN_IP3_30,
2155                 GP_1_26_FN,     FN_IP3_29,
2156                 GP_1_25_FN,     FN_IP3_28,
2157                 GP_1_24_FN,     FN_IP3_27,
2158                 GP_1_23_FN,     FN_IP3_26_24,
2159                 GP_1_22_FN,     FN_IP3_23_21,
2160                 GP_1_21_FN,     FN_IP3_20_19,
2161                 GP_1_20_FN,     FN_IP3_18_16,
2162                 GP_1_19_FN,     FN_IP3_15_13,
2163                 GP_1_18_FN,     FN_IP3_12_10,
2164                 GP_1_17_FN,     FN_IP3_9_8,
2165                 GP_1_16_FN,     FN_IP3_7_5,
2166                 GP_1_15_FN,     FN_IP3_4_2,
2167                 GP_1_14_FN,     FN_IP3_1_0,
2168                 GP_1_13_FN,     FN_IP2_31,
2169                 GP_1_12_FN,     FN_IP2_30,
2170                 GP_1_11_FN,     FN_IP2_17,
2171                 GP_1_10_FN,     FN_IP2_16_14,
2172                 GP_1_9_FN,      FN_IP2_13_12,
2173                 GP_1_8_FN,      FN_IP2_11_9,
2174                 GP_1_7_FN,      FN_IP2_8_6,
2175                 GP_1_6_FN,      FN_IP2_5_3,
2176                 GP_1_5_FN,      FN_IP2_2_0,
2177                 GP_1_4_FN,      FN_IP1_29_28,
2178                 GP_1_3_FN,      FN_IP1_27_25,
2179                 GP_1_2_FN,      FN_IP1_24,
2180                 GP_1_1_FN,      FN_WE0,
2181                 GP_1_0_FN,      FN_IP1_23_21 }
2182         },
2183         { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
2184                 GP_2_31_FN,     FN_IP6_7,
2185                 GP_2_30_FN,     FN_IP6_6_5,
2186                 GP_2_29_FN,     FN_IP6_4_2,
2187                 GP_2_28_FN,     FN_IP6_1_0,
2188                 GP_2_27_FN,     FN_IP5_30_29,
2189                 GP_2_26_FN,     FN_IP5_28_26,
2190                 GP_2_25_FN,     FN_IP5_25_23,
2191                 GP_2_24_FN,     FN_IP5_22_21,
2192                 GP_2_23_FN,     FN_AUDIO_CLKB,
2193                 GP_2_22_FN,     FN_AUDIO_CLKA,
2194                 GP_2_21_FN,     FN_IP5_20_18,
2195                 GP_2_20_FN,     FN_IP5_17_15,
2196                 GP_2_19_FN,     FN_IP5_14_13,
2197                 GP_2_18_FN,     FN_IP5_12,
2198                 GP_2_17_FN,     FN_IP5_11_10,
2199                 GP_2_16_FN,     FN_IP5_9_8,
2200                 GP_2_15_FN,     FN_IP5_7,
2201                 GP_2_14_FN,     FN_IP5_6,
2202                 GP_2_13_FN,     FN_IP5_5_4,
2203                 GP_2_12_FN,     FN_IP5_3_2,
2204                 GP_2_11_FN,     FN_IP5_1_0,
2205                 GP_2_10_FN,     FN_IP4_30_29,
2206                 GP_2_9_FN,      FN_IP4_28_27,
2207                 GP_2_8_FN,      FN_IP4_26_25,
2208                 GP_2_7_FN,      FN_IP4_24_21,
2209                 GP_2_6_FN,      FN_IP4_20_17,
2210                 GP_2_5_FN,      FN_IP4_16_15,
2211                 GP_2_4_FN,      FN_IP4_14_13,
2212                 GP_2_3_FN,      FN_IP4_12_11,
2213                 GP_2_2_FN,      FN_IP4_10_9,
2214                 GP_2_1_FN,      FN_IP4_8,
2215                 GP_2_0_FN,      FN_IP4_7 }
2216         },
2217         { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
2218                 GP_3_31_FN,     FN_IP8_10_9,
2219                 GP_3_30_FN,     FN_IP8_8_6,
2220                 GP_3_29_FN,     FN_IP8_5_3,
2221                 GP_3_28_FN,     FN_IP8_2_0,
2222                 GP_3_27_FN,     FN_IP7_31_29,
2223                 GP_3_26_FN,     FN_IP7_28_25,
2224                 GP_3_25_FN,     FN_IP7_24_22,
2225                 GP_3_24_FN,     FN_IP7_21,
2226                 GP_3_23_FN,     FN_IP7_20_18,
2227                 GP_3_22_FN,     FN_IP7_17_15,
2228                 GP_3_21_FN,     FN_IP7_14_12,
2229                 GP_3_20_FN,     FN_IP7_11_9,
2230                 GP_3_19_FN,     FN_IP7_8_6,
2231                 GP_3_18_FN,     FN_IP7_5_4,
2232                 GP_3_17_FN,     FN_IP7_3_2,
2233                 GP_3_16_FN,     FN_IP7_1_0,
2234                 GP_3_15_FN,     FN_IP6_31_30,
2235                 GP_3_14_FN,     FN_IP6_29_28,
2236                 GP_3_13_FN,     FN_IP6_27_26,
2237                 GP_3_12_FN,     FN_IP6_25_24,
2238                 GP_3_11_FN,     FN_IP6_23_22,
2239                 GP_3_10_FN,     FN_IP6_21,
2240                 GP_3_9_FN,      FN_IP6_20_19,
2241                 GP_3_8_FN,      FN_IP6_18_17,
2242                 GP_3_7_FN,      FN_IP6_16,
2243                 GP_3_6_FN,      FN_IP6_15_14,
2244                 GP_3_5_FN,      FN_IP6_13,
2245                 GP_3_4_FN,      FN_IP6_12_11,
2246                 GP_3_3_FN,      FN_IP6_10,
2247                 GP_3_2_FN,      FN_SSI_SCK34,
2248                 GP_3_1_FN,      FN_IP6_9,
2249                 GP_3_0_FN,      FN_IP6_8 }
2250         },
2251         { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
2252                 0, 0,
2253                 0, 0,
2254                 0, 0,
2255                 0, 0,
2256                 0, 0,
2257                 GP_4_26_FN,     FN_AVS2,
2258                 GP_4_25_FN,     FN_AVS1,
2259                 GP_4_24_FN,     FN_IP10_24_22,
2260                 GP_4_23_FN,     FN_IP10_21_19,
2261                 GP_4_22_FN,     FN_IP10_18_16,
2262                 GP_4_21_FN,     FN_IP10_15_13,
2263                 GP_4_20_FN,     FN_IP10_12_9,
2264                 GP_4_19_FN,     FN_IP10_8_6,
2265                 GP_4_18_FN,     FN_IP10_5_3,
2266                 GP_4_17_FN,     FN_IP10_2_0,
2267                 GP_4_16_FN,     FN_IP9_29_27,
2268                 GP_4_15_FN,     FN_IP9_26_24,
2269                 GP_4_14_FN,     FN_IP9_23_21,
2270                 GP_4_13_FN,     FN_IP9_20_18,
2271                 GP_4_12_FN,     FN_IP9_17_15,
2272                 GP_4_11_FN,     FN_IP9_14_12,
2273                 GP_4_10_FN,     FN_IP9_11_9,
2274                 GP_4_9_FN,      FN_IP9_8_6,
2275                 GP_4_8_FN,      FN_IP9_5_3,
2276                 GP_4_7_FN,      FN_IP9_2_0,
2277                 GP_4_6_FN,      FN_IP8_29_27,
2278                 GP_4_5_FN,      FN_IP8_26_24,
2279                 GP_4_4_FN,      FN_IP8_23_22,
2280                 GP_4_3_FN,      FN_IP8_21_19,
2281                 GP_4_2_FN,      FN_IP8_18_16,
2282                 GP_4_1_FN,      FN_IP8_15_14,
2283                 GP_4_0_FN,      FN_IP8_13_11 }
2284         },
2285
2286         { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2287                              1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2288                              1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) {
2289                 /* IP0_31 [1] */
2290                 0,      0,
2291                 /* IP0_30 [1] */
2292                 FN_A19, 0,
2293                 /* IP0_29 [1] */
2294                 FN_A18, 0,
2295                 /* IP0_28 [1] */
2296                 FN_A17, 0,
2297                 /* IP0_27 [1] */
2298                 FN_A16, 0,
2299                 /* IP0_26 [1] */
2300                 FN_A15, 0,
2301                 /* IP0_25 [1] */
2302                 FN_A14, 0,
2303                 /* IP0_24 [1] */
2304                 FN_A13, 0,
2305                 /* IP0_23 [1] */
2306                 FN_A12, 0,
2307                 /* IP0_22 [1] */
2308                 FN_A11, 0,
2309                 /* IP0_21 [1] */
2310                 FN_A10, 0,
2311                 /* IP0_20 [1] */
2312                 FN_A9,  0,
2313                 /* IP0_19 [1] */
2314                 FN_A8,  0,
2315                 /* IP0_18 [1] */
2316                 FN_A7,  0,
2317                 /* IP0_17 [1] */
2318                 FN_A6,  0,
2319                 /* IP0_16 [1] */
2320                 FN_A5,  0,
2321                 /* IP0_15 [1] */
2322                 FN_A4,  0,
2323                 /* IP0_14_12 [3] */
2324                 FN_SD1_DAT3_A,  FN_MMC_D3,      0,              FN_A0,
2325                 FN_ATAG0_A,     0,              FN_REMOCON_B,   0,
2326                 /* IP0_11_8 [4] */
2327                 FN_SD1_DAT2_A,  FN_MMC_D2,      0,              FN_BS,
2328                 FN_ATADIR0_A,   0,              FN_SDSELF_A,    0,
2329                 FN_PWM4_B,      0,              0,              0,
2330                 0,              0,              0,              0,
2331                 /* IP0_7_5 [3] */
2332                 FN_AUDATA1,     FN_ARM_TRACEDATA_1,     FN_GPSIN_C,     FN_USB_OVC1,
2333                 FN_RX2_E,       FN_SCL2_B,              0,              0,
2334                 /* IP0_4_2 [3] */
2335                 FN_AUDATA0,     FN_ARM_TRACEDATA_0,     FN_GPSCLK_C,    FN_USB_OVC0,
2336                 FN_TX2_E,       FN_SDA2_B,              0,              0,
2337                 /* IP0_1_0 [2] */
2338                 FN_PRESETOUT,   0,      FN_PWM1,        0,
2339                 }
2340         },
2341         { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
2342                              1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) {
2343                 /* IP1_31 [1] */
2344                 0,      0,
2345                 /* IP1_30 [1] */
2346                 0,      0,
2347                 /* IP1_29_28 [2] */
2348                 FN_EX_CS1,      FN_MMC_D4,      0,      0,
2349                 /* IP1_27_25 [3] */
2350                 FN_SSI_WS1_B,   FN_EX_CS0,      FN_SCL2_A,      FN_TX3_C,
2351                 FN_TS_SCK0_A,   0,              0,              0,
2352                 /* IP1_24 [1] */
2353                 FN_WE1,         FN_ATAWR0_B,
2354                 /* IP1_23_21 [3] */
2355                 FN_MMC_D5,      FN_ATADIR0_B,   0,              FN_RD_WR,
2356                 0,              0,              0,              0,
2357                 /* IP1_20_18 [3] */
2358                 FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
2359                 FN_SCK2_B,      0,              0,              0,
2360                 /* IP1_17 [1] */
2361                 FN_CS0,         FN_HSPI_RX1_B,
2362                 /* IP1_16_15 [2] */
2363                 FN_CLKOUT,      FN_HSPI_TX1_B,  FN_PWM0_B,      0,
2364                 /* IP1_14_11 [4] */
2365                 FN_SD1_WP_A,    FN_MMC_D7,      0,              FN_A25,
2366                 FN_DACK1_A,     0,              FN_HCTS0_B,     FN_RX3_C,
2367                 FN_TS_SDAT0_A,  0,              0,              0,
2368                 0,              0,              0,              0,
2369                 /* IP1_10_8 [3] */
2370                 FN_SD1_CD_A,    FN_MMC_D6,      0,              FN_A24,
2371                 FN_DREQ1_A,     0,              FN_HRX0_B,      FN_TS_SPSYNC0_A,
2372                 /* IP1_7_5 [3] */
2373                 FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
2374                 FN_TS_SDEN0_A,  0,              0,              0,
2375                 /* IP1_4_2 [3] */
2376                 FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
2377                 0,              0,              0,              0,
2378                 /* IP1_1 [1] */
2379                 FN_A21,         FN_HSPI_CLK1_B,
2380                 /* IP1_0 [1] */
2381                 FN_A20,         FN_HSPI_CS1_B,
2382                 }
2383         },
2384         { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2385                              1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2386                              1, 1, 1, 1, 3, 2, 3, 3, 3, 3) {
2387                 /* IP2_31 [1] */
2388                 FN_MLB_CLK,     FN_IRQ1_A,
2389                 /* IP2_30 [1] */
2390                 FN_RD_WR_B,     FN_IRQ0,
2391                 /* IP2_29 [1] */
2392                 FN_D11,         0,
2393                 /* IP2_28 [1] */
2394                 FN_D10,         0,
2395                 /* IP2_27 [1] */
2396                 FN_D9,          0,
2397                 /* IP2_26 [1] */
2398                 FN_D8,          0,
2399                 /* IP2_25 [1] */
2400                 FN_D7,          0,
2401                 /* IP2_24 [1] */
2402                 FN_D6,          0,
2403                 /* IP2_23 [1] */
2404                 FN_D5,          0,
2405                 /* IP2_22 [1] */
2406                 FN_D4,          0,
2407                 /* IP2_21 [1] */
2408                 FN_D3,          0,
2409                 /* IP2_20 [1] */
2410                 FN_D2,          0,
2411                 /* IP2_19 [1] */
2412                 FN_D1,          0,
2413                 /* IP2_18 [1] */
2414                 FN_D0,          0,
2415                 /* IP2_17 [1] */
2416                 FN_EX_WAIT0,    FN_PWM0_C,
2417                 /* IP2_16_14 [3] */
2418                 FN_DACK0,       0,      0,      FN_TX3_A,
2419                 FN_DRACK0,      0,      0,      0,
2420                 /* IP2_13_12 [2] */
2421                 FN_DREQ0_A,     0,      0,      FN_RX3_A,
2422                 /* IP2_11_9 [3] */
2423                 FN_SD1_DAT1_A,  FN_MMC_D1,      0,      FN_ATAWR0_A,
2424                 FN_EX_CS5,      FN_EX_WAIT2_A,  0,      0,
2425                 /* IP2_8_6 [3] */
2426                 FN_SD1_DAT0_A,  FN_MMC_D0,      0,      FN_ATARD0,
2427                 FN_EX_CS4,      FN_EX_WAIT1_A,  0,      0,
2428                 /* IP2_5_3 [3] */
2429                 FN_SD1_CMD_A,   FN_MMC_CMD,     0,      FN_ATACS10,
2430                 FN_EX_CS3,      0,              0,      0,
2431                 /* IP2_2_0 [3] */
2432                 FN_SD1_CLK_A,   FN_MMC_CLK,     0,      FN_ATACS00,
2433                 FN_EX_CS2,      0,              0,      0,
2434                 }
2435         },
2436         { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2437                              1, 1, 1, 1, 1, 3, 3, 2,
2438                              3, 3, 3, 2, 3, 3, 2) {
2439                 /* IP3_31 [1] */
2440                 FN_DU0_DR6,     FN_LCDOUT6,
2441                 /* IP3_30 [1] */
2442                 FN_DU0_DR5,     FN_LCDOUT5,
2443                 /* IP3_29 [1] */
2444                 FN_DU0_DR4,     FN_LCDOUT4,
2445                 /* IP3_28 [1] */
2446                 FN_DU0_DR3,     FN_LCDOUT3,
2447                 /* IP3_27 [1] */
2448                 FN_DU0_DR2,     FN_LCDOUT2,
2449                 /* IP3_26_24 [3] */
2450                 FN_SSI_WS4,             FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,
2451                 FN_ARM_TRACEDATA_3,     FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
2452                 /* IP3_23_21 [3] */
2453                 FN_SSI_SCK4,            FN_DU0_DR0,     FN_LCDOUT0,     FN_AUDATA2,
2454                 FN_ARM_TRACEDATA_2,     FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,
2455                 /* IP3_20_19 [2] */
2456                 FN_SD1_DAT3_B,  FN_HRTS0_A,     FN_RTS0,        0,
2457                 /* IP3_18_16 [3] */
2458                 FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        0,
2459                 0,              0,              0,              0,
2460                 /* IP3_15_13 [3] */
2461                 FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
2462                 0,              0,              0,              0,
2463                 /* IP3_12_10 [3] */
2464                 FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,       0,
2465                 0,              0,              0,              0,
2466                 /* IP3_9_8 [2] */
2467                 FN_SD1_CLK_B,   FN_HTX0_A,      FN_TX0_A,       0,
2468                 /* IP3_7_5 [3] */
2469                 FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,      FN_CAN_CLK_B,
2470                 FN_SDA3_B,      0,              0,                      0,
2471                 /* IP3_4_2 [3] */
2472                 FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
2473                 FN_SDSELF_B,    0,              0,              0,
2474                 /* IP3_1_0 [2] */
2475                 FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
2476                 }
2477         },
2478         { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2479                              1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) {
2480                 /* IP4_31 [1] */
2481                 0,      0,
2482                 /* IP4_30_29 [2] */
2483                 FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,    0,
2484                 /* IP4_28_27 [2] */
2485                 FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,    0,
2486                 /* IP4_26_25 [2] */
2487                 FN_VI0_R2_B,    FN_DU0_DB2,     FN_LCDOUT18,    0,
2488                 /* IP4_24_21 [4] */
2489                 FN_AUDIO_CLKC,  FN_VI0_R1_B,            FN_DU0_DB1,     FN_LCDOUT17,
2490                 FN_AUDATA7,     FN_ARM_TRACEDATA_7,     FN_GPSIN_A,     0,
2491                 FN_ADICS_SAMP,  FN_TS_SCK0_B,           0,              0,
2492                 0,              0,                      0,              0,
2493                 /* IP4_20_17 [4] */
2494                 FN_SSI_SCK2_B,  FN_VI0_R0_B,            FN_DU0_DB0,     FN_LCDOUT16,
2495                 FN_AUDATA6,     FN_ARM_TRACEDATA_6,     FN_GPSCLK_A,    FN_PWM0_A,
2496                 FN_ADICLK,      FN_TS_SDAT0_B,          0,              0,
2497                 0,              0,                      0,              0,
2498                 /* IP4_16_15 [2] */
2499                 FN_DU0_DG7,     FN_LCDOUT15,    FN_TX4_A,       0,
2500                 /* IP4_14_13 [2] */
2501                 FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       0,
2502                 /* IP4_12_11 [2] */
2503                 FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,       0,
2504                 /* IP4_10_9 [2] */
2505                 FN_DU0_DG4,     FN_LCDOUT12,    FN_RX0_B,       0,
2506                 /* IP4_8 [1] */
2507                 FN_DU0_DG3,     FN_LCDOUT11,
2508                 /* IP4_7 [1] */
2509                 FN_DU0_DG2,     FN_LCDOUT10,
2510                 /* IP4_6_4 [3] */
2511                 FN_DU0_DG1,     FN_LCDOUT9,     FN_AUDATA5,     FN_ARM_TRACEDATA_5,
2512                 FN_RX1_D,       FN_CAN0_RX_A,   FN_ADIDATA,     0,
2513                 /* IP4_3_1 [3] */
2514                 FN_DU0_DG0,     FN_LCDOUT8,     FN_AUDATA4,     FN_ARM_TRACEDATA_4,
2515                 FN_TX1_D,       FN_CAN0_TX_A,   FN_ADICHS0,     0,
2516                 /* IP4_0 [1] */
2517                 FN_DU0_DR7,     FN_LCDOUT7,
2518                 }
2519         },
2520         { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2521                              1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) {
2522
2523                 /* IP5_31 [1] */
2524                 0, 0,
2525                 /* IP5_30_29 [2] */
2526                 FN_SSI_SDATA7,  FN_HSPI_TX0_B,  FN_RX2_A,       FN_CAN0_RX_B,
2527                 /* IP5_28_26 [3] */
2528                 FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,  FN_TX2_A,
2529                 FN_CAN0_TX_B,   0,              0,              0,
2530                 /* IP5_25_23 [3] */
2531                 FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
2532                 FN_CAN_CLK_D,   0,              0,              0,
2533                 /* IP5_22_21 [2] */
2534                 FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
2535                 /* IP5_20_18 [3] */
2536                 FN_SSI_WS1_A,           FN_DU0_CDE,     FN_QPOLB,       FN_AUDSYNC,
2537                 FN_ARM_TRACECTL,        FN_FMIN_D,      0,              0,
2538                 /* IP5_17_15 [3] */
2539                 FN_SSI_SCK1_A,          FN_DU0_DISP,    FN_QPOLA,       FN_AUDCK,
2540                 FN_ARM_TRACECLK,        FN_BPFCLK_D,    0,              0,
2541                 /* IP5_14_13 [2] */
2542                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,        FN_QCPV_QDE,
2543                 FN_FMCLK_D,                             0,
2544                 /* IP5_12 [1] */
2545                 FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
2546                 /* IP5_11_10 [2] */
2547                 FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
2548                 FN_QSTH_QHS,    0,
2549                 /* IP5_9_8 [2] */
2550                 FN_DU0_DOTCLKO_UT1,     FN_QSTVB_QVE,
2551                 FN_AUDIO_CLKOUT_A,      FN_REMOCON_C,
2552                 /* IP5_7 [1] */
2553                 FN_DU0_DOTCLKO_UT0,     FN_QCLK,
2554                 /* IP5_6 [1] */
2555                 FN_DU0_DOTCLKIN,        FN_QSTVA_QVS,
2556                 /* IP5_5_4 [2] */
2557                 FN_VI1_DATA11_B,        FN_DU0_DB7,     FN_LCDOUT23,    0,
2558                 /* IP5_3_2 [2] */
2559                 FN_VI1_DATA10_B,        FN_DU0_DB6,     FN_LCDOUT22,    0,
2560                 /* IP5_1_0 [2] */
2561                 FN_VI0_R5_B,            FN_DU0_DB5,     FN_LCDOUT21,    0,
2562                 }
2563         },
2564         { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2565                              2, 2, 2, 2, 2, 1, 2, 2, 1, 2,
2566                              1, 2, 1, 1, 1, 1, 2, 3, 2) {
2567                 /* IP6_31_30 [2] */
2568                 FN_SD0_DAT2,    0,      FN_SUB_TDI,     0,
2569                 /* IP6_29_28 [2] */
2570                 FN_SD0_DAT1,    0,      FN_SUB_TCK,     0,
2571                 /* IP6_27_26 [2] */
2572                 FN_SD0_DAT0,    0,      FN_SUB_TMS,     0,
2573                 /* IP6_25_24 [2] */
2574                 FN_SD0_CMD,     0,      FN_SUB_TRST,    0,
2575                 /* IP6_23_22 [2] */
2576                 FN_SD0_CLK,     0,      FN_SUB_TDO,     0,
2577                 /* IP6_21 [1] */
2578                 FN_SSI_SDATA0,          FN_ARM_TRACEDATA_15,
2579                 /* IP6_20_19 [2] */
2580                 FN_SSI_SDATA1,          FN_ARM_TRACEDATA_14,
2581                 FN_SCL1_A,              FN_SCK2_A,
2582                 /* IP6_18_17 [2] */
2583                 FN_SSI_SDATA2,          FN_HSPI_CS2_A,
2584                 FN_ARM_TRACEDATA_13,    FN_SDA1_A,
2585                 /* IP6_16 [1] */
2586                 FN_SSI_WS012,           FN_ARM_TRACEDATA_12,
2587                 /* IP6_15_14 [2] */
2588                 FN_SSI_SCK012,          FN_ARM_TRACEDATA_11,
2589                 FN_TX0_D,               0,
2590                 /* IP6_13 [1] */
2591                 FN_SSI_SDATA3,          FN_ARM_TRACEDATA_10,
2592                 /* IP6_12_11 [2] */
2593                 FN_SSI_SDATA4,          FN_SSI_WS2_A,
2594                 FN_ARM_TRACEDATA_9,     0,
2595                 /* IP6_10 [1] */
2596                 FN_SSI_WS34,            FN_ARM_TRACEDATA_8,
2597                 /* IP6_9 [1] */
2598                 FN_SSI_SDATA5,          FN_RX0_D,
2599                 /* IP6_8 [1] */
2600                 FN_SSI_WS5,             FN_TX4_C,
2601                 /* IP6_7 [1] */
2602                 FN_SSI_SCK5,            FN_RX4_C,
2603                 /* IP6_6_5 [2] */
2604                 FN_SSI_SDATA6,          FN_HSPI_TX2_A,
2605                 FN_FMIN_B,              0,
2606                 /* IP6_4_2 [3] */
2607                 FN_SSI_WS6,             FN_HSPI_CLK2_A,
2608                 FN_BPFCLK_B,            FN_CAN1_RX_B,
2609                 0,      0,      0,      0,
2610                 /* IP6_1_0 [2] */
2611                 FN_SSI_SCK6,            FN_HSPI_RX2_A,
2612                 FN_FMCLK_B,             FN_CAN1_TX_B,
2613                 }
2614         },
2615         { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2616                              3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) {
2617
2618                 /* IP7_31_29 [3] */
2619                 FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,   FN_DU1_DR2,
2620                 0,              FN_HSPI_CS1_A,  FN_RX3_B,       0,
2621                 /* IP7_28_25 [4] */
2622                 FN_VI0_FIELD,   FN_SD2_DAT3_B,  FN_VI0_R3_C,    FN_VI1_DATA1,
2623                 FN_DU1_DG7,     0,              FN_HSPI_CLK1_A, FN_TX4_B,
2624                 0,      0,      0,      0,
2625                 0,      0,      0,      0,
2626                 /* IP7_24_22 [3] */
2627                 FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
2628                 0,              FN_HSPI_RX1_A,  FN_RX4_B,       0,
2629                 /* IP7_21 [1] */
2630                 FN_VI0_CLK,     FN_CAN_CLK_A,
2631                 /* IP7_20_18 [3] */
2632                 FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      0,
2633                 FN_IRQ2_C,      FN_CTS1_C,      FN_SPEEDIN,     0,
2634                 /* IP7_17_15 [3] */
2635                 FN_VI1_VSYNC,   FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,
2636                 0,              FN_TX1_C,       0,              0,
2637                 /* IP7_14_12 [3] */
2638                 FN_VI1_HSYNC,   FN_HSPI_RX0_A,  FN_HRTS1_A,     FN_FMCLK_A,
2639                 0,              FN_RX1_C,       0,              0,
2640                 /* IP7_11_9 [3] */
2641                 FN_VI1_FIELD,   FN_HSPI_CS0_A,  FN_HRX1_A,      0,
2642                 FN_SCK1_C,      0,              0,              0,
2643                 /* IP7_8_6 [3] */
2644                 FN_VI1_CLKENB,  FN_HSPI_CLK0_A, FN_HTX1_A,      0,
2645                 FN_RTS1_C,      0,              0,              0,
2646                 /* IP7_5_4 [2] */
2647                 FN_SD0_WP,      0,              FN_RX5_A,       0,
2648                 /* IP7_3_2 [2] */
2649                 FN_SD0_CD,      0,              FN_TX5_A,       0,
2650                 /* IP7_1_0 [2] */
2651                 FN_SD0_DAT3,    0,              FN_IRQ1_B,      0,
2652                 }
2653         },
2654         { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2655                              1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) {
2656                 /* IP8_31 [1] */
2657                 0, 0,
2658                 /* IP8_30 [1] */
2659                 0, 0,
2660                 /* IP8_29_27 [3] */
2661                 FN_VI0_G3,      FN_SD2_CMD_B,   FN_VI1_DATA5,   FN_DU1_DR5,
2662                 0,              FN_HRX1_B,      0,              0,
2663                 /* IP8_26_24 [3] */
2664                 FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,   FN_DU1_DR4,
2665                 0,              FN_HTX1_B,      0,              0,
2666                 /* IP8_23_22 [2] */
2667                 FN_VI0_DATA7_VI0_G1,    FN_DU1_DB5,
2668                 FN_RTS1_A,              0,
2669                 /* IP8_21_19 [3] */
2670                 FN_VI0_DATA6_VI0_G0,    FN_DU1_DB4,
2671                 FN_CTS1_A,              FN_PWM5,
2672                 0,      0,      0,      0,
2673                 /* IP8_18_16 [3] */
2674                 FN_VI0_DATA5_VI0_B5,    FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,
2675                 0,                      FN_HSCK1_B,     0,              0,
2676                 /* IP8_15_14 [2] */
2677                 FN_VI0_DATA4_VI0_B4,    FN_DU1_DB2,     FN_RX1_A,       0,
2678                 /* IP8_13_11 [3] */
2679                 FN_VI0_DATA3_VI0_B3,    FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,
2680                 0,                       0,             0,              0,
2681                 /* IP8_10_9 [2] */
2682                 FN_VI0_DATA2_VI0_B2,    FN_DU1_DG4,     FN_RX0_C,       0,
2683                 /* IP8_8_6 [3] */
2684                 FN_VI0_DATA1_VI0_B1,    FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,
2685                 0,                       0,             0,              0,
2686                 /* IP8_5_3 [3] */
2687                 FN_VI0_DATA0_VI0_B0,    FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,
2688                 0,                       0,             0,              0,
2689                 /* IP8_2_0 [3] */
2690                 FN_VI0_VSYNC,           FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
2691                 0,                      FN_HSPI_TX1_A,  FN_TX3_B,       0,
2692                 }
2693         },
2694         { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
2695                              1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
2696                 /* IP9_31 [1] */
2697                 0, 0,
2698                 /* IP9_30 [1] */
2699                 0, 0,
2700                 /* IP9_29_27 [3] */
2701                 FN_VI1_DATA11_A,        FN_DU1_EXHSYNC_DU1_HSYNC,
2702                 FN_ETH_RXD1,            FN_FMIN_C,
2703                 0,                      FN_RX2_D,
2704                 FN_SCL2_C,              0,
2705                 /* IP9_26_24 [3] */
2706                 FN_VI1_DATA10_A,        FN_DU1_DOTCLKOUT,
2707                 FN_ETH_RXD0,            FN_BPFCLK_C,
2708                 0,                      FN_TX2_D,
2709                 FN_SDA2_C,              0,
2710                 /* IP9_23_21 [3] */
2711                 FN_VI0_R5_A,    0,              FN_ETH_RX_ER,   FN_FMCLK_C,
2712                 FN_IERX,        FN_RX2_C,       0,              0,
2713                 /* IP9_20_18 [3] */
2714                 FN_VI0_R4_A,    FN_ETH_TX_EN,   0,              0,
2715                 FN_IETX,        FN_TX2_C,       0,              0,
2716                 /* IP9_17_15 [3] */
2717                 FN_VI0_R3_A,    FN_ETH_CRS_DV,  0,              FN_IECLK,
2718                 FN_SCK2_C,      0,              0,              0,
2719                 /* IP9_14_12 [3] */
2720                 FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,     FN_ETH_TXD1,
2721                 0,              FN_PWM3,        0,              0,
2722                 /* IP9_11_9 [3] */
2723                 FN_VI0_R1_A,    FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,
2724                 0,              FN_PWM2,        FN_TCLK1,       0,
2725                 /* IP9_8_6 [3] */
2726                 FN_VI0_R0_A,    FN_VI1_CLK,     FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,
2727                 0,              0,              0,              0,
2728                 /* IP9_5_3 [3] */
2729                 FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,   FN_DU1_DR7,
2730                 0,              FN_HCTS1_B,     0,              0,
2731                 /* IP9_2_0 [3] */
2732                 FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
2733                 0,              FN_HRTS1_B,     0,              0,
2734                 }
2735         },
2736         { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
2737                              1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) {
2738
2739                 /* IP10_31 [1] */
2740                 0, 0,
2741                 /* IP10_30 [1] */
2742                 0, 0,
2743                 /* IP10_29 [1] */
2744                 0, 0,
2745                 /* IP10_28 [1] */
2746                 0, 0,
2747                 /* IP10_27 [1] */
2748                 0, 0,
2749                 /* IP10_26 [1] */
2750                 0, 0,
2751                 /* IP10_25 [1] */
2752                 0, 0,
2753                 /* IP10_24_22 [3] */
2754                 FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,  FN_DACK0_B,
2755                 FN_HSPI_TX2_B,  FN_CAN_CLK_C,   0,              0,
2756                 /* IP10_21_19 [3] */
2757                 FN_SD2_CD_A,    FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,
2758                 FN_HSPI_RX2_B,  FN_REMOCON_A,   0,              0,
2759                 /* IP10_18_16 [3] */
2760                 FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,     FN_ATAG1,
2761                 FN_HSPI_CS2_B,  FN_GPSIN_B,     0,              0,
2762                 /* IP10_15_13 [3] */
2763                 FN_SD2_DAT2_A,  FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,
2764                 FN_HSPI_CLK2_B, FN_GPSCLK_B,    0,              0,
2765                 /* IP10_12_9 [4] */
2766                 FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
2767                 FN_ETH_MAGIC,   FN_CAN1_TX_A,   0,              FN_PWM6,
2768                 0, 0, 0, 0,
2769                 0, 0, 0, 0,
2770                 /* IP10_8_6 [3] */
2771                 FN_SD2_DAT0_A,  FN_DU1_DISP,    FN_ATACS01,     FN_DREQ1_B,
2772                 FN_ETH_LINK,    FN_CAN1_RX_A,   0,              0,
2773                 /* IP10_5_3 [3] */
2774                 FN_SD2_CMD_A,   FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2775                 FN_ATAWR1,      FN_ETH_MDIO,
2776                 FN_SCL1_B,      0,
2777                 0,              0,
2778                 /* IP10_2_0 [3] */
2779                 FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,
2780                 FN_ATARD1,      FN_ETH_MDC,
2781                 FN_SDA1_B,      0,
2782                 0,              0,
2783                 }
2784         },
2785         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
2786                              1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
2787                              1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
2788
2789                 /* SEL 31  [1] */
2790                 0, 0,
2791                 /* SEL_30 (SCIF5) [1] */
2792                 FN_SEL_SCIF5_A,         FN_SEL_SCIF5_B,
2793                 /* SEL_29_28 (SCIF4) [2] */
2794                 FN_SEL_SCIF4_A,         FN_SEL_SCIF4_B,
2795                 FN_SEL_SCIF4_C,         0,
2796                 /* SEL_27_26 (SCIF3) [2] */
2797                 FN_SEL_SCIF3_A,         FN_SEL_SCIF3_B,
2798                 FN_SEL_SCIF3_C,         FN_SEL_SCIF3_D,
2799                 /* SEL_25_23 (SCIF2) [3] */
2800                 FN_SEL_SCIF2_A,         FN_SEL_SCIF2_B,
2801                 FN_SEL_SCIF2_C,         FN_SEL_SCIF2_D,
2802                 FN_SEL_SCIF2_E,         0,
2803                 0,                      0,
2804                 /* SEL_22_21 (SCIF1) [2] */
2805                 FN_SEL_SCIF1_A,         FN_SEL_SCIF1_B,
2806                 FN_SEL_SCIF1_C,         FN_SEL_SCIF1_D,
2807                 /* SEL_20_19 (SCIF0) [2] */
2808                 FN_SEL_SCIF0_A,         FN_SEL_SCIF0_B,
2809                 FN_SEL_SCIF0_C,         FN_SEL_SCIF0_D,
2810                 /* SEL_18 [1] */
2811                 0, 0,
2812                 /* SEL_17 (SSI2) [1] */
2813                 FN_SEL_SSI2_A,          FN_SEL_SSI2_B,
2814                 /* SEL_16 (SSI1) [1] */
2815                 FN_SEL_SSI1_A,          FN_SEL_SSI1_B,
2816                 /* SEL_15 (VI1) [1] */
2817                 FN_SEL_VI1_A,           FN_SEL_VI1_B,
2818                 /* SEL_14_13 (VI0) [2] */
2819                 FN_SEL_VI0_A,           FN_SEL_VI0_B,
2820                 FN_SEL_VI0_C,           FN_SEL_VI0_D,
2821                 /* SEL_12 [1] */
2822                 0, 0,
2823                 /* SEL_11 (SD2) [1] */
2824                 FN_SEL_SD2_A,           FN_SEL_SD2_B,
2825                 /* SEL_10 (SD1) [1] */
2826                 FN_SEL_SD1_A,           FN_SEL_SD1_B,
2827                 /* SEL_9 (IRQ3) [1] */
2828                 FN_SEL_IRQ3_A,          FN_SEL_IRQ3_B,
2829                 /* SEL_8_7 (IRQ2) [2] */
2830                 FN_SEL_IRQ2_A,          FN_SEL_IRQ2_B,
2831                 FN_SEL_IRQ2_C,          0,
2832                 /* SEL_6 (IRQ1) [1] */
2833                 FN_SEL_IRQ1_A,          FN_SEL_IRQ1_B,
2834                 /* SEL_5 [1] */
2835                 0, 0,
2836                 /* SEL_4 (DREQ2) [1] */
2837                 FN_SEL_DREQ2_A,         FN_SEL_DREQ2_B,
2838                 /* SEL_3 (DREQ1) [1] */
2839                 FN_SEL_DREQ1_A,         FN_SEL_DREQ1_B,
2840                 /* SEL_2 (DREQ0) [1] */
2841                 FN_SEL_DREQ0_A,         FN_SEL_DREQ0_B,
2842                 /* SEL_1 (WAIT2) [1] */
2843                 FN_SEL_WAIT2_A,         FN_SEL_WAIT2_B,
2844                 /* SEL_0 (WAIT1) [1] */
2845                 FN_SEL_WAIT1_A,         FN_SEL_WAIT1_B,
2846                 }
2847         },
2848         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
2849                              1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1,
2850                              1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) {
2851
2852                 /* SEL_31 [1] */
2853                 0, 0,
2854                 /* SEL_30 [1] */
2855                 0, 0,
2856                 /* SEL_29 [1] */
2857                 0, 0,
2858                 /* SEL_28 [1] */
2859                 0, 0,
2860                 /* SEL_27 (CAN1) [1] */
2861                 FN_SEL_CAN1_A,          FN_SEL_CAN1_B,
2862                 /* SEL_26 (CAN0) [1] */
2863                 FN_SEL_CAN0_A,          FN_SEL_CAN0_B,
2864                 /* SEL_25_24 (CANCLK) [2] */
2865                 FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
2866                 FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
2867                 /* SEL_23 (HSCIF1) [1] */
2868                 FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
2869                 /* SEL_22 (HSCIF0) [1] */
2870                 FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
2871                 /* SEL_21 [1] */
2872                 0, 0,
2873                 /* SEL_20 [1] */
2874                 0, 0,
2875                 /* SEL_19 [1] */
2876                 0, 0,
2877                 /* SEL_18 [1] */
2878                 0, 0,
2879                 /* SEL_17 [1] */
2880                 0, 0,
2881                 /* SEL_16 [1] */
2882                 0, 0,
2883                 /* SEL_15 [1] */
2884                 0, 0,
2885                 /* SEL_14_13 (REMOCON) [2] */
2886                 FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,
2887                 FN_SEL_REMOCON_C,       0,
2888                 /* SEL_12_11 (FM) [2] */
2889                 FN_SEL_FM_A,            FN_SEL_FM_B,
2890                 FN_SEL_FM_C,            FN_SEL_FM_D,
2891                 /* SEL_10_9 (GPS) [2] */
2892                 FN_SEL_GPS_A,           FN_SEL_GPS_B,
2893                 FN_SEL_GPS_C,           0,
2894                 /* SEL_8 (TSIF0) [1] */
2895                 FN_SEL_TSIF0_A,         FN_SEL_TSIF0_B,
2896                 /* SEL_7 (HSPI2) [1] */
2897                 FN_SEL_HSPI2_A,         FN_SEL_HSPI2_B,
2898                 /* SEL_6 (HSPI1) [1] */
2899                 FN_SEL_HSPI1_A,         FN_SEL_HSPI1_B,
2900                 /* SEL_5 (HSPI0) [1] */
2901                 FN_SEL_HSPI0_A,         FN_SEL_HSPI0_B,
2902                 /* SEL_4_3 (I2C3) [2] */
2903                 FN_SEL_I2C3_A,          FN_SEL_I2C3_B,
2904                 FN_SEL_I2C3_C,          0,
2905                 /* SEL_2_1 (I2C2) [2] */
2906                 FN_SEL_I2C2_A,          FN_SEL_I2C2_B,
2907                 FN_SEL_I2C2_C,          0,
2908                 /* SEL_0 (I2C1) [1] */
2909                 FN_SEL_I2C1_A,          FN_SEL_I2C1_B,
2910                 }
2911         },
2912         { },
2913 };
2914
2915 #define PUPR0   0x100
2916 #define PUPR1   0x104
2917 #define PUPR2   0x108
2918 #define PUPR3   0x10c
2919 #define PUPR4   0x110
2920 #define PUPR5   0x114
2921
2922 static const struct sh_pfc_bias_info bias_info[] = {
2923         { RCAR_GP_PIN(0,  6), PUPR0,  0 },      /* A0 */
2924         { RCAR_GP_PIN(0,  7), PUPR0,  1 },      /* A1 */
2925         { RCAR_GP_PIN(0,  8), PUPR0,  2 },      /* A2 */
2926         { RCAR_GP_PIN(0,  9), PUPR0,  3 },      /* A3 */
2927         { RCAR_GP_PIN(0, 10), PUPR0,  4 },      /* A4 */
2928         { RCAR_GP_PIN(0, 11), PUPR0,  5 },      /* A5 */
2929         { RCAR_GP_PIN(0, 12), PUPR0,  6 },      /* A6 */
2930         { RCAR_GP_PIN(0, 13), PUPR0,  7 },      /* A7 */
2931         { RCAR_GP_PIN(0, 14), PUPR0,  8 },      /* A8 */
2932         { RCAR_GP_PIN(0, 15), PUPR0,  9 },      /* A9 */
2933         { RCAR_GP_PIN(0, 16), PUPR0, 10 },      /* A10 */
2934         { RCAR_GP_PIN(0, 17), PUPR0, 11 },      /* A11 */
2935         { RCAR_GP_PIN(0, 18), PUPR0, 12 },      /* A12 */
2936         { RCAR_GP_PIN(0, 19), PUPR0, 13 },      /* A13 */
2937         { RCAR_GP_PIN(0, 20), PUPR0, 14 },      /* A14 */
2938         { RCAR_GP_PIN(0, 21), PUPR0, 15 },      /* A15 */
2939         { RCAR_GP_PIN(0, 22), PUPR0, 16 },      /* A16 */
2940         { RCAR_GP_PIN(0, 23), PUPR0, 17 },      /* A17 */
2941         { RCAR_GP_PIN(0, 24), PUPR0, 18 },      /* A18 */
2942         { RCAR_GP_PIN(0, 25), PUPR0, 19 },      /* A19 */
2943         { RCAR_GP_PIN(0, 26), PUPR0, 20 },      /* A20 */
2944         { RCAR_GP_PIN(0, 27), PUPR0, 21 },      /* A21 */
2945         { RCAR_GP_PIN(0, 28), PUPR0, 22 },      /* A22 */
2946         { RCAR_GP_PIN(0, 29), PUPR0, 23 },      /* A23 */
2947         { RCAR_GP_PIN(0, 30), PUPR0, 24 },      /* A24 */
2948         { RCAR_GP_PIN(0, 31), PUPR0, 25 },      /* A25 */
2949         { RCAR_GP_PIN(1,  3), PUPR0, 26 },      /* /EX_CS0 */
2950         { RCAR_GP_PIN(1,  4), PUPR0, 27 },      /* /EX_CS1 */
2951         { RCAR_GP_PIN(1,  5), PUPR0, 28 },      /* /EX_CS2 */
2952         { RCAR_GP_PIN(1,  6), PUPR0, 29 },      /* /EX_CS3 */
2953         { RCAR_GP_PIN(1,  7), PUPR0, 30 },      /* /EX_CS4 */
2954         { RCAR_GP_PIN(1,  8), PUPR0, 31 },      /* /EX_CS5 */
2955
2956         { RCAR_GP_PIN(0,  0), PUPR1,  0 },      /* /PRESETOUT   */
2957         { RCAR_GP_PIN(0,  5), PUPR1,  1 },      /* /BS          */
2958         { RCAR_GP_PIN(1,  0), PUPR1,  2 },      /* RD//WR       */
2959         { RCAR_GP_PIN(1,  1), PUPR1,  3 },      /* /WE0         */
2960         { RCAR_GP_PIN(1,  2), PUPR1,  4 },      /* /WE1         */
2961         { RCAR_GP_PIN(1, 11), PUPR1,  5 },      /* EX_WAIT0     */
2962         { RCAR_GP_PIN(1,  9), PUPR1,  6 },      /* DREQ0        */
2963         { RCAR_GP_PIN(1, 10), PUPR1,  7 },      /* DACK0        */
2964         { RCAR_GP_PIN(1, 12), PUPR1,  8 },      /* IRQ0         */
2965         { RCAR_GP_PIN(1, 13), PUPR1,  9 },      /* IRQ1         */
2966
2967         { RCAR_GP_PIN(1, 22), PUPR2,  0 },      /* DU0_DR0      */
2968         { RCAR_GP_PIN(1, 23), PUPR2,  1 },      /* DU0_DR1      */
2969         { RCAR_GP_PIN(1, 24), PUPR2,  2 },      /* DU0_DR2      */
2970         { RCAR_GP_PIN(1, 25), PUPR2,  3 },      /* DU0_DR3      */
2971         { RCAR_GP_PIN(1, 26), PUPR2,  4 },      /* DU0_DR4      */
2972         { RCAR_GP_PIN(1, 27), PUPR2,  5 },      /* DU0_DR5      */
2973         { RCAR_GP_PIN(1, 28), PUPR2,  6 },      /* DU0_DR6      */
2974         { RCAR_GP_PIN(1, 29), PUPR2,  7 },      /* DU0_DR7      */
2975         { RCAR_GP_PIN(1, 30), PUPR2,  8 },      /* DU0_DG0      */
2976         { RCAR_GP_PIN(1, 31), PUPR2,  9 },      /* DU0_DG1      */
2977         { RCAR_GP_PIN(2,  0), PUPR2, 10 },      /* DU0_DG2      */
2978         { RCAR_GP_PIN(2,  1), PUPR2, 11 },      /* DU0_DG3      */
2979         { RCAR_GP_PIN(2,  2), PUPR2, 12 },      /* DU0_DG4      */
2980         { RCAR_GP_PIN(2,  3), PUPR2, 13 },      /* DU0_DG5      */
2981         { RCAR_GP_PIN(2,  4), PUPR2, 14 },      /* DU0_DG6      */
2982         { RCAR_GP_PIN(2,  5), PUPR2, 15 },      /* DU0_DG7      */
2983         { RCAR_GP_PIN(2,  6), PUPR2, 16 },      /* DU0_DB0      */
2984         { RCAR_GP_PIN(2,  7), PUPR2, 17 },      /* DU0_DB1      */
2985         { RCAR_GP_PIN(2,  8), PUPR2, 18 },      /* DU0_DB2      */
2986         { RCAR_GP_PIN(2,  9), PUPR2, 19 },      /* DU0_DB3      */
2987         { RCAR_GP_PIN(2, 10), PUPR2, 20 },      /* DU0_DB4      */
2988         { RCAR_GP_PIN(2, 11), PUPR2, 21 },      /* DU0_DB5      */
2989         { RCAR_GP_PIN(2, 12), PUPR2, 22 },      /* DU0_DB6      */
2990         { RCAR_GP_PIN(2, 13), PUPR2, 23 },      /* DU0_DB7      */
2991         { RCAR_GP_PIN(2, 14), PUPR2, 24 },      /* DU0_DOTCLKIN */
2992         { RCAR_GP_PIN(2, 15), PUPR2, 25 },      /* DU0_DOTCLKOUT0 */
2993         { RCAR_GP_PIN(2, 17), PUPR2, 26 },      /* DU0_HSYNC    */
2994         { RCAR_GP_PIN(2, 18), PUPR2, 27 },      /* DU0_VSYNC    */
2995         { RCAR_GP_PIN(2, 19), PUPR2, 28 },      /* DU0_EXODDF   */
2996         { RCAR_GP_PIN(2, 20), PUPR2, 29 },      /* DU0_DISP     */
2997         { RCAR_GP_PIN(2, 21), PUPR2, 30 },      /* DU0_CDE      */
2998         { RCAR_GP_PIN(2, 16), PUPR2, 31 },      /* DU0_DOTCLKOUT1 */
2999
3000         { RCAR_GP_PIN(3, 24), PUPR3,  0 },      /* VI0_CLK      */
3001         { RCAR_GP_PIN(3, 25), PUPR3,  1 },      /* VI0_CLKENB   */
3002         { RCAR_GP_PIN(3, 26), PUPR3,  2 },      /* VI0_FIELD    */
3003         { RCAR_GP_PIN(3, 27), PUPR3,  3 },      /* /VI0_HSYNC   */
3004         { RCAR_GP_PIN(3, 28), PUPR3,  4 },      /* /VI0_VSYNC   */
3005         { RCAR_GP_PIN(3, 29), PUPR3,  5 },      /* VI0_DATA0    */
3006         { RCAR_GP_PIN(3, 30), PUPR3,  6 },      /* VI0_DATA1    */
3007         { RCAR_GP_PIN(3, 31), PUPR3,  7 },      /* VI0_DATA2    */
3008         { RCAR_GP_PIN(4,  0), PUPR3,  8 },      /* VI0_DATA3    */
3009         { RCAR_GP_PIN(4,  1), PUPR3,  9 },      /* VI0_DATA4    */
3010         { RCAR_GP_PIN(4,  2), PUPR3, 10 },      /* VI0_DATA5    */
3011         { RCAR_GP_PIN(4,  3), PUPR3, 11 },      /* VI0_DATA6    */
3012         { RCAR_GP_PIN(4,  4), PUPR3, 12 },      /* VI0_DATA7    */
3013         { RCAR_GP_PIN(4,  5), PUPR3, 13 },      /* VI0_G2       */
3014         { RCAR_GP_PIN(4,  6), PUPR3, 14 },      /* VI0_G3       */
3015         { RCAR_GP_PIN(4,  7), PUPR3, 15 },      /* VI0_G4       */
3016         { RCAR_GP_PIN(4,  8), PUPR3, 16 },      /* VI0_G5       */
3017         { RCAR_GP_PIN(4, 21), PUPR3, 17 },      /* VI1_DATA12   */
3018         { RCAR_GP_PIN(4, 22), PUPR3, 18 },      /* VI1_DATA13   */
3019         { RCAR_GP_PIN(4, 23), PUPR3, 19 },      /* VI1_DATA14   */
3020         { RCAR_GP_PIN(4, 24), PUPR3, 20 },      /* VI1_DATA15   */
3021         { RCAR_GP_PIN(4,  9), PUPR3, 21 },      /* ETH_REF_CLK  */
3022         { RCAR_GP_PIN(4, 10), PUPR3, 22 },      /* ETH_TXD0     */
3023         { RCAR_GP_PIN(4, 11), PUPR3, 23 },      /* ETH_TXD1     */
3024         { RCAR_GP_PIN(4, 12), PUPR3, 24 },      /* ETH_CRS_DV   */
3025         { RCAR_GP_PIN(4, 13), PUPR3, 25 },      /* ETH_TX_EN    */
3026         { RCAR_GP_PIN(4, 14), PUPR3, 26 },      /* ETH_RX_ER    */
3027         { RCAR_GP_PIN(4, 15), PUPR3, 27 },      /* ETH_RXD0     */
3028         { RCAR_GP_PIN(4, 16), PUPR3, 28 },      /* ETH_RXD1     */
3029         { RCAR_GP_PIN(4, 17), PUPR3, 29 },      /* ETH_MDC      */
3030         { RCAR_GP_PIN(4, 18), PUPR3, 30 },      /* ETH_MDIO     */
3031         { RCAR_GP_PIN(4, 19), PUPR3, 31 },      /* ETH_LINK     */
3032
3033         { RCAR_GP_PIN(3,  6), PUPR4,  0 },      /* SSI_SCK012   */
3034         { RCAR_GP_PIN(3,  7), PUPR4,  1 },      /* SSI_WS012    */
3035         { RCAR_GP_PIN(3, 10), PUPR4,  2 },      /* SSI_SDATA0   */
3036         { RCAR_GP_PIN(3,  9), PUPR4,  3 },      /* SSI_SDATA1   */
3037         { RCAR_GP_PIN(3,  8), PUPR4,  4 },      /* SSI_SDATA2   */
3038         { RCAR_GP_PIN(3,  2), PUPR4,  5 },      /* SSI_SCK34    */
3039         { RCAR_GP_PIN(3,  3), PUPR4,  6 },      /* SSI_WS34     */
3040         { RCAR_GP_PIN(3,  5), PUPR4,  7 },      /* SSI_SDATA3   */
3041         { RCAR_GP_PIN(3,  4), PUPR4,  8 },      /* SSI_SDATA4   */
3042         { RCAR_GP_PIN(2, 31), PUPR4,  9 },      /* SSI_SCK5     */
3043         { RCAR_GP_PIN(3,  0), PUPR4, 10 },      /* SSI_WS5      */
3044         { RCAR_GP_PIN(3,  1), PUPR4, 11 },      /* SSI_SDATA5   */
3045         { RCAR_GP_PIN(2, 28), PUPR4, 12 },      /* SSI_SCK6     */
3046         { RCAR_GP_PIN(2, 29), PUPR4, 13 },      /* SSI_WS6      */
3047         { RCAR_GP_PIN(2, 30), PUPR4, 14 },      /* SSI_SDATA6   */
3048         { RCAR_GP_PIN(2, 24), PUPR4, 15 },      /* SSI_SCK78    */
3049         { RCAR_GP_PIN(2, 25), PUPR4, 16 },      /* SSI_WS78     */
3050         { RCAR_GP_PIN(2, 27), PUPR4, 17 },      /* SSI_SDATA7   */
3051         { RCAR_GP_PIN(2, 26), PUPR4, 18 },      /* SSI_SDATA8   */
3052         { RCAR_GP_PIN(3, 23), PUPR4, 19 },      /* TCLK0        */
3053         { RCAR_GP_PIN(3, 11), PUPR4, 20 },      /* SD0_CLK      */
3054         { RCAR_GP_PIN(3, 12), PUPR4, 21 },      /* SD0_CMD      */
3055         { RCAR_GP_PIN(3, 13), PUPR4, 22 },      /* SD0_DAT0     */
3056         { RCAR_GP_PIN(3, 14), PUPR4, 23 },      /* SD0_DAT1     */
3057         { RCAR_GP_PIN(3, 15), PUPR4, 24 },      /* SD0_DAT2     */
3058         { RCAR_GP_PIN(3, 16), PUPR4, 25 },      /* SD0_DAT3     */
3059         { RCAR_GP_PIN(3, 17), PUPR4, 26 },      /* SD0_CD       */
3060         { RCAR_GP_PIN(3, 18), PUPR4, 27 },      /* SD0_WP       */
3061         { RCAR_GP_PIN(2, 22), PUPR4, 28 },      /* AUDIO_CLKA   */
3062         { RCAR_GP_PIN(2, 23), PUPR4, 29 },      /* AUDIO_CLKB   */
3063         { RCAR_GP_PIN(1, 14), PUPR4, 30 },      /* IRQ2         */
3064         { RCAR_GP_PIN(1, 15), PUPR4, 31 },      /* IRQ3         */
3065
3066         { RCAR_GP_PIN(0,  1), PUPR5,  0 },      /* PENC0        */
3067         { RCAR_GP_PIN(0,  2), PUPR5,  1 },      /* PENC1        */
3068         { RCAR_GP_PIN(0,  3), PUPR5,  2 },      /* USB_OVC0     */
3069         { RCAR_GP_PIN(0,  4), PUPR5,  3 },      /* USB_OVC1     */
3070         { RCAR_GP_PIN(1, 16), PUPR5,  4 },      /* SCIF_CLK     */
3071         { RCAR_GP_PIN(1, 17), PUPR5,  5 },      /* TX0          */
3072         { RCAR_GP_PIN(1, 18), PUPR5,  6 },      /* RX0          */
3073         { RCAR_GP_PIN(1, 19), PUPR5,  7 },      /* SCK0         */
3074         { RCAR_GP_PIN(1, 20), PUPR5,  8 },      /* /CTS0        */
3075         { RCAR_GP_PIN(1, 21), PUPR5,  9 },      /* /RTS0        */
3076         { RCAR_GP_PIN(3, 19), PUPR5, 10 },      /* HSPI_CLK0    */
3077         { RCAR_GP_PIN(3, 20), PUPR5, 11 },      /* /HSPI_CS0    */
3078         { RCAR_GP_PIN(3, 21), PUPR5, 12 },      /* HSPI_RX0     */
3079         { RCAR_GP_PIN(3, 22), PUPR5, 13 },      /* HSPI_TX0     */
3080         { RCAR_GP_PIN(4, 20), PUPR5, 14 },      /* ETH_MAGIC    */
3081         { RCAR_GP_PIN(4, 25), PUPR5, 15 },      /* AVS1         */
3082         { RCAR_GP_PIN(4, 26), PUPR5, 16 },      /* AVS2         */
3083 };
3084
3085 static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
3086                                             unsigned int pin)
3087 {
3088         const struct sh_pfc_bias_info *info;
3089         void __iomem *addr;
3090
3091         info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
3092         if (!info)
3093                 return PIN_CONFIG_BIAS_DISABLE;
3094
3095         addr = pfc->windows->virt + info->reg;
3096
3097         if (ioread32(addr) & BIT(info->bit))
3098                 return PIN_CONFIG_BIAS_PULL_UP;
3099         else
3100                 return PIN_CONFIG_BIAS_DISABLE;
3101 }
3102
3103 static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3104                                    unsigned int bias)
3105 {
3106         const struct sh_pfc_bias_info *info;
3107         void __iomem *addr;
3108         u32 value;
3109         u32 bit;
3110
3111         info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
3112         if (!info)
3113                 return;
3114
3115         addr = pfc->windows->virt + info->reg;
3116         bit = BIT(info->bit);
3117
3118         value = ioread32(addr) & ~bit;
3119         if (bias == PIN_CONFIG_BIAS_PULL_UP)
3120                 value |= bit;
3121         iowrite32(value, addr);
3122 }
3123
3124 static const struct sh_pfc_soc_operations r8a7778_pfc_ops = {
3125         .get_bias = r8a7778_pinmux_get_bias,
3126         .set_bias = r8a7778_pinmux_set_bias,
3127 };
3128
3129 const struct sh_pfc_soc_info r8a7778_pinmux_info = {
3130         .name = "r8a7778_pfc",
3131         .ops  = &r8a7778_pfc_ops,
3132
3133         .unlock_reg = 0xfffc0000, /* PMMR */
3134
3135         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3136
3137         .pins = pinmux_pins,
3138         .nr_pins = ARRAY_SIZE(pinmux_pins),
3139
3140         .groups = pinmux_groups,
3141         .nr_groups = ARRAY_SIZE(pinmux_groups),
3142
3143         .functions = pinmux_functions,
3144         .nr_functions = ARRAY_SIZE(pinmux_functions),
3145
3146         .cfg_regs = pinmux_config_regs,
3147
3148         .pinmux_data = pinmux_data,
3149         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3150 };