drivers/pinctrl/sh-pfc/pfc-r8a7792.c

   1 /*
   2  * r8a7792 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2
   9  * as published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13
  14 #include "core.h"
  15 #include "sh_pfc.h"
  16
  17 #define CPU_ALL_PORT(fn, sfx)                                           \
  18         PORT_GP_29(0, fn, sfx),                                         \
  19         PORT_GP_23(1, fn, sfx),                                         \
  20         PORT_GP_32(2, fn, sfx),                                         \
  21         PORT_GP_28(3, fn, sfx),                                         \
  22         PORT_GP_17(4, fn, sfx),                                         \
  23         PORT_GP_17(5, fn, sfx),                                         \
  24         PORT_GP_17(6, fn, sfx),                                         \
  25         PORT_GP_17(7, fn, sfx),                                         \
  26         PORT_GP_17(8, fn, sfx),                                         \
  27         PORT_GP_17(9, fn, sfx),                                         \
  28         PORT_GP_32(10, fn, sfx),                                        \
  29         PORT_GP_30(11, fn, sfx)
  30
  31 enum {
  32         PINMUX_RESERVED = 0,
  33
  34         PINMUX_DATA_BEGIN,
  35         GP_ALL(DATA),
  36         PINMUX_DATA_END,
  37
  38         PINMUX_FUNCTION_BEGIN,
  39         GP_ALL(FN),
  40
  41         /* GPSR0 */
  42         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  43         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  44         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
  45         FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
  46         FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
  47         FN_IP1_3, FN_IP1_4,
  48
  49         /* GPSR1 */
  50         FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
  51         FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
  52         FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
  53         FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
  54         FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
  55         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
  56
  57         /* GPSR2 */
  58         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
  59         FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
  60         FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
  61         FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
  62
  63         /* GPSR3 */
  64         FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
  65         FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
  66         FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
  67         FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
  68         FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
  69
  70         /* GPSR4 */
  71         FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
  72         FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
  73         FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
  74         FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
  75         FN_VI0_FIELD,
  76
  77         /* GPSR5 */
  78         FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
  79         FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
  80         FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
  81         FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
  82         FN_VI1_FIELD,
  83
  84         /* GPSR6 */
  85         FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
  86         FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
  87         FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
  88
  89         /* GPSR7 */
  90         FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
  91         FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
  92         FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
  93
  94         /* GPSR8 */
  95         FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
  96         FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
  97         FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
  98
  99         /* GPSR9 */
 100         FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
 101         FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
 102         FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
 103
 104         /* GPSR10 */
 105         FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
 106         FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
 107         FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
 108         FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
 109         FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
 110         FN_CAN1_TX, FN_CAN1_RX,
 111
 112         /* GPSR11 */
 113         FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
 114         FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
 115         FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
 116         FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
 117         FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
 118         FN_ADICHS2, FN_AVS1, FN_AVS2,
 119
 120         /* IPSR0 */
 121         FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
 122         FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
 123         FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
 124         FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
 125         FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
 126         FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
 127         FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
 128         FN_DU0_DB7_C5,
 129
 130         /* IPSR1 */
 131         FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
 132         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
 133         FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
 134         FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
 135         FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
 136         FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
 137         FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
 138         FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
 139
 140         /* IPSR2 */
 141         FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
 142         FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
 143         FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
 144         FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
 145         FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
 146         FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
 147         FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
 148         FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
 149         FN_VI2_FIELD, FN_AVB_TXD2,
 150
 151         /* IPSR3 */
 152         FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
 153         FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
 154         FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
 155         FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
 156         FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
 157         FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
 158         FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
 159         FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
 160
 161         /* IPSR4 */
 162         FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
 163         FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
 164         FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
 165         FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
 166         FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
 167         FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
 168         FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
 169         FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
 170         FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
 171         FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
 172         FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
 173         FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
 174         FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
 175
 176         /* IPSR5 */
 177         FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
 178         FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
 179         FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
 180         FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
 181         FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
 182         FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
 183
 184         /* IPSR6 */
 185         FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
 186         FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
 187         FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
 188         FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
 189         FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
 190         FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
 191
 192         /* IPSR7 */
 193         FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
 194         FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
 195         FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
 196         FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
 197         FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
 198         FN_AUDIO_CLKA, FN_AUDIO_CLKB,
 199
 200         /* MOD_SEL */
 201         FN_SEL_VI1_0, FN_SEL_VI1_1,
 202         PINMUX_FUNCTION_END,
 203
 204         PINMUX_MARK_BEGIN,
 205         DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
 206         DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
 207         DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 208         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
 209         DU1_DISP_MARK, DU1_CDE_MARK,
 210
 211         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
 212         D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
 213         D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
 214         A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
 215         A12_MARK, A13_MARK, A14_MARK, A15_MARK,
 216
 217         A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
 218         EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
 219         EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
 220         WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
 221         IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
 222
 223         VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
 224         VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
 225         VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
 226         VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
 227         VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
 228         VI0_FIELD_MARK,
 229
 230         VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
 231         VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
 232         VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
 233         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
 234         VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
 235         VI1_FIELD_MARK,
 236
 237         VI3_D10_Y2_MARK, VI3_FIELD_MARK,
 238
 239         VI4_CLK_MARK,
 240
 241         VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
 242         VI5_FIELD_MARK,
 243
 244         HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
 245         TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
 246         TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
 247         CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
 248
 249         SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
 250         SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
 251         ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
 252         ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
 253
 254         /* IPSR0 */
 255         DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
 256         DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
 257         DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
 258         DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
 259         DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
 260         DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
 261         DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
 262         DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
 263
 264         /* IPSR1 */
 265         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
 266         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
 267         DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
 268         DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
 269         DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
 270         DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
 271         A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
 272         A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
 273
 274         /* IPSR2 */
 275         VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
 276         VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
 277         VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
 278         VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
 279         VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
 280         VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
 281         VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
 282         VI2_D10_Y2_MARK, AVB_TXD0_MARK,
 283         VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
 284
 285         /* IPSR3 */
 286         VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
 287         VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
 288         VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
 289         VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
 290         VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
 291         VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
 292         VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
 293         VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
 294
 295         /* IPSR4 */
 296         VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
 297         VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
 298         RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
 299         VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
 300         VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
 301         VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
 302         VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
 303         VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
 304         VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
 305         VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
 306         VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
 307
 308         /* IPSR5 */
 309         VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
 310         VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
 311         VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
 312         VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
 313         VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
 314         VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
 315         VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
 316
 317         /* IPSR6 */
 318         MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
 319         MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
 320         MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
 321         MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
 322         DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
 323         RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
 324         RX3_MARK,
 325
 326         /* IPSR7 */
 327         PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
 328         FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
 329         PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
 330         SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
 331         SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
 332         AUDIO_CLKB_MARK,
 333         PINMUX_MARK_END,
 334 };
 335
 336 static const u16 pinmux_data[] = {
 337         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 338
 339         PINMUX_SINGLE(DU1_DB2_C0_DATA12),
 340         PINMUX_SINGLE(DU1_DB3_C1_DATA13),
 341         PINMUX_SINGLE(DU1_DB4_C2_DATA14),
 342         PINMUX_SINGLE(DU1_DB5_C3_DATA15),
 343         PINMUX_SINGLE(DU1_DB6_C4),
 344         PINMUX_SINGLE(DU1_DB7_C5),
 345         PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
 346         PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
 347         PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
 348         PINMUX_SINGLE(DU1_DISP),
 349         PINMUX_SINGLE(DU1_CDE),
 350         PINMUX_SINGLE(D0),
 351         PINMUX_SINGLE(D1),
 352         PINMUX_SINGLE(D2),
 353         PINMUX_SINGLE(D3),
 354         PINMUX_SINGLE(D4),
 355         PINMUX_SINGLE(D5),
 356         PINMUX_SINGLE(D6),
 357         PINMUX_SINGLE(D7),
 358         PINMUX_SINGLE(D8),
 359         PINMUX_SINGLE(D9),
 360         PINMUX_SINGLE(D10),
 361         PINMUX_SINGLE(D11),
 362         PINMUX_SINGLE(D12),
 363         PINMUX_SINGLE(D13),
 364         PINMUX_SINGLE(D14),
 365         PINMUX_SINGLE(D15),
 366         PINMUX_SINGLE(A0),
 367         PINMUX_SINGLE(A1),
 368         PINMUX_SINGLE(A2),
 369         PINMUX_SINGLE(A3),
 370         PINMUX_SINGLE(A4),
 371         PINMUX_SINGLE(A5),
 372         PINMUX_SINGLE(A6),
 373         PINMUX_SINGLE(A7),
 374         PINMUX_SINGLE(A8),
 375         PINMUX_SINGLE(A9),
 376         PINMUX_SINGLE(A10),
 377         PINMUX_SINGLE(A11),
 378         PINMUX_SINGLE(A12),
 379         PINMUX_SINGLE(A13),
 380         PINMUX_SINGLE(A14),
 381         PINMUX_SINGLE(A15),
 382         PINMUX_SINGLE(A16),
 383         PINMUX_SINGLE(A17),
 384         PINMUX_SINGLE(A18),
 385         PINMUX_SINGLE(A19),
 386         PINMUX_SINGLE(CS1_N_A26),
 387         PINMUX_SINGLE(EX_CS0_N),
 388         PINMUX_SINGLE(EX_CS1_N),
 389         PINMUX_SINGLE(EX_CS2_N),
 390         PINMUX_SINGLE(EX_CS3_N),
 391         PINMUX_SINGLE(EX_CS4_N),
 392         PINMUX_SINGLE(EX_CS5_N),
 393         PINMUX_SINGLE(BS_N),
 394         PINMUX_SINGLE(RD_N),
 395         PINMUX_SINGLE(RD_WR_N),
 396         PINMUX_SINGLE(WE0_N),
 397         PINMUX_SINGLE(WE1_N),
 398         PINMUX_SINGLE(EX_WAIT0),
 399         PINMUX_SINGLE(IRQ0),
 400         PINMUX_SINGLE(IRQ1),
 401         PINMUX_SINGLE(IRQ2),
 402         PINMUX_SINGLE(IRQ3),
 403         PINMUX_SINGLE(CS0_N),
 404         PINMUX_SINGLE(VI0_CLK),
 405         PINMUX_SINGLE(VI0_CLKENB),
 406         PINMUX_SINGLE(VI0_HSYNC_N),
 407         PINMUX_SINGLE(VI0_VSYNC_N),
 408         PINMUX_SINGLE(VI0_D0_B0_C0),
 409         PINMUX_SINGLE(VI0_D1_B1_C1),
 410         PINMUX_SINGLE(VI0_D2_B2_C2),
 411         PINMUX_SINGLE(VI0_D3_B3_C3),
 412         PINMUX_SINGLE(VI0_D4_B4_C4),
 413         PINMUX_SINGLE(VI0_D5_B5_C5),
 414         PINMUX_SINGLE(VI0_D6_B6_C6),
 415         PINMUX_SINGLE(VI0_D7_B7_C7),
 416         PINMUX_SINGLE(VI0_D8_G0_Y0),
 417         PINMUX_SINGLE(VI0_D9_G1_Y1),
 418         PINMUX_SINGLE(VI0_D10_G2_Y2),
 419         PINMUX_SINGLE(VI0_D11_G3_Y3),
 420         PINMUX_SINGLE(VI0_FIELD),
 421         PINMUX_SINGLE(VI1_CLK),
 422         PINMUX_SINGLE(VI1_CLKENB),
 423         PINMUX_SINGLE(VI1_HSYNC_N),
 424         PINMUX_SINGLE(VI1_VSYNC_N),
 425         PINMUX_SINGLE(VI1_D0_B0_C0),
 426         PINMUX_SINGLE(VI1_D1_B1_C1),
 427         PINMUX_SINGLE(VI1_D2_B2_C2),
 428         PINMUX_SINGLE(VI1_D3_B3_C3),
 429         PINMUX_SINGLE(VI1_D4_B4_C4),
 430         PINMUX_SINGLE(VI1_D5_B5_C5),
 431         PINMUX_SINGLE(VI1_D6_B6_C6),
 432         PINMUX_SINGLE(VI1_D7_B7_C7),
 433         PINMUX_SINGLE(VI1_D8_G0_Y0),
 434         PINMUX_SINGLE(VI1_D9_G1_Y1),
 435         PINMUX_SINGLE(VI1_D10_G2_Y2),
 436         PINMUX_SINGLE(VI1_D11_G3_Y3),
 437         PINMUX_SINGLE(VI1_FIELD),
 438         PINMUX_SINGLE(VI3_D10_Y2),
 439         PINMUX_SINGLE(VI3_FIELD),
 440         PINMUX_SINGLE(VI4_CLK),
 441         PINMUX_SINGLE(VI5_CLK),
 442         PINMUX_SINGLE(VI5_D9_Y1),
 443         PINMUX_SINGLE(VI5_D10_Y2),
 444         PINMUX_SINGLE(VI5_D11_Y3),
 445         PINMUX_SINGLE(VI5_FIELD),
 446         PINMUX_SINGLE(HRTS0_N),
 447         PINMUX_SINGLE(HCTS1_N),
 448         PINMUX_SINGLE(SCK0),
 449         PINMUX_SINGLE(CTS0_N),
 450         PINMUX_SINGLE(RTS0_N),
 451         PINMUX_SINGLE(TX0),
 452         PINMUX_SINGLE(RX0),
 453         PINMUX_SINGLE(SCK1),
 454         PINMUX_SINGLE(CTS1_N),
 455         PINMUX_SINGLE(RTS1_N),
 456         PINMUX_SINGLE(TX1),
 457         PINMUX_SINGLE(RX1),
 458         PINMUX_SINGLE(SCIF_CLK),
 459         PINMUX_SINGLE(CAN0_TX),
 460         PINMUX_SINGLE(CAN0_RX),
 461         PINMUX_SINGLE(CAN_CLK),
 462         PINMUX_SINGLE(CAN1_TX),
 463         PINMUX_SINGLE(CAN1_RX),
 464         PINMUX_SINGLE(SD0_CLK),
 465         PINMUX_SINGLE(SD0_CMD),
 466         PINMUX_SINGLE(SD0_DAT0),
 467         PINMUX_SINGLE(SD0_DAT1),
 468         PINMUX_SINGLE(SD0_DAT2),
 469         PINMUX_SINGLE(SD0_DAT3),
 470         PINMUX_SINGLE(SD0_CD),
 471         PINMUX_SINGLE(SD0_WP),
 472         PINMUX_SINGLE(ADICLK),
 473         PINMUX_SINGLE(ADICS_SAMP),
 474         PINMUX_SINGLE(ADIDATA),
 475         PINMUX_SINGLE(ADICHS0),
 476         PINMUX_SINGLE(ADICHS1),
 477         PINMUX_SINGLE(ADICHS2),
 478         PINMUX_SINGLE(AVS1),
 479         PINMUX_SINGLE(AVS2),
 480
 481         /* IPSR0 */
 482         PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
 483         PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
 484         PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
 485         PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
 486         PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
 487         PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
 488         PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
 489         PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
 490         PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
 491         PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
 492         PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
 493         PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
 494         PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
 495         PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
 496         PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
 497         PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
 498         PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
 499         PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
 500         PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
 501         PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
 502         PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
 503         PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
 504         PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
 505         PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
 506
 507         /* IPSR1 */
 508         PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
 509         PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
 510         PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 511         PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
 512         PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
 513         PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
 514         PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
 515         PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
 516         PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
 517         PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
 518         PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
 519         PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
 520         PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
 521         PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
 522         PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
 523         PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
 524         PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
 525         PINMUX_IPSR_GPSR(IP1_17, A20),
 526         PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
 527         PINMUX_IPSR_GPSR(IP1_18, A21),
 528         PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
 529         PINMUX_IPSR_GPSR(IP1_19, A22),
 530         PINMUX_IPSR_GPSR(IP1_19, IO2),
 531         PINMUX_IPSR_GPSR(IP1_20, A23),
 532         PINMUX_IPSR_GPSR(IP1_20, IO3),
 533         PINMUX_IPSR_GPSR(IP1_21, A24),
 534         PINMUX_IPSR_GPSR(IP1_21, SPCLK),
 535         PINMUX_IPSR_GPSR(IP1_22, A25),
 536         PINMUX_IPSR_GPSR(IP1_22, SSL),
 537
 538         /* IPSR2 */
 539         PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
 540         PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
 541         PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
 542         PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
 543         PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
 544         PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
 545         PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
 546         PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
 547         PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
 548         PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
 549         PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
 550         PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
 551         PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
 552         PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
 553         PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
 554         PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
 555         PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
 556         PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
 557         PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
 558         PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
 559         PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
 560         PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
 561         PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
 562         PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
 563         PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
 564         PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
 565         PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
 566         PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
 567         PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
 568         PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
 569         PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
 570         PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
 571         PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
 572         PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
 573
 574         /* IPSR3 */
 575         PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
 576         PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
 577         PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
 578         PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
 579         PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
 580         PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
 581         PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
 582         PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
 583         PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
 584         PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
 585         PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
 586         PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
 587         PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
 588         PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
 589         PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
 590         PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
 591         PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
 592         PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
 593         PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
 594         PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
 595         PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
 596         PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
 597         PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
 598         PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
 599         PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
 600         PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
 601         PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
 602         PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
 603         PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
 604         PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
 605
 606         /* IPSR4 */
 607         PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
 608         PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
 609         PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
 610         PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
 611         PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
 612         PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
 613         PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
 614         PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
 615         PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
 616         PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
 617         PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
 618         PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
 619         PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
 620         PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
 621         PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
 622         PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
 623         PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
 624         PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
 625         PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
 626         PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
 627         PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
 628         PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
 629         PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
 630         PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
 631         PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
 632         PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
 633         PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
 634         PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
 635         PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
 636         PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
 637         PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
 638         PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
 639         PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
 640         PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
 641         PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
 642         PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
 643         PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
 644         PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
 645         PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
 646         PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
 647
 648         /* IPSR5 */
 649         PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
 650         PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
 651         PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
 652         PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
 653         PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
 654         PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
 655         PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
 656         PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
 657         PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
 658         PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
 659         PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
 660         PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
 661         PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
 662         PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
 663         PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
 664         PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
 665         PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
 666         PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
 667         PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
 668         PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
 669         PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
 670         PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
 671         PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
 672         PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
 673
 674         /* IPSR6 */
 675         PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
 676         PINMUX_IPSR_GPSR(IP6_0, HSCK0),
 677         PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
 678         PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
 679         PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
 680         PINMUX_IPSR_GPSR(IP6_2, HTX0),
 681         PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
 682         PINMUX_IPSR_GPSR(IP6_3, HRX0),
 683         PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
 684         PINMUX_IPSR_GPSR(IP6_4, HSCK1),
 685         PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
 686         PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
 687         PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
 688         PINMUX_IPSR_GPSR(IP6_6, HTX1),
 689         PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
 690         PINMUX_IPSR_GPSR(IP6_7, HRX1),
 691         PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
 692         PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
 693         PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
 694         PINMUX_IPSR_GPSR(IP6_11_10, TX2),
 695         PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
 696         PINMUX_IPSR_GPSR(IP6_13_12, RX2),
 697         PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
 698         PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
 699         PINMUX_IPSR_GPSR(IP6_16, TX3),
 700         PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
 701         PINMUX_IPSR_GPSR(IP6_18_17, RX3),
 702
 703         /* IPSR7 */
 704         PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
 705         PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
 706         PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
 707         PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
 708         PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
 709         PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
 710         PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
 711         PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
 712         PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
 713         PINMUX_IPSR_GPSR(IP7_6, PWM3),
 714         PINMUX_IPSR_GPSR(IP7_7, PWM4),
 715         PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
 716         PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
 717         PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
 718         PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
 719         PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
 720         PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
 721         PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
 722         PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
 723         PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
 724         PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
 725         PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
 726         PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
 727         PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
 728 };
 729
 730 static const struct sh_pfc_pin pinmux_pins[] = {
 731         PINMUX_GPIO_GP_ALL(),
 732 };
 733
 734 /* - AVB -------------------------------------------------------------------- */
 735 static const unsigned int avb_link_pins[] = {
 736         RCAR_GP_PIN(7, 9),
 737 };
 738 static const unsigned int avb_link_mux[] = {
 739         AVB_LINK_MARK,
 740 };
 741 static const unsigned int avb_magic_pins[] = {
 742         RCAR_GP_PIN(7, 10),
 743 };
 744 static const unsigned int avb_magic_mux[] = {
 745         AVB_MAGIC_MARK,
 746 };
 747 static const unsigned int avb_phy_int_pins[] = {
 748         RCAR_GP_PIN(7, 11),
 749 };
 750 static const unsigned int avb_phy_int_mux[] = {
 751         AVB_PHY_INT_MARK,
 752 };
 753 static const unsigned int avb_mdio_pins[] = {
 754         RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
 755 };
 756 static const unsigned int avb_mdio_mux[] = {
 757         AVB_MDC_MARK, AVB_MDIO_MARK,
 758 };
 759 static const unsigned int avb_mii_pins[] = {
 760         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
 761         RCAR_GP_PIN(6, 12),
 762
 763         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(6, 4),
 764         RCAR_GP_PIN(6, 5),
 765
 766         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(6, 1),
 767         RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
 768         RCAR_GP_PIN(7, 0),  RCAR_GP_PIN(6, 11),
 769 };
 770 static const unsigned int avb_mii_mux[] = {
 771         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
 772         AVB_TXD3_MARK,
 773
 774         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
 775         AVB_RXD3_MARK,
 776
 777         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
 778         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
 779         AVB_TX_CLK_MARK, AVB_COL_MARK,
 780 };
 781 static const unsigned int avb_gmii_pins[] = {
 782         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
 783         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1),  RCAR_GP_PIN(7, 2),
 784         RCAR_GP_PIN(7, 3),  RCAR_GP_PIN(7, 4),
 785
 786         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
 787         RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
 788         RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 9),
 789
 790         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
 791         RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
 792         RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
 793         RCAR_GP_PIN(6, 11),
 794 };
 795 static const unsigned int avb_gmii_mux[] = {
 796         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
 797         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
 798         AVB_TXD6_MARK, AVB_TXD7_MARK,
 799
 800         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
 801         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
 802         AVB_RXD6_MARK, AVB_RXD7_MARK,
 803
 804         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
 805         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
 806         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
 807         AVB_COL_MARK,
 808 };
 809 static const unsigned int avb_avtp_match_pins[] = {
 810         RCAR_GP_PIN(7, 15),
 811 };
 812 static const unsigned int avb_avtp_match_mux[] = {
 813         AVB_AVTP_MATCH_MARK,
 814 };
 815 /* - CAN -------------------------------------------------------------------- */
 816 static const unsigned int can0_data_pins[] = {
 817         /* TX, RX */
 818         RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
 819 };
 820 static const unsigned int can0_data_mux[] = {
 821         CAN0_TX_MARK, CAN0_RX_MARK,
 822 };
 823 static const unsigned int can1_data_pins[] = {
 824         /* TX, RX */
 825         RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
 826 };
 827 static const unsigned int can1_data_mux[] = {
 828         CAN1_TX_MARK, CAN1_RX_MARK,
 829 };
 830 static const unsigned int can_clk_pins[] = {
 831         /* CAN_CLK */
 832         RCAR_GP_PIN(10, 29),
 833 };
 834 static const unsigned int can_clk_mux[] = {
 835         CAN_CLK_MARK,
 836 };
 837 /* - DU --------------------------------------------------------------------- */
 838 static const unsigned int du0_rgb666_pins[] = {
 839         /* R[7:2], G[7:2], B[7:2] */
 840         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
 841         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 842         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
 843         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 844         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 845         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
 846 };
 847 static const unsigned int du0_rgb666_mux[] = {
 848         DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
 849         DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
 850         DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
 851         DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
 852         DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
 853         DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
 854 };
 855 static const unsigned int du0_rgb888_pins[] = {
 856         /* R[7:0], G[7:0], B[7:0] */
 857         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
 858         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 859         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 860         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
 861         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 862         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
 863         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 864         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
 865         RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
 866 };
 867 static const unsigned int du0_rgb888_mux[] = {
 868         DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
 869         DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
 870         DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
 871         DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
 872         DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
 873         DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
 874         DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
 875         DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
 876         DU0_DB1_MARK, DU0_DB0_MARK,
 877 };
 878 static const unsigned int du0_sync_pins[] = {
 879         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 880         RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
 881 };
 882 static const unsigned int du0_sync_mux[] = {
 883         DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
 884 };
 885 static const unsigned int du0_oddf_pins[] = {
 886         /* EXODDF/ODDF/DISP/CDE */
 887         RCAR_GP_PIN(0, 26),
 888 };
 889 static const unsigned int du0_oddf_mux[] = {
 890         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
 891 };
 892 static const unsigned int du0_disp_pins[] = {
 893         /* DISP */
 894         RCAR_GP_PIN(0, 27),
 895 };
 896 static const unsigned int du0_disp_mux[] = {
 897         DU0_DISP_MARK,
 898 };
 899 static const unsigned int du0_cde_pins[] = {
 900         /* CDE */
 901         RCAR_GP_PIN(0, 28),
 902 };
 903 static const unsigned int du0_cde_mux[] = {
 904         DU0_CDE_MARK,
 905 };
 906 static const unsigned int du1_rgb666_pins[] = {
 907         /* R[7:2], G[7:2], B[7:2] */
 908         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
 909         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
 910         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
 911         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
 912         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
 913         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
 914 };
 915 static const unsigned int du1_rgb666_mux[] = {
 916         DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
 917         DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
 918         DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
 919         DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
 920         DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
 921         DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
 922 };
 923 static const unsigned int du1_sync_pins[] = {
 924         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 925         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 926 };
 927 static const unsigned int du1_sync_mux[] = {
 928         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 929 };
 930 static const unsigned int du1_oddf_pins[] = {
 931         /* EXODDF/ODDF/DISP/CDE */
 932         RCAR_GP_PIN(1, 20),
 933 };
 934 static const unsigned int du1_oddf_mux[] = {
 935         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
 936 };
 937 static const unsigned int du1_disp_pins[] = {
 938         /* DISP */
 939         RCAR_GP_PIN(1, 21),
 940 };
 941 static const unsigned int du1_disp_mux[] = {
 942         DU1_DISP_MARK,
 943 };
 944 static const unsigned int du1_cde_pins[] = {
 945         /* CDE */
 946         RCAR_GP_PIN(1, 22),
 947 };
 948 static const unsigned int du1_cde_mux[] = {
 949         DU1_CDE_MARK,
 950 };
 951 /* - INTC ------------------------------------------------------------------- */
 952 static const unsigned int intc_irq0_pins[] = {
 953         /* IRQ0 */
 954         RCAR_GP_PIN(3, 19),
 955 };
 956 static const unsigned int intc_irq0_mux[] = {
 957         IRQ0_MARK,
 958 };
 959 static const unsigned int intc_irq1_pins[] = {
 960         /* IRQ1 */
 961         RCAR_GP_PIN(3, 20),
 962 };
 963 static const unsigned int intc_irq1_mux[] = {
 964         IRQ1_MARK,
 965 };
 966 static const unsigned int intc_irq2_pins[] = {
 967         /* IRQ2 */
 968         RCAR_GP_PIN(3, 21),
 969 };
 970 static const unsigned int intc_irq2_mux[] = {
 971         IRQ2_MARK,
 972 };
 973 static const unsigned int intc_irq3_pins[] = {
 974         /* IRQ3 */
 975         RCAR_GP_PIN(3, 22),
 976 };
 977 static const unsigned int intc_irq3_mux[] = {
 978         IRQ3_MARK,
 979 };
 980 /* - LBSC ------------------------------------------------------------------- */
 981 static const unsigned int lbsc_cs0_pins[] = {
 982         /* CS0# */
 983         RCAR_GP_PIN(3, 27),
 984 };
 985 static const unsigned int lbsc_cs0_mux[] = {
 986         CS0_N_MARK,
 987 };
 988 static const unsigned int lbsc_cs1_pins[] = {
 989         /* CS1#_A26 */
 990         RCAR_GP_PIN(3, 6),
 991 };
 992 static const unsigned int lbsc_cs1_mux[] = {
 993         CS1_N_A26_MARK,
 994 };
 995 static const unsigned int lbsc_ex_cs0_pins[] = {
 996         /* EX_CS0# */
 997         RCAR_GP_PIN(3, 7),
 998 };
 999 static const unsigned int lbsc_ex_cs0_mux[] = {
1000         EX_CS0_N_MARK,
1001 };
1002 static const unsigned int lbsc_ex_cs1_pins[] = {
1003         /* EX_CS1# */
1004         RCAR_GP_PIN(3, 8),
1005 };
1006 static const unsigned int lbsc_ex_cs1_mux[] = {
1007         EX_CS1_N_MARK,
1008 };
1009 static const unsigned int lbsc_ex_cs2_pins[] = {
1010         /* EX_CS2# */
1011         RCAR_GP_PIN(3, 9),
1012 };
1013 static const unsigned int lbsc_ex_cs2_mux[] = {
1014         EX_CS2_N_MARK,
1015 };
1016 static const unsigned int lbsc_ex_cs3_pins[] = {
1017         /* EX_CS3# */
1018         RCAR_GP_PIN(3, 10),
1019 };
1020 static const unsigned int lbsc_ex_cs3_mux[] = {
1021         EX_CS3_N_MARK,
1022 };
1023 static const unsigned int lbsc_ex_cs4_pins[] = {
1024         /* EX_CS4# */
1025         RCAR_GP_PIN(3, 11),
1026 };
1027 static const unsigned int lbsc_ex_cs4_mux[] = {
1028         EX_CS4_N_MARK,
1029 };
1030 static const unsigned int lbsc_ex_cs5_pins[] = {
1031         /* EX_CS5# */
1032         RCAR_GP_PIN(3, 12),
1033 };
1034 static const unsigned int lbsc_ex_cs5_mux[] = {
1035         EX_CS5_N_MARK,
1036 };
1037 /* - MSIOF0 ----------------------------------------------------------------- */
1038 static const unsigned int msiof0_clk_pins[] = {
1039         /* SCK */
1040         RCAR_GP_PIN(10, 0),
1041 };
1042 static const unsigned int msiof0_clk_mux[] = {
1043         MSIOF0_SCK_MARK,
1044 };
1045 static const unsigned int msiof0_sync_pins[] = {
1046         /* SYNC */
1047         RCAR_GP_PIN(10, 1),
1048 };
1049 static const unsigned int msiof0_sync_mux[] = {
1050         MSIOF0_SYNC_MARK,
1051 };
1052 static const unsigned int msiof0_rx_pins[] = {
1053         /* RXD */
1054         RCAR_GP_PIN(10, 4),
1055 };
1056 static const unsigned int msiof0_rx_mux[] = {
1057         MSIOF0_RXD_MARK,
1058 };
1059 static const unsigned int msiof0_tx_pins[] = {
1060         /* TXD */
1061         RCAR_GP_PIN(10, 3),
1062 };
1063 static const unsigned int msiof0_tx_mux[] = {
1064         MSIOF0_TXD_MARK,
1065 };
1066 /* - MSIOF1 ----------------------------------------------------------------- */
1067 static const unsigned int msiof1_clk_pins[] = {
1068         /* SCK */
1069         RCAR_GP_PIN(10, 5),
1070 };
1071 static const unsigned int msiof1_clk_mux[] = {
1072         MSIOF1_SCK_MARK,
1073 };
1074 static const unsigned int msiof1_sync_pins[] = {
1075         /* SYNC */
1076         RCAR_GP_PIN(10, 6),
1077 };
1078 static const unsigned int msiof1_sync_mux[] = {
1079         MSIOF1_SYNC_MARK,
1080 };
1081 static const unsigned int msiof1_rx_pins[] = {
1082         /* RXD */
1083         RCAR_GP_PIN(10, 9),
1084 };
1085 static const unsigned int msiof1_rx_mux[] = {
1086         MSIOF1_RXD_MARK,
1087 };
1088 static const unsigned int msiof1_tx_pins[] = {
1089         /* TXD */
1090         RCAR_GP_PIN(10, 8),
1091 };
1092 static const unsigned int msiof1_tx_mux[] = {
1093         MSIOF1_TXD_MARK,
1094 };
1095 /* - QSPI ------------------------------------------------------------------- */
1096 static const unsigned int qspi_ctrl_pins[] = {
1097         /* SPCLK, SSL */
1098         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1099 };
1100 static const unsigned int qspi_ctrl_mux[] = {
1101         SPCLK_MARK, SSL_MARK,
1102 };
1103 static const unsigned int qspi_data2_pins[] = {
1104         /* MOSI_IO0, MISO_IO1 */
1105         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1106 };
1107 static const unsigned int qspi_data2_mux[] = {
1108         MOSI_IO0_MARK, MISO_IO1_MARK,
1109 };
1110 static const unsigned int qspi_data4_pins[] = {
1111         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1112         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
1113         RCAR_GP_PIN(3, 24),
1114 };
1115 static const unsigned int qspi_data4_mux[] = {
1116         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
1117 };
1118 /* - SCIF0 ------------------------------------------------------------------ */
1119 static const unsigned int scif0_data_pins[] = {
1120         /* RX, TX */
1121         RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
1122 };
1123 static const unsigned int scif0_data_mux[] = {
1124         RX0_MARK, TX0_MARK,
1125 };
1126 static const unsigned int scif0_clk_pins[] = {
1127         /* SCK */
1128         RCAR_GP_PIN(10, 10),
1129 };
1130 static const unsigned int scif0_clk_mux[] = {
1131         SCK0_MARK,
1132 };
1133 static const unsigned int scif0_ctrl_pins[] = {
1134         /* RTS, CTS */
1135         RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
1136 };
1137 static const unsigned int scif0_ctrl_mux[] = {
1138         RTS0_N_MARK, CTS0_N_MARK,
1139 };
1140 /* - SCIF3 ------------------------------------------------------------------ */
1141 static const unsigned int scif3_data_pins[] = {
1142         /* RX, TX */
1143         RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
1144 };
1145 static const unsigned int scif3_data_mux[] = {
1146         RX3_MARK, TX3_MARK,
1147 };
1148 static const unsigned int scif3_clk_pins[] = {
1149         /* SCK */
1150         RCAR_GP_PIN(10, 23),
1151 };
1152 static const unsigned int scif3_clk_mux[] = {
1153         SCK3_MARK,
1154 };
1155 /* - SDHI0 ------------------------------------------------------------------ */
1156 static const unsigned int sdhi0_data1_pins[] = {
1157         /* DAT0 */
1158         RCAR_GP_PIN(11, 7),
1159 };
1160 static const unsigned int sdhi0_data1_mux[] = {
1161         SD0_DAT0_MARK,
1162 };
1163 static const unsigned int sdhi0_data4_pins[] = {
1164         /* DAT[0-3] */
1165         RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
1166         RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
1167 };
1168 static const unsigned int sdhi0_data4_mux[] = {
1169         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1170 };
1171 static const unsigned int sdhi0_ctrl_pins[] = {
1172         /* CLK, CMD */
1173         RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
1174 };
1175 static const unsigned int sdhi0_ctrl_mux[] = {
1176         SD0_CLK_MARK, SD0_CMD_MARK,
1177 };
1178 static const unsigned int sdhi0_cd_pins[] = {
1179         /* CD */
1180         RCAR_GP_PIN(11, 11),
1181 };
1182 static const unsigned int sdhi0_cd_mux[] = {
1183         SD0_CD_MARK,
1184 };
1185 static const unsigned int sdhi0_wp_pins[] = {
1186         /* WP */
1187         RCAR_GP_PIN(11, 12),
1188 };
1189 static const unsigned int sdhi0_wp_mux[] = {
1190         SD0_WP_MARK,
1191 };
1192 /* - VIN0 ------------------------------------------------------------------- */
1193 static const union vin_data vin0_data_pins = {
1194         .data24 = {
1195                 /* B */
1196                 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1197                 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1198                 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1199                 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1200                 /* G */
1201                 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1202                 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1203                 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1204                 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1205                 /* R */
1206                 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1207                 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1208                 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1209                 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1210         },
1211 };
1212 static const union vin_data vin0_data_mux = {
1213         .data24 = {
1214                 /* B */
1215                 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1216                 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1217                 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1218                 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1219                 /* G */
1220                 VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1221                 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1222                 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1223                 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1224                 /* R */
1225                 VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1226                 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1227                 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1228                 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1229         },
1230 };
1231 static const unsigned int vin0_data18_pins[] = {
1232         /* B */
1233         RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1234         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1235         RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1236         /* G */
1237         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1238         RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1239         RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1240         /* R */
1241         RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1242         RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1243         RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1244 };
1245 static const unsigned int vin0_data18_mux[] = {
1246         /* B */
1247         VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1248         VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1249         VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1250         /* G */
1251         VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1252         VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1253         VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1254         /* R */
1255         VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1256         VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1257         VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1258 };
1259 static const unsigned int vin0_sync_pins[] = {
1260         /* HSYNC#, VSYNC# */
1261         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1262 };
1263 static const unsigned int vin0_sync_mux[] = {
1264         VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1265 };
1266 static const unsigned int vin0_field_pins[] = {
1267         RCAR_GP_PIN(4, 16),
1268 };
1269 static const unsigned int vin0_field_mux[] = {
1270         VI0_FIELD_MARK,
1271 };
1272 static const unsigned int vin0_clkenb_pins[] = {
1273         RCAR_GP_PIN(4, 1),
1274 };
1275 static const unsigned int vin0_clkenb_mux[] = {
1276         VI0_CLKENB_MARK,
1277 };
1278 static const unsigned int vin0_clk_pins[] = {
1279         RCAR_GP_PIN(4, 0),
1280 };
1281 static const unsigned int vin0_clk_mux[] = {
1282         VI0_CLK_MARK,
1283 };
1284 /* - VIN1 ------------------------------------------------------------------- */
1285 static const union vin_data vin1_data_pins = {
1286         .data24 = {
1287                 /* B */
1288                 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1289                 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1290                 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1291                 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1292                 /* G */
1293                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1294                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1295                 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1296                 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1297                 /* R */
1298                 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1299                 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1300                 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1301                 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1302         },
1303 };
1304 static const union vin_data vin1_data_mux = {
1305         .data24 = {
1306                 /* B */
1307                 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1308                 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1309                 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1310                 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1311                 /* G */
1312                 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1313                 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1314                 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1315                 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1316                 /* R */
1317                 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1318                 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1319                 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1320                 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1321         },
1322 };
1323 static const unsigned int vin1_data18_pins[] = {
1324         /* B */
1325         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1326         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1327         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1328         /* G */
1329         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1330         RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1331         RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1332         /* R */
1333         RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1334         RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1335         RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1336 };
1337 static const unsigned int vin1_data18_mux[] = {
1338         /* B */
1339         VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1340         VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1341         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1342         /* G */
1343         VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1344         VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1345         VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1346         /* R */
1347         VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1348         VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1349         VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1350 };
1351 static const union vin_data vin1_data_b_pins = {
1352         .data24 = {
1353                 /* B */
1354                 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1355                 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1356                 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1357                 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1358                 /* G */
1359                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1360                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1361                 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1362                 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1363                 /* R */
1364                 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1365                 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1366                 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1367                 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1368         },
1369 };
1370 static const union vin_data vin1_data_b_mux = {
1371         .data24 = {
1372                 /* B */
1373                 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1374                 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1375                 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1376                 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1377                 /* G */
1378                 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1379                 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1380                 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1381                 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1382                 /* R */
1383                 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1384                 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1385                 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1386                 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1387         },
1388 };
1389 static const unsigned int vin1_data18_b_pins[] = {
1390         /* B */
1391         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1392         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1393         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1394         /* G */
1395         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1396         RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1397         RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1398         /* R */
1399         RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1400         RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1401         RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1402 };
1403 static const unsigned int vin1_data18_b_mux[] = {
1404         /* B */
1405         VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1406         VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1407         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1408         /* G */
1409         VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1410         VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1411         VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1412         /* R */
1413         VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1414         VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1415         VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1416 };
1417 static const unsigned int vin1_sync_pins[] = {
1418         /* HSYNC#, VSYNC# */
1419         RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1420 };
1421 static const unsigned int vin1_sync_mux[] = {
1422         VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1423 };
1424 static const unsigned int vin1_field_pins[] = {
1425         RCAR_GP_PIN(5, 16),
1426 };
1427 static const unsigned int vin1_field_mux[] = {
1428         VI1_FIELD_MARK,
1429 };
1430 static const unsigned int vin1_clkenb_pins[] = {
1431         RCAR_GP_PIN(5, 1),
1432 };
1433 static const unsigned int vin1_clkenb_mux[] = {
1434         VI1_CLKENB_MARK,
1435 };
1436 static const unsigned int vin1_clk_pins[] = {
1437         RCAR_GP_PIN(5, 0),
1438 };
1439 static const unsigned int vin1_clk_mux[] = {
1440         VI1_CLK_MARK,
1441 };
1442 /* - VIN2 ------------------------------------------------------------------- */
1443 static const union vin_data vin2_data_pins = {
1444         .data16 = {
1445                 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1446                 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1447                 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1448                 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1449                 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1450                 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1451                 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1452                 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1453         },
1454 };
1455 static const union vin_data vin2_data_mux = {
1456         .data16 = {
1457                 VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1458                 VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1459                 VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1460                 VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1461                 VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1462                 VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1463                 VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1464                 VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
1465         },
1466 };
1467 static const unsigned int vin2_sync_pins[] = {
1468         /* HSYNC#, VSYNC# */
1469         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1470 };
1471 static const unsigned int vin2_sync_mux[] = {
1472         VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
1473 };
1474 static const unsigned int vin2_field_pins[] = {
1475         RCAR_GP_PIN(6, 16),
1476 };
1477 static const unsigned int vin2_field_mux[] = {
1478         VI2_FIELD_MARK,
1479 };
1480 static const unsigned int vin2_clkenb_pins[] = {
1481         RCAR_GP_PIN(6, 1),
1482 };
1483 static const unsigned int vin2_clkenb_mux[] = {
1484         VI2_CLKENB_MARK,
1485 };
1486 static const unsigned int vin2_clk_pins[] = {
1487         RCAR_GP_PIN(6, 0),
1488 };
1489 static const unsigned int vin2_clk_mux[] = {
1490         VI2_CLK_MARK,
1491 };
1492 /* - VIN3 ------------------------------------------------------------------- */
1493 static const union vin_data vin3_data_pins = {
1494         .data16 = {
1495                 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1496                 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1497                 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1498                 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1499                 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1500                 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1501                 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1502                 RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
1503         },
1504 };
1505 static const union vin_data vin3_data_mux = {
1506         .data16 = {
1507                 VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1508                 VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1509                 VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1510                 VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1511                 VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1512                 VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1513                 VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1514                 VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
1515         },
1516 };
1517 static const unsigned int vin3_sync_pins[] = {
1518         /* HSYNC#, VSYNC# */
1519         RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1520 };
1521 static const unsigned int vin3_sync_mux[] = {
1522         VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
1523 };
1524 static const unsigned int vin3_field_pins[] = {
1525         RCAR_GP_PIN(7, 16),
1526 };
1527 static const unsigned int vin3_field_mux[] = {
1528         VI3_FIELD_MARK,
1529 };
1530 static const unsigned int vin3_clkenb_pins[] = {
1531         RCAR_GP_PIN(7, 1),
1532 };
1533 static const unsigned int vin3_clkenb_mux[] = {
1534         VI3_CLKENB_MARK,
1535 };
1536 static const unsigned int vin3_clk_pins[] = {
1537         RCAR_GP_PIN(7, 0),
1538 };
1539 static const unsigned int vin3_clk_mux[] = {
1540         VI3_CLK_MARK,
1541 };
1542 /* - VIN4 ------------------------------------------------------------------- */
1543 static const union vin_data vin4_data_pins = {
1544         .data12 = {
1545                 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1546                 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1547                 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1548                 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1549                 RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1550                 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
1551         },
1552 };
1553 static const union vin_data vin4_data_mux = {
1554         .data12 = {
1555                 VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1556                 VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1557                 VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1558                 VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1559                 VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1560                 VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
1561         },
1562 };
1563 static const unsigned int vin4_sync_pins[] = {
1564          /* HSYNC#, VSYNC# */
1565         RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1566 };
1567 static const unsigned int vin4_sync_mux[] = {
1568         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1569 };
1570 static const unsigned int vin4_field_pins[] = {
1571         RCAR_GP_PIN(8, 16),
1572 };
1573 static const unsigned int vin4_field_mux[] = {
1574         VI4_FIELD_MARK,
1575 };
1576 static const unsigned int vin4_clkenb_pins[] = {
1577         RCAR_GP_PIN(8, 1),
1578 };
1579 static const unsigned int vin4_clkenb_mux[] = {
1580         VI4_CLKENB_MARK,
1581 };
1582 static const unsigned int vin4_clk_pins[] = {
1583         RCAR_GP_PIN(8, 0),
1584 };
1585 static const unsigned int vin4_clk_mux[] = {
1586         VI4_CLK_MARK,
1587 };
1588 /* - VIN5 ------------------------------------------------------------------- */
1589 static const union vin_data vin5_data_pins = {
1590         .data12 = {
1591                 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1592                 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1593                 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1594                 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1595                 RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1596                 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
1597         },
1598 };
1599 static const union vin_data vin5_data_mux = {
1600         .data12 = {
1601                 VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1602                 VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1603                 VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1604                 VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1605                 VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1606                 VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
1607         },
1608 };
1609 static const unsigned int vin5_sync_pins[] = {
1610         /* HSYNC#, VSYNC# */
1611         RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1612 };
1613 static const unsigned int vin5_sync_mux[] = {
1614         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
1615 };
1616 static const unsigned int vin5_field_pins[] = {
1617         RCAR_GP_PIN(9, 16),
1618 };
1619 static const unsigned int vin5_field_mux[] = {
1620         VI5_FIELD_MARK,
1621 };
1622 static const unsigned int vin5_clkenb_pins[] = {
1623         RCAR_GP_PIN(9, 1),
1624 };
1625 static const unsigned int vin5_clkenb_mux[] = {
1626         VI5_CLKENB_MARK,
1627 };
1628 static const unsigned int vin5_clk_pins[] = {
1629         RCAR_GP_PIN(9, 0),
1630 };
1631 static const unsigned int vin5_clk_mux[] = {
1632         VI5_CLK_MARK,
1633 };
1634
1635 static const struct sh_pfc_pin_group pinmux_groups[] = {
1636         SH_PFC_PIN_GROUP(avb_link),
1637         SH_PFC_PIN_GROUP(avb_magic),
1638         SH_PFC_PIN_GROUP(avb_phy_int),
1639         SH_PFC_PIN_GROUP(avb_mdio),
1640         SH_PFC_PIN_GROUP(avb_mii),
1641         SH_PFC_PIN_GROUP(avb_gmii),
1642         SH_PFC_PIN_GROUP(avb_avtp_match),
1643         SH_PFC_PIN_GROUP(can0_data),
1644         SH_PFC_PIN_GROUP(can1_data),
1645         SH_PFC_PIN_GROUP(can_clk),
1646         SH_PFC_PIN_GROUP(du0_rgb666),
1647         SH_PFC_PIN_GROUP(du0_rgb888),
1648         SH_PFC_PIN_GROUP(du0_sync),
1649         SH_PFC_PIN_GROUP(du0_oddf),
1650         SH_PFC_PIN_GROUP(du0_disp),
1651         SH_PFC_PIN_GROUP(du0_cde),
1652         SH_PFC_PIN_GROUP(du1_rgb666),
1653         SH_PFC_PIN_GROUP(du1_sync),
1654         SH_PFC_PIN_GROUP(du1_oddf),
1655         SH_PFC_PIN_GROUP(du1_disp),
1656         SH_PFC_PIN_GROUP(du1_cde),
1657         SH_PFC_PIN_GROUP(intc_irq0),
1658         SH_PFC_PIN_GROUP(intc_irq1),
1659         SH_PFC_PIN_GROUP(intc_irq2),
1660         SH_PFC_PIN_GROUP(intc_irq3),
1661         SH_PFC_PIN_GROUP(lbsc_cs0),
1662         SH_PFC_PIN_GROUP(lbsc_cs1),
1663         SH_PFC_PIN_GROUP(lbsc_ex_cs0),
1664         SH_PFC_PIN_GROUP(lbsc_ex_cs1),
1665         SH_PFC_PIN_GROUP(lbsc_ex_cs2),
1666         SH_PFC_PIN_GROUP(lbsc_ex_cs3),
1667         SH_PFC_PIN_GROUP(lbsc_ex_cs4),
1668         SH_PFC_PIN_GROUP(lbsc_ex_cs5),
1669         SH_PFC_PIN_GROUP(msiof0_clk),
1670         SH_PFC_PIN_GROUP(msiof0_sync),
1671         SH_PFC_PIN_GROUP(msiof0_rx),
1672         SH_PFC_PIN_GROUP(msiof0_tx),
1673         SH_PFC_PIN_GROUP(msiof1_clk),
1674         SH_PFC_PIN_GROUP(msiof1_sync),
1675         SH_PFC_PIN_GROUP(msiof1_rx),
1676         SH_PFC_PIN_GROUP(msiof1_tx),
1677         SH_PFC_PIN_GROUP(qspi_ctrl),
1678         SH_PFC_PIN_GROUP(qspi_data2),
1679         SH_PFC_PIN_GROUP(qspi_data4),
1680         SH_PFC_PIN_GROUP(scif0_data),
1681         SH_PFC_PIN_GROUP(scif0_clk),
1682         SH_PFC_PIN_GROUP(scif0_ctrl),
1683         SH_PFC_PIN_GROUP(scif3_data),
1684         SH_PFC_PIN_GROUP(scif3_clk),
1685         SH_PFC_PIN_GROUP(sdhi0_data1),
1686         SH_PFC_PIN_GROUP(sdhi0_data4),
1687         SH_PFC_PIN_GROUP(sdhi0_ctrl),
1688         SH_PFC_PIN_GROUP(sdhi0_cd),
1689         SH_PFC_PIN_GROUP(sdhi0_wp),
1690         VIN_DATA_PIN_GROUP(vin0_data, 24),
1691         VIN_DATA_PIN_GROUP(vin0_data, 20),
1692         SH_PFC_PIN_GROUP(vin0_data18),
1693         VIN_DATA_PIN_GROUP(vin0_data, 16),
1694         VIN_DATA_PIN_GROUP(vin0_data, 12),
1695         VIN_DATA_PIN_GROUP(vin0_data, 10),
1696         VIN_DATA_PIN_GROUP(vin0_data, 8),
1697         SH_PFC_PIN_GROUP(vin0_sync),
1698         SH_PFC_PIN_GROUP(vin0_field),
1699         SH_PFC_PIN_GROUP(vin0_clkenb),
1700         SH_PFC_PIN_GROUP(vin0_clk),
1701         VIN_DATA_PIN_GROUP(vin1_data, 24),
1702         VIN_DATA_PIN_GROUP(vin1_data, 20),
1703         SH_PFC_PIN_GROUP(vin1_data18),
1704         VIN_DATA_PIN_GROUP(vin1_data, 16),
1705         VIN_DATA_PIN_GROUP(vin1_data, 12),
1706         VIN_DATA_PIN_GROUP(vin1_data, 10),
1707         VIN_DATA_PIN_GROUP(vin1_data, 8),
1708         VIN_DATA_PIN_GROUP(vin1_data_b, 24),
1709         VIN_DATA_PIN_GROUP(vin1_data_b, 20),
1710         SH_PFC_PIN_GROUP(vin1_data18_b),
1711         VIN_DATA_PIN_GROUP(vin1_data_b, 16),
1712         SH_PFC_PIN_GROUP(vin1_sync),
1713         SH_PFC_PIN_GROUP(vin1_field),
1714         SH_PFC_PIN_GROUP(vin1_clkenb),
1715         SH_PFC_PIN_GROUP(vin1_clk),
1716         VIN_DATA_PIN_GROUP(vin2_data, 16),
1717         VIN_DATA_PIN_GROUP(vin2_data, 12),
1718         VIN_DATA_PIN_GROUP(vin2_data, 10),
1719         VIN_DATA_PIN_GROUP(vin2_data, 8),
1720         SH_PFC_PIN_GROUP(vin2_sync),
1721         SH_PFC_PIN_GROUP(vin2_field),
1722         SH_PFC_PIN_GROUP(vin2_clkenb),
1723         SH_PFC_PIN_GROUP(vin2_clk),
1724         VIN_DATA_PIN_GROUP(vin3_data, 16),
1725         VIN_DATA_PIN_GROUP(vin3_data, 12),
1726         VIN_DATA_PIN_GROUP(vin3_data, 10),
1727         VIN_DATA_PIN_GROUP(vin3_data, 8),
1728         SH_PFC_PIN_GROUP(vin3_sync),
1729         SH_PFC_PIN_GROUP(vin3_field),
1730         SH_PFC_PIN_GROUP(vin3_clkenb),
1731         SH_PFC_PIN_GROUP(vin3_clk),
1732         VIN_DATA_PIN_GROUP(vin4_data, 12),
1733         VIN_DATA_PIN_GROUP(vin4_data, 10),
1734         VIN_DATA_PIN_GROUP(vin4_data, 8),
1735         SH_PFC_PIN_GROUP(vin4_sync),
1736         SH_PFC_PIN_GROUP(vin4_field),
1737         SH_PFC_PIN_GROUP(vin4_clkenb),
1738         SH_PFC_PIN_GROUP(vin4_clk),
1739         VIN_DATA_PIN_GROUP(vin5_data, 12),
1740         VIN_DATA_PIN_GROUP(vin5_data, 10),
1741         VIN_DATA_PIN_GROUP(vin5_data, 8),
1742         SH_PFC_PIN_GROUP(vin5_sync),
1743         SH_PFC_PIN_GROUP(vin5_field),
1744         SH_PFC_PIN_GROUP(vin5_clkenb),
1745         SH_PFC_PIN_GROUP(vin5_clk),
1746 };
1747
1748 static const char * const avb_groups[] = {
1749         "avb_link",
1750         "avb_magic",
1751         "avb_phy_int",
1752         "avb_mdio",
1753         "avb_mii",
1754         "avb_gmii",
1755         "avb_avtp_match",
1756 };
1757
1758 static const char * const can0_groups[] = {
1759         "can0_data",
1760         "can_clk",
1761 };
1762
1763 static const char * const can1_groups[] = {
1764         "can1_data",
1765         "can_clk",
1766 };
1767
1768 static const char * const du0_groups[] = {
1769         "du0_rgb666",
1770         "du0_rgb888",
1771         "du0_sync",
1772         "du0_oddf",
1773         "du0_disp",
1774         "du0_cde",
1775 };
1776
1777 static const char * const du1_groups[] = {
1778         "du1_rgb666",
1779         "du1_sync",
1780         "du1_oddf",
1781         "du1_disp",
1782         "du1_cde",
1783 };
1784
1785 static const char * const intc_groups[] = {
1786         "intc_irq0",
1787         "intc_irq1",
1788         "intc_irq2",
1789         "intc_irq3",
1790 };
1791
1792 static const char * const lbsc_groups[] = {
1793         "lbsc_cs0",
1794         "lbsc_cs1",
1795         "lbsc_ex_cs0",
1796         "lbsc_ex_cs1",
1797         "lbsc_ex_cs2",
1798         "lbsc_ex_cs3",
1799         "lbsc_ex_cs4",
1800         "lbsc_ex_cs5",
1801 };
1802
1803 static const char * const msiof0_groups[] = {
1804         "msiof0_clk",
1805         "msiof0_sync",
1806         "msiof0_rx",
1807         "msiof0_tx",
1808 };
1809
1810 static const char * const msiof1_groups[] = {
1811         "msiof1_clk",
1812         "msiof1_sync",
1813         "msiof1_rx",
1814         "msiof1_tx",
1815 };
1816
1817 static const char * const qspi_groups[] = {
1818         "qspi_ctrl",
1819         "qspi_data2",
1820         "qspi_data4",
1821 };
1822
1823 static const char * const scif0_groups[] = {
1824         "scif0_data",
1825         "scif0_clk",
1826         "scif0_ctrl",
1827 };
1828
1829 static const char * const scif3_groups[] = {
1830         "scif3_data",
1831         "scif3_clk",
1832 };
1833
1834 static const char * const sdhi0_groups[] = {
1835         "sdhi0_data1",
1836         "sdhi0_data4",
1837         "sdhi0_ctrl",
1838         "sdhi0_cd",
1839         "sdhi0_wp",
1840 };
1841
1842 static const char * const vin0_groups[] = {
1843         "vin0_data24",
1844         "vin0_data20",
1845         "vin0_data18",
1846         "vin0_data16",
1847         "vin0_data12",
1848         "vin0_data10",
1849         "vin0_data8",
1850         "vin0_sync",
1851         "vin0_field",
1852         "vin0_clkenb",
1853         "vin0_clk",
1854 };
1855
1856 static const char * const vin1_groups[] = {
1857         "vin1_data24",
1858         "vin1_data20",
1859         "vin1_data18",
1860         "vin1_data16",
1861         "vin1_data12",
1862         "vin1_data10",
1863         "vin1_data8",
1864         "vin1_data24_b",
1865         "vin1_data20_b",
1866         "vin1_data16_b",
1867         "vin1_sync",
1868         "vin1_field",
1869         "vin1_clkenb",
1870         "vin1_clk",
1871 };
1872
1873 static const char * const vin2_groups[] = {
1874         "vin2_data16",
1875         "vin2_data12",
1876         "vin2_data10",
1877         "vin2_data8",
1878         "vin2_sync",
1879         "vin2_field",
1880         "vin2_clkenb",
1881         "vin2_clk",
1882 };
1883
1884 static const char * const vin3_groups[] = {
1885         "vin3_data16",
1886         "vin3_data12",
1887         "vin3_data10",
1888         "vin3_data8",
1889         "vin3_sync",
1890         "vin3_field",
1891         "vin3_clkenb",
1892         "vin3_clk",
1893 };
1894
1895 static const char * const vin4_groups[] = {
1896         "vin4_data12",
1897         "vin4_data10",
1898         "vin4_data8",
1899         "vin4_sync",
1900         "vin4_field",
1901         "vin4_clkenb",
1902         "vin4_clk",
1903 };
1904
1905 static const char * const vin5_groups[] = {
1906         "vin5_data12",
1907         "vin5_data10",
1908         "vin5_data8",
1909         "vin5_sync",
1910         "vin5_field",
1911         "vin5_clkenb",
1912         "vin5_clk",
1913 };
1914
1915 static const struct sh_pfc_function pinmux_functions[] = {
1916         SH_PFC_FUNCTION(avb),
1917         SH_PFC_FUNCTION(can0),
1918         SH_PFC_FUNCTION(can1),
1919         SH_PFC_FUNCTION(du0),
1920         SH_PFC_FUNCTION(du1),
1921         SH_PFC_FUNCTION(intc),
1922         SH_PFC_FUNCTION(lbsc),
1923         SH_PFC_FUNCTION(msiof0),
1924         SH_PFC_FUNCTION(msiof1),
1925         SH_PFC_FUNCTION(qspi),
1926         SH_PFC_FUNCTION(scif0),
1927         SH_PFC_FUNCTION(scif3),
1928         SH_PFC_FUNCTION(sdhi0),
1929         SH_PFC_FUNCTION(vin0),
1930         SH_PFC_FUNCTION(vin1),
1931         SH_PFC_FUNCTION(vin2),
1932         SH_PFC_FUNCTION(vin3),
1933         SH_PFC_FUNCTION(vin4),
1934         SH_PFC_FUNCTION(vin5),
1935 };
1936
1937 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1938         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
1939                 0, 0,
1940                 0, 0,
1941                 0, 0,
1942                 GP_0_28_FN, FN_IP1_4,
1943                 GP_0_27_FN, FN_IP1_3,
1944                 GP_0_26_FN, FN_IP1_2,
1945                 GP_0_25_FN, FN_IP1_1,
1946                 GP_0_24_FN, FN_IP1_0,
1947                 GP_0_23_FN, FN_IP0_23,
1948                 GP_0_22_FN, FN_IP0_22,
1949                 GP_0_21_FN, FN_IP0_21,
1950                 GP_0_20_FN, FN_IP0_20,
1951                 GP_0_19_FN, FN_IP0_19,
1952                 GP_0_18_FN, FN_IP0_18,
1953                 GP_0_17_FN, FN_IP0_17,
1954                 GP_0_16_FN, FN_IP0_16,
1955                 GP_0_15_FN, FN_IP0_15,
1956                 GP_0_14_FN, FN_IP0_14,
1957                 GP_0_13_FN, FN_IP0_13,
1958                 GP_0_12_FN, FN_IP0_12,
1959                 GP_0_11_FN, FN_IP0_11,
1960                 GP_0_10_FN, FN_IP0_10,
1961                 GP_0_9_FN, FN_IP0_9,
1962                 GP_0_8_FN, FN_IP0_8,
1963                 GP_0_7_FN, FN_IP0_7,
1964                 GP_0_6_FN, FN_IP0_6,
1965                 GP_0_5_FN, FN_IP0_5,
1966                 GP_0_4_FN, FN_IP0_4,
1967                 GP_0_3_FN, FN_IP0_3,
1968                 GP_0_2_FN, FN_IP0_2,
1969                 GP_0_1_FN, FN_IP0_1,
1970                 GP_0_0_FN, FN_IP0_0 }
1971         },
1972         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
1973                 0, 0,
1974                 0, 0,
1975                 0, 0,
1976                 0, 0,
1977                 0, 0,
1978                 0, 0,
1979                 0, 0,
1980                 0, 0,
1981                 0, 0,
1982                 GP_1_22_FN, FN_DU1_CDE,
1983                 GP_1_21_FN, FN_DU1_DISP,
1984                 GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
1985                 GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
1986                 GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
1987                 GP_1_17_FN, FN_DU1_DB7_C5,
1988                 GP_1_16_FN, FN_DU1_DB6_C4,
1989                 GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
1990                 GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
1991                 GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
1992                 GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
1993                 GP_1_11_FN, FN_IP1_16,
1994                 GP_1_10_FN, FN_IP1_15,
1995                 GP_1_9_FN, FN_IP1_14,
1996                 GP_1_8_FN, FN_IP1_13,
1997                 GP_1_7_FN, FN_IP1_12,
1998                 GP_1_6_FN, FN_IP1_11,
1999                 GP_1_5_FN, FN_IP1_10,
2000                 GP_1_4_FN, FN_IP1_9,
2001                 GP_1_3_FN, FN_IP1_8,
2002                 GP_1_2_FN, FN_IP1_7,
2003                 GP_1_1_FN, FN_IP1_6,
2004                 GP_1_0_FN, FN_IP1_5, }
2005         },
2006         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
2007                 GP_2_31_FN, FN_A15,
2008                 GP_2_30_FN, FN_A14,
2009                 GP_2_29_FN, FN_A13,
2010                 GP_2_28_FN, FN_A12,
2011                 GP_2_27_FN, FN_A11,
2012                 GP_2_26_FN, FN_A10,
2013                 GP_2_25_FN, FN_A9,
2014                 GP_2_24_FN, FN_A8,
2015                 GP_2_23_FN, FN_A7,
2016                 GP_2_22_FN, FN_A6,
2017                 GP_2_21_FN, FN_A5,
2018                 GP_2_20_FN, FN_A4,
2019                 GP_2_19_FN, FN_A3,
2020                 GP_2_18_FN, FN_A2,
2021                 GP_2_17_FN, FN_A1,
2022                 GP_2_16_FN, FN_A0,
2023                 GP_2_15_FN, FN_D15,
2024                 GP_2_14_FN, FN_D14,
2025                 GP_2_13_FN, FN_D13,
2026                 GP_2_12_FN, FN_D12,
2027                 GP_2_11_FN, FN_D11,
2028                 GP_2_10_FN, FN_D10,
2029                 GP_2_9_FN, FN_D9,
2030                 GP_2_8_FN, FN_D8,
2031                 GP_2_7_FN, FN_D7,
2032                 GP_2_6_FN, FN_D6,
2033                 GP_2_5_FN, FN_D5,
2034                 GP_2_4_FN, FN_D4,
2035                 GP_2_3_FN, FN_D3,
2036                 GP_2_2_FN, FN_D2,
2037                 GP_2_1_FN, FN_D1,
2038                 GP_2_0_FN, FN_D0 }
2039         },
2040         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
2041                 0, 0,
2042                 0, 0,
2043                 0, 0,
2044                 0, 0,
2045                 GP_3_27_FN, FN_CS0_N,
2046                 GP_3_26_FN, FN_IP1_22,
2047                 GP_3_25_FN, FN_IP1_21,
2048                 GP_3_24_FN, FN_IP1_20,
2049                 GP_3_23_FN, FN_IP1_19,
2050                 GP_3_22_FN, FN_IRQ3,
2051                 GP_3_21_FN, FN_IRQ2,
2052                 GP_3_20_FN, FN_IRQ1,
2053                 GP_3_19_FN, FN_IRQ0,
2054                 GP_3_18_FN, FN_EX_WAIT0,
2055                 GP_3_17_FN, FN_WE1_N,
2056                 GP_3_16_FN, FN_WE0_N,
2057                 GP_3_15_FN, FN_RD_WR_N,
2058                 GP_3_14_FN, FN_RD_N,
2059                 GP_3_13_FN, FN_BS_N,
2060                 GP_3_12_FN, FN_EX_CS5_N,
2061                 GP_3_11_FN, FN_EX_CS4_N,
2062                 GP_3_10_FN, FN_EX_CS3_N,
2063                 GP_3_9_FN, FN_EX_CS2_N,
2064                 GP_3_8_FN, FN_EX_CS1_N,
2065                 GP_3_7_FN, FN_EX_CS0_N,
2066                 GP_3_6_FN, FN_CS1_N_A26,
2067                 GP_3_5_FN, FN_IP1_18,
2068                 GP_3_4_FN, FN_IP1_17,
2069                 GP_3_3_FN, FN_A19,
2070                 GP_3_2_FN, FN_A18,
2071                 GP_3_1_FN, FN_A17,
2072                 GP_3_0_FN, FN_A16 }
2073         },
2074         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
2075                 0, 0,
2076                 0, 0,
2077                 0, 0,
2078                 0, 0,
2079                 0, 0,
2080                 0, 0,
2081                 0, 0,
2082                 0, 0,
2083                 0, 0,
2084                 0, 0,
2085                 0, 0,
2086                 0, 0,
2087                 0, 0,
2088                 0, 0,
2089                 0, 0,
2090                 GP_4_16_FN, FN_VI0_FIELD,
2091                 GP_4_15_FN, FN_VI0_D11_G3_Y3,
2092                 GP_4_14_FN, FN_VI0_D10_G2_Y2,
2093                 GP_4_13_FN, FN_VI0_D9_G1_Y1,
2094                 GP_4_12_FN, FN_VI0_D8_G0_Y0,
2095                 GP_4_11_FN, FN_VI0_D7_B7_C7,
2096                 GP_4_10_FN, FN_VI0_D6_B6_C6,
2097                 GP_4_9_FN, FN_VI0_D5_B5_C5,
2098                 GP_4_8_FN, FN_VI0_D4_B4_C4,
2099                 GP_4_7_FN, FN_VI0_D3_B3_C3,
2100                 GP_4_6_FN, FN_VI0_D2_B2_C2,
2101                 GP_4_5_FN, FN_VI0_D1_B1_C1,
2102                 GP_4_4_FN, FN_VI0_D0_B0_C0,
2103                 GP_4_3_FN, FN_VI0_VSYNC_N,
2104                 GP_4_2_FN, FN_VI0_HSYNC_N,
2105                 GP_4_1_FN, FN_VI0_CLKENB,
2106                 GP_4_0_FN, FN_VI0_CLK }
2107         },
2108         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
2109                 0, 0,
2110                 0, 0,
2111                 0, 0,
2112                 0, 0,
2113                 0, 0,
2114                 0, 0,
2115                 0, 0,
2116                 0, 0,
2117                 0, 0,
2118                 0, 0,
2119                 0, 0,
2120                 0, 0,
2121                 0, 0,
2122                 0, 0,
2123                 0, 0,
2124                 GP_5_16_FN, FN_VI1_FIELD,
2125                 GP_5_15_FN, FN_VI1_D11_G3_Y3,
2126                 GP_5_14_FN, FN_VI1_D10_G2_Y2,
2127                 GP_5_13_FN, FN_VI1_D9_G1_Y1,
2128                 GP_5_12_FN, FN_VI1_D8_G0_Y0,
2129                 GP_5_11_FN, FN_VI1_D7_B7_C7,
2130                 GP_5_10_FN, FN_VI1_D6_B6_C6,
2131                 GP_5_9_FN, FN_VI1_D5_B5_C5,
2132                 GP_5_8_FN, FN_VI1_D4_B4_C4,
2133                 GP_5_7_FN, FN_VI1_D3_B3_C3,
2134                 GP_5_6_FN, FN_VI1_D2_B2_C2,
2135                 GP_5_5_FN, FN_VI1_D1_B1_C1,
2136                 GP_5_4_FN, FN_VI1_D0_B0_C0,
2137                 GP_5_3_FN, FN_VI1_VSYNC_N,
2138                 GP_5_2_FN, FN_VI1_HSYNC_N,
2139                 GP_5_1_FN, FN_VI1_CLKENB,
2140                 GP_5_0_FN, FN_VI1_CLK }
2141         },
2142         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
2143                 0, 0,
2144                 0, 0,
2145                 0, 0,
2146                 0, 0,
2147                 0, 0,
2148                 0, 0,
2149                 0, 0,
2150                 0, 0,
2151                 0, 0,
2152                 0, 0,
2153                 0, 0,
2154                 0, 0,
2155                 0, 0,
2156                 0, 0,
2157                 0, 0,
2158                 GP_6_16_FN, FN_IP2_16,
2159                 GP_6_15_FN, FN_IP2_15,
2160                 GP_6_14_FN, FN_IP2_14,
2161                 GP_6_13_FN, FN_IP2_13,
2162                 GP_6_12_FN, FN_IP2_12,
2163                 GP_6_11_FN, FN_IP2_11,
2164                 GP_6_10_FN, FN_IP2_10,
2165                 GP_6_9_FN, FN_IP2_9,
2166                 GP_6_8_FN, FN_IP2_8,
2167                 GP_6_7_FN, FN_IP2_7,
2168                 GP_6_6_FN, FN_IP2_6,
2169                 GP_6_5_FN, FN_IP2_5,
2170                 GP_6_4_FN, FN_IP2_4,
2171                 GP_6_3_FN, FN_IP2_3,
2172                 GP_6_2_FN, FN_IP2_2,
2173                 GP_6_1_FN, FN_IP2_1,
2174                 GP_6_0_FN, FN_IP2_0 }
2175         },
2176         { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
2177                 0, 0,
2178                 0, 0,
2179                 0, 0,
2180                 0, 0,
2181                 0, 0,
2182                 0, 0,
2183                 0, 0,
2184                 0, 0,
2185                 0, 0,
2186                 0, 0,
2187                 0, 0,
2188                 0, 0,
2189                 0, 0,
2190                 0, 0,
2191                 0, 0,
2192                 GP_7_16_FN, FN_VI3_FIELD,
2193                 GP_7_15_FN, FN_IP3_14,
2194                 GP_7_14_FN, FN_VI3_D10_Y2,
2195                 GP_7_13_FN, FN_IP3_13,
2196                 GP_7_12_FN, FN_IP3_12,
2197                 GP_7_11_FN, FN_IP3_11,
2198                 GP_7_10_FN, FN_IP3_10,
2199                 GP_7_9_FN, FN_IP3_9,
2200                 GP_7_8_FN, FN_IP3_8,
2201                 GP_7_7_FN, FN_IP3_7,
2202                 GP_7_6_FN, FN_IP3_6,
2203                 GP_7_5_FN, FN_IP3_5,
2204                 GP_7_4_FN, FN_IP3_4,
2205                 GP_7_3_FN, FN_IP3_3,
2206                 GP_7_2_FN, FN_IP3_2,
2207                 GP_7_1_FN, FN_IP3_1,
2208                 GP_7_0_FN, FN_IP3_0 }
2209         },
2210         { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
2211                 0, 0,
2212                 0, 0,
2213                 0, 0,
2214                 0, 0,
2215                 0, 0,
2216                 0, 0,
2217                 0, 0,
2218                 0, 0,
2219                 0, 0,
2220                 0, 0,
2221                 0, 0,
2222                 0, 0,
2223                 0, 0,
2224                 0, 0,
2225                 0, 0,
2226                 GP_8_16_FN, FN_IP4_24,
2227                 GP_8_15_FN, FN_IP4_23,
2228                 GP_8_14_FN, FN_IP4_22,
2229                 GP_8_13_FN, FN_IP4_21,
2230                 GP_8_12_FN, FN_IP4_20_19,
2231                 GP_8_11_FN, FN_IP4_18_17,
2232                 GP_8_10_FN, FN_IP4_16_15,
2233                 GP_8_9_FN, FN_IP4_14_13,
2234                 GP_8_8_FN, FN_IP4_12_11,
2235                 GP_8_7_FN, FN_IP4_10_9,
2236                 GP_8_6_FN, FN_IP4_8_7,
2237                 GP_8_5_FN, FN_IP4_6_5,
2238                 GP_8_4_FN, FN_IP4_4,
2239                 GP_8_3_FN, FN_IP4_3_2,
2240                 GP_8_2_FN, FN_IP4_1,
2241                 GP_8_1_FN, FN_IP4_0,
2242                 GP_8_0_FN, FN_VI4_CLK }
2243         },
2244         { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
2245                 0, 0,
2246                 0, 0,
2247                 0, 0,
2248                 0, 0,
2249                 0, 0,
2250                 0, 0,
2251                 0, 0,
2252                 0, 0,
2253                 0, 0,
2254                 0, 0,
2255                 0, 0,
2256                 0, 0,
2257                 0, 0,
2258                 0, 0,
2259                 0, 0,
2260                 GP_9_16_FN, FN_VI5_FIELD,
2261                 GP_9_15_FN, FN_VI5_D11_Y3,
2262                 GP_9_14_FN, FN_VI5_D10_Y2,
2263                 GP_9_13_FN, FN_VI5_D9_Y1,
2264                 GP_9_12_FN, FN_IP5_11,
2265                 GP_9_11_FN, FN_IP5_10,
2266                 GP_9_10_FN, FN_IP5_9,
2267                 GP_9_9_FN, FN_IP5_8,
2268                 GP_9_8_FN, FN_IP5_7,
2269                 GP_9_7_FN, FN_IP5_6,
2270                 GP_9_6_FN, FN_IP5_5,
2271                 GP_9_5_FN, FN_IP5_4,
2272                 GP_9_4_FN, FN_IP5_3,
2273                 GP_9_3_FN, FN_IP5_2,
2274                 GP_9_2_FN, FN_IP5_1,
2275                 GP_9_1_FN, FN_IP5_0,
2276                 GP_9_0_FN, FN_VI5_CLK }
2277         },
2278         { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
2279                 GP_10_31_FN, FN_CAN1_RX,
2280                 GP_10_30_FN, FN_CAN1_TX,
2281                 GP_10_29_FN, FN_CAN_CLK,
2282                 GP_10_28_FN, FN_CAN0_RX,
2283                 GP_10_27_FN, FN_CAN0_TX,
2284                 GP_10_26_FN, FN_SCIF_CLK,
2285                 GP_10_25_FN, FN_IP6_18_17,
2286                 GP_10_24_FN, FN_IP6_16,
2287                 GP_10_23_FN, FN_IP6_15_14,
2288                 GP_10_22_FN, FN_IP6_13_12,
2289                 GP_10_21_FN, FN_IP6_11_10,
2290                 GP_10_20_FN, FN_IP6_9_8,
2291                 GP_10_19_FN, FN_RX1,
2292                 GP_10_18_FN, FN_TX1,
2293                 GP_10_17_FN, FN_RTS1_N,
2294                 GP_10_16_FN, FN_CTS1_N,
2295                 GP_10_15_FN, FN_SCK1,
2296                 GP_10_14_FN, FN_RX0,
2297                 GP_10_13_FN, FN_TX0,
2298                 GP_10_12_FN, FN_RTS0_N,
2299                 GP_10_11_FN, FN_CTS0_N,
2300                 GP_10_10_FN, FN_SCK0,
2301                 GP_10_9_FN, FN_IP6_7,
2302                 GP_10_8_FN, FN_IP6_6,
2303                 GP_10_7_FN, FN_HCTS1_N,
2304                 GP_10_6_FN, FN_IP6_5,
2305                 GP_10_5_FN, FN_IP6_4,
2306                 GP_10_4_FN, FN_IP6_3,
2307                 GP_10_3_FN, FN_IP6_2,
2308                 GP_10_2_FN, FN_HRTS0_N,
2309                 GP_10_1_FN, FN_IP6_1,
2310                 GP_10_0_FN, FN_IP6_0 }
2311         },
2312         { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
2313                 0, 0,
2314                 0, 0,
2315                 GP_11_29_FN, FN_AVS2,
2316                 GP_11_28_FN, FN_AVS1,
2317                 GP_11_27_FN, FN_ADICHS2,
2318                 GP_11_26_FN, FN_ADICHS1,
2319                 GP_11_25_FN, FN_ADICHS0,
2320                 GP_11_24_FN, FN_ADIDATA,
2321                 GP_11_23_FN, FN_ADICS_SAMP,
2322                 GP_11_22_FN, FN_ADICLK,
2323                 GP_11_21_FN, FN_IP7_20,
2324                 GP_11_20_FN, FN_IP7_19,
2325                 GP_11_19_FN, FN_IP7_18,
2326                 GP_11_18_FN, FN_IP7_17,
2327                 GP_11_17_FN, FN_IP7_16,
2328                 GP_11_16_FN, FN_IP7_15_14,
2329                 GP_11_15_FN, FN_IP7_13_12,
2330                 GP_11_14_FN, FN_IP7_11_10,
2331                 GP_11_13_FN, FN_IP7_9_8,
2332                 GP_11_12_FN, FN_SD0_WP,
2333                 GP_11_11_FN, FN_SD0_CD,
2334                 GP_11_10_FN, FN_SD0_DAT3,
2335                 GP_11_9_FN, FN_SD0_DAT2,
2336                 GP_11_8_FN, FN_SD0_DAT1,
2337                 GP_11_7_FN, FN_SD0_DAT0,
2338                 GP_11_6_FN, FN_SD0_CMD,
2339                 GP_11_5_FN, FN_SD0_CLK,
2340                 GP_11_4_FN, FN_IP7_7,
2341                 GP_11_3_FN, FN_IP7_6,
2342                 GP_11_2_FN, FN_IP7_5_4,
2343                 GP_11_1_FN, FN_IP7_3_2,
2344                 GP_11_0_FN, FN_IP7_1_0 }
2345         },
2346         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2347                              4, 4,
2348                              1, 1, 1, 1, 1, 1, 1, 1,
2349                              1, 1, 1, 1, 1, 1, 1, 1,
2350                              1, 1, 1, 1, 1, 1, 1, 1) {
2351                 /* IP0_31_28 [4] */
2352                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2353                 /* IP0_27_24 [4] */
2354                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2355                 /* IP0_23 [1] */
2356                 FN_DU0_DB7_C5, 0,
2357                 /* IP0_22 [1] */
2358                 FN_DU0_DB6_C4, 0,
2359                 /* IP0_21 [1] */
2360                 FN_DU0_DB5_C3, 0,
2361                 /* IP0_20 [1] */
2362                 FN_DU0_DB4_C2, 0,
2363                 /* IP0_19 [1] */
2364                 FN_DU0_DB3_C1, 0,
2365                 /* IP0_18 [1] */
2366                 FN_DU0_DB2_C0, 0,
2367                 /* IP0_17 [1] */
2368                 FN_DU0_DB1, 0,
2369                 /* IP0_16 [1] */
2370                 FN_DU0_DB0, 0,
2371                 /* IP0_15 [1] */
2372                 FN_DU0_DG7_Y3_DATA15, 0,
2373                 /* IP0_14 [1] */
2374                 FN_DU0_DG6_Y2_DATA14, 0,
2375                 /* IP0_13 [1] */
2376                 FN_DU0_DG5_Y1_DATA13, 0,
2377                 /* IP0_12 [1] */
2378                 FN_DU0_DG4_Y0_DATA12, 0,
2379                 /* IP0_11 [1] */
2380                 FN_DU0_DG3_C7_DATA11, 0,
2381                 /* IP0_10 [1] */
2382                 FN_DU0_DG2_C6_DATA10, 0,
2383                 /* IP0_9 [1] */
2384                 FN_DU0_DG1_DATA9, 0,
2385                 /* IP0_8 [1] */
2386                 FN_DU0_DG0_DATA8, 0,
2387                 /* IP0_7 [1] */
2388                 FN_DU0_DR7_Y9_DATA7, 0,
2389                 /* IP0_6 [1] */
2390                 FN_DU0_DR6_Y8_DATA6, 0,
2391                 /* IP0_5 [1] */
2392                 FN_DU0_DR5_Y7_DATA5, 0,
2393                 /* IP0_4 [1] */
2394                 FN_DU0_DR4_Y6_DATA4, 0,
2395                 /* IP0_3 [1] */
2396                 FN_DU0_DR3_Y5_DATA3, 0,
2397                 /* IP0_2 [1] */
2398                 FN_DU0_DR2_Y4_DATA2, 0,
2399                 /* IP0_1 [1] */
2400                 FN_DU0_DR1_DATA1, 0,
2401                 /* IP0_0 [1] */
2402                 FN_DU0_DR0_DATA0, 0 }
2403         },
2404         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2405                              4, 4,
2406                              1, 1, 1, 1, 1, 1, 1, 1,
2407                              1, 1, 1, 1, 1, 1, 1, 1,
2408                              1, 1, 1, 1, 1, 1, 1, 1) {
2409                 /* IP1_31_28 [4] */
2410                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2411                 /* IP1_27_24 [4] */
2412                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2413                 /* IP1_23 [1] */
2414                 0, 0,
2415                 /* IP1_22 [1] */
2416                 FN_A25, FN_SSL,
2417                 /* IP1_21 [1] */
2418                 FN_A24, FN_SPCLK,
2419                 /* IP1_20 [1] */
2420                 FN_A23, FN_IO3,
2421                 /* IP1_19 [1] */
2422                 FN_A22, FN_IO2,
2423                 /* IP1_18 [1] */
2424                 FN_A21, FN_MISO_IO1,
2425                 /* IP1_17 [1] */
2426                 FN_A20, FN_MOSI_IO0,
2427                 /* IP1_16 [1] */
2428                 FN_DU1_DG7_Y3_DATA11, 0,
2429                 /* IP1_15 [1] */
2430                 FN_DU1_DG6_Y2_DATA10, 0,
2431                 /* IP1_14 [1] */
2432                 FN_DU1_DG5_Y1_DATA9, 0,
2433                 /* IP1_13 [1] */
2434                 FN_DU1_DG4_Y0_DATA8, 0,
2435                 /* IP1_12 [1] */
2436                 FN_DU1_DG3_C7_DATA7, 0,
2437                 /* IP1_11 [1] */
2438                 FN_DU1_DG2_C6_DATA6, 0,
2439                 /* IP1_10 [1] */
2440                 FN_DU1_DR7_DATA5, 0,
2441                 /* IP1_9 [1] */
2442                 FN_DU1_DR6_DATA4, 0,
2443                 /* IP1_8 [1] */
2444                 FN_DU1_DR5_Y7_DATA3, 0,
2445                 /* IP1_7 [1] */
2446                 FN_DU1_DR4_Y6_DATA2, 0,
2447                 /* IP1_6 [1] */
2448                 FN_DU1_DR3_Y5_DATA1, 0,
2449                 /* IP1_5 [1] */
2450                 FN_DU1_DR2_Y4_DATA0, 0,
2451                 /* IP1_4 [1] */
2452                 FN_DU0_CDE, 0,
2453                 /* IP1_3 [1] */
2454                 FN_DU0_DISP, 0,
2455                 /* IP1_2 [1] */
2456                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
2457                 /* IP1_1 [1] */
2458                 FN_DU0_EXVSYNC_DU0_VSYNC, 0,
2459                 /* IP1_0 [1] */
2460                 FN_DU0_EXHSYNC_DU0_HSYNC, 0 }
2461         },
2462         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2463                              4, 4,
2464                              4, 3, 1,
2465                              1, 1, 1, 1, 1, 1, 1, 1,
2466                              1, 1, 1, 1, 1, 1, 1, 1) {
2467                 /* IP2_31_28 [4] */
2468                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2469                 /* IP2_27_24 [4] */
2470                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2471                 /* IP2_23_20 [4] */
2472                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2473                 /* IP2_19_17 [3] */
2474                 0, 0, 0, 0, 0, 0, 0, 0,
2475                 /* IP2_16 [1] */
2476                 FN_VI2_FIELD, FN_AVB_TXD2,
2477                 /* IP2_15 [1] */
2478                 FN_VI2_D11_Y3, FN_AVB_TXD1,
2479                 /* IP2_14 [1] */
2480                 FN_VI2_D10_Y2, FN_AVB_TXD0,
2481                 /* IP2_13 [1] */
2482                 FN_VI2_D9_Y1, FN_AVB_TX_EN,
2483                 /* IP2_12 [1] */
2484                 FN_VI2_D8_Y0, FN_AVB_TXD3,
2485                 /* IP2_11 [1] */
2486                 FN_VI2_D7_C7, FN_AVB_COL,
2487                 /* IP2_10 [1] */
2488                 FN_VI2_D6_C6, FN_AVB_RX_ER,
2489                 /* IP2_9 [1] */
2490                 FN_VI2_D5_C5, FN_AVB_RXD7,
2491                 /* IP2_8 [1] */
2492                 FN_VI2_D4_C4, FN_AVB_RXD6,
2493                 /* IP2_7 [1] */
2494                 FN_VI2_D3_C3, FN_AVB_RXD5,
2495                 /* IP2_6 [1] */
2496                 FN_VI2_D2_C2, FN_AVB_RXD4,
2497                 /* IP2_5 [1] */
2498                 FN_VI2_D1_C1, FN_AVB_RXD3,
2499                 /* IP2_4 [1] */
2500                 FN_VI2_D0_C0, FN_AVB_RXD2,
2501                 /* IP2_3 [1] */
2502                 FN_VI2_VSYNC_N, FN_AVB_RXD1,
2503                 /* IP2_2 [1] */
2504                 FN_VI2_HSYNC_N, FN_AVB_RXD0,
2505                 /* IP2_1 [1] */
2506                 FN_VI2_CLKENB, FN_AVB_RX_DV,
2507                 /* IP2_0 [1] */
2508                 FN_VI2_CLK, FN_AVB_RX_CLK }
2509         },
2510         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2511                              4, 4,
2512                              4, 4,
2513                              1, 1, 1, 1, 1, 1, 1, 1,
2514                              1, 1, 1, 1, 1, 1, 1, 1) {
2515                 /* IP3_31_28 [4] */
2516                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2517                 /* IP3_27_24 [4] */
2518                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2519                 /* IP3_23_20 [4] */
2520                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2521                 /* IP3_19_16 [4] */
2522                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2523                 /* IP3_15 [1] */
2524                 0, 0,
2525                 /* IP3_14 [1] */
2526                 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
2527                 /* IP3_13 [1] */
2528                 FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
2529                 /* IP3_12 [1] */
2530                 FN_VI3_D8_Y0, FN_AVB_CRS,
2531                 /* IP3_11 [1] */
2532                 FN_VI3_D7_C7, FN_AVB_PHY_INT,
2533                 /* IP3_10 [1] */
2534                 FN_VI3_D6_C6, FN_AVB_MAGIC,
2535                 /* IP3_9 [1] */
2536                 FN_VI3_D5_C5, FN_AVB_LINK,
2537                 /* IP3_8 [1] */
2538                 FN_VI3_D4_C4, FN_AVB_MDIO,
2539                 /* IP3_7 [1] */
2540                 FN_VI3_D3_C3, FN_AVB_MDC,
2541                 /* IP3_6 [1] */
2542                 FN_VI3_D2_C2, FN_AVB_GTX_CLK,
2543                 /* IP3_5 [1] */
2544                 FN_VI3_D1_C1, FN_AVB_TX_ER,
2545                 /* IP3_4 [1] */
2546                 FN_VI3_D0_C0, FN_AVB_TXD7,
2547                 /* IP3_3 [1] */
2548                 FN_VI3_VSYNC_N, FN_AVB_TXD6,
2549                 /* IP3_2 [1] */
2550                 FN_VI3_HSYNC_N, FN_AVB_TXD5,
2551                 /* IP3_1 [1] */
2552                 FN_VI3_CLKENB, FN_AVB_TXD4,
2553                 /* IP3_0 [1] */
2554                 FN_VI3_CLK, FN_AVB_TX_CLK }
2555         },
2556         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2557                              4, 3, 1,
2558                              1, 1, 1, 2, 2, 2,
2559                              2, 2, 2, 2, 2, 1, 2, 1, 1) {
2560                 /* IP4_31_28 [4] */
2561                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2562                 /* IP4_27_25 [3] */
2563                 0, 0, 0, 0, 0, 0, 0, 0,
2564                 /* IP4_24 [1] */
2565                 FN_VI4_FIELD, FN_VI3_D15_Y7,
2566                 /* IP4_23 [1] */
2567                 FN_VI4_D11_Y3, FN_VI3_D14_Y6,
2568                 /* IP4_22 [1] */
2569                 FN_VI4_D10_Y2, FN_VI3_D13_Y5,
2570                 /* IP4_21 [1] */
2571                 FN_VI4_D9_Y1, FN_VI3_D12_Y4,
2572                 /* IP4_20_19 [2] */
2573                 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
2574                 /* IP4_18_17 [2] */
2575                 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
2576                 /* IP4_16_15 [2] */
2577                 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
2578                 /* IP4_14_13 [2] */
2579                 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
2580                 /* IP4_12_11 [2] */
2581                 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
2582                 /* IP4_10_9 [2] */
2583                 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
2584                 /* IP4_8_7 [2] */
2585                 FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
2586                 /* IP4_6_5 [2] */
2587                 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
2588                 /* IP4_4 [1] */
2589                 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
2590                 /* IP4_3_2 [2] */
2591                 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
2592                 /* IP4_1 [1] */
2593                 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
2594                 /* IP4_0 [1] */
2595                 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 }
2596         },
2597         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2598                              4, 4,
2599                              4, 4,
2600                              4, 1, 1, 1, 1,
2601                              1, 1, 1, 1, 1, 1, 1, 1) {
2602                 /* IP5_31_28 [4] */
2603                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2604                 /* IP5_27_24 [4] */
2605                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2606                 /* IP5_23_20 [4] */
2607                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2608                 /* IP5_19_16 [4] */
2609                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2610                 /* IP5_15_12 [4] */
2611                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2612                 /* IP5_11 [1] */
2613                 FN_VI5_D8_Y0, FN_VI1_D23_R7,
2614                 /* IP5_10 [1] */
2615                 FN_VI5_D7_C7, FN_VI1_D22_R6,
2616                 /* IP5_9 [1] */
2617                 FN_VI5_D6_C6, FN_VI1_D21_R5,
2618                 /* IP5_8 [1] */
2619                 FN_VI5_D5_C5, FN_VI1_D20_R4,
2620                 /* IP5_7 [1] */
2621                 FN_VI5_D4_C4, FN_VI1_D19_R3,
2622                 /* IP5_6 [1] */
2623                 FN_VI5_D3_C3, FN_VI1_D18_R2,
2624                 /* IP5_5 [1] */
2625                 FN_VI5_D2_C2, FN_VI1_D17_R1,
2626                 /* IP5_4 [1] */
2627                 FN_VI5_D1_C1, FN_VI1_D16_R0,
2628                 /* IP5_3 [1] */
2629                 FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
2630                 /* IP5_2 [1] */
2631                 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
2632                 /* IP5_1 [1] */
2633                 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
2634                 /* IP5_0 [1] */
2635                 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B }
2636         },
2637         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2638                              4, 4,
2639                              4, 1, 2, 1,
2640                              2, 2, 2, 2,
2641                              1, 1, 1, 1, 1, 1, 1, 1) {
2642                 /* IP6_31_28 [4] */
2643                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2644                 /* IP6_27_24 [4] */
2645                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2646                 /* IP6_23_20 [4] */
2647                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2648                 /* IP6_19 [1] */
2649                 0, 0,
2650                 /* IP6_18_17 [2] */
2651                 FN_DREQ1_N, FN_RX3, 0, 0,
2652                 /* IP6_16 [1] */
2653                 FN_TX3, 0,
2654                 /* IP6_15_14 [2] */
2655                 FN_DACK1, FN_SCK3, 0, 0,
2656                 /* IP6_13_12 [2] */
2657                 FN_DREQ0_N, FN_RX2, 0, 0,
2658                 /* IP6_11_10 [2] */
2659                 FN_DACK0, FN_TX2, 0, 0,
2660                 /* IP6_9_8 [2] */
2661                 FN_DRACK0, FN_SCK2, 0, 0,
2662                 /* IP6_7 [1] */
2663                 FN_MSIOF1_RXD, FN_HRX1,
2664                 /* IP6_6 [1] */
2665                 FN_MSIOF1_TXD, FN_HTX1,
2666                 /* IP6_5 [1] */
2667                 FN_MSIOF1_SYNC, FN_HRTS1_N,
2668                 /* IP6_4 [1] */
2669                 FN_MSIOF1_SCK, FN_HSCK1,
2670                 /* IP6_3 [1] */
2671                 FN_MSIOF0_RXD, FN_HRX0,
2672                 /* IP6_2 [1] */
2673                 FN_MSIOF0_TXD, FN_HTX0,
2674                 /* IP6_1 [1] */
2675                 FN_MSIOF0_SYNC, FN_HCTS0_N,
2676                 /* IP6_0 [1] */
2677                 FN_MSIOF0_SCK, FN_HSCK0 }
2678         },
2679         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2680                              4, 4,
2681                              3, 1, 1, 1, 1, 1,
2682                              2, 2, 2, 2,
2683                              1, 1, 2, 2, 2) {
2684                 /* IP7_31_28 [4] */
2685                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2686                 /* IP7_27_24 [4] */
2687                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2688                 /* IP7_23_21 [3] */
2689                 0, 0, 0, 0, 0, 0, 0, 0,
2690                 /* IP7_20 [1] */
2691                 FN_AUDIO_CLKB, 0,
2692                 /* IP7_19 [1] */
2693                 FN_AUDIO_CLKA, 0,
2694                 /* IP7_18 [1] */
2695                 FN_AUDIO_CLKOUT, 0,
2696                 /* IP7_17 [1] */
2697                 FN_SSI_SDATA4, 0,
2698                 /* IP7_16 [1] */
2699                 FN_SSI_WS4, 0,
2700                 /* IP7_15_14 [2] */
2701                 FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
2702                 /* IP7_13_12 [2] */
2703                 FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
2704                 /* IP7_11_10 [2] */
2705                 FN_SSI_WS34, FN_TPU0TO1, 0, 0,
2706                 /* IP7_9_8 [2] */
2707                 FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
2708                 /* IP7_7 [1] */
2709                 FN_PWM4, 0,
2710                 /* IP7_6 [1] */
2711                 FN_PWM3, 0,
2712                 /* IP7_5_4 [2] */
2713                 FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
2714                 /* IP7_3_2 [2] */
2715                 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
2716                 /* IP7_1_0 [2] */
2717                 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 }
2718         },
2719         { },
2720 };
2721
2722 const struct sh_pfc_soc_info r8a7792_pinmux_info = {
2723         .name = "r8a77920_pfc",
2724         .unlock_reg = 0xe6060000, /* PMMR */
2725
2726         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2727
2728         .pins = pinmux_pins,
2729         .nr_pins = ARRAY_SIZE(pinmux_pins),
2730         .groups = pinmux_groups,
2731         .nr_groups = ARRAY_SIZE(pinmux_groups),
2732         .functions = pinmux_functions,
2733         .nr_functions = ARRAY_SIZE(pinmux_functions),
2734
2735         .cfg_regs = pinmux_config_regs,
2736
2737         .pinmux_data = pinmux_data,
2738         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2739 };