drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c

   1 /*
   2  * R8A7795 ES1.x processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2015-2017  Renesas Electronics Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  */
  10
  11 #include <linux/kernel.h>
  12
  13 #include "core.h"
  14 #include "sh_pfc.h"
  15
  16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  17                    SH_PFC_PIN_CFG_PULL_UP | \
  18                    SH_PFC_PIN_CFG_PULL_DOWN)
  19
  20 #define CPU_ALL_PORT(fn, sfx)                                           \
  21         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  22         PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS),  \
  23         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  24         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  25         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  26         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  27         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  28         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  29         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  30         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  31         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  32         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  33 /*
  34  * F_() : just information
  35  * FM() : macro for FN_xxx / xxx_MARK
  36  */
  37
  38 /* GPSR0 */
  39 #define GPSR0_15        F_(D15,                 IP7_11_8)
  40 #define GPSR0_14        F_(D14,                 IP7_7_4)
  41 #define GPSR0_13        F_(D13,                 IP7_3_0)
  42 #define GPSR0_12        F_(D12,                 IP6_31_28)
  43 #define GPSR0_11        F_(D11,                 IP6_27_24)
  44 #define GPSR0_10        F_(D10,                 IP6_23_20)
  45 #define GPSR0_9         F_(D9,                  IP6_19_16)
  46 #define GPSR0_8         F_(D8,                  IP6_15_12)
  47 #define GPSR0_7         F_(D7,                  IP6_11_8)
  48 #define GPSR0_6         F_(D6,                  IP6_7_4)
  49 #define GPSR0_5         F_(D5,                  IP6_3_0)
  50 #define GPSR0_4         F_(D4,                  IP5_31_28)
  51 #define GPSR0_3         F_(D3,                  IP5_27_24)
  52 #define GPSR0_2         F_(D2,                  IP5_23_20)
  53 #define GPSR0_1         F_(D1,                  IP5_19_16)
  54 #define GPSR0_0         F_(D0,                  IP5_15_12)
  55
  56 /* GPSR1 */
  57 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  58 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  59 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  60 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  61 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  62 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  63 #define GPSR1_21        F_(CS1_N_A26,           IP4_19_16)
  64 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  65 #define GPSR1_19        F_(A19,                 IP4_11_8)
  66 #define GPSR1_18        F_(A18,                 IP4_7_4)
  67 #define GPSR1_17        F_(A17,                 IP4_3_0)
  68 #define GPSR1_16        F_(A16,                 IP3_31_28)
  69 #define GPSR1_15        F_(A15,                 IP3_27_24)
  70 #define GPSR1_14        F_(A14,                 IP3_23_20)
  71 #define GPSR1_13        F_(A13,                 IP3_19_16)
  72 #define GPSR1_12        F_(A12,                 IP3_15_12)
  73 #define GPSR1_11        F_(A11,                 IP3_11_8)
  74 #define GPSR1_10        F_(A10,                 IP3_7_4)
  75 #define GPSR1_9         F_(A9,                  IP3_3_0)
  76 #define GPSR1_8         F_(A8,                  IP2_31_28)
  77 #define GPSR1_7         F_(A7,                  IP2_27_24)
  78 #define GPSR1_6         F_(A6,                  IP2_23_20)
  79 #define GPSR1_5         F_(A5,                  IP2_19_16)
  80 #define GPSR1_4         F_(A4,                  IP2_15_12)
  81 #define GPSR1_3         F_(A3,                  IP2_11_8)
  82 #define GPSR1_2         F_(A2,                  IP2_7_4)
  83 #define GPSR1_1         F_(A1,                  IP2_3_0)
  84 #define GPSR1_0         F_(A0,                  IP1_31_28)
  85
  86 /* GPSR2 */
  87 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  88 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  89 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  90 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  91 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  92 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
  93 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
  94 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
  95 #define GPSR2_6         F_(PWM0,                IP1_19_16)
  96 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
  97 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
  98 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
  99 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
 100 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 101 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 102
 103 /* GPSR3 */
 104 #define GPSR3_15        F_(SD1_WP,              IP10_23_20)
 105 #define GPSR3_14        F_(SD1_CD,              IP10_19_16)
 106 #define GPSR3_13        F_(SD0_WP,              IP10_15_12)
 107 #define GPSR3_12        F_(SD0_CD,              IP10_11_8)
 108 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 109 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 110 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 111 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 112 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 113 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 114 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 115 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 116 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 117 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 118 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 119 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 120
 121 /* GPSR4 */
 122 #define GPSR4_17        FM(SD3_DS)
 123 #define GPSR4_16        F_(SD3_DAT7,            IP10_7_4)
 124 #define GPSR4_15        F_(SD3_DAT6,            IP10_3_0)
 125 #define GPSR4_14        F_(SD3_DAT5,            IP9_31_28)
 126 #define GPSR4_13        F_(SD3_DAT4,            IP9_27_24)
 127 #define GPSR4_12        FM(SD3_DAT3)
 128 #define GPSR4_11        FM(SD3_DAT2)
 129 #define GPSR4_10        FM(SD3_DAT1)
 130 #define GPSR4_9         FM(SD3_DAT0)
 131 #define GPSR4_8         FM(SD3_CMD)
 132 #define GPSR4_7         FM(SD3_CLK)
 133 #define GPSR4_6         F_(SD2_DS,              IP9_23_20)
 134 #define GPSR4_5         F_(SD2_DAT3,            IP9_19_16)
 135 #define GPSR4_4         F_(SD2_DAT2,            IP9_15_12)
 136 #define GPSR4_3         F_(SD2_DAT1,            IP9_11_8)
 137 #define GPSR4_2         F_(SD2_DAT0,            IP9_7_4)
 138 #define GPSR4_1         FM(SD2_CMD)
 139 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 140
 141 /* GPSR5 */
 142 #define GPSR5_25        F_(MLB_DAT,             IP13_19_16)
 143 #define GPSR5_24        F_(MLB_SIG,             IP13_15_12)
 144 #define GPSR5_23        F_(MLB_CLK,             IP13_11_8)
 145 #define GPSR5_22        FM(MSIOF0_RXD)
 146 #define GPSR5_21        F_(MSIOF0_SS2,          IP13_7_4)
 147 #define GPSR5_20        FM(MSIOF0_TXD)
 148 #define GPSR5_19        F_(MSIOF0_SS1,          IP13_3_0)
 149 #define GPSR5_18        F_(MSIOF0_SYNC,         IP12_31_28)
 150 #define GPSR5_17        FM(MSIOF0_SCK)
 151 #define GPSR5_16        F_(HRTS0_N,             IP12_27_24)
 152 #define GPSR5_15        F_(HCTS0_N,             IP12_23_20)
 153 #define GPSR5_14        F_(HTX0,                IP12_19_16)
 154 #define GPSR5_13        F_(HRX0,                IP12_15_12)
 155 #define GPSR5_12        F_(HSCK0,               IP12_11_8)
 156 #define GPSR5_11        F_(RX2_A,               IP12_7_4)
 157 #define GPSR5_10        F_(TX2_A,               IP12_3_0)
 158 #define GPSR5_9         F_(SCK2,                IP11_31_28)
 159 #define GPSR5_8         F_(RTS1_N_TANS,         IP11_27_24)
 160 #define GPSR5_7         F_(CTS1_N,              IP11_23_20)
 161 #define GPSR5_6         F_(TX1_A,               IP11_19_16)
 162 #define GPSR5_5         F_(RX1_A,               IP11_15_12)
 163 #define GPSR5_4         F_(RTS0_N_TANS,         IP11_11_8)
 164 #define GPSR5_3         F_(CTS0_N,              IP11_7_4)
 165 #define GPSR5_2         F_(TX0,                 IP11_3_0)
 166 #define GPSR5_1         F_(RX0,                 IP10_31_28)
 167 #define GPSR5_0         F_(SCK0,                IP10_27_24)
 168
 169 /* GPSR6 */
 170 #define GPSR6_31        F_(USB31_OVC,           IP17_7_4)
 171 #define GPSR6_30        F_(USB31_PWEN,          IP17_3_0)
 172 #define GPSR6_29        F_(USB30_OVC,           IP16_31_28)
 173 #define GPSR6_28        F_(USB30_PWEN,          IP16_27_24)
 174 #define GPSR6_27        F_(USB1_OVC,            IP16_23_20)
 175 #define GPSR6_26        F_(USB1_PWEN,           IP16_19_16)
 176 #define GPSR6_25        F_(USB0_OVC,            IP16_15_12)
 177 #define GPSR6_24        F_(USB0_PWEN,           IP16_11_8)
 178 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP16_7_4)
 179 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP16_3_0)
 180 #define GPSR6_21        F_(SSI_SDATA9_A,        IP15_31_28)
 181 #define GPSR6_20        F_(SSI_SDATA8,          IP15_27_24)
 182 #define GPSR6_19        F_(SSI_SDATA7,          IP15_23_20)
 183 #define GPSR6_18        F_(SSI_WS78,            IP15_19_16)
 184 #define GPSR6_17        F_(SSI_SCK78,           IP15_15_12)
 185 #define GPSR6_16        F_(SSI_SDATA6,          IP15_11_8)
 186 #define GPSR6_15        F_(SSI_WS6,             IP15_7_4)
 187 #define GPSR6_14        F_(SSI_SCK6,            IP15_3_0)
 188 #define GPSR6_13        FM(SSI_SDATA5)
 189 #define GPSR6_12        FM(SSI_WS5)
 190 #define GPSR6_11        FM(SSI_SCK5)
 191 #define GPSR6_10        F_(SSI_SDATA4,          IP14_31_28)
 192 #define GPSR6_9         F_(SSI_WS4,             IP14_27_24)
 193 #define GPSR6_8         F_(SSI_SCK4,            IP14_23_20)
 194 #define GPSR6_7         F_(SSI_SDATA3,          IP14_19_16)
 195 #define GPSR6_6         F_(SSI_WS349,           IP14_15_12)
 196 #define GPSR6_5         F_(SSI_SCK349,          IP14_11_8)
 197 #define GPSR6_4         F_(SSI_SDATA2_A,        IP14_7_4)
 198 #define GPSR6_3         F_(SSI_SDATA1_A,        IP14_3_0)
 199 #define GPSR6_2         F_(SSI_SDATA0,          IP13_31_28)
 200 #define GPSR6_1         F_(SSI_WS01239,         IP13_27_24)
 201 #define GPSR6_0         F_(SSI_SCK01239,        IP13_23_20)
 202
 203 /* GPSR7 */
 204 #define GPSR7_3         FM(HDMI1_CEC)
 205 #define GPSR7_2         FM(HDMI0_CEC)
 206 #define GPSR7_1         FM(AVS2)
 207 #define GPSR7_0         FM(AVS1)
 208
 209
 210 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 211 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 212 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 213 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 214 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 215 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 216 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_TANS_A)               F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 217 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 218 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   FM(A25)                 FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    FM(A24)                 FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    FM(A23)                 FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)FM(A22)                 F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        FM(A21)                 FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        FM(A20)                 FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230
 231 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 232 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_TANS_B)               F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 245 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 246 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 247 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP4_19_16       FM(CS1_N_A26)           F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N_TANS)                 FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3)             F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272 #define IP7_15_12       FM(FSCLKST)             F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274
 275 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 276 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 277 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 278 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       F_(0, 0)                        F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP9_7_4         FM(SD2_DAT0)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP9_11_8        FM(SD2_DAT1)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP9_15_12       FM(SD2_DAT2)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP9_19_16       FM(SD2_DAT3)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP9_23_20       FM(SD2_DS)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP9_27_24       FM(SD3_DAT4)            FM(SD2_CD_A)    F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP9_31_28       FM(SD3_DAT5)            FM(SD2_WP_A)    F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP10_3_0        FM(SD3_DAT6)            FM(SD3_CD)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP10_7_4        FM(SD3_DAT7)            FM(SD3_WP)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP10_11_8       FM(SD0_CD)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP10_15_12      FM(SD0_WP)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP10_19_16      FM(SD1_CD)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP10_23_20      FM(SD1_WP)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP10_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP10_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP11_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP11_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP11_11_8       FM(RTS0_N_TANS)         FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP11_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP11_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP11_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP11_27_24      FM(RTS1_N_TANS)         FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP11_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311 #define IP12_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_B) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312 #define IP12_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_B) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 313 #define IP12_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 314 #define IP12_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315 #define IP12_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP12_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP12_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318
 319 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 320 #define IP12_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP13_3_0        FM(MSIOF0_SS1)          FM(RX5)         F_(0, 0)                FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP13_7_4        FM(MSIOF0_SS2)          FM(TX5)         FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP13_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP13_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP13_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP13_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP13_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP13_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP14_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP14_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP14_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP14_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP14_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP14_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 335 #define IP14_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336 #define IP14_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP15_3_0        FM(SSI_SCK6)            FM(USB2_PWEN)   F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP15_7_4        FM(SSI_WS6)             FM(USB2_OVC)    F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP15_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP15_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341 #define IP15_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342 #define IP15_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 343 #define IP15_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 344 #define IP15_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP16_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(CC5_OSCOUT)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP16_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP16_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP16_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP16_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP16_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP16_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP16_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_B)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP17_3_0        FM(USB31_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP17_7_4        FM(USB31_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355
 356 #define PINMUX_GPSR     \
 357 \
 358                                                                                                 GPSR6_31 \
 359                                                                                                 GPSR6_30 \
 360                                                                                                 GPSR6_29 \
 361                                                                                                 GPSR6_28 \
 362                 GPSR1_27                                                                        GPSR6_27 \
 363                 GPSR1_26                                                                        GPSR6_26 \
 364                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 365                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 366                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 367                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 368                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 369                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 370                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 371                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 372                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 373                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 374 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 375 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 376 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 377 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 378 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 379 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 380 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 381 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 382 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 383 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 384 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 385 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 386 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 387 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 388 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 389 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 390
 391 #define PINMUX_IPSR                             \
 392 \
 393 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 394 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 395 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 396 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 397 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 398 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 399 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 400 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 401 \
 402 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 403 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 404 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 405 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12       FM(IP7_15_12)   IP7_15_12 \
 406 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 407 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 408 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 409 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 410 \
 411 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 412 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 413 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 414 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 415 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 416 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 417 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 418 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 419 \
 420 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 421 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 422 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 423 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 424 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 425 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 426 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 427 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 428 \
 429 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0 \
 430 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4 \
 431 FM(IP16_11_8)   IP16_11_8 \
 432 FM(IP16_15_12)  IP16_15_12 \
 433 FM(IP16_19_16)  IP16_19_16 \
 434 FM(IP16_23_20)  IP16_23_20 \
 435 FM(IP16_27_24)  IP16_27_24 \
 436 FM(IP16_31_28)  IP16_31_28
 437
 438 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 439 #define MOD_SEL0_30_29          FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)
 440 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 441 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 442 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 443 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 444 #define MOD_SEL0_21_20          FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)
 445 #define MOD_SEL0_19             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 446 #define MOD_SEL0_18             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 447 #define MOD_SEL0_17             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 448 #define MOD_SEL0_16_15          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 449 #define MOD_SEL0_14             FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)
 450 #define MOD_SEL0_13             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 451 #define MOD_SEL0_12             FM(SEL_FSO_0)           FM(SEL_FSO_1)
 452 #define MOD_SEL0_11             FM(SEL_FM_0)            FM(SEL_FM_1)
 453 #define MOD_SEL0_10             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 454 #define MOD_SEL0_9              FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 455 #define MOD_SEL0_8              FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 456 #define MOD_SEL0_7_6            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 457 #define MOD_SEL0_5_4            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 458 #define MOD_SEL0_3              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 459 #define MOD_SEL0_2_1            FM(SEL_ADG_0)           FM(SEL_ADG_1)           FM(SEL_ADG_2)           FM(SEL_ADG_3)
 460
 461 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 462 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 463 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 464 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 465 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 466 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 467 #define MOD_SEL1_20             FM(SEL_SSI_0)           FM(SEL_SSI_1)
 468 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 469 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 470 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 471 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 472 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 473 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 474 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 475 #define MOD_SEL1_10             FM(SEL_SATA_0)          FM(SEL_SATA_1)
 476 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 477 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 478 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 479 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 480 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 481 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 482 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 483 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 484
 485 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */
 486 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 487 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 488 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 489 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 490
 491 #define PINMUX_MOD_SELS\
 492 \
 493                         MOD_SEL1_31_30          MOD_SEL2_31 \
 494 MOD_SEL0_30_29                                  MOD_SEL2_30 \
 495                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 496 MOD_SEL0_28_27 \
 497 \
 498 MOD_SEL0_26_25_24       MOD_SEL1_26 \
 499                         MOD_SEL1_25_24 \
 500 \
 501 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 502 MOD_SEL0_22 \
 503 MOD_SEL0_21_20 \
 504                         MOD_SEL1_20 \
 505 MOD_SEL0_19             MOD_SEL1_19 \
 506 MOD_SEL0_18             MOD_SEL1_18_17 \
 507 MOD_SEL0_17 \
 508 MOD_SEL0_16_15          MOD_SEL1_16 \
 509                         MOD_SEL1_15_14 \
 510 MOD_SEL0_14 \
 511 MOD_SEL0_13             MOD_SEL1_13 \
 512 MOD_SEL0_12             MOD_SEL1_12 \
 513 MOD_SEL0_11             MOD_SEL1_11 \
 514 MOD_SEL0_10             MOD_SEL1_10 \
 515 MOD_SEL0_9              MOD_SEL1_9 \
 516 MOD_SEL0_8 \
 517 MOD_SEL0_7_6 \
 518                         MOD_SEL1_6 \
 519 MOD_SEL0_5_4            MOD_SEL1_5 \
 520                         MOD_SEL1_4 \
 521 MOD_SEL0_3              MOD_SEL1_3 \
 522 MOD_SEL0_2_1            MOD_SEL1_2 \
 523                         MOD_SEL1_1 \
 524                         MOD_SEL1_0              MOD_SEL2_0
 525
 526 /*
 527  * These pins are not able to be muxed but have other properties
 528  * that can be set, such as drive-strength or pull-up/pull-down enable.
 529  */
 530 #define PINMUX_STATIC \
 531         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 532         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 533         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 534         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 535         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 536         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 537         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 538         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 539         FM(CLKOUT) FM(PRESETOUT) \
 540         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
 541         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 542
 543 enum {
 544         PINMUX_RESERVED = 0,
 545
 546         PINMUX_DATA_BEGIN,
 547         GP_ALL(DATA),
 548         PINMUX_DATA_END,
 549
 550 #define F_(x, y)
 551 #define FM(x)   FN_##x,
 552         PINMUX_FUNCTION_BEGIN,
 553         GP_ALL(FN),
 554         PINMUX_GPSR
 555         PINMUX_IPSR
 556         PINMUX_MOD_SELS
 557         PINMUX_FUNCTION_END,
 558 #undef F_
 559 #undef FM
 560
 561 #define F_(x, y)
 562 #define FM(x)   x##_MARK,
 563         PINMUX_MARK_BEGIN,
 564         PINMUX_GPSR
 565         PINMUX_IPSR
 566         PINMUX_MOD_SELS
 567         PINMUX_STATIC
 568         PINMUX_MARK_END,
 569 #undef F_
 570 #undef FM
 571 };
 572
 573 static const u16 pinmux_data[] = {
 574         PINMUX_DATA_GP_ALL(),
 575
 576         PINMUX_SINGLE(AVS1),
 577         PINMUX_SINGLE(AVS2),
 578         PINMUX_SINGLE(HDMI0_CEC),
 579         PINMUX_SINGLE(HDMI1_CEC),
 580         PINMUX_SINGLE(I2C_SEL_0_1),
 581         PINMUX_SINGLE(I2C_SEL_3_1),
 582         PINMUX_SINGLE(I2C_SEL_5_1),
 583         PINMUX_SINGLE(MSIOF0_RXD),
 584         PINMUX_SINGLE(MSIOF0_SCK),
 585         PINMUX_SINGLE(MSIOF0_TXD),
 586         PINMUX_SINGLE(SD2_CMD),
 587         PINMUX_SINGLE(SD3_CLK),
 588         PINMUX_SINGLE(SD3_CMD),
 589         PINMUX_SINGLE(SD3_DAT0),
 590         PINMUX_SINGLE(SD3_DAT1),
 591         PINMUX_SINGLE(SD3_DAT2),
 592         PINMUX_SINGLE(SD3_DAT3),
 593         PINMUX_SINGLE(SD3_DS),
 594         PINMUX_SINGLE(SSI_SCK5),
 595         PINMUX_SINGLE(SSI_SDATA5),
 596         PINMUX_SINGLE(SSI_WS5),
 597
 598         /* IPSR0 */
 599         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 600         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 601
 602         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 603         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 604         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 605
 606         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 607         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 608         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 609
 610         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 611         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 612         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 613
 614         PINMUX_IPSR_MSEL(IP0_19_16,     AVB_AVTP_MATCH_A,       SEL_ETHERAVB_0),
 615         PINMUX_IPSR_MSEL(IP0_19_16,     MSIOF2_RXD_C,           SEL_MSIOF2_2),
 616         PINMUX_IPSR_MSEL(IP0_19_16,     CTS4_N_A,               SEL_SCIF4_0),
 617
 618         PINMUX_IPSR_MSEL(IP0_23_20,     AVB_AVTP_CAPTURE_A,     SEL_ETHERAVB_0),
 619         PINMUX_IPSR_MSEL(IP0_23_20,     MSIOF2_TXD_C,           SEL_MSIOF2_2),
 620         PINMUX_IPSR_MSEL(IP0_23_20,     RTS4_N_TANS_A,          SEL_SCIF4_0),
 621
 622         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 623         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 624         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 625         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 626         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 627         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 628
 629         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 630         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 631         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 632         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 633         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 634         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 635
 636         /* IPSR1 */
 637         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 638         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 639         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 640         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 641         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 642
 643         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 644         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 645         PINMUX_IPSR_GPSR(IP1_7_4,       A25),
 646         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 647         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 648         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 649
 650         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 651         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 652         PINMUX_IPSR_GPSR(IP1_11_8,      A24),
 653         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 654         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 655         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 656
 657         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 658         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 659         PINMUX_IPSR_GPSR(IP1_15_12,     A23),
 660         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 661         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 662         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 663
 664         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 665         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 666         PINMUX_IPSR_GPSR(IP1_19_16,     A22),
 667         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 668         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 669
 670         PINMUX_IPSR_MSEL(IP1_23_20,     PWM1_A,                 SEL_PWM1_0),
 671         PINMUX_IPSR_GPSR(IP1_23_20,     A21),
 672         PINMUX_IPSR_MSEL(IP1_23_20,     HRX3_D,                 SEL_HSCIF3_3),
 673         PINMUX_IPSR_MSEL(IP1_23_20,     VI4_DATA7_B,            SEL_VIN4_1),
 674         PINMUX_IPSR_MSEL(IP1_23_20,     IERX_B,                 SEL_IEBUS_1),
 675
 676         PINMUX_IPSR_MSEL(IP1_27_24,     PWM2_A,                 SEL_PWM2_0),
 677         PINMUX_IPSR_GPSR(IP1_27_24,     A20),
 678         PINMUX_IPSR_MSEL(IP1_27_24,     HTX3_D,                 SEL_HSCIF3_3),
 679         PINMUX_IPSR_MSEL(IP1_27_24,     IETX_B,                 SEL_IEBUS_1),
 680
 681         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 682         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 683         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 684         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 685         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 686         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 687
 688         /* IPSR2 */
 689         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 690         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 691         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 692         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 693         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 694         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 695
 696         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 697         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 698         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 699         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 700         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 701         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 702
 703         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 704         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 705         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 706         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 707         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 708         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 709
 710         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 711         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 712         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 713         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 714         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 715         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 716
 717         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 718         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 719         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 720         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 721         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 722         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 723         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 724
 725         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 726         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 727         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 728         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 729         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 730         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 731         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 732
 733         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 734         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 735         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 736         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 737         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 738         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 739         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 740
 741         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 742         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 743         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 744         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 745         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 746         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 747         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 748
 749         /* IPSR3 */
 750         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 751         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 752         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 753         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 754
 755         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 756         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 757         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_TANS_B,          SEL_SCIF4_1),
 758         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 759
 760         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 761         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 762         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 763         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 764         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 765         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 766         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 767         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 768         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 769
 770         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 771         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 772         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 773         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 774         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 775         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 776
 777         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 778         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 779         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 780         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 781         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 782         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 783
 784         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 785         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 786         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 787         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 788         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 789         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 790
 791         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 792         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 793         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 794         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 795         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 796         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 797
 798         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 799         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 800         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 801         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 802
 803         /* IPSR4 */
 804         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 805         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 806         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 807         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 808
 809         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 810         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 811         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 812         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 813
 814         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 815         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 816         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 817         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 818
 819         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 820         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 821
 822         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N_A26),
 823         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 824         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 825
 826         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 827         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 828         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 829         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 830         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 831         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 832         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 833         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 834
 835         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 836         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 837         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 838         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 839         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 840         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 841
 842         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 843         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 844         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 845         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 846         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 847         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 848
 849         /* IPSR5 */
 850         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 851         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 852         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 853         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 854         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 855         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 856         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 857
 858         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 859         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 860         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N_TANS),
 861         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 862         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 863         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 864         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 865         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 866
 867         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 868         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 869         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 870         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 871
 872         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 873         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 874         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 875         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 876         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 877
 878         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 879         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 880         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 881         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 882         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 883
 884         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 885         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 886         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 887         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 888
 889         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 890         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 891         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 892         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 893
 894         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 895         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 896         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 897         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 898
 899         /* IPSR6 */
 900         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 901         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 902         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 903         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 904
 905         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 906         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 907         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 908         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 909
 910         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 911         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 912         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 913         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 914
 915         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 916         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 917         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 918         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 919         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 920         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 921
 922         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 923         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 924         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 925         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 926         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 927
 928         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 929         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 930         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 931         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 932         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 933         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 934         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 935
 936         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 937         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 938         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 939         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 940         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 941         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_TANS_C,          SEL_SCIF4_2),
 942         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 943
 944         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 945         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 946         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 947         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 948         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 949         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 950
 951         /* IPSR7 */
 952         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 953         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 954         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 955         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 956         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 957         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 958
 959         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 960         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 961         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 962         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 963         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 964         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 965         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 966
 967         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 968         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 969         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 970         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 971         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 972         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 973         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 974
 975         PINMUX_IPSR_GPSR(IP7_15_12,     FSCLKST),
 976
 977         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 978         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 979         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 980
 981         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 982         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 983         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 984
 985         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
 986         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
 987         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
 988         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
 989
 990         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
 991         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
 992         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
 993         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
 994
 995         /* IPSR8 */
 996         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
 997         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
 998         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
 999         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1000
1001         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1002         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1003         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1004         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1005
1006         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1007         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1008         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1009
1010         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1011         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1012         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1013         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1014
1015         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1016         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1017         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1018         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1019         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1020
1021         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1022         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1023         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1024         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1025         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1026
1027         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1028         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1029         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1030         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1031         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1032
1033         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1034         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1035         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1036         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1037         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1038
1039         /* IPSR9 */
1040         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1041
1042         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_DAT0),
1043
1044         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT1),
1045
1046         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT2),
1047
1048         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT3),
1049
1050         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DS),
1051         PINMUX_IPSR_MSEL(IP9_23_20,     SATA_DEVSLP_B,          SEL_SATA_1),
1052
1053         PINMUX_IPSR_GPSR(IP9_27_24,     SD3_DAT4),
1054         PINMUX_IPSR_MSEL(IP9_27_24,     SD2_CD_A,               SEL_SDHI2_0),
1055
1056         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_DAT5),
1057         PINMUX_IPSR_MSEL(IP9_31_28,     SD2_WP_A,               SEL_SDHI2_0),
1058
1059         /* IPSR10 */
1060         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_DAT6),
1061         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CD),
1062
1063         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT7),
1064         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_WP),
1065
1066         PINMUX_IPSR_GPSR(IP10_11_8,     SD0_CD),
1067         PINMUX_IPSR_MSEL(IP10_11_8,     SCL2_B,                 SEL_I2C2_1),
1068         PINMUX_IPSR_MSEL(IP10_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1069
1070         PINMUX_IPSR_GPSR(IP10_15_12,    SD0_WP),
1071         PINMUX_IPSR_MSEL(IP10_15_12,    SDA2_B,                 SEL_I2C2_1),
1072
1073         PINMUX_IPSR_GPSR(IP10_19_16,    SD1_CD),
1074         PINMUX_IPSR_MSEL(IP10_19_16,    SIM0_CLK_B,             SEL_SIMCARD_1),
1075
1076         PINMUX_IPSR_GPSR(IP10_23_20,    SD1_WP),
1077         PINMUX_IPSR_MSEL(IP10_23_20,    SIM0_D_B,               SEL_SIMCARD_1),
1078
1079         PINMUX_IPSR_GPSR(IP10_27_24,    SCK0),
1080         PINMUX_IPSR_MSEL(IP10_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1081         PINMUX_IPSR_MSEL(IP10_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1082         PINMUX_IPSR_MSEL(IP10_27_24,    AUDIO_CLKC_B,           SEL_ADG_1),
1083         PINMUX_IPSR_MSEL(IP10_27_24,    SDA2_A,                 SEL_I2C2_0),
1084         PINMUX_IPSR_MSEL(IP10_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1085         PINMUX_IPSR_MSEL(IP10_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1086         PINMUX_IPSR_MSEL(IP10_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1087         PINMUX_IPSR_GPSR(IP10_27_24,    ADICHS2),
1088
1089         PINMUX_IPSR_GPSR(IP10_31_28,    RX0),
1090         PINMUX_IPSR_MSEL(IP10_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1091         PINMUX_IPSR_MSEL(IP10_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1092         PINMUX_IPSR_MSEL(IP10_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1093         PINMUX_IPSR_MSEL(IP10_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1094
1095         /* IPSR11 */
1096         PINMUX_IPSR_GPSR(IP11_3_0,      TX0),
1097         PINMUX_IPSR_MSEL(IP11_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1098         PINMUX_IPSR_MSEL(IP11_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1099         PINMUX_IPSR_MSEL(IP11_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1100         PINMUX_IPSR_MSEL(IP11_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1101
1102         PINMUX_IPSR_GPSR(IP11_7_4,      CTS0_N),
1103         PINMUX_IPSR_MSEL(IP11_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1104         PINMUX_IPSR_MSEL(IP11_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1105         PINMUX_IPSR_MSEL(IP11_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1106         PINMUX_IPSR_MSEL(IP11_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1107         PINMUX_IPSR_MSEL(IP11_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1108         PINMUX_IPSR_MSEL(IP11_7_4,      AUDIO_CLKOUT_C,         SEL_ADG_2),
1109         PINMUX_IPSR_GPSR(IP11_7_4,      ADICS_SAMP),
1110
1111         PINMUX_IPSR_GPSR(IP11_11_8,     RTS0_N_TANS),
1112         PINMUX_IPSR_MSEL(IP11_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1113         PINMUX_IPSR_MSEL(IP11_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1114         PINMUX_IPSR_MSEL(IP11_11_8,     AUDIO_CLKA_B,           SEL_ADG_1),
1115         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_A,                 SEL_I2C2_0),
1116         PINMUX_IPSR_MSEL(IP11_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1117         PINMUX_IPSR_MSEL(IP11_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1118         PINMUX_IPSR_GPSR(IP11_11_8,     ADICHS1),
1119
1120         PINMUX_IPSR_MSEL(IP11_15_12,    RX1_A,                  SEL_SCIF1_0),
1121         PINMUX_IPSR_MSEL(IP11_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1122         PINMUX_IPSR_MSEL(IP11_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1123         PINMUX_IPSR_MSEL(IP11_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1124         PINMUX_IPSR_MSEL(IP11_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1125
1126         PINMUX_IPSR_MSEL(IP11_19_16,    TX1_A,                  SEL_SCIF1_0),
1127         PINMUX_IPSR_MSEL(IP11_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1128         PINMUX_IPSR_MSEL(IP11_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1129         PINMUX_IPSR_MSEL(IP11_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1130         PINMUX_IPSR_MSEL(IP11_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1131
1132         PINMUX_IPSR_GPSR(IP11_23_20,    CTS1_N),
1133         PINMUX_IPSR_MSEL(IP11_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1134         PINMUX_IPSR_MSEL(IP11_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1135         PINMUX_IPSR_MSEL(IP11_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1136         PINMUX_IPSR_MSEL(IP11_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1137         PINMUX_IPSR_MSEL(IP11_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1138         PINMUX_IPSR_GPSR(IP11_23_20,    ADIDATA),
1139
1140         PINMUX_IPSR_GPSR(IP11_27_24,    RTS1_N_TANS),
1141         PINMUX_IPSR_MSEL(IP11_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1142         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1143         PINMUX_IPSR_MSEL(IP11_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1144         PINMUX_IPSR_MSEL(IP11_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1145         PINMUX_IPSR_MSEL(IP11_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1146         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS0),
1147
1148         PINMUX_IPSR_GPSR(IP11_31_28,    SCK2),
1149         PINMUX_IPSR_MSEL(IP11_31_28,    SCIF_CLK_B,             SEL_SCIF1_1),
1150         PINMUX_IPSR_MSEL(IP11_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1151         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1152         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1153         PINMUX_IPSR_MSEL(IP11_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1154         PINMUX_IPSR_GPSR(IP11_31_28,    ADICLK),
1155
1156         /* IPSR12 */
1157         PINMUX_IPSR_MSEL(IP12_3_0,      TX2_A,                  SEL_SCIF2_0),
1158         PINMUX_IPSR_MSEL(IP12_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1159         PINMUX_IPSR_MSEL(IP12_3_0,      SCL1_A,                 SEL_I2C1_0),
1160         PINMUX_IPSR_MSEL(IP12_3_0,      FMCLK_A,                SEL_FM_0),
1161         PINMUX_IPSR_MSEL(IP12_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1162         PINMUX_IPSR_MSEL(IP12_3_0,      FSO_CFE_0_B,            SEL_FSO_1),
1163
1164         PINMUX_IPSR_MSEL(IP12_7_4,      RX2_A,                  SEL_SCIF2_0),
1165         PINMUX_IPSR_MSEL(IP12_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1166         PINMUX_IPSR_MSEL(IP12_7_4,      SDA1_A,                 SEL_I2C1_0),
1167         PINMUX_IPSR_MSEL(IP12_7_4,      FMIN_A,                 SEL_FM_0),
1168         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1169         PINMUX_IPSR_MSEL(IP12_7_4,      FSO_CFE_1_B,            SEL_FSO_1),
1170
1171         PINMUX_IPSR_GPSR(IP12_11_8,     HSCK0),
1172         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1173         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKB_A,           SEL_ADG_0),
1174         PINMUX_IPSR_MSEL(IP12_11_8,     SSI_SDATA1_B,           SEL_SSI_1),
1175         PINMUX_IPSR_MSEL(IP12_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1176         PINMUX_IPSR_MSEL(IP12_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1177         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1178
1179         PINMUX_IPSR_GPSR(IP12_15_12,    HRX0),
1180         PINMUX_IPSR_MSEL(IP12_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1181         PINMUX_IPSR_MSEL(IP12_15_12,    SSI_SDATA2_B,           SEL_SSI_1),
1182         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1183         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1184         PINMUX_IPSR_MSEL(IP12_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1185
1186         PINMUX_IPSR_GPSR(IP12_19_16,    HTX0),
1187         PINMUX_IPSR_MSEL(IP12_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1188         PINMUX_IPSR_MSEL(IP12_19_16,    SSI_SDATA9_B,           SEL_SSI_1),
1189         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1190         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1191         PINMUX_IPSR_MSEL(IP12_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1192
1193         PINMUX_IPSR_GPSR(IP12_23_20,    HCTS0_N),
1194         PINMUX_IPSR_MSEL(IP12_23_20,    RX2_B,                  SEL_SCIF2_1),
1195         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1196         PINMUX_IPSR_MSEL(IP12_23_20,    SSI_SCK9_A,             SEL_SSI_0),
1197         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1198         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1199         PINMUX_IPSR_MSEL(IP12_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1200         PINMUX_IPSR_MSEL(IP12_23_20,    AUDIO_CLKOUT1_A,        SEL_ADG_0),
1201
1202         PINMUX_IPSR_GPSR(IP12_27_24,    HRTS0_N),
1203         PINMUX_IPSR_MSEL(IP12_27_24,    TX2_B,                  SEL_SCIF2_1),
1204         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1205         PINMUX_IPSR_MSEL(IP12_27_24,    SSI_WS9_A,              SEL_SSI_0),
1206         PINMUX_IPSR_MSEL(IP12_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1207         PINMUX_IPSR_MSEL(IP12_27_24,    BPFCLK_A,               SEL_FM_0),
1208         PINMUX_IPSR_MSEL(IP12_27_24,    AUDIO_CLKOUT2_A,        SEL_ADG_0),
1209
1210         PINMUX_IPSR_GPSR(IP12_31_28,    MSIOF0_SYNC),
1211         PINMUX_IPSR_MSEL(IP12_31_28,    AUDIO_CLKOUT_A,         SEL_ADG_0),
1212
1213         /* IPSR13 */
1214         PINMUX_IPSR_GPSR(IP13_3_0,      MSIOF0_SS1),
1215         PINMUX_IPSR_GPSR(IP13_3_0,      RX5),
1216         PINMUX_IPSR_MSEL(IP13_3_0,      AUDIO_CLKA_C,           SEL_ADG_2),
1217         PINMUX_IPSR_MSEL(IP13_3_0,      SSI_SCK2_A,             SEL_SSI_0),
1218         PINMUX_IPSR_MSEL(IP13_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1219         PINMUX_IPSR_MSEL(IP13_3_0,      AUDIO_CLKOUT3_A,        SEL_ADG_0),
1220         PINMUX_IPSR_MSEL(IP13_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1221
1222         PINMUX_IPSR_GPSR(IP13_7_4,      MSIOF0_SS2),
1223         PINMUX_IPSR_GPSR(IP13_7_4,      TX5),
1224         PINMUX_IPSR_MSEL(IP13_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1225         PINMUX_IPSR_MSEL(IP13_7_4,      AUDIO_CLKC_A,           SEL_ADG_0),
1226         PINMUX_IPSR_MSEL(IP13_7_4,      SSI_WS2_A,              SEL_SSI_0),
1227         PINMUX_IPSR_MSEL(IP13_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1228         PINMUX_IPSR_MSEL(IP13_7_4,      AUDIO_CLKOUT_D,         SEL_ADG_3),
1229         PINMUX_IPSR_MSEL(IP13_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1230
1231         PINMUX_IPSR_GPSR(IP13_11_8,     MLB_CLK),
1232         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1233         PINMUX_IPSR_MSEL(IP13_11_8,     SCL1_B,                 SEL_I2C1_1),
1234
1235         PINMUX_IPSR_GPSR(IP13_15_12,    MLB_SIG),
1236         PINMUX_IPSR_MSEL(IP13_15_12,    RX1_B,                  SEL_SCIF1_1),
1237         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1238         PINMUX_IPSR_MSEL(IP13_15_12,    SDA1_B,                 SEL_I2C1_1),
1239
1240         PINMUX_IPSR_GPSR(IP13_19_16,    MLB_DAT),
1241         PINMUX_IPSR_MSEL(IP13_19_16,    TX1_B,                  SEL_SCIF1_1),
1242         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1243
1244         PINMUX_IPSR_GPSR(IP13_23_20,    SSI_SCK01239),
1245         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1246
1247         PINMUX_IPSR_GPSR(IP13_27_24,    SSI_WS01239),
1248         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1249
1250         PINMUX_IPSR_GPSR(IP13_31_28,    SSI_SDATA0),
1251         PINMUX_IPSR_MSEL(IP13_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1252
1253         /* IPSR14 */
1254         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SDATA1_A,           SEL_SSI_0),
1255
1256         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_SDATA2_A,           SEL_SSI_0),
1257         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_SCK1_B,             SEL_SSI_1),
1258
1259         PINMUX_IPSR_GPSR(IP14_11_8,     SSI_SCK349),
1260         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1261         PINMUX_IPSR_MSEL(IP14_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1262
1263         PINMUX_IPSR_GPSR(IP14_15_12,    SSI_WS349),
1264         PINMUX_IPSR_MSEL(IP14_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1265         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1266         PINMUX_IPSR_MSEL(IP14_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1267
1268         PINMUX_IPSR_GPSR(IP14_19_16,    SSI_SDATA3),
1269         PINMUX_IPSR_MSEL(IP14_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1270         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1271         PINMUX_IPSR_MSEL(IP14_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1272         PINMUX_IPSR_MSEL(IP14_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1273         PINMUX_IPSR_MSEL(IP14_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1274         PINMUX_IPSR_MSEL(IP14_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1275
1276         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK4),
1277         PINMUX_IPSR_MSEL(IP14_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1278         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1279         PINMUX_IPSR_MSEL(IP14_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1280         PINMUX_IPSR_MSEL(IP14_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1281         PINMUX_IPSR_MSEL(IP14_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1282         PINMUX_IPSR_MSEL(IP14_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1283
1284         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS4),
1285         PINMUX_IPSR_MSEL(IP14_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1286         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1287         PINMUX_IPSR_MSEL(IP14_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1288         PINMUX_IPSR_MSEL(IP14_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1289         PINMUX_IPSR_MSEL(IP14_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1290         PINMUX_IPSR_MSEL(IP14_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1291
1292         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA4),
1293         PINMUX_IPSR_MSEL(IP14_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1294         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1295         PINMUX_IPSR_MSEL(IP14_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1296         PINMUX_IPSR_MSEL(IP14_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1297         PINMUX_IPSR_MSEL(IP14_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1298         PINMUX_IPSR_MSEL(IP14_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1299
1300         /* IPSR15 */
1301         PINMUX_IPSR_GPSR(IP15_3_0,      SSI_SCK6),
1302         PINMUX_IPSR_GPSR(IP15_3_0,      USB2_PWEN),
1303         PINMUX_IPSR_MSEL(IP15_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1304
1305         PINMUX_IPSR_GPSR(IP15_7_4,      SSI_WS6),
1306         PINMUX_IPSR_GPSR(IP15_7_4,      USB2_OVC),
1307         PINMUX_IPSR_MSEL(IP15_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1308
1309         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SDATA6),
1310         PINMUX_IPSR_MSEL(IP15_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1311         PINMUX_IPSR_MSEL(IP15_11_8,     SATA_DEVSLP_A,          SEL_SATA_0),
1312
1313         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_SCK78),
1314         PINMUX_IPSR_MSEL(IP15_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1315         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1316         PINMUX_IPSR_MSEL(IP15_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1317         PINMUX_IPSR_MSEL(IP15_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1318         PINMUX_IPSR_MSEL(IP15_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1319         PINMUX_IPSR_MSEL(IP15_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1320
1321         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_WS78),
1322         PINMUX_IPSR_MSEL(IP15_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1323         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1324         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1325         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1326         PINMUX_IPSR_MSEL(IP15_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1327         PINMUX_IPSR_MSEL(IP15_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1328
1329         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SDATA7),
1330         PINMUX_IPSR_MSEL(IP15_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1331         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1332         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1333         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1334         PINMUX_IPSR_MSEL(IP15_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1335         PINMUX_IPSR_MSEL(IP15_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1336         PINMUX_IPSR_MSEL(IP15_23_20,    TCLK2_A,                SEL_TIMER_TMU_0),
1337
1338         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_SDATA8),
1339         PINMUX_IPSR_MSEL(IP15_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1340         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1341         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1342         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1343         PINMUX_IPSR_MSEL(IP15_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1344         PINMUX_IPSR_MSEL(IP15_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1345
1346         PINMUX_IPSR_MSEL(IP15_31_28,    SSI_SDATA9_A,           SEL_SSI_0),
1347         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1348         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1349         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1350         PINMUX_IPSR_MSEL(IP15_31_28,    SSI_WS1_B,              SEL_SSI_1),
1351         PINMUX_IPSR_GPSR(IP15_31_28,    SCK1),
1352         PINMUX_IPSR_MSEL(IP15_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1353         PINMUX_IPSR_GPSR(IP15_31_28,    SCK5),
1354
1355         /* IPSR16 */
1356         PINMUX_IPSR_MSEL(IP16_3_0,      AUDIO_CLKA_A,           SEL_ADG_0),
1357         PINMUX_IPSR_GPSR(IP16_3_0,      CC5_OSCOUT),
1358
1359         PINMUX_IPSR_MSEL(IP16_7_4,      AUDIO_CLKB_B,           SEL_ADG_1),
1360         PINMUX_IPSR_MSEL(IP16_7_4,      SCIF_CLK_A,             SEL_SCIF1_0),
1361         PINMUX_IPSR_MSEL(IP16_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1362         PINMUX_IPSR_MSEL(IP16_7_4,      REMOCON_A,              SEL_REMOCON_0),
1363         PINMUX_IPSR_MSEL(IP16_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1364
1365         PINMUX_IPSR_GPSR(IP16_11_8,     USB0_PWEN),
1366         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1367         PINMUX_IPSR_MSEL(IP16_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1368         PINMUX_IPSR_MSEL(IP16_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1369         PINMUX_IPSR_MSEL(IP16_11_8,     BPFCLK_B,               SEL_FM_1),
1370         PINMUX_IPSR_MSEL(IP16_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1371
1372         PINMUX_IPSR_GPSR(IP16_15_12,    USB0_OVC),
1373         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_D_C,               SEL_SIMCARD_2),
1374         PINMUX_IPSR_MSEL(IP16_11_8,     TS_SDAT1_D,             SEL_TSIF1_3),
1375         PINMUX_IPSR_MSEL(IP16_11_8,     STP_ISD_1_D,            SEL_SSP1_1_3),
1376         PINMUX_IPSR_MSEL(IP16_11_8,     RIF3_SYNC_B,            SEL_DRIF3_1),
1377
1378         PINMUX_IPSR_GPSR(IP16_19_16,    USB1_PWEN),
1379         PINMUX_IPSR_MSEL(IP16_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1380         PINMUX_IPSR_MSEL(IP16_19_16,    SSI_SCK1_A,             SEL_SSI_0),
1381         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1382         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1383         PINMUX_IPSR_MSEL(IP16_19_16,    FMCLK_B,                SEL_FM_1),
1384         PINMUX_IPSR_MSEL(IP16_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1385         PINMUX_IPSR_MSEL(IP16_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1386
1387         PINMUX_IPSR_GPSR(IP16_23_20,    USB1_OVC),
1388         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1389         PINMUX_IPSR_MSEL(IP16_23_20,    SSI_WS1_A,              SEL_SSI_0),
1390         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1391         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1392         PINMUX_IPSR_MSEL(IP16_23_20,    FMIN_B,                 SEL_FM_1),
1393         PINMUX_IPSR_MSEL(IP16_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1394         PINMUX_IPSR_MSEL(IP16_23_20,    REMOCON_B,              SEL_REMOCON_1),
1395
1396         PINMUX_IPSR_GPSR(IP16_27_24,    USB30_PWEN),
1397         PINMUX_IPSR_MSEL(IP16_27_24,    AUDIO_CLKOUT_B,         SEL_ADG_1),
1398         PINMUX_IPSR_MSEL(IP16_27_24,    SSI_SCK2_B,             SEL_SSI_1),
1399         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1400         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1401         PINMUX_IPSR_MSEL(IP16_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1402         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1403         PINMUX_IPSR_MSEL(IP16_27_24,    TCLK2_B,                SEL_TIMER_TMU_1),
1404         PINMUX_IPSR_GPSR(IP16_27_24,    TPU0TO0),
1405
1406         PINMUX_IPSR_GPSR(IP16_31_28,    USB30_OVC),
1407         PINMUX_IPSR_MSEL(IP16_31_28,    AUDIO_CLKOUT1_B,        SEL_ADG_1),
1408         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS2_B,              SEL_SSI_1),
1409         PINMUX_IPSR_MSEL(IP16_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1410         PINMUX_IPSR_MSEL(IP16_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1411         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1412         PINMUX_IPSR_MSEL(IP16_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1413         PINMUX_IPSR_MSEL(IP16_31_28,    FSO_TOE_B,              SEL_FSO_1),
1414         PINMUX_IPSR_GPSR(IP16_31_28,    TPU0TO1),
1415
1416         /* IPSR17 */
1417         PINMUX_IPSR_GPSR(IP17_3_0,      USB31_PWEN),
1418         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKOUT2_B,        SEL_ADG_1),
1419         PINMUX_IPSR_MSEL(IP17_3_0,      SSI_SCK9_B,             SEL_SSI_1),
1420         PINMUX_IPSR_MSEL(IP17_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1421         PINMUX_IPSR_MSEL(IP17_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1422         PINMUX_IPSR_MSEL(IP17_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1423         PINMUX_IPSR_GPSR(IP17_3_0,      TPU0TO2),
1424
1425         PINMUX_IPSR_GPSR(IP17_7_4,      USB31_OVC),
1426         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKOUT3_B,        SEL_ADG_1),
1427         PINMUX_IPSR_MSEL(IP17_7_4,      SSI_WS9_B,              SEL_SSI_1),
1428         PINMUX_IPSR_MSEL(IP17_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1429         PINMUX_IPSR_MSEL(IP17_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1430         PINMUX_IPSR_MSEL(IP17_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1431         PINMUX_IPSR_GPSR(IP17_7_4,      TPU0TO3),
1432
1433 /*
1434  * Static pins can not be muxed between different functions but
1435  * still need mark entries in the pinmux list. Add each static
1436  * pin to the list without an associated function. The sh-pfc
1437  * core will do the right thing and skip trying to mux the pin
1438  * while still applying configuration to it.
1439  */
1440 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1441         PINMUX_STATIC
1442 #undef FM
1443 };
1444
1445 /*
1446  * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1447  * Physical layout rows: A - AW, cols: 1 - 39.
1448  */
1449 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1450 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1451 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1452 #define PIN_NONE U16_MAX
1453
1454 static const struct sh_pfc_pin pinmux_pins[] = {
1455         PINMUX_GPIO_GP_ALL(),
1456
1457         /*
1458          * Pins not associated with a GPIO port.
1459          *
1460          * The pin positions are different between different r8a7795
1461          * packages, all that is needed for the pfc driver is a unique
1462          * number for each pin. To this end use the pin layout from
1463          * R-Car H3SiP to calculate a unique number for each pin.
1464          */
1465         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1466         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1467         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1468         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1469         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1470         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1471         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1472         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1473         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1474         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1475         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1476         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1477         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1478         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1479         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1480         SH_PFC_PIN_NAMED_CFG('F',  1, CLKOUT, CFG_FLAGS),
1481         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1482         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1483         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1484         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1485         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1486         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1487         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1488         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1489         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1490         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1491         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1492         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1493         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1494         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1495         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1496         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1497         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1498         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1499         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1500         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1501         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  7, DU_DOTCLKIN2, CFG_FLAGS),
1502         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN3, CFG_FLAGS),
1503         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1504         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1505         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1506         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1507         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1508         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1509 };
1510
1511 /* - AUDIO CLOCK ------------------------------------------------------------ */
1512 static const unsigned int audio_clk_a_a_pins[] = {
1513         /* CLK A */
1514         RCAR_GP_PIN(6, 22),
1515 };
1516 static const unsigned int audio_clk_a_a_mux[] = {
1517         AUDIO_CLKA_A_MARK,
1518 };
1519 static const unsigned int audio_clk_a_b_pins[] = {
1520         /* CLK A */
1521         RCAR_GP_PIN(5, 4),
1522 };
1523 static const unsigned int audio_clk_a_b_mux[] = {
1524         AUDIO_CLKA_B_MARK,
1525 };
1526 static const unsigned int audio_clk_a_c_pins[] = {
1527         /* CLK A */
1528         RCAR_GP_PIN(5, 19),
1529 };
1530 static const unsigned int audio_clk_a_c_mux[] = {
1531         AUDIO_CLKA_C_MARK,
1532 };
1533 static const unsigned int audio_clk_b_a_pins[] = {
1534         /* CLK B */
1535         RCAR_GP_PIN(5, 12),
1536 };
1537 static const unsigned int audio_clk_b_a_mux[] = {
1538         AUDIO_CLKB_A_MARK,
1539 };
1540 static const unsigned int audio_clk_b_b_pins[] = {
1541         /* CLK B */
1542         RCAR_GP_PIN(6, 23),
1543 };
1544 static const unsigned int audio_clk_b_b_mux[] = {
1545         AUDIO_CLKB_B_MARK,
1546 };
1547 static const unsigned int audio_clk_c_a_pins[] = {
1548         /* CLK C */
1549         RCAR_GP_PIN(5, 21),
1550 };
1551 static const unsigned int audio_clk_c_a_mux[] = {
1552         AUDIO_CLKC_A_MARK,
1553 };
1554 static const unsigned int audio_clk_c_b_pins[] = {
1555         /* CLK C */
1556         RCAR_GP_PIN(5, 0),
1557 };
1558 static const unsigned int audio_clk_c_b_mux[] = {
1559         AUDIO_CLKC_B_MARK,
1560 };
1561 static const unsigned int audio_clkout_a_pins[] = {
1562         /* CLKOUT */
1563         RCAR_GP_PIN(5, 18),
1564 };
1565 static const unsigned int audio_clkout_a_mux[] = {
1566         AUDIO_CLKOUT_A_MARK,
1567 };
1568 static const unsigned int audio_clkout_b_pins[] = {
1569         /* CLKOUT */
1570         RCAR_GP_PIN(6, 28),
1571 };
1572 static const unsigned int audio_clkout_b_mux[] = {
1573         AUDIO_CLKOUT_B_MARK,
1574 };
1575 static const unsigned int audio_clkout_c_pins[] = {
1576         /* CLKOUT */
1577         RCAR_GP_PIN(5, 3),
1578 };
1579 static const unsigned int audio_clkout_c_mux[] = {
1580         AUDIO_CLKOUT_C_MARK,
1581 };
1582 static const unsigned int audio_clkout_d_pins[] = {
1583         /* CLKOUT */
1584         RCAR_GP_PIN(5, 21),
1585 };
1586 static const unsigned int audio_clkout_d_mux[] = {
1587         AUDIO_CLKOUT_D_MARK,
1588 };
1589 static const unsigned int audio_clkout1_a_pins[] = {
1590         /* CLKOUT1 */
1591         RCAR_GP_PIN(5, 15),
1592 };
1593 static const unsigned int audio_clkout1_a_mux[] = {
1594         AUDIO_CLKOUT1_A_MARK,
1595 };
1596 static const unsigned int audio_clkout1_b_pins[] = {
1597         /* CLKOUT1 */
1598         RCAR_GP_PIN(6, 29),
1599 };
1600 static const unsigned int audio_clkout1_b_mux[] = {
1601         AUDIO_CLKOUT1_B_MARK,
1602 };
1603 static const unsigned int audio_clkout2_a_pins[] = {
1604         /* CLKOUT2 */
1605         RCAR_GP_PIN(5, 16),
1606 };
1607 static const unsigned int audio_clkout2_a_mux[] = {
1608         AUDIO_CLKOUT2_A_MARK,
1609 };
1610 static const unsigned int audio_clkout2_b_pins[] = {
1611         /* CLKOUT2 */
1612         RCAR_GP_PIN(6, 30),
1613 };
1614 static const unsigned int audio_clkout2_b_mux[] = {
1615         AUDIO_CLKOUT2_B_MARK,
1616 };
1617
1618 static const unsigned int audio_clkout3_a_pins[] = {
1619         /* CLKOUT3 */
1620         RCAR_GP_PIN(5, 19),
1621 };
1622 static const unsigned int audio_clkout3_a_mux[] = {
1623         AUDIO_CLKOUT3_A_MARK,
1624 };
1625 static const unsigned int audio_clkout3_b_pins[] = {
1626         /* CLKOUT3 */
1627         RCAR_GP_PIN(6, 31),
1628 };
1629 static const unsigned int audio_clkout3_b_mux[] = {
1630         AUDIO_CLKOUT3_B_MARK,
1631 };
1632
1633 /* - EtherAVB --------------------------------------------------------------- */
1634 static const unsigned int avb_link_pins[] = {
1635         /* AVB_LINK */
1636         RCAR_GP_PIN(2, 12),
1637 };
1638 static const unsigned int avb_link_mux[] = {
1639         AVB_LINK_MARK,
1640 };
1641 static const unsigned int avb_magic_pins[] = {
1642         /* AVB_MAGIC_ */
1643         RCAR_GP_PIN(2, 10),
1644 };
1645 static const unsigned int avb_magic_mux[] = {
1646         AVB_MAGIC_MARK,
1647 };
1648 static const unsigned int avb_phy_int_pins[] = {
1649         /* AVB_PHY_INT */
1650         RCAR_GP_PIN(2, 11),
1651 };
1652 static const unsigned int avb_phy_int_mux[] = {
1653         AVB_PHY_INT_MARK,
1654 };
1655 static const unsigned int avb_mdio_pins[] = {
1656         /* AVB_MDC, AVB_MDIO */
1657         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1658 };
1659 static const unsigned int avb_mdio_mux[] = {
1660         AVB_MDC_MARK, AVB_MDIO_MARK,
1661 };
1662 static const unsigned int avb_mii_pins[] = {
1663         /*
1664          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1665          * AVB_TD1, AVB_TD2, AVB_TD3,
1666          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1667          * AVB_RD1, AVB_RD2, AVB_RD3,
1668          * AVB_TXCREFCLK
1669          */
1670         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1671         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1672         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1673         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1674         PIN_NUMBER('A', 12),
1675
1676 };
1677 static const unsigned int avb_mii_mux[] = {
1678         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1679         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1680         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1681         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1682         AVB_TXCREFCLK_MARK,
1683 };
1684 static const unsigned int avb_avtp_pps_pins[] = {
1685         /* AVB_AVTP_PPS */
1686         RCAR_GP_PIN(2, 6),
1687 };
1688 static const unsigned int avb_avtp_pps_mux[] = {
1689         AVB_AVTP_PPS_MARK,
1690 };
1691 static const unsigned int avb_avtp_match_a_pins[] = {
1692         /* AVB_AVTP_MATCH_A */
1693         RCAR_GP_PIN(2, 13),
1694 };
1695 static const unsigned int avb_avtp_match_a_mux[] = {
1696         AVB_AVTP_MATCH_A_MARK,
1697 };
1698 static const unsigned int avb_avtp_capture_a_pins[] = {
1699         /* AVB_AVTP_CAPTURE_A */
1700         RCAR_GP_PIN(2, 14),
1701 };
1702 static const unsigned int avb_avtp_capture_a_mux[] = {
1703         AVB_AVTP_CAPTURE_A_MARK,
1704 };
1705 static const unsigned int avb_avtp_match_b_pins[] = {
1706         /*  AVB_AVTP_MATCH_B */
1707         RCAR_GP_PIN(1, 8),
1708 };
1709 static const unsigned int avb_avtp_match_b_mux[] = {
1710         AVB_AVTP_MATCH_B_MARK,
1711 };
1712 static const unsigned int avb_avtp_capture_b_pins[] = {
1713         /* AVB_AVTP_CAPTURE_B */
1714         RCAR_GP_PIN(1, 11),
1715 };
1716 static const unsigned int avb_avtp_capture_b_mux[] = {
1717         AVB_AVTP_CAPTURE_B_MARK,
1718 };
1719
1720 /* - CAN ------------------------------------------------------------------ */
1721 static const unsigned int can0_data_a_pins[] = {
1722         /* TX, RX */
1723         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1724 };
1725 static const unsigned int can0_data_a_mux[] = {
1726         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1727 };
1728 static const unsigned int can0_data_b_pins[] = {
1729         /* TX, RX */
1730         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1731 };
1732 static const unsigned int can0_data_b_mux[] = {
1733         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1734 };
1735 static const unsigned int can1_data_pins[] = {
1736         /* TX, RX */
1737         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1738 };
1739 static const unsigned int can1_data_mux[] = {
1740         CAN1_TX_MARK,           CAN1_RX_MARK,
1741 };
1742
1743 /* - CAN Clock -------------------------------------------------------------- */
1744 static const unsigned int can_clk_pins[] = {
1745         /* CLK */
1746         RCAR_GP_PIN(1, 25),
1747 };
1748 static const unsigned int can_clk_mux[] = {
1749         CAN_CLK_MARK,
1750 };
1751
1752 /* - CAN FD --------------------------------------------------------------- */
1753 static const unsigned int canfd0_data_a_pins[] = {
1754         /* TX, RX */
1755         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1756 };
1757 static const unsigned int canfd0_data_a_mux[] = {
1758         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1759 };
1760 static const unsigned int canfd0_data_b_pins[] = {
1761         /* TX, RX */
1762         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1763 };
1764 static const unsigned int canfd0_data_b_mux[] = {
1765         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1766 };
1767 static const unsigned int canfd1_data_pins[] = {
1768         /* TX, RX */
1769         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1770 };
1771 static const unsigned int canfd1_data_mux[] = {
1772         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1773 };
1774
1775 /* - DRIF0 --------------------------------------------------------------- */
1776 static const unsigned int drif0_ctrl_a_pins[] = {
1777         /* CLK, SYNC */
1778         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1779 };
1780 static const unsigned int drif0_ctrl_a_mux[] = {
1781         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1782 };
1783 static const unsigned int drif0_data0_a_pins[] = {
1784         /* D0 */
1785         RCAR_GP_PIN(6, 10),
1786 };
1787 static const unsigned int drif0_data0_a_mux[] = {
1788         RIF0_D0_A_MARK,
1789 };
1790 static const unsigned int drif0_data1_a_pins[] = {
1791         /* D1 */
1792         RCAR_GP_PIN(6, 7),
1793 };
1794 static const unsigned int drif0_data1_a_mux[] = {
1795         RIF0_D1_A_MARK,
1796 };
1797 static const unsigned int drif0_ctrl_b_pins[] = {
1798         /* CLK, SYNC */
1799         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1800 };
1801 static const unsigned int drif0_ctrl_b_mux[] = {
1802         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1803 };
1804 static const unsigned int drif0_data0_b_pins[] = {
1805         /* D0 */
1806         RCAR_GP_PIN(5, 1),
1807 };
1808 static const unsigned int drif0_data0_b_mux[] = {
1809         RIF0_D0_B_MARK,
1810 };
1811 static const unsigned int drif0_data1_b_pins[] = {
1812         /* D1 */
1813         RCAR_GP_PIN(5, 2),
1814 };
1815 static const unsigned int drif0_data1_b_mux[] = {
1816         RIF0_D1_B_MARK,
1817 };
1818 static const unsigned int drif0_ctrl_c_pins[] = {
1819         /* CLK, SYNC */
1820         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1821 };
1822 static const unsigned int drif0_ctrl_c_mux[] = {
1823         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1824 };
1825 static const unsigned int drif0_data0_c_pins[] = {
1826         /* D0 */
1827         RCAR_GP_PIN(5, 13),
1828 };
1829 static const unsigned int drif0_data0_c_mux[] = {
1830         RIF0_D0_C_MARK,
1831 };
1832 static const unsigned int drif0_data1_c_pins[] = {
1833         /* D1 */
1834         RCAR_GP_PIN(5, 14),
1835 };
1836 static const unsigned int drif0_data1_c_mux[] = {
1837         RIF0_D1_C_MARK,
1838 };
1839 /* - DRIF1 --------------------------------------------------------------- */
1840 static const unsigned int drif1_ctrl_a_pins[] = {
1841         /* CLK, SYNC */
1842         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1843 };
1844 static const unsigned int drif1_ctrl_a_mux[] = {
1845         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1846 };
1847 static const unsigned int drif1_data0_a_pins[] = {
1848         /* D0 */
1849         RCAR_GP_PIN(6, 19),
1850 };
1851 static const unsigned int drif1_data0_a_mux[] = {
1852         RIF1_D0_A_MARK,
1853 };
1854 static const unsigned int drif1_data1_a_pins[] = {
1855         /* D1 */
1856         RCAR_GP_PIN(6, 20),
1857 };
1858 static const unsigned int drif1_data1_a_mux[] = {
1859         RIF1_D1_A_MARK,
1860 };
1861 static const unsigned int drif1_ctrl_b_pins[] = {
1862         /* CLK, SYNC */
1863         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1864 };
1865 static const unsigned int drif1_ctrl_b_mux[] = {
1866         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1867 };
1868 static const unsigned int drif1_data0_b_pins[] = {
1869         /* D0 */
1870         RCAR_GP_PIN(5, 7),
1871 };
1872 static const unsigned int drif1_data0_b_mux[] = {
1873         RIF1_D0_B_MARK,
1874 };
1875 static const unsigned int drif1_data1_b_pins[] = {
1876         /* D1 */
1877         RCAR_GP_PIN(5, 8),
1878 };
1879 static const unsigned int drif1_data1_b_mux[] = {
1880         RIF1_D1_B_MARK,
1881 };
1882 static const unsigned int drif1_ctrl_c_pins[] = {
1883         /* CLK, SYNC */
1884         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1885 };
1886 static const unsigned int drif1_ctrl_c_mux[] = {
1887         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1888 };
1889 static const unsigned int drif1_data0_c_pins[] = {
1890         /* D0 */
1891         RCAR_GP_PIN(5, 6),
1892 };
1893 static const unsigned int drif1_data0_c_mux[] = {
1894         RIF1_D0_C_MARK,
1895 };
1896 static const unsigned int drif1_data1_c_pins[] = {
1897         /* D1 */
1898         RCAR_GP_PIN(5, 10),
1899 };
1900 static const unsigned int drif1_data1_c_mux[] = {
1901         RIF1_D1_C_MARK,
1902 };
1903 /* - DRIF2 --------------------------------------------------------------- */
1904 static const unsigned int drif2_ctrl_a_pins[] = {
1905         /* CLK, SYNC */
1906         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1907 };
1908 static const unsigned int drif2_ctrl_a_mux[] = {
1909         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1910 };
1911 static const unsigned int drif2_data0_a_pins[] = {
1912         /* D0 */
1913         RCAR_GP_PIN(6, 7),
1914 };
1915 static const unsigned int drif2_data0_a_mux[] = {
1916         RIF2_D0_A_MARK,
1917 };
1918 static const unsigned int drif2_data1_a_pins[] = {
1919         /* D1 */
1920         RCAR_GP_PIN(6, 10),
1921 };
1922 static const unsigned int drif2_data1_a_mux[] = {
1923         RIF2_D1_A_MARK,
1924 };
1925 static const unsigned int drif2_ctrl_b_pins[] = {
1926         /* CLK, SYNC */
1927         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1928 };
1929 static const unsigned int drif2_ctrl_b_mux[] = {
1930         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1931 };
1932 static const unsigned int drif2_data0_b_pins[] = {
1933         /* D0 */
1934         RCAR_GP_PIN(6, 30),
1935 };
1936 static const unsigned int drif2_data0_b_mux[] = {
1937         RIF2_D0_B_MARK,
1938 };
1939 static const unsigned int drif2_data1_b_pins[] = {
1940         /* D1 */
1941         RCAR_GP_PIN(6, 31),
1942 };
1943 static const unsigned int drif2_data1_b_mux[] = {
1944         RIF2_D1_B_MARK,
1945 };
1946 /* - DRIF3 --------------------------------------------------------------- */
1947 static const unsigned int drif3_ctrl_a_pins[] = {
1948         /* CLK, SYNC */
1949         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1950 };
1951 static const unsigned int drif3_ctrl_a_mux[] = {
1952         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1953 };
1954 static const unsigned int drif3_data0_a_pins[] = {
1955         /* D0 */
1956         RCAR_GP_PIN(6, 19),
1957 };
1958 static const unsigned int drif3_data0_a_mux[] = {
1959         RIF3_D0_A_MARK,
1960 };
1961 static const unsigned int drif3_data1_a_pins[] = {
1962         /* D1 */
1963         RCAR_GP_PIN(6, 20),
1964 };
1965 static const unsigned int drif3_data1_a_mux[] = {
1966         RIF3_D1_A_MARK,
1967 };
1968 static const unsigned int drif3_ctrl_b_pins[] = {
1969         /* CLK, SYNC */
1970         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1971 };
1972 static const unsigned int drif3_ctrl_b_mux[] = {
1973         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1974 };
1975 static const unsigned int drif3_data0_b_pins[] = {
1976         /* D0 */
1977         RCAR_GP_PIN(6, 28),
1978 };
1979 static const unsigned int drif3_data0_b_mux[] = {
1980         RIF3_D0_B_MARK,
1981 };
1982 static const unsigned int drif3_data1_b_pins[] = {
1983         /* D1 */
1984         RCAR_GP_PIN(6, 29),
1985 };
1986 static const unsigned int drif3_data1_b_mux[] = {
1987         RIF3_D1_B_MARK,
1988 };
1989
1990 /* - DU --------------------------------------------------------------------- */
1991 static const unsigned int du_rgb666_pins[] = {
1992         /* R[7:2], G[7:2], B[7:2] */
1993         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1994         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1995         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1996         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1997         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
1998         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
1999 };
2000 static const unsigned int du_rgb666_mux[] = {
2001         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2002         DU_DR3_MARK, DU_DR2_MARK,
2003         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2004         DU_DG3_MARK, DU_DG2_MARK,
2005         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2006         DU_DB3_MARK, DU_DB2_MARK,
2007 };
2008 static const unsigned int du_rgb888_pins[] = {
2009         /* R[7:0], G[7:0], B[7:0] */
2010         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2011         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2012         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2013         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2014         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2015         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2016         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2017         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2018         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2019 };
2020 static const unsigned int du_rgb888_mux[] = {
2021         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2022         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2023         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2024         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2025         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2026         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2027 };
2028 static const unsigned int du_clk_out_0_pins[] = {
2029         /* CLKOUT */
2030         RCAR_GP_PIN(1, 27),
2031 };
2032 static const unsigned int du_clk_out_0_mux[] = {
2033         DU_DOTCLKOUT0_MARK
2034 };
2035 static const unsigned int du_clk_out_1_pins[] = {
2036         /* CLKOUT */
2037         RCAR_GP_PIN(2, 3),
2038 };
2039 static const unsigned int du_clk_out_1_mux[] = {
2040         DU_DOTCLKOUT1_MARK
2041 };
2042 static const unsigned int du_sync_pins[] = {
2043         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2044         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2045 };
2046 static const unsigned int du_sync_mux[] = {
2047         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2048 };
2049 static const unsigned int du_oddf_pins[] = {
2050         /* EXDISP/EXODDF/EXCDE */
2051         RCAR_GP_PIN(2, 2),
2052 };
2053 static const unsigned int du_oddf_mux[] = {
2054         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2055 };
2056 static const unsigned int du_cde_pins[] = {
2057         /* CDE */
2058         RCAR_GP_PIN(2, 0),
2059 };
2060 static const unsigned int du_cde_mux[] = {
2061         DU_CDE_MARK,
2062 };
2063 static const unsigned int du_disp_pins[] = {
2064         /* DISP */
2065         RCAR_GP_PIN(2, 1),
2066 };
2067 static const unsigned int du_disp_mux[] = {
2068         DU_DISP_MARK,
2069 };
2070 /* - HDMI ------------------------------------------------------------------- */
2071 static const unsigned int hdmi0_cec_pins[] = {
2072         /* HDMI0_CEC */
2073         RCAR_GP_PIN(7, 2),
2074 };
2075 static const unsigned int hdmi0_cec_mux[] = {
2076         HDMI0_CEC_MARK,
2077 };
2078 static const unsigned int hdmi1_cec_pins[] = {
2079         /* HDMI1_CEC */
2080         RCAR_GP_PIN(7, 3),
2081 };
2082 static const unsigned int hdmi1_cec_mux[] = {
2083         HDMI1_CEC_MARK,
2084 };
2085
2086 /* - HSCIF0 ----------------------------------------------------------------- */
2087 static const unsigned int hscif0_data_pins[] = {
2088         /* RX, TX */
2089         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2090 };
2091 static const unsigned int hscif0_data_mux[] = {
2092         HRX0_MARK, HTX0_MARK,
2093 };
2094 static const unsigned int hscif0_clk_pins[] = {
2095         /* SCK */
2096         RCAR_GP_PIN(5, 12),
2097 };
2098 static const unsigned int hscif0_clk_mux[] = {
2099         HSCK0_MARK,
2100 };
2101 static const unsigned int hscif0_ctrl_pins[] = {
2102         /* RTS, CTS */
2103         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2104 };
2105 static const unsigned int hscif0_ctrl_mux[] = {
2106         HRTS0_N_MARK, HCTS0_N_MARK,
2107 };
2108 /* - HSCIF1 ----------------------------------------------------------------- */
2109 static const unsigned int hscif1_data_a_pins[] = {
2110         /* RX, TX */
2111         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2112 };
2113 static const unsigned int hscif1_data_a_mux[] = {
2114         HRX1_A_MARK, HTX1_A_MARK,
2115 };
2116 static const unsigned int hscif1_clk_a_pins[] = {
2117         /* SCK */
2118         RCAR_GP_PIN(6, 21),
2119 };
2120 static const unsigned int hscif1_clk_a_mux[] = {
2121         HSCK1_A_MARK,
2122 };
2123 static const unsigned int hscif1_ctrl_a_pins[] = {
2124         /* RTS, CTS */
2125         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2126 };
2127 static const unsigned int hscif1_ctrl_a_mux[] = {
2128         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2129 };
2130
2131 static const unsigned int hscif1_data_b_pins[] = {
2132         /* RX, TX */
2133         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2134 };
2135 static const unsigned int hscif1_data_b_mux[] = {
2136         HRX1_B_MARK, HTX1_B_MARK,
2137 };
2138 static const unsigned int hscif1_clk_b_pins[] = {
2139         /* SCK */
2140         RCAR_GP_PIN(5, 0),
2141 };
2142 static const unsigned int hscif1_clk_b_mux[] = {
2143         HSCK1_B_MARK,
2144 };
2145 static const unsigned int hscif1_ctrl_b_pins[] = {
2146         /* RTS, CTS */
2147         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2148 };
2149 static const unsigned int hscif1_ctrl_b_mux[] = {
2150         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2151 };
2152 /* - HSCIF2 ----------------------------------------------------------------- */
2153 static const unsigned int hscif2_data_a_pins[] = {
2154         /* RX, TX */
2155         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2156 };
2157 static const unsigned int hscif2_data_a_mux[] = {
2158         HRX2_A_MARK, HTX2_A_MARK,
2159 };
2160 static const unsigned int hscif2_clk_a_pins[] = {
2161         /* SCK */
2162         RCAR_GP_PIN(6, 10),
2163 };
2164 static const unsigned int hscif2_clk_a_mux[] = {
2165         HSCK2_A_MARK,
2166 };
2167 static const unsigned int hscif2_ctrl_a_pins[] = {
2168         /* RTS, CTS */
2169         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2170 };
2171 static const unsigned int hscif2_ctrl_a_mux[] = {
2172         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2173 };
2174
2175 static const unsigned int hscif2_data_b_pins[] = {
2176         /* RX, TX */
2177         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2178 };
2179 static const unsigned int hscif2_data_b_mux[] = {
2180         HRX2_B_MARK, HTX2_B_MARK,
2181 };
2182 static const unsigned int hscif2_clk_b_pins[] = {
2183         /* SCK */
2184         RCAR_GP_PIN(6, 21),
2185 };
2186 static const unsigned int hscif2_clk_b_mux[] = {
2187         HSCK2_B_MARK,
2188 };
2189 static const unsigned int hscif2_ctrl_b_pins[] = {
2190         /* RTS, CTS */
2191         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2192 };
2193 static const unsigned int hscif2_ctrl_b_mux[] = {
2194         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2195 };
2196 /* - HSCIF3 ----------------------------------------------------------------- */
2197 static const unsigned int hscif3_data_a_pins[] = {
2198         /* RX, TX */
2199         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2200 };
2201 static const unsigned int hscif3_data_a_mux[] = {
2202         HRX3_A_MARK, HTX3_A_MARK,
2203 };
2204 static const unsigned int hscif3_clk_pins[] = {
2205         /* SCK */
2206         RCAR_GP_PIN(1, 22),
2207 };
2208 static const unsigned int hscif3_clk_mux[] = {
2209         HSCK3_MARK,
2210 };
2211 static const unsigned int hscif3_ctrl_pins[] = {
2212         /* RTS, CTS */
2213         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2214 };
2215 static const unsigned int hscif3_ctrl_mux[] = {
2216         HRTS3_N_MARK, HCTS3_N_MARK,
2217 };
2218
2219 static const unsigned int hscif3_data_b_pins[] = {
2220         /* RX, TX */
2221         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2222 };
2223 static const unsigned int hscif3_data_b_mux[] = {
2224         HRX3_B_MARK, HTX3_B_MARK,
2225 };
2226 static const unsigned int hscif3_data_c_pins[] = {
2227         /* RX, TX */
2228         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2229 };
2230 static const unsigned int hscif3_data_c_mux[] = {
2231         HRX3_C_MARK, HTX3_C_MARK,
2232 };
2233 static const unsigned int hscif3_data_d_pins[] = {
2234         /* RX, TX */
2235         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2236 };
2237 static const unsigned int hscif3_data_d_mux[] = {
2238         HRX3_D_MARK, HTX3_D_MARK,
2239 };
2240 /* - HSCIF4 ----------------------------------------------------------------- */
2241 static const unsigned int hscif4_data_a_pins[] = {
2242         /* RX, TX */
2243         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2244 };
2245 static const unsigned int hscif4_data_a_mux[] = {
2246         HRX4_A_MARK, HTX4_A_MARK,
2247 };
2248 static const unsigned int hscif4_clk_pins[] = {
2249         /* SCK */
2250         RCAR_GP_PIN(1, 11),
2251 };
2252 static const unsigned int hscif4_clk_mux[] = {
2253         HSCK4_MARK,
2254 };
2255 static const unsigned int hscif4_ctrl_pins[] = {
2256         /* RTS, CTS */
2257         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2258 };
2259 static const unsigned int hscif4_ctrl_mux[] = {
2260         HRTS4_N_MARK, HCTS4_N_MARK,
2261 };
2262
2263 static const unsigned int hscif4_data_b_pins[] = {
2264         /* RX, TX */
2265         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2266 };
2267 static const unsigned int hscif4_data_b_mux[] = {
2268         HRX4_B_MARK, HTX4_B_MARK,
2269 };
2270
2271 /* - I2C -------------------------------------------------------------------- */
2272 static const unsigned int i2c1_a_pins[] = {
2273         /* SDA, SCL */
2274         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2275 };
2276 static const unsigned int i2c1_a_mux[] = {
2277         SDA1_A_MARK, SCL1_A_MARK,
2278 };
2279 static const unsigned int i2c1_b_pins[] = {
2280         /* SDA, SCL */
2281         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2282 };
2283 static const unsigned int i2c1_b_mux[] = {
2284         SDA1_B_MARK, SCL1_B_MARK,
2285 };
2286 static const unsigned int i2c2_a_pins[] = {
2287         /* SDA, SCL */
2288         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2289 };
2290 static const unsigned int i2c2_a_mux[] = {
2291         SDA2_A_MARK, SCL2_A_MARK,
2292 };
2293 static const unsigned int i2c2_b_pins[] = {
2294         /* SDA, SCL */
2295         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2296 };
2297 static const unsigned int i2c2_b_mux[] = {
2298         SDA2_B_MARK, SCL2_B_MARK,
2299 };
2300 static const unsigned int i2c6_a_pins[] = {
2301         /* SDA, SCL */
2302         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2303 };
2304 static const unsigned int i2c6_a_mux[] = {
2305         SDA6_A_MARK, SCL6_A_MARK,
2306 };
2307 static const unsigned int i2c6_b_pins[] = {
2308         /* SDA, SCL */
2309         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2310 };
2311 static const unsigned int i2c6_b_mux[] = {
2312         SDA6_B_MARK, SCL6_B_MARK,
2313 };
2314 static const unsigned int i2c6_c_pins[] = {
2315         /* SDA, SCL */
2316         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2317 };
2318 static const unsigned int i2c6_c_mux[] = {
2319         SDA6_C_MARK, SCL6_C_MARK,
2320 };
2321
2322 /* - INTC-EX ---------------------------------------------------------------- */
2323 static const unsigned int intc_ex_irq0_pins[] = {
2324         /* IRQ0 */
2325         RCAR_GP_PIN(2, 0),
2326 };
2327 static const unsigned int intc_ex_irq0_mux[] = {
2328         IRQ0_MARK,
2329 };
2330 static const unsigned int intc_ex_irq1_pins[] = {
2331         /* IRQ1 */
2332         RCAR_GP_PIN(2, 1),
2333 };
2334 static const unsigned int intc_ex_irq1_mux[] = {
2335         IRQ1_MARK,
2336 };
2337 static const unsigned int intc_ex_irq2_pins[] = {
2338         /* IRQ2 */
2339         RCAR_GP_PIN(2, 2),
2340 };
2341 static const unsigned int intc_ex_irq2_mux[] = {
2342         IRQ2_MARK,
2343 };
2344 static const unsigned int intc_ex_irq3_pins[] = {
2345         /* IRQ3 */
2346         RCAR_GP_PIN(2, 3),
2347 };
2348 static const unsigned int intc_ex_irq3_mux[] = {
2349         IRQ3_MARK,
2350 };
2351 static const unsigned int intc_ex_irq4_pins[] = {
2352         /* IRQ4 */
2353         RCAR_GP_PIN(2, 4),
2354 };
2355 static const unsigned int intc_ex_irq4_mux[] = {
2356         IRQ4_MARK,
2357 };
2358 static const unsigned int intc_ex_irq5_pins[] = {
2359         /* IRQ5 */
2360         RCAR_GP_PIN(2, 5),
2361 };
2362 static const unsigned int intc_ex_irq5_mux[] = {
2363         IRQ5_MARK,
2364 };
2365
2366 /* - MSIOF0 ----------------------------------------------------------------- */
2367 static const unsigned int msiof0_clk_pins[] = {
2368         /* SCK */
2369         RCAR_GP_PIN(5, 17),
2370 };
2371 static const unsigned int msiof0_clk_mux[] = {
2372         MSIOF0_SCK_MARK,
2373 };
2374 static const unsigned int msiof0_sync_pins[] = {
2375         /* SYNC */
2376         RCAR_GP_PIN(5, 18),
2377 };
2378 static const unsigned int msiof0_sync_mux[] = {
2379         MSIOF0_SYNC_MARK,
2380 };
2381 static const unsigned int msiof0_ss1_pins[] = {
2382         /* SS1 */
2383         RCAR_GP_PIN(5, 19),
2384 };
2385 static const unsigned int msiof0_ss1_mux[] = {
2386         MSIOF0_SS1_MARK,
2387 };
2388 static const unsigned int msiof0_ss2_pins[] = {
2389         /* SS2 */
2390         RCAR_GP_PIN(5, 21),
2391 };
2392 static const unsigned int msiof0_ss2_mux[] = {
2393         MSIOF0_SS2_MARK,
2394 };
2395 static const unsigned int msiof0_txd_pins[] = {
2396         /* TXD */
2397         RCAR_GP_PIN(5, 20),
2398 };
2399 static const unsigned int msiof0_txd_mux[] = {
2400         MSIOF0_TXD_MARK,
2401 };
2402 static const unsigned int msiof0_rxd_pins[] = {
2403         /* RXD */
2404         RCAR_GP_PIN(5, 22),
2405 };
2406 static const unsigned int msiof0_rxd_mux[] = {
2407         MSIOF0_RXD_MARK,
2408 };
2409 /* - MSIOF1 ----------------------------------------------------------------- */
2410 static const unsigned int msiof1_clk_a_pins[] = {
2411         /* SCK */
2412         RCAR_GP_PIN(6, 8),
2413 };
2414 static const unsigned int msiof1_clk_a_mux[] = {
2415         MSIOF1_SCK_A_MARK,
2416 };
2417 static const unsigned int msiof1_sync_a_pins[] = {
2418         /* SYNC */
2419         RCAR_GP_PIN(6, 9),
2420 };
2421 static const unsigned int msiof1_sync_a_mux[] = {
2422         MSIOF1_SYNC_A_MARK,
2423 };
2424 static const unsigned int msiof1_ss1_a_pins[] = {
2425         /* SS1 */
2426         RCAR_GP_PIN(6, 5),
2427 };
2428 static const unsigned int msiof1_ss1_a_mux[] = {
2429         MSIOF1_SS1_A_MARK,
2430 };
2431 static const unsigned int msiof1_ss2_a_pins[] = {
2432         /* SS2 */
2433         RCAR_GP_PIN(6, 6),
2434 };
2435 static const unsigned int msiof1_ss2_a_mux[] = {
2436         MSIOF1_SS2_A_MARK,
2437 };
2438 static const unsigned int msiof1_txd_a_pins[] = {
2439         /* TXD */
2440         RCAR_GP_PIN(6, 7),
2441 };
2442 static const unsigned int msiof1_txd_a_mux[] = {
2443         MSIOF1_TXD_A_MARK,
2444 };
2445 static const unsigned int msiof1_rxd_a_pins[] = {
2446         /* RXD */
2447         RCAR_GP_PIN(6, 10),
2448 };
2449 static const unsigned int msiof1_rxd_a_mux[] = {
2450         MSIOF1_RXD_A_MARK,
2451 };
2452 static const unsigned int msiof1_clk_b_pins[] = {
2453         /* SCK */
2454         RCAR_GP_PIN(5, 9),
2455 };
2456 static const unsigned int msiof1_clk_b_mux[] = {
2457         MSIOF1_SCK_B_MARK,
2458 };
2459 static const unsigned int msiof1_sync_b_pins[] = {
2460         /* SYNC */
2461         RCAR_GP_PIN(5, 3),
2462 };
2463 static const unsigned int msiof1_sync_b_mux[] = {
2464         MSIOF1_SYNC_B_MARK,
2465 };
2466 static const unsigned int msiof1_ss1_b_pins[] = {
2467         /* SS1 */
2468         RCAR_GP_PIN(5, 4),
2469 };
2470 static const unsigned int msiof1_ss1_b_mux[] = {
2471         MSIOF1_SS1_B_MARK,
2472 };
2473 static const unsigned int msiof1_ss2_b_pins[] = {
2474         /* SS2 */
2475         RCAR_GP_PIN(5, 0),
2476 };
2477 static const unsigned int msiof1_ss2_b_mux[] = {
2478         MSIOF1_SS2_B_MARK,
2479 };
2480 static const unsigned int msiof1_txd_b_pins[] = {
2481         /* TXD */
2482         RCAR_GP_PIN(5, 8),
2483 };
2484 static const unsigned int msiof1_txd_b_mux[] = {
2485         MSIOF1_TXD_B_MARK,
2486 };
2487 static const unsigned int msiof1_rxd_b_pins[] = {
2488         /* RXD */
2489         RCAR_GP_PIN(5, 7),
2490 };
2491 static const unsigned int msiof1_rxd_b_mux[] = {
2492         MSIOF1_RXD_B_MARK,
2493 };
2494 static const unsigned int msiof1_clk_c_pins[] = {
2495         /* SCK */
2496         RCAR_GP_PIN(6, 17),
2497 };
2498 static const unsigned int msiof1_clk_c_mux[] = {
2499         MSIOF1_SCK_C_MARK,
2500 };
2501 static const unsigned int msiof1_sync_c_pins[] = {
2502         /* SYNC */
2503         RCAR_GP_PIN(6, 18),
2504 };
2505 static const unsigned int msiof1_sync_c_mux[] = {
2506         MSIOF1_SYNC_C_MARK,
2507 };
2508 static const unsigned int msiof1_ss1_c_pins[] = {
2509         /* SS1 */
2510         RCAR_GP_PIN(6, 21),
2511 };
2512 static const unsigned int msiof1_ss1_c_mux[] = {
2513         MSIOF1_SS1_C_MARK,
2514 };
2515 static const unsigned int msiof1_ss2_c_pins[] = {
2516         /* SS2 */
2517         RCAR_GP_PIN(6, 27),
2518 };
2519 static const unsigned int msiof1_ss2_c_mux[] = {
2520         MSIOF1_SS2_C_MARK,
2521 };
2522 static const unsigned int msiof1_txd_c_pins[] = {
2523         /* TXD */
2524         RCAR_GP_PIN(6, 20),
2525 };
2526 static const unsigned int msiof1_txd_c_mux[] = {
2527         MSIOF1_TXD_C_MARK,
2528 };
2529 static const unsigned int msiof1_rxd_c_pins[] = {
2530         /* RXD */
2531         RCAR_GP_PIN(6, 19),
2532 };
2533 static const unsigned int msiof1_rxd_c_mux[] = {
2534         MSIOF1_RXD_C_MARK,
2535 };
2536 static const unsigned int msiof1_clk_d_pins[] = {
2537         /* SCK */
2538         RCAR_GP_PIN(5, 12),
2539 };
2540 static const unsigned int msiof1_clk_d_mux[] = {
2541         MSIOF1_SCK_D_MARK,
2542 };
2543 static const unsigned int msiof1_sync_d_pins[] = {
2544         /* SYNC */
2545         RCAR_GP_PIN(5, 15),
2546 };
2547 static const unsigned int msiof1_sync_d_mux[] = {
2548         MSIOF1_SYNC_D_MARK,
2549 };
2550 static const unsigned int msiof1_ss1_d_pins[] = {
2551         /* SS1 */
2552         RCAR_GP_PIN(5, 16),
2553 };
2554 static const unsigned int msiof1_ss1_d_mux[] = {
2555         MSIOF1_SS1_D_MARK,
2556 };
2557 static const unsigned int msiof1_ss2_d_pins[] = {
2558         /* SS2 */
2559         RCAR_GP_PIN(5, 21),
2560 };
2561 static const unsigned int msiof1_ss2_d_mux[] = {
2562         MSIOF1_SS2_D_MARK,
2563 };
2564 static const unsigned int msiof1_txd_d_pins[] = {
2565         /* TXD */
2566         RCAR_GP_PIN(5, 14),
2567 };
2568 static const unsigned int msiof1_txd_d_mux[] = {
2569         MSIOF1_TXD_D_MARK,
2570 };
2571 static const unsigned int msiof1_rxd_d_pins[] = {
2572         /* RXD */
2573         RCAR_GP_PIN(5, 13),
2574 };
2575 static const unsigned int msiof1_rxd_d_mux[] = {
2576         MSIOF1_RXD_D_MARK,
2577 };
2578 static const unsigned int msiof1_clk_e_pins[] = {
2579         /* SCK */
2580         RCAR_GP_PIN(3, 0),
2581 };
2582 static const unsigned int msiof1_clk_e_mux[] = {
2583         MSIOF1_SCK_E_MARK,
2584 };
2585 static const unsigned int msiof1_sync_e_pins[] = {
2586         /* SYNC */
2587         RCAR_GP_PIN(3, 1),
2588 };
2589 static const unsigned int msiof1_sync_e_mux[] = {
2590         MSIOF1_SYNC_E_MARK,
2591 };
2592 static const unsigned int msiof1_ss1_e_pins[] = {
2593         /* SS1 */
2594         RCAR_GP_PIN(3, 4),
2595 };
2596 static const unsigned int msiof1_ss1_e_mux[] = {
2597         MSIOF1_SS1_E_MARK,
2598 };
2599 static const unsigned int msiof1_ss2_e_pins[] = {
2600         /* SS2 */
2601         RCAR_GP_PIN(3, 5),
2602 };
2603 static const unsigned int msiof1_ss2_e_mux[] = {
2604         MSIOF1_SS2_E_MARK,
2605 };
2606 static const unsigned int msiof1_txd_e_pins[] = {
2607         /* TXD */
2608         RCAR_GP_PIN(3, 3),
2609 };
2610 static const unsigned int msiof1_txd_e_mux[] = {
2611         MSIOF1_TXD_E_MARK,
2612 };
2613 static const unsigned int msiof1_rxd_e_pins[] = {
2614         /* RXD */
2615         RCAR_GP_PIN(3, 2),
2616 };
2617 static const unsigned int msiof1_rxd_e_mux[] = {
2618         MSIOF1_RXD_E_MARK,
2619 };
2620 static const unsigned int msiof1_clk_f_pins[] = {
2621         /* SCK */
2622         RCAR_GP_PIN(5, 23),
2623 };
2624 static const unsigned int msiof1_clk_f_mux[] = {
2625         MSIOF1_SCK_F_MARK,
2626 };
2627 static const unsigned int msiof1_sync_f_pins[] = {
2628         /* SYNC */
2629         RCAR_GP_PIN(5, 24),
2630 };
2631 static const unsigned int msiof1_sync_f_mux[] = {
2632         MSIOF1_SYNC_F_MARK,
2633 };
2634 static const unsigned int msiof1_ss1_f_pins[] = {
2635         /* SS1 */
2636         RCAR_GP_PIN(6, 1),
2637 };
2638 static const unsigned int msiof1_ss1_f_mux[] = {
2639         MSIOF1_SS1_F_MARK,
2640 };
2641 static const unsigned int msiof1_ss2_f_pins[] = {
2642         /* SS2 */
2643         RCAR_GP_PIN(6, 2),
2644 };
2645 static const unsigned int msiof1_ss2_f_mux[] = {
2646         MSIOF1_SS2_F_MARK,
2647 };
2648 static const unsigned int msiof1_txd_f_pins[] = {
2649         /* TXD */
2650         RCAR_GP_PIN(6, 0),
2651 };
2652 static const unsigned int msiof1_txd_f_mux[] = {
2653         MSIOF1_TXD_F_MARK,
2654 };
2655 static const unsigned int msiof1_rxd_f_pins[] = {
2656         /* RXD */
2657         RCAR_GP_PIN(5, 25),
2658 };
2659 static const unsigned int msiof1_rxd_f_mux[] = {
2660         MSIOF1_RXD_F_MARK,
2661 };
2662 static const unsigned int msiof1_clk_g_pins[] = {
2663         /* SCK */
2664         RCAR_GP_PIN(3, 6),
2665 };
2666 static const unsigned int msiof1_clk_g_mux[] = {
2667         MSIOF1_SCK_G_MARK,
2668 };
2669 static const unsigned int msiof1_sync_g_pins[] = {
2670         /* SYNC */
2671         RCAR_GP_PIN(3, 7),
2672 };
2673 static const unsigned int msiof1_sync_g_mux[] = {
2674         MSIOF1_SYNC_G_MARK,
2675 };
2676 static const unsigned int msiof1_ss1_g_pins[] = {
2677         /* SS1 */
2678         RCAR_GP_PIN(3, 10),
2679 };
2680 static const unsigned int msiof1_ss1_g_mux[] = {
2681         MSIOF1_SS1_G_MARK,
2682 };
2683 static const unsigned int msiof1_ss2_g_pins[] = {
2684         /* SS2 */
2685         RCAR_GP_PIN(3, 11),
2686 };
2687 static const unsigned int msiof1_ss2_g_mux[] = {
2688         MSIOF1_SS2_G_MARK,
2689 };
2690 static const unsigned int msiof1_txd_g_pins[] = {
2691         /* TXD */
2692         RCAR_GP_PIN(3, 9),
2693 };
2694 static const unsigned int msiof1_txd_g_mux[] = {
2695         MSIOF1_TXD_G_MARK,
2696 };
2697 static const unsigned int msiof1_rxd_g_pins[] = {
2698         /* RXD */
2699         RCAR_GP_PIN(3, 8),
2700 };
2701 static const unsigned int msiof1_rxd_g_mux[] = {
2702         MSIOF1_RXD_G_MARK,
2703 };
2704 /* - MSIOF2 ----------------------------------------------------------------- */
2705 static const unsigned int msiof2_clk_a_pins[] = {
2706         /* SCK */
2707         RCAR_GP_PIN(1, 9),
2708 };
2709 static const unsigned int msiof2_clk_a_mux[] = {
2710         MSIOF2_SCK_A_MARK,
2711 };
2712 static const unsigned int msiof2_sync_a_pins[] = {
2713         /* SYNC */
2714         RCAR_GP_PIN(1, 8),
2715 };
2716 static const unsigned int msiof2_sync_a_mux[] = {
2717         MSIOF2_SYNC_A_MARK,
2718 };
2719 static const unsigned int msiof2_ss1_a_pins[] = {
2720         /* SS1 */
2721         RCAR_GP_PIN(1, 6),
2722 };
2723 static const unsigned int msiof2_ss1_a_mux[] = {
2724         MSIOF2_SS1_A_MARK,
2725 };
2726 static const unsigned int msiof2_ss2_a_pins[] = {
2727         /* SS2 */
2728         RCAR_GP_PIN(1, 7),
2729 };
2730 static const unsigned int msiof2_ss2_a_mux[] = {
2731         MSIOF2_SS2_A_MARK,
2732 };
2733 static const unsigned int msiof2_txd_a_pins[] = {
2734         /* TXD */
2735         RCAR_GP_PIN(1, 11),
2736 };
2737 static const unsigned int msiof2_txd_a_mux[] = {
2738         MSIOF2_TXD_A_MARK,
2739 };
2740 static const unsigned int msiof2_rxd_a_pins[] = {
2741         /* RXD */
2742         RCAR_GP_PIN(1, 10),
2743 };
2744 static const unsigned int msiof2_rxd_a_mux[] = {
2745         MSIOF2_RXD_A_MARK,
2746 };
2747 static const unsigned int msiof2_clk_b_pins[] = {
2748         /* SCK */
2749         RCAR_GP_PIN(0, 4),
2750 };
2751 static const unsigned int msiof2_clk_b_mux[] = {
2752         MSIOF2_SCK_B_MARK,
2753 };
2754 static const unsigned int msiof2_sync_b_pins[] = {
2755         /* SYNC */
2756         RCAR_GP_PIN(0, 5),
2757 };
2758 static const unsigned int msiof2_sync_b_mux[] = {
2759         MSIOF2_SYNC_B_MARK,
2760 };
2761 static const unsigned int msiof2_ss1_b_pins[] = {
2762         /* SS1 */
2763         RCAR_GP_PIN(0, 0),
2764 };
2765 static const unsigned int msiof2_ss1_b_mux[] = {
2766         MSIOF2_SS1_B_MARK,
2767 };
2768 static const unsigned int msiof2_ss2_b_pins[] = {
2769         /* SS2 */
2770         RCAR_GP_PIN(0, 1),
2771 };
2772 static const unsigned int msiof2_ss2_b_mux[] = {
2773         MSIOF2_SS2_B_MARK,
2774 };
2775 static const unsigned int msiof2_txd_b_pins[] = {
2776         /* TXD */
2777         RCAR_GP_PIN(0, 7),
2778 };
2779 static const unsigned int msiof2_txd_b_mux[] = {
2780         MSIOF2_TXD_B_MARK,
2781 };
2782 static const unsigned int msiof2_rxd_b_pins[] = {
2783         /* RXD */
2784         RCAR_GP_PIN(0, 6),
2785 };
2786 static const unsigned int msiof2_rxd_b_mux[] = {
2787         MSIOF2_RXD_B_MARK,
2788 };
2789 static const unsigned int msiof2_clk_c_pins[] = {
2790         /* SCK */
2791         RCAR_GP_PIN(2, 12),
2792 };
2793 static const unsigned int msiof2_clk_c_mux[] = {
2794         MSIOF2_SCK_C_MARK,
2795 };
2796 static const unsigned int msiof2_sync_c_pins[] = {
2797         /* SYNC */
2798         RCAR_GP_PIN(2, 11),
2799 };
2800 static const unsigned int msiof2_sync_c_mux[] = {
2801         MSIOF2_SYNC_C_MARK,
2802 };
2803 static const unsigned int msiof2_ss1_c_pins[] = {
2804         /* SS1 */
2805         RCAR_GP_PIN(2, 10),
2806 };
2807 static const unsigned int msiof2_ss1_c_mux[] = {
2808         MSIOF2_SS1_C_MARK,
2809 };
2810 static const unsigned int msiof2_ss2_c_pins[] = {
2811         /* SS2 */
2812         RCAR_GP_PIN(2, 9),
2813 };
2814 static const unsigned int msiof2_ss2_c_mux[] = {
2815         MSIOF2_SS2_C_MARK,
2816 };
2817 static const unsigned int msiof2_txd_c_pins[] = {
2818         /* TXD */
2819         RCAR_GP_PIN(2, 14),
2820 };
2821 static const unsigned int msiof2_txd_c_mux[] = {
2822         MSIOF2_TXD_C_MARK,
2823 };
2824 static const unsigned int msiof2_rxd_c_pins[] = {
2825         /* RXD */
2826         RCAR_GP_PIN(2, 13),
2827 };
2828 static const unsigned int msiof2_rxd_c_mux[] = {
2829         MSIOF2_RXD_C_MARK,
2830 };
2831 static const unsigned int msiof2_clk_d_pins[] = {
2832         /* SCK */
2833         RCAR_GP_PIN(0, 8),
2834 };
2835 static const unsigned int msiof2_clk_d_mux[] = {
2836         MSIOF2_SCK_D_MARK,
2837 };
2838 static const unsigned int msiof2_sync_d_pins[] = {
2839         /* SYNC */
2840         RCAR_GP_PIN(0, 9),
2841 };
2842 static const unsigned int msiof2_sync_d_mux[] = {
2843         MSIOF2_SYNC_D_MARK,
2844 };
2845 static const unsigned int msiof2_ss1_d_pins[] = {
2846         /* SS1 */
2847         RCAR_GP_PIN(0, 12),
2848 };
2849 static const unsigned int msiof2_ss1_d_mux[] = {
2850         MSIOF2_SS1_D_MARK,
2851 };
2852 static const unsigned int msiof2_ss2_d_pins[] = {
2853         /* SS2 */
2854         RCAR_GP_PIN(0, 13),
2855 };
2856 static const unsigned int msiof2_ss2_d_mux[] = {
2857         MSIOF2_SS2_D_MARK,
2858 };
2859 static const unsigned int msiof2_txd_d_pins[] = {
2860         /* TXD */
2861         RCAR_GP_PIN(0, 11),
2862 };
2863 static const unsigned int msiof2_txd_d_mux[] = {
2864         MSIOF2_TXD_D_MARK,
2865 };
2866 static const unsigned int msiof2_rxd_d_pins[] = {
2867         /* RXD */
2868         RCAR_GP_PIN(0, 10),
2869 };
2870 static const unsigned int msiof2_rxd_d_mux[] = {
2871         MSIOF2_RXD_D_MARK,
2872 };
2873 /* - MSIOF3 ----------------------------------------------------------------- */
2874 static const unsigned int msiof3_clk_a_pins[] = {
2875         /* SCK */
2876         RCAR_GP_PIN(0, 0),
2877 };
2878 static const unsigned int msiof3_clk_a_mux[] = {
2879         MSIOF3_SCK_A_MARK,
2880 };
2881 static const unsigned int msiof3_sync_a_pins[] = {
2882         /* SYNC */
2883         RCAR_GP_PIN(0, 1),
2884 };
2885 static const unsigned int msiof3_sync_a_mux[] = {
2886         MSIOF3_SYNC_A_MARK,
2887 };
2888 static const unsigned int msiof3_ss1_a_pins[] = {
2889         /* SS1 */
2890         RCAR_GP_PIN(0, 14),
2891 };
2892 static const unsigned int msiof3_ss1_a_mux[] = {
2893         MSIOF3_SS1_A_MARK,
2894 };
2895 static const unsigned int msiof3_ss2_a_pins[] = {
2896         /* SS2 */
2897         RCAR_GP_PIN(0, 15),
2898 };
2899 static const unsigned int msiof3_ss2_a_mux[] = {
2900         MSIOF3_SS2_A_MARK,
2901 };
2902 static const unsigned int msiof3_txd_a_pins[] = {
2903         /* TXD */
2904         RCAR_GP_PIN(0, 3),
2905 };
2906 static const unsigned int msiof3_txd_a_mux[] = {
2907         MSIOF3_TXD_A_MARK,
2908 };
2909 static const unsigned int msiof3_rxd_a_pins[] = {
2910         /* RXD */
2911         RCAR_GP_PIN(0, 2),
2912 };
2913 static const unsigned int msiof3_rxd_a_mux[] = {
2914         MSIOF3_RXD_A_MARK,
2915 };
2916 static const unsigned int msiof3_clk_b_pins[] = {
2917         /* SCK */
2918         RCAR_GP_PIN(1, 2),
2919 };
2920 static const unsigned int msiof3_clk_b_mux[] = {
2921         MSIOF3_SCK_B_MARK,
2922 };
2923 static const unsigned int msiof3_sync_b_pins[] = {
2924         /* SYNC */
2925         RCAR_GP_PIN(1, 0),
2926 };
2927 static const unsigned int msiof3_sync_b_mux[] = {
2928         MSIOF3_SYNC_B_MARK,
2929 };
2930 static const unsigned int msiof3_ss1_b_pins[] = {
2931         /* SS1 */
2932         RCAR_GP_PIN(1, 4),
2933 };
2934 static const unsigned int msiof3_ss1_b_mux[] = {
2935         MSIOF3_SS1_B_MARK,
2936 };
2937 static const unsigned int msiof3_ss2_b_pins[] = {
2938         /* SS2 */
2939         RCAR_GP_PIN(1, 5),
2940 };
2941 static const unsigned int msiof3_ss2_b_mux[] = {
2942         MSIOF3_SS2_B_MARK,
2943 };
2944 static const unsigned int msiof3_txd_b_pins[] = {
2945         /* TXD */
2946         RCAR_GP_PIN(1, 1),
2947 };
2948 static const unsigned int msiof3_txd_b_mux[] = {
2949         MSIOF3_TXD_B_MARK,
2950 };
2951 static const unsigned int msiof3_rxd_b_pins[] = {
2952         /* RXD */
2953         RCAR_GP_PIN(1, 3),
2954 };
2955 static const unsigned int msiof3_rxd_b_mux[] = {
2956         MSIOF3_RXD_B_MARK,
2957 };
2958 static const unsigned int msiof3_clk_c_pins[] = {
2959         /* SCK */
2960         RCAR_GP_PIN(1, 12),
2961 };
2962 static const unsigned int msiof3_clk_c_mux[] = {
2963         MSIOF3_SCK_C_MARK,
2964 };
2965 static const unsigned int msiof3_sync_c_pins[] = {
2966         /* SYNC */
2967         RCAR_GP_PIN(1, 13),
2968 };
2969 static const unsigned int msiof3_sync_c_mux[] = {
2970         MSIOF3_SYNC_C_MARK,
2971 };
2972 static const unsigned int msiof3_txd_c_pins[] = {
2973         /* TXD */
2974         RCAR_GP_PIN(1, 15),
2975 };
2976 static const unsigned int msiof3_txd_c_mux[] = {
2977         MSIOF3_TXD_C_MARK,
2978 };
2979 static const unsigned int msiof3_rxd_c_pins[] = {
2980         /* RXD */
2981         RCAR_GP_PIN(1, 14),
2982 };
2983 static const unsigned int msiof3_rxd_c_mux[] = {
2984         MSIOF3_RXD_C_MARK,
2985 };
2986 static const unsigned int msiof3_clk_d_pins[] = {
2987         /* SCK */
2988         RCAR_GP_PIN(1, 22),
2989 };
2990 static const unsigned int msiof3_clk_d_mux[] = {
2991         MSIOF3_SCK_D_MARK,
2992 };
2993 static const unsigned int msiof3_sync_d_pins[] = {
2994         /* SYNC */
2995         RCAR_GP_PIN(1, 23),
2996 };
2997 static const unsigned int msiof3_sync_d_mux[] = {
2998         MSIOF3_SYNC_D_MARK,
2999 };
3000 static const unsigned int msiof3_ss1_d_pins[] = {
3001         /* SS1 */
3002         RCAR_GP_PIN(1, 26),
3003 };
3004 static const unsigned int msiof3_ss1_d_mux[] = {
3005         MSIOF3_SS1_D_MARK,
3006 };
3007 static const unsigned int msiof3_txd_d_pins[] = {
3008         /* TXD */
3009         RCAR_GP_PIN(1, 25),
3010 };
3011 static const unsigned int msiof3_txd_d_mux[] = {
3012         MSIOF3_TXD_D_MARK,
3013 };
3014 static const unsigned int msiof3_rxd_d_pins[] = {
3015         /* RXD */
3016         RCAR_GP_PIN(1, 24),
3017 };
3018 static const unsigned int msiof3_rxd_d_mux[] = {
3019         MSIOF3_RXD_D_MARK,
3020 };
3021
3022 /* - PWM0 --------------------------------------------------------------------*/
3023 static const unsigned int pwm0_pins[] = {
3024         /* PWM */
3025         RCAR_GP_PIN(2, 6),
3026 };
3027 static const unsigned int pwm0_mux[] = {
3028         PWM0_MARK,
3029 };
3030 /* - PWM1 --------------------------------------------------------------------*/
3031 static const unsigned int pwm1_a_pins[] = {
3032         /* PWM */
3033         RCAR_GP_PIN(2, 7),
3034 };
3035 static const unsigned int pwm1_a_mux[] = {
3036         PWM1_A_MARK,
3037 };
3038 static const unsigned int pwm1_b_pins[] = {
3039         /* PWM */
3040         RCAR_GP_PIN(1, 8),
3041 };
3042 static const unsigned int pwm1_b_mux[] = {
3043         PWM1_B_MARK,
3044 };
3045 /* - PWM2 --------------------------------------------------------------------*/
3046 static const unsigned int pwm2_a_pins[] = {
3047         /* PWM */
3048         RCAR_GP_PIN(2, 8),
3049 };
3050 static const unsigned int pwm2_a_mux[] = {
3051         PWM2_A_MARK,
3052 };
3053 static const unsigned int pwm2_b_pins[] = {
3054         /* PWM */
3055         RCAR_GP_PIN(1, 11),
3056 };
3057 static const unsigned int pwm2_b_mux[] = {
3058         PWM2_B_MARK,
3059 };
3060 /* - PWM3 --------------------------------------------------------------------*/
3061 static const unsigned int pwm3_a_pins[] = {
3062         /* PWM */
3063         RCAR_GP_PIN(1, 0),
3064 };
3065 static const unsigned int pwm3_a_mux[] = {
3066         PWM3_A_MARK,
3067 };
3068 static const unsigned int pwm3_b_pins[] = {
3069         /* PWM */
3070         RCAR_GP_PIN(2, 2),
3071 };
3072 static const unsigned int pwm3_b_mux[] = {
3073         PWM3_B_MARK,
3074 };
3075 /* - PWM4 --------------------------------------------------------------------*/
3076 static const unsigned int pwm4_a_pins[] = {
3077         /* PWM */
3078         RCAR_GP_PIN(1, 1),
3079 };
3080 static const unsigned int pwm4_a_mux[] = {
3081         PWM4_A_MARK,
3082 };
3083 static const unsigned int pwm4_b_pins[] = {
3084         /* PWM */
3085         RCAR_GP_PIN(2, 3),
3086 };
3087 static const unsigned int pwm4_b_mux[] = {
3088         PWM4_B_MARK,
3089 };
3090 /* - PWM5 --------------------------------------------------------------------*/
3091 static const unsigned int pwm5_a_pins[] = {
3092         /* PWM */
3093         RCAR_GP_PIN(1, 2),
3094 };
3095 static const unsigned int pwm5_a_mux[] = {
3096         PWM5_A_MARK,
3097 };
3098 static const unsigned int pwm5_b_pins[] = {
3099         /* PWM */
3100         RCAR_GP_PIN(2, 4),
3101 };
3102 static const unsigned int pwm5_b_mux[] = {
3103         PWM5_B_MARK,
3104 };
3105 /* - PWM6 --------------------------------------------------------------------*/
3106 static const unsigned int pwm6_a_pins[] = {
3107         /* PWM */
3108         RCAR_GP_PIN(1, 3),
3109 };
3110 static const unsigned int pwm6_a_mux[] = {
3111         PWM6_A_MARK,
3112 };
3113 static const unsigned int pwm6_b_pins[] = {
3114         /* PWM */
3115         RCAR_GP_PIN(2, 5),
3116 };
3117 static const unsigned int pwm6_b_mux[] = {
3118         PWM6_B_MARK,
3119 };
3120
3121 /* - QSPI0 ------------------------------------------------------------------ */
3122 static const unsigned int qspi0_ctrl_pins[] = {
3123         /* QSPI0_SPCLK, QSPI0_SSL */
3124         PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3),
3125 };
3126 static const unsigned int qspi0_ctrl_mux[] = {
3127         QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3128 };
3129 static const unsigned int qspi0_data2_pins[] = {
3130         /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3131         PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3132 };
3133 static const unsigned int qspi0_data2_mux[] = {
3134         QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3135 };
3136 static const unsigned int qspi0_data4_pins[] = {
3137         /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
3138         PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3139         PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6),
3140 };
3141 static const unsigned int qspi0_data4_mux[] = {
3142         QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3143         QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3144 };
3145 /* - QSPI1 ------------------------------------------------------------------ */
3146 static const unsigned int qspi1_ctrl_pins[] = {
3147         /* QSPI1_SPCLK, QSPI1_SSL */
3148         PIN_NUMBER('V', 3), PIN_NUMBER('V', 5),
3149 };
3150 static const unsigned int qspi1_ctrl_mux[] = {
3151         QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3152 };
3153 static const unsigned int qspi1_data2_pins[] = {
3154         /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3155         PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3156 };
3157 static const unsigned int qspi1_data2_mux[] = {
3158         QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3159 };
3160 static const unsigned int qspi1_data4_pins[] = {
3161         /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
3162         PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3163         PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3),
3164 };
3165 static const unsigned int qspi1_data4_mux[] = {
3166         QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3167         QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3168 };
3169
3170 /* - SATA --------------------------------------------------------------------*/
3171 static const unsigned int sata0_devslp_a_pins[] = {
3172         /* DEVSLP */
3173         RCAR_GP_PIN(6, 16),
3174 };
3175 static const unsigned int sata0_devslp_a_mux[] = {
3176         SATA_DEVSLP_A_MARK,
3177 };
3178 static const unsigned int sata0_devslp_b_pins[] = {
3179         /* DEVSLP */
3180         RCAR_GP_PIN(4, 6),
3181 };
3182 static const unsigned int sata0_devslp_b_mux[] = {
3183         SATA_DEVSLP_B_MARK,
3184 };
3185
3186 /* - SCIF0 ------------------------------------------------------------------ */
3187 static const unsigned int scif0_data_pins[] = {
3188         /* RX, TX */
3189         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3190 };
3191 static const unsigned int scif0_data_mux[] = {
3192         RX0_MARK, TX0_MARK,
3193 };
3194 static const unsigned int scif0_clk_pins[] = {
3195         /* SCK */
3196         RCAR_GP_PIN(5, 0),
3197 };
3198 static const unsigned int scif0_clk_mux[] = {
3199         SCK0_MARK,
3200 };
3201 static const unsigned int scif0_ctrl_pins[] = {
3202         /* RTS, CTS */
3203         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3204 };
3205 static const unsigned int scif0_ctrl_mux[] = {
3206         RTS0_N_TANS_MARK, CTS0_N_MARK,
3207 };
3208 /* - SCIF1 ------------------------------------------------------------------ */
3209 static const unsigned int scif1_data_a_pins[] = {
3210         /* RX, TX */
3211         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3212 };
3213 static const unsigned int scif1_data_a_mux[] = {
3214         RX1_A_MARK, TX1_A_MARK,
3215 };
3216 static const unsigned int scif1_clk_pins[] = {
3217         /* SCK */
3218         RCAR_GP_PIN(6, 21),
3219 };
3220 static const unsigned int scif1_clk_mux[] = {
3221         SCK1_MARK,
3222 };
3223 static const unsigned int scif1_ctrl_pins[] = {
3224         /* RTS, CTS */
3225         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3226 };
3227 static const unsigned int scif1_ctrl_mux[] = {
3228         RTS1_N_TANS_MARK, CTS1_N_MARK,
3229 };
3230
3231 static const unsigned int scif1_data_b_pins[] = {
3232         /* RX, TX */
3233         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3234 };
3235 static const unsigned int scif1_data_b_mux[] = {
3236         RX1_B_MARK, TX1_B_MARK,
3237 };
3238 /* - SCIF2 ------------------------------------------------------------------ */
3239 static const unsigned int scif2_data_a_pins[] = {
3240         /* RX, TX */
3241         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3242 };
3243 static const unsigned int scif2_data_a_mux[] = {
3244         RX2_A_MARK, TX2_A_MARK,
3245 };
3246 static const unsigned int scif2_clk_pins[] = {
3247         /* SCK */
3248         RCAR_GP_PIN(5, 9),
3249 };
3250 static const unsigned int scif2_clk_mux[] = {
3251         SCK2_MARK,
3252 };
3253 static const unsigned int scif2_data_b_pins[] = {
3254         /* RX, TX */
3255         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3256 };
3257 static const unsigned int scif2_data_b_mux[] = {
3258         RX2_B_MARK, TX2_B_MARK,
3259 };
3260 /* - SCIF3 ------------------------------------------------------------------ */
3261 static const unsigned int scif3_data_a_pins[] = {
3262         /* RX, TX */
3263         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3264 };
3265 static const unsigned int scif3_data_a_mux[] = {
3266         RX3_A_MARK, TX3_A_MARK,
3267 };
3268 static const unsigned int scif3_clk_pins[] = {
3269         /* SCK */
3270         RCAR_GP_PIN(1, 22),
3271 };
3272 static const unsigned int scif3_clk_mux[] = {
3273         SCK3_MARK,
3274 };
3275 static const unsigned int scif3_ctrl_pins[] = {
3276         /* RTS, CTS */
3277         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3278 };
3279 static const unsigned int scif3_ctrl_mux[] = {
3280         RTS3_N_TANS_MARK, CTS3_N_MARK,
3281 };
3282 static const unsigned int scif3_data_b_pins[] = {
3283         /* RX, TX */
3284         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3285 };
3286 static const unsigned int scif3_data_b_mux[] = {
3287         RX3_B_MARK, TX3_B_MARK,
3288 };
3289 /* - SCIF4 ------------------------------------------------------------------ */
3290 static const unsigned int scif4_data_a_pins[] = {
3291         /* RX, TX */
3292         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3293 };
3294 static const unsigned int scif4_data_a_mux[] = {
3295         RX4_A_MARK, TX4_A_MARK,
3296 };
3297 static const unsigned int scif4_clk_a_pins[] = {
3298         /* SCK */
3299         RCAR_GP_PIN(2, 10),
3300 };
3301 static const unsigned int scif4_clk_a_mux[] = {
3302         SCK4_A_MARK,
3303 };
3304 static const unsigned int scif4_ctrl_a_pins[] = {
3305         /* RTS, CTS */
3306         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3307 };
3308 static const unsigned int scif4_ctrl_a_mux[] = {
3309         RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3310 };
3311 static const unsigned int scif4_data_b_pins[] = {
3312         /* RX, TX */
3313         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3314 };
3315 static const unsigned int scif4_data_b_mux[] = {
3316         RX4_B_MARK, TX4_B_MARK,
3317 };
3318 static const unsigned int scif4_clk_b_pins[] = {
3319         /* SCK */
3320         RCAR_GP_PIN(1, 5),
3321 };
3322 static const unsigned int scif4_clk_b_mux[] = {
3323         SCK4_B_MARK,
3324 };
3325 static const unsigned int scif4_ctrl_b_pins[] = {
3326         /* RTS, CTS */
3327         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3328 };
3329 static const unsigned int scif4_ctrl_b_mux[] = {
3330         RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3331 };
3332 static const unsigned int scif4_data_c_pins[] = {
3333         /* RX, TX */
3334         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3335 };
3336 static const unsigned int scif4_data_c_mux[] = {
3337         RX4_C_MARK, TX4_C_MARK,
3338 };
3339 static const unsigned int scif4_clk_c_pins[] = {
3340         /* SCK */
3341         RCAR_GP_PIN(0, 8),
3342 };
3343 static const unsigned int scif4_clk_c_mux[] = {
3344         SCK4_C_MARK,
3345 };
3346 static const unsigned int scif4_ctrl_c_pins[] = {
3347         /* RTS, CTS */
3348         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3349 };
3350 static const unsigned int scif4_ctrl_c_mux[] = {
3351         RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3352 };
3353 /* - SCIF5 ------------------------------------------------------------------ */
3354 static const unsigned int scif5_data_pins[] = {
3355         /* RX, TX */
3356         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3357 };
3358 static const unsigned int scif5_data_mux[] = {
3359         RX5_MARK, TX5_MARK,
3360 };
3361 static const unsigned int scif5_clk_pins[] = {
3362         /* SCK */
3363         RCAR_GP_PIN(6, 21),
3364 };
3365 static const unsigned int scif5_clk_mux[] = {
3366         SCK5_MARK,
3367 };
3368
3369 /* - SCIF Clock ------------------------------------------------------------- */
3370 static const unsigned int scif_clk_a_pins[] = {
3371         /* SCIF_CLK */
3372         RCAR_GP_PIN(6, 23),
3373 };
3374 static const unsigned int scif_clk_a_mux[] = {
3375         SCIF_CLK_A_MARK,
3376 };
3377 static const unsigned int scif_clk_b_pins[] = {
3378         /* SCIF_CLK */
3379         RCAR_GP_PIN(5, 9),
3380 };
3381 static const unsigned int scif_clk_b_mux[] = {
3382         SCIF_CLK_B_MARK,
3383 };
3384
3385 /* - SDHI0 ------------------------------------------------------------------ */
3386 static const unsigned int sdhi0_data1_pins[] = {
3387         /* D0 */
3388         RCAR_GP_PIN(3, 2),
3389 };
3390 static const unsigned int sdhi0_data1_mux[] = {
3391         SD0_DAT0_MARK,
3392 };
3393 static const unsigned int sdhi0_data4_pins[] = {
3394         /* D[0:3] */
3395         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3396         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3397 };
3398 static const unsigned int sdhi0_data4_mux[] = {
3399         SD0_DAT0_MARK, SD0_DAT1_MARK,
3400         SD0_DAT2_MARK, SD0_DAT3_MARK,
3401 };
3402 static const unsigned int sdhi0_ctrl_pins[] = {
3403         /* CLK, CMD */
3404         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3405 };
3406 static const unsigned int sdhi0_ctrl_mux[] = {
3407         SD0_CLK_MARK, SD0_CMD_MARK,
3408 };
3409 static const unsigned int sdhi0_cd_pins[] = {
3410         /* CD */
3411         RCAR_GP_PIN(3, 12),
3412 };
3413 static const unsigned int sdhi0_cd_mux[] = {
3414         SD0_CD_MARK,
3415 };
3416 static const unsigned int sdhi0_wp_pins[] = {
3417         /* WP */
3418         RCAR_GP_PIN(3, 13),
3419 };
3420 static const unsigned int sdhi0_wp_mux[] = {
3421         SD0_WP_MARK,
3422 };
3423 /* - SDHI1 ------------------------------------------------------------------ */
3424 static const unsigned int sdhi1_data1_pins[] = {
3425         /* D0 */
3426         RCAR_GP_PIN(3, 8),
3427 };
3428 static const unsigned int sdhi1_data1_mux[] = {
3429         SD1_DAT0_MARK,
3430 };
3431 static const unsigned int sdhi1_data4_pins[] = {
3432         /* D[0:3] */
3433         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3434         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3435 };
3436 static const unsigned int sdhi1_data4_mux[] = {
3437         SD1_DAT0_MARK, SD1_DAT1_MARK,
3438         SD1_DAT2_MARK, SD1_DAT3_MARK,
3439 };
3440 static const unsigned int sdhi1_ctrl_pins[] = {
3441         /* CLK, CMD */
3442         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3443 };
3444 static const unsigned int sdhi1_ctrl_mux[] = {
3445         SD1_CLK_MARK, SD1_CMD_MARK,
3446 };
3447 static const unsigned int sdhi1_cd_pins[] = {
3448         /* CD */
3449         RCAR_GP_PIN(3, 14),
3450 };
3451 static const unsigned int sdhi1_cd_mux[] = {
3452         SD1_CD_MARK,
3453 };
3454 static const unsigned int sdhi1_wp_pins[] = {
3455         /* WP */
3456         RCAR_GP_PIN(3, 15),
3457 };
3458 static const unsigned int sdhi1_wp_mux[] = {
3459         SD1_WP_MARK,
3460 };
3461 /* - SDHI2 ------------------------------------------------------------------ */
3462 static const unsigned int sdhi2_data1_pins[] = {
3463         /* D0 */
3464         RCAR_GP_PIN(4, 2),
3465 };
3466 static const unsigned int sdhi2_data1_mux[] = {
3467         SD2_DAT0_MARK,
3468 };
3469 static const unsigned int sdhi2_data4_pins[] = {
3470         /* D[0:3] */
3471         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3472         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3473 };
3474 static const unsigned int sdhi2_data4_mux[] = {
3475         SD2_DAT0_MARK, SD2_DAT1_MARK,
3476         SD2_DAT2_MARK, SD2_DAT3_MARK,
3477 };
3478 static const unsigned int sdhi2_data8_pins[] = {
3479         /* D[0:7] */
3480         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3481         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3482         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3483         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3484 };
3485 static const unsigned int sdhi2_data8_mux[] = {
3486         SD2_DAT0_MARK, SD2_DAT1_MARK,
3487         SD2_DAT2_MARK, SD2_DAT3_MARK,
3488         SD2_DAT4_MARK, SD2_DAT5_MARK,
3489         SD2_DAT6_MARK, SD2_DAT7_MARK,
3490 };
3491 static const unsigned int sdhi2_ctrl_pins[] = {
3492         /* CLK, CMD */
3493         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3494 };
3495 static const unsigned int sdhi2_ctrl_mux[] = {
3496         SD2_CLK_MARK, SD2_CMD_MARK,
3497 };
3498 static const unsigned int sdhi2_cd_a_pins[] = {
3499         /* CD */
3500         RCAR_GP_PIN(4, 13),
3501 };
3502 static const unsigned int sdhi2_cd_a_mux[] = {
3503         SD2_CD_A_MARK,
3504 };
3505 static const unsigned int sdhi2_cd_b_pins[] = {
3506         /* CD */
3507         RCAR_GP_PIN(5, 10),
3508 };
3509 static const unsigned int sdhi2_cd_b_mux[] = {
3510         SD2_CD_B_MARK,
3511 };
3512 static const unsigned int sdhi2_wp_a_pins[] = {
3513         /* WP */
3514         RCAR_GP_PIN(4, 14),
3515 };
3516 static const unsigned int sdhi2_wp_a_mux[] = {
3517         SD2_WP_A_MARK,
3518 };
3519 static const unsigned int sdhi2_wp_b_pins[] = {
3520         /* WP */
3521         RCAR_GP_PIN(5, 11),
3522 };
3523 static const unsigned int sdhi2_wp_b_mux[] = {
3524         SD2_WP_B_MARK,
3525 };
3526 static const unsigned int sdhi2_ds_pins[] = {
3527         /* DS */
3528         RCAR_GP_PIN(4, 6),
3529 };
3530 static const unsigned int sdhi2_ds_mux[] = {
3531         SD2_DS_MARK,
3532 };
3533 /* - SDHI3 ------------------------------------------------------------------ */
3534 static const unsigned int sdhi3_data1_pins[] = {
3535         /* D0 */
3536         RCAR_GP_PIN(4, 9),
3537 };
3538 static const unsigned int sdhi3_data1_mux[] = {
3539         SD3_DAT0_MARK,
3540 };
3541 static const unsigned int sdhi3_data4_pins[] = {
3542         /* D[0:3] */
3543         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3544         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3545 };
3546 static const unsigned int sdhi3_data4_mux[] = {
3547         SD3_DAT0_MARK, SD3_DAT1_MARK,
3548         SD3_DAT2_MARK, SD3_DAT3_MARK,
3549 };
3550 static const unsigned int sdhi3_data8_pins[] = {
3551         /* D[0:7] */
3552         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3553         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3554         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3555         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3556 };
3557 static const unsigned int sdhi3_data8_mux[] = {
3558         SD3_DAT0_MARK, SD3_DAT1_MARK,
3559         SD3_DAT2_MARK, SD3_DAT3_MARK,
3560         SD3_DAT4_MARK, SD3_DAT5_MARK,
3561         SD3_DAT6_MARK, SD3_DAT7_MARK,
3562 };
3563 static const unsigned int sdhi3_ctrl_pins[] = {
3564         /* CLK, CMD */
3565         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3566 };
3567 static const unsigned int sdhi3_ctrl_mux[] = {
3568         SD3_CLK_MARK, SD3_CMD_MARK,
3569 };
3570 static const unsigned int sdhi3_cd_pins[] = {
3571         /* CD */
3572         RCAR_GP_PIN(4, 15),
3573 };
3574 static const unsigned int sdhi3_cd_mux[] = {
3575         SD3_CD_MARK,
3576 };
3577 static const unsigned int sdhi3_wp_pins[] = {
3578         /* WP */
3579         RCAR_GP_PIN(4, 16),
3580 };
3581 static const unsigned int sdhi3_wp_mux[] = {
3582         SD3_WP_MARK,
3583 };
3584 static const unsigned int sdhi3_ds_pins[] = {
3585         /* DS */
3586         RCAR_GP_PIN(4, 17),
3587 };
3588 static const unsigned int sdhi3_ds_mux[] = {
3589         SD3_DS_MARK,
3590 };
3591
3592 /* - SSI -------------------------------------------------------------------- */
3593 static const unsigned int ssi0_data_pins[] = {
3594         /* SDATA */
3595         RCAR_GP_PIN(6, 2),
3596 };
3597 static const unsigned int ssi0_data_mux[] = {
3598         SSI_SDATA0_MARK,
3599 };
3600 static const unsigned int ssi01239_ctrl_pins[] = {
3601         /* SCK, WS */
3602         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3603 };
3604 static const unsigned int ssi01239_ctrl_mux[] = {
3605         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3606 };
3607 static const unsigned int ssi1_data_a_pins[] = {
3608         /* SDATA */
3609         RCAR_GP_PIN(6, 3),
3610 };
3611 static const unsigned int ssi1_data_a_mux[] = {
3612         SSI_SDATA1_A_MARK,
3613 };
3614 static const unsigned int ssi1_data_b_pins[] = {
3615         /* SDATA */
3616         RCAR_GP_PIN(5, 12),
3617 };
3618 static const unsigned int ssi1_data_b_mux[] = {
3619         SSI_SDATA1_B_MARK,
3620 };
3621 static const unsigned int ssi1_ctrl_a_pins[] = {
3622         /* SCK, WS */
3623         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3624 };
3625 static const unsigned int ssi1_ctrl_a_mux[] = {
3626         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3627 };
3628 static const unsigned int ssi1_ctrl_b_pins[] = {
3629         /* SCK, WS */
3630         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3631 };
3632 static const unsigned int ssi1_ctrl_b_mux[] = {
3633         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3634 };
3635 static const unsigned int ssi2_data_a_pins[] = {
3636         /* SDATA */
3637         RCAR_GP_PIN(6, 4),
3638 };
3639 static const unsigned int ssi2_data_a_mux[] = {
3640         SSI_SDATA2_A_MARK,
3641 };
3642 static const unsigned int ssi2_data_b_pins[] = {
3643         /* SDATA */
3644         RCAR_GP_PIN(5, 13),
3645 };
3646 static const unsigned int ssi2_data_b_mux[] = {
3647         SSI_SDATA2_B_MARK,
3648 };
3649 static const unsigned int ssi2_ctrl_a_pins[] = {
3650         /* SCK, WS */
3651         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3652 };
3653 static const unsigned int ssi2_ctrl_a_mux[] = {
3654         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3655 };
3656 static const unsigned int ssi2_ctrl_b_pins[] = {
3657         /* SCK, WS */
3658         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3659 };
3660 static const unsigned int ssi2_ctrl_b_mux[] = {
3661         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3662 };
3663 static const unsigned int ssi3_data_pins[] = {
3664         /* SDATA */
3665         RCAR_GP_PIN(6, 7),
3666 };
3667 static const unsigned int ssi3_data_mux[] = {
3668         SSI_SDATA3_MARK,
3669 };
3670 static const unsigned int ssi349_ctrl_pins[] = {
3671         /* SCK, WS */
3672         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3673 };
3674 static const unsigned int ssi349_ctrl_mux[] = {
3675         SSI_SCK349_MARK, SSI_WS349_MARK,
3676 };
3677 static const unsigned int ssi4_data_pins[] = {
3678         /* SDATA */
3679         RCAR_GP_PIN(6, 10),
3680 };
3681 static const unsigned int ssi4_data_mux[] = {
3682         SSI_SDATA4_MARK,
3683 };
3684 static const unsigned int ssi4_ctrl_pins[] = {
3685         /* SCK, WS */
3686         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3687 };
3688 static const unsigned int ssi4_ctrl_mux[] = {
3689         SSI_SCK4_MARK, SSI_WS4_MARK,
3690 };
3691 static const unsigned int ssi5_data_pins[] = {
3692         /* SDATA */
3693         RCAR_GP_PIN(6, 13),
3694 };
3695 static const unsigned int ssi5_data_mux[] = {
3696         SSI_SDATA5_MARK,
3697 };
3698 static const unsigned int ssi5_ctrl_pins[] = {
3699         /* SCK, WS */
3700         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3701 };
3702 static const unsigned int ssi5_ctrl_mux[] = {
3703         SSI_SCK5_MARK, SSI_WS5_MARK,
3704 };
3705 static const unsigned int ssi6_data_pins[] = {
3706         /* SDATA */
3707         RCAR_GP_PIN(6, 16),
3708 };
3709 static const unsigned int ssi6_data_mux[] = {
3710         SSI_SDATA6_MARK,
3711 };
3712 static const unsigned int ssi6_ctrl_pins[] = {
3713         /* SCK, WS */
3714         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3715 };
3716 static const unsigned int ssi6_ctrl_mux[] = {
3717         SSI_SCK6_MARK, SSI_WS6_MARK,
3718 };
3719 static const unsigned int ssi7_data_pins[] = {
3720         /* SDATA */
3721         RCAR_GP_PIN(6, 19),
3722 };
3723 static const unsigned int ssi7_data_mux[] = {
3724         SSI_SDATA7_MARK,
3725 };
3726 static const unsigned int ssi78_ctrl_pins[] = {
3727         /* SCK, WS */
3728         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3729 };
3730 static const unsigned int ssi78_ctrl_mux[] = {
3731         SSI_SCK78_MARK, SSI_WS78_MARK,
3732 };
3733 static const unsigned int ssi8_data_pins[] = {
3734         /* SDATA */
3735         RCAR_GP_PIN(6, 20),
3736 };
3737 static const unsigned int ssi8_data_mux[] = {
3738         SSI_SDATA8_MARK,
3739 };
3740 static const unsigned int ssi9_data_a_pins[] = {
3741         /* SDATA */
3742         RCAR_GP_PIN(6, 21),
3743 };
3744 static const unsigned int ssi9_data_a_mux[] = {
3745         SSI_SDATA9_A_MARK,
3746 };
3747 static const unsigned int ssi9_data_b_pins[] = {
3748         /* SDATA */
3749         RCAR_GP_PIN(5, 14),
3750 };
3751 static const unsigned int ssi9_data_b_mux[] = {
3752         SSI_SDATA9_B_MARK,
3753 };
3754 static const unsigned int ssi9_ctrl_a_pins[] = {
3755         /* SCK, WS */
3756         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3757 };
3758 static const unsigned int ssi9_ctrl_a_mux[] = {
3759         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3760 };
3761 static const unsigned int ssi9_ctrl_b_pins[] = {
3762         /* SCK, WS */
3763         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3764 };
3765 static const unsigned int ssi9_ctrl_b_mux[] = {
3766         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3767 };
3768
3769 /* - TMU -------------------------------------------------------------------- */
3770 static const unsigned int tmu_tclk1_a_pins[] = {
3771         /* TCLK */
3772         RCAR_GP_PIN(6, 23),
3773 };
3774 static const unsigned int tmu_tclk1_a_mux[] = {
3775         TCLK1_A_MARK,
3776 };
3777 static const unsigned int tmu_tclk1_b_pins[] = {
3778         /* TCLK */
3779         RCAR_GP_PIN(5, 19),
3780 };
3781 static const unsigned int tmu_tclk1_b_mux[] = {
3782         TCLK1_B_MARK,
3783 };
3784 static const unsigned int tmu_tclk2_a_pins[] = {
3785         /* TCLK */
3786         RCAR_GP_PIN(6, 19),
3787 };
3788 static const unsigned int tmu_tclk2_a_mux[] = {
3789         TCLK2_A_MARK,
3790 };
3791 static const unsigned int tmu_tclk2_b_pins[] = {
3792         /* TCLK */
3793         RCAR_GP_PIN(6, 28),
3794 };
3795 static const unsigned int tmu_tclk2_b_mux[] = {
3796         TCLK2_B_MARK,
3797 };
3798
3799 /* - USB0 ------------------------------------------------------------------- */
3800 static const unsigned int usb0_pins[] = {
3801         /* PWEN, OVC */
3802         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3803 };
3804 static const unsigned int usb0_mux[] = {
3805         USB0_PWEN_MARK, USB0_OVC_MARK,
3806 };
3807 /* - USB1 ------------------------------------------------------------------- */
3808 static const unsigned int usb1_pins[] = {
3809         /* PWEN, OVC */
3810         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3811 };
3812 static const unsigned int usb1_mux[] = {
3813         USB1_PWEN_MARK, USB1_OVC_MARK,
3814 };
3815 /* - USB2 ------------------------------------------------------------------- */
3816 static const unsigned int usb2_pins[] = {
3817         /* PWEN, OVC */
3818         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3819 };
3820 static const unsigned int usb2_mux[] = {
3821         USB2_PWEN_MARK, USB2_OVC_MARK,
3822 };
3823
3824 /* - USB30 ------------------------------------------------------------------ */
3825 static const unsigned int usb30_pins[] = {
3826         /* PWEN, OVC */
3827         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3828 };
3829 static const unsigned int usb30_mux[] = {
3830         USB30_PWEN_MARK, USB30_OVC_MARK,
3831 };
3832 /* - USB31 ------------------------------------------------------------------ */
3833 static const unsigned int usb31_pins[] = {
3834         /* PWEN, OVC */
3835         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3836 };
3837 static const unsigned int usb31_mux[] = {
3838         USB31_PWEN_MARK, USB31_OVC_MARK,
3839 };
3840
3841 static const struct sh_pfc_pin_group pinmux_groups[] = {
3842         SH_PFC_PIN_GROUP(audio_clk_a_a),
3843         SH_PFC_PIN_GROUP(audio_clk_a_b),
3844         SH_PFC_PIN_GROUP(audio_clk_a_c),
3845         SH_PFC_PIN_GROUP(audio_clk_b_a),
3846         SH_PFC_PIN_GROUP(audio_clk_b_b),
3847         SH_PFC_PIN_GROUP(audio_clk_c_a),
3848         SH_PFC_PIN_GROUP(audio_clk_c_b),
3849         SH_PFC_PIN_GROUP(audio_clkout_a),
3850         SH_PFC_PIN_GROUP(audio_clkout_b),
3851         SH_PFC_PIN_GROUP(audio_clkout_c),
3852         SH_PFC_PIN_GROUP(audio_clkout_d),
3853         SH_PFC_PIN_GROUP(audio_clkout1_a),
3854         SH_PFC_PIN_GROUP(audio_clkout1_b),
3855         SH_PFC_PIN_GROUP(audio_clkout2_a),
3856         SH_PFC_PIN_GROUP(audio_clkout2_b),
3857         SH_PFC_PIN_GROUP(audio_clkout3_a),
3858         SH_PFC_PIN_GROUP(audio_clkout3_b),
3859         SH_PFC_PIN_GROUP(avb_link),
3860         SH_PFC_PIN_GROUP(avb_magic),
3861         SH_PFC_PIN_GROUP(avb_phy_int),
3862         SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),      /* Deprecated */
3863         SH_PFC_PIN_GROUP(avb_mdio),
3864         SH_PFC_PIN_GROUP(avb_mii),
3865         SH_PFC_PIN_GROUP(avb_avtp_pps),
3866         SH_PFC_PIN_GROUP(avb_avtp_match_a),
3867         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3868         SH_PFC_PIN_GROUP(avb_avtp_match_b),
3869         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3870         SH_PFC_PIN_GROUP(can0_data_a),
3871         SH_PFC_PIN_GROUP(can0_data_b),
3872         SH_PFC_PIN_GROUP(can1_data),
3873         SH_PFC_PIN_GROUP(can_clk),
3874         SH_PFC_PIN_GROUP(canfd0_data_a),
3875         SH_PFC_PIN_GROUP(canfd0_data_b),
3876         SH_PFC_PIN_GROUP(canfd1_data),
3877         SH_PFC_PIN_GROUP(drif0_ctrl_a),
3878         SH_PFC_PIN_GROUP(drif0_data0_a),
3879         SH_PFC_PIN_GROUP(drif0_data1_a),
3880         SH_PFC_PIN_GROUP(drif0_ctrl_b),
3881         SH_PFC_PIN_GROUP(drif0_data0_b),
3882         SH_PFC_PIN_GROUP(drif0_data1_b),
3883         SH_PFC_PIN_GROUP(drif0_ctrl_c),
3884         SH_PFC_PIN_GROUP(drif0_data0_c),
3885         SH_PFC_PIN_GROUP(drif0_data1_c),
3886         SH_PFC_PIN_GROUP(drif1_ctrl_a),
3887         SH_PFC_PIN_GROUP(drif1_data0_a),
3888         SH_PFC_PIN_GROUP(drif1_data1_a),
3889         SH_PFC_PIN_GROUP(drif1_ctrl_b),
3890         SH_PFC_PIN_GROUP(drif1_data0_b),
3891         SH_PFC_PIN_GROUP(drif1_data1_b),
3892         SH_PFC_PIN_GROUP(drif1_ctrl_c),
3893         SH_PFC_PIN_GROUP(drif1_data0_c),
3894         SH_PFC_PIN_GROUP(drif1_data1_c),
3895         SH_PFC_PIN_GROUP(drif2_ctrl_a),
3896         SH_PFC_PIN_GROUP(drif2_data0_a),
3897         SH_PFC_PIN_GROUP(drif2_data1_a),
3898         SH_PFC_PIN_GROUP(drif2_ctrl_b),
3899         SH_PFC_PIN_GROUP(drif2_data0_b),
3900         SH_PFC_PIN_GROUP(drif2_data1_b),
3901         SH_PFC_PIN_GROUP(drif3_ctrl_a),
3902         SH_PFC_PIN_GROUP(drif3_data0_a),
3903         SH_PFC_PIN_GROUP(drif3_data1_a),
3904         SH_PFC_PIN_GROUP(drif3_ctrl_b),
3905         SH_PFC_PIN_GROUP(drif3_data0_b),
3906         SH_PFC_PIN_GROUP(drif3_data1_b),
3907         SH_PFC_PIN_GROUP(du_rgb666),
3908         SH_PFC_PIN_GROUP(du_rgb888),
3909         SH_PFC_PIN_GROUP(du_clk_out_0),
3910         SH_PFC_PIN_GROUP(du_clk_out_1),
3911         SH_PFC_PIN_GROUP(du_sync),
3912         SH_PFC_PIN_GROUP(du_oddf),
3913         SH_PFC_PIN_GROUP(du_cde),
3914         SH_PFC_PIN_GROUP(du_disp),
3915         SH_PFC_PIN_GROUP(hdmi0_cec),
3916         SH_PFC_PIN_GROUP(hdmi1_cec),
3917         SH_PFC_PIN_GROUP(hscif0_data),
3918         SH_PFC_PIN_GROUP(hscif0_clk),
3919         SH_PFC_PIN_GROUP(hscif0_ctrl),
3920         SH_PFC_PIN_GROUP(hscif1_data_a),
3921         SH_PFC_PIN_GROUP(hscif1_clk_a),
3922         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3923         SH_PFC_PIN_GROUP(hscif1_data_b),
3924         SH_PFC_PIN_GROUP(hscif1_clk_b),
3925         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3926         SH_PFC_PIN_GROUP(hscif2_data_a),
3927         SH_PFC_PIN_GROUP(hscif2_clk_a),
3928         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3929         SH_PFC_PIN_GROUP(hscif2_data_b),
3930         SH_PFC_PIN_GROUP(hscif2_clk_b),
3931         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3932         SH_PFC_PIN_GROUP(hscif3_data_a),
3933         SH_PFC_PIN_GROUP(hscif3_clk),
3934         SH_PFC_PIN_GROUP(hscif3_ctrl),
3935         SH_PFC_PIN_GROUP(hscif3_data_b),
3936         SH_PFC_PIN_GROUP(hscif3_data_c),
3937         SH_PFC_PIN_GROUP(hscif3_data_d),
3938         SH_PFC_PIN_GROUP(hscif4_data_a),
3939         SH_PFC_PIN_GROUP(hscif4_clk),
3940         SH_PFC_PIN_GROUP(hscif4_ctrl),
3941         SH_PFC_PIN_GROUP(hscif4_data_b),
3942         SH_PFC_PIN_GROUP(i2c1_a),
3943         SH_PFC_PIN_GROUP(i2c1_b),
3944         SH_PFC_PIN_GROUP(i2c2_a),
3945         SH_PFC_PIN_GROUP(i2c2_b),
3946         SH_PFC_PIN_GROUP(i2c6_a),
3947         SH_PFC_PIN_GROUP(i2c6_b),
3948         SH_PFC_PIN_GROUP(i2c6_c),
3949         SH_PFC_PIN_GROUP(intc_ex_irq0),
3950         SH_PFC_PIN_GROUP(intc_ex_irq1),
3951         SH_PFC_PIN_GROUP(intc_ex_irq2),
3952         SH_PFC_PIN_GROUP(intc_ex_irq3),
3953         SH_PFC_PIN_GROUP(intc_ex_irq4),
3954         SH_PFC_PIN_GROUP(intc_ex_irq5),
3955         SH_PFC_PIN_GROUP(msiof0_clk),
3956         SH_PFC_PIN_GROUP(msiof0_sync),
3957         SH_PFC_PIN_GROUP(msiof0_ss1),
3958         SH_PFC_PIN_GROUP(msiof0_ss2),
3959         SH_PFC_PIN_GROUP(msiof0_txd),
3960         SH_PFC_PIN_GROUP(msiof0_rxd),
3961         SH_PFC_PIN_GROUP(msiof1_clk_a),
3962         SH_PFC_PIN_GROUP(msiof1_sync_a),
3963         SH_PFC_PIN_GROUP(msiof1_ss1_a),
3964         SH_PFC_PIN_GROUP(msiof1_ss2_a),
3965         SH_PFC_PIN_GROUP(msiof1_txd_a),
3966         SH_PFC_PIN_GROUP(msiof1_rxd_a),
3967         SH_PFC_PIN_GROUP(msiof1_clk_b),
3968         SH_PFC_PIN_GROUP(msiof1_sync_b),
3969         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3970         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3971         SH_PFC_PIN_GROUP(msiof1_txd_b),
3972         SH_PFC_PIN_GROUP(msiof1_rxd_b),
3973         SH_PFC_PIN_GROUP(msiof1_clk_c),
3974         SH_PFC_PIN_GROUP(msiof1_sync_c),
3975         SH_PFC_PIN_GROUP(msiof1_ss1_c),
3976         SH_PFC_PIN_GROUP(msiof1_ss2_c),
3977         SH_PFC_PIN_GROUP(msiof1_txd_c),
3978         SH_PFC_PIN_GROUP(msiof1_rxd_c),
3979         SH_PFC_PIN_GROUP(msiof1_clk_d),
3980         SH_PFC_PIN_GROUP(msiof1_sync_d),
3981         SH_PFC_PIN_GROUP(msiof1_ss1_d),
3982         SH_PFC_PIN_GROUP(msiof1_ss2_d),
3983         SH_PFC_PIN_GROUP(msiof1_txd_d),
3984         SH_PFC_PIN_GROUP(msiof1_rxd_d),
3985         SH_PFC_PIN_GROUP(msiof1_clk_e),
3986         SH_PFC_PIN_GROUP(msiof1_sync_e),
3987         SH_PFC_PIN_GROUP(msiof1_ss1_e),
3988         SH_PFC_PIN_GROUP(msiof1_ss2_e),
3989         SH_PFC_PIN_GROUP(msiof1_txd_e),
3990         SH_PFC_PIN_GROUP(msiof1_rxd_e),
3991         SH_PFC_PIN_GROUP(msiof1_clk_f),
3992         SH_PFC_PIN_GROUP(msiof1_sync_f),
3993         SH_PFC_PIN_GROUP(msiof1_ss1_f),
3994         SH_PFC_PIN_GROUP(msiof1_ss2_f),
3995         SH_PFC_PIN_GROUP(msiof1_txd_f),
3996         SH_PFC_PIN_GROUP(msiof1_rxd_f),
3997         SH_PFC_PIN_GROUP(msiof1_clk_g),
3998         SH_PFC_PIN_GROUP(msiof1_sync_g),
3999         SH_PFC_PIN_GROUP(msiof1_ss1_g),
4000         SH_PFC_PIN_GROUP(msiof1_ss2_g),
4001         SH_PFC_PIN_GROUP(msiof1_txd_g),
4002         SH_PFC_PIN_GROUP(msiof1_rxd_g),
4003         SH_PFC_PIN_GROUP(msiof2_clk_a),
4004         SH_PFC_PIN_GROUP(msiof2_sync_a),
4005         SH_PFC_PIN_GROUP(msiof2_ss1_a),
4006         SH_PFC_PIN_GROUP(msiof2_ss2_a),
4007         SH_PFC_PIN_GROUP(msiof2_txd_a),
4008         SH_PFC_PIN_GROUP(msiof2_rxd_a),
4009         SH_PFC_PIN_GROUP(msiof2_clk_b),
4010         SH_PFC_PIN_GROUP(msiof2_sync_b),
4011         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4012         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4013         SH_PFC_PIN_GROUP(msiof2_txd_b),
4014         SH_PFC_PIN_GROUP(msiof2_rxd_b),
4015         SH_PFC_PIN_GROUP(msiof2_clk_c),
4016         SH_PFC_PIN_GROUP(msiof2_sync_c),
4017         SH_PFC_PIN_GROUP(msiof2_ss1_c),
4018         SH_PFC_PIN_GROUP(msiof2_ss2_c),
4019         SH_PFC_PIN_GROUP(msiof2_txd_c),
4020         SH_PFC_PIN_GROUP(msiof2_rxd_c),
4021         SH_PFC_PIN_GROUP(msiof2_clk_d),
4022         SH_PFC_PIN_GROUP(msiof2_sync_d),
4023         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4024         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4025         SH_PFC_PIN_GROUP(msiof2_txd_d),
4026         SH_PFC_PIN_GROUP(msiof2_rxd_d),
4027         SH_PFC_PIN_GROUP(msiof3_clk_a),
4028         SH_PFC_PIN_GROUP(msiof3_sync_a),
4029         SH_PFC_PIN_GROUP(msiof3_ss1_a),
4030         SH_PFC_PIN_GROUP(msiof3_ss2_a),
4031         SH_PFC_PIN_GROUP(msiof3_txd_a),
4032         SH_PFC_PIN_GROUP(msiof3_rxd_a),
4033         SH_PFC_PIN_GROUP(msiof3_clk_b),
4034         SH_PFC_PIN_GROUP(msiof3_sync_b),
4035         SH_PFC_PIN_GROUP(msiof3_ss1_b),
4036         SH_PFC_PIN_GROUP(msiof3_ss2_b),
4037         SH_PFC_PIN_GROUP(msiof3_txd_b),
4038         SH_PFC_PIN_GROUP(msiof3_rxd_b),
4039         SH_PFC_PIN_GROUP(msiof3_clk_c),
4040         SH_PFC_PIN_GROUP(msiof3_sync_c),
4041         SH_PFC_PIN_GROUP(msiof3_txd_c),
4042         SH_PFC_PIN_GROUP(msiof3_rxd_c),
4043         SH_PFC_PIN_GROUP(msiof3_clk_d),
4044         SH_PFC_PIN_GROUP(msiof3_sync_d),
4045         SH_PFC_PIN_GROUP(msiof3_ss1_d),
4046         SH_PFC_PIN_GROUP(msiof3_txd_d),
4047         SH_PFC_PIN_GROUP(msiof3_rxd_d),
4048         SH_PFC_PIN_GROUP(pwm0),
4049         SH_PFC_PIN_GROUP(pwm1_a),
4050         SH_PFC_PIN_GROUP(pwm1_b),
4051         SH_PFC_PIN_GROUP(pwm2_a),
4052         SH_PFC_PIN_GROUP(pwm2_b),
4053         SH_PFC_PIN_GROUP(pwm3_a),
4054         SH_PFC_PIN_GROUP(pwm3_b),
4055         SH_PFC_PIN_GROUP(pwm4_a),
4056         SH_PFC_PIN_GROUP(pwm4_b),
4057         SH_PFC_PIN_GROUP(pwm5_a),
4058         SH_PFC_PIN_GROUP(pwm5_b),
4059         SH_PFC_PIN_GROUP(pwm6_a),
4060         SH_PFC_PIN_GROUP(pwm6_b),
4061         SH_PFC_PIN_GROUP(qspi0_ctrl),
4062         SH_PFC_PIN_GROUP(qspi0_data2),
4063         SH_PFC_PIN_GROUP(qspi0_data4),
4064         SH_PFC_PIN_GROUP(qspi1_ctrl),
4065         SH_PFC_PIN_GROUP(qspi1_data2),
4066         SH_PFC_PIN_GROUP(qspi1_data4),
4067         SH_PFC_PIN_GROUP(sata0_devslp_a),
4068         SH_PFC_PIN_GROUP(sata0_devslp_b),
4069         SH_PFC_PIN_GROUP(scif0_data),
4070         SH_PFC_PIN_GROUP(scif0_clk),
4071         SH_PFC_PIN_GROUP(scif0_ctrl),
4072         SH_PFC_PIN_GROUP(scif1_data_a),
4073         SH_PFC_PIN_GROUP(scif1_clk),
4074         SH_PFC_PIN_GROUP(scif1_ctrl),
4075         SH_PFC_PIN_GROUP(scif1_data_b),
4076         SH_PFC_PIN_GROUP(scif2_data_a),
4077         SH_PFC_PIN_GROUP(scif2_clk),
4078         SH_PFC_PIN_GROUP(scif2_data_b),
4079         SH_PFC_PIN_GROUP(scif3_data_a),
4080         SH_PFC_PIN_GROUP(scif3_clk),
4081         SH_PFC_PIN_GROUP(scif3_ctrl),
4082         SH_PFC_PIN_GROUP(scif3_data_b),
4083         SH_PFC_PIN_GROUP(scif4_data_a),
4084         SH_PFC_PIN_GROUP(scif4_clk_a),
4085         SH_PFC_PIN_GROUP(scif4_ctrl_a),
4086         SH_PFC_PIN_GROUP(scif4_data_b),
4087         SH_PFC_PIN_GROUP(scif4_clk_b),
4088         SH_PFC_PIN_GROUP(scif4_ctrl_b),
4089         SH_PFC_PIN_GROUP(scif4_data_c),
4090         SH_PFC_PIN_GROUP(scif4_clk_c),
4091         SH_PFC_PIN_GROUP(scif4_ctrl_c),
4092         SH_PFC_PIN_GROUP(scif5_data),
4093         SH_PFC_PIN_GROUP(scif5_clk),
4094         SH_PFC_PIN_GROUP(scif_clk_a),
4095         SH_PFC_PIN_GROUP(scif_clk_b),
4096         SH_PFC_PIN_GROUP(sdhi0_data1),
4097         SH_PFC_PIN_GROUP(sdhi0_data4),
4098         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4099         SH_PFC_PIN_GROUP(sdhi0_cd),
4100         SH_PFC_PIN_GROUP(sdhi0_wp),
4101         SH_PFC_PIN_GROUP(sdhi1_data1),
4102         SH_PFC_PIN_GROUP(sdhi1_data4),
4103         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4104         SH_PFC_PIN_GROUP(sdhi1_cd),
4105         SH_PFC_PIN_GROUP(sdhi1_wp),
4106         SH_PFC_PIN_GROUP(sdhi2_data1),
4107         SH_PFC_PIN_GROUP(sdhi2_data4),
4108         SH_PFC_PIN_GROUP(sdhi2_data8),
4109         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4110         SH_PFC_PIN_GROUP(sdhi2_cd_a),
4111         SH_PFC_PIN_GROUP(sdhi2_wp_a),
4112         SH_PFC_PIN_GROUP(sdhi2_cd_b),
4113         SH_PFC_PIN_GROUP(sdhi2_wp_b),
4114         SH_PFC_PIN_GROUP(sdhi2_ds),
4115         SH_PFC_PIN_GROUP(sdhi3_data1),
4116         SH_PFC_PIN_GROUP(sdhi3_data4),
4117         SH_PFC_PIN_GROUP(sdhi3_data8),
4118         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4119         SH_PFC_PIN_GROUP(sdhi3_cd),
4120         SH_PFC_PIN_GROUP(sdhi3_wp),
4121         SH_PFC_PIN_GROUP(sdhi3_ds),
4122         SH_PFC_PIN_GROUP(ssi0_data),
4123         SH_PFC_PIN_GROUP(ssi01239_ctrl),
4124         SH_PFC_PIN_GROUP(ssi1_data_a),
4125         SH_PFC_PIN_GROUP(ssi1_data_b),
4126         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4127         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4128         SH_PFC_PIN_GROUP(ssi2_data_a),
4129         SH_PFC_PIN_GROUP(ssi2_data_b),
4130         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4131         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4132         SH_PFC_PIN_GROUP(ssi3_data),
4133         SH_PFC_PIN_GROUP(ssi349_ctrl),
4134         SH_PFC_PIN_GROUP(ssi4_data),
4135         SH_PFC_PIN_GROUP(ssi4_ctrl),
4136         SH_PFC_PIN_GROUP(ssi5_data),
4137         SH_PFC_PIN_GROUP(ssi5_ctrl),
4138         SH_PFC_PIN_GROUP(ssi6_data),
4139         SH_PFC_PIN_GROUP(ssi6_ctrl),
4140         SH_PFC_PIN_GROUP(ssi7_data),
4141         SH_PFC_PIN_GROUP(ssi78_ctrl),
4142         SH_PFC_PIN_GROUP(ssi8_data),
4143         SH_PFC_PIN_GROUP(ssi9_data_a),
4144         SH_PFC_PIN_GROUP(ssi9_data_b),
4145         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4146         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4147         SH_PFC_PIN_GROUP(tmu_tclk1_a),
4148         SH_PFC_PIN_GROUP(tmu_tclk1_b),
4149         SH_PFC_PIN_GROUP(tmu_tclk2_a),
4150         SH_PFC_PIN_GROUP(tmu_tclk2_b),
4151         SH_PFC_PIN_GROUP(usb0),
4152         SH_PFC_PIN_GROUP(usb1),
4153         SH_PFC_PIN_GROUP(usb2),
4154         SH_PFC_PIN_GROUP(usb30),
4155         SH_PFC_PIN_GROUP(usb31),
4156 };
4157
4158 static const char * const audio_clk_groups[] = {
4159         "audio_clk_a_a",
4160         "audio_clk_a_b",
4161         "audio_clk_a_c",
4162         "audio_clk_b_a",
4163         "audio_clk_b_b",
4164         "audio_clk_c_a",
4165         "audio_clk_c_b",
4166         "audio_clkout_a",
4167         "audio_clkout_b",
4168         "audio_clkout_c",
4169         "audio_clkout_d",
4170         "audio_clkout1_a",
4171         "audio_clkout1_b",
4172         "audio_clkout2_a",
4173         "audio_clkout2_b",
4174         "audio_clkout3_a",
4175         "audio_clkout3_b",
4176 };
4177
4178 static const char * const avb_groups[] = {
4179         "avb_link",
4180         "avb_magic",
4181         "avb_phy_int",
4182         "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
4183         "avb_mdio",
4184         "avb_mii",
4185         "avb_avtp_pps",
4186         "avb_avtp_match_a",
4187         "avb_avtp_capture_a",
4188         "avb_avtp_match_b",
4189         "avb_avtp_capture_b",
4190 };
4191
4192 static const char * const can0_groups[] = {
4193         "can0_data_a",
4194         "can0_data_b",
4195 };
4196
4197 static const char * const can1_groups[] = {
4198         "can1_data",
4199 };
4200
4201 static const char * const can_clk_groups[] = {
4202         "can_clk",
4203 };
4204
4205 static const char * const canfd0_groups[] = {
4206         "canfd0_data_a",
4207         "canfd0_data_b",
4208 };
4209
4210 static const char * const canfd1_groups[] = {
4211         "canfd1_data",
4212 };
4213
4214 static const char * const drif0_groups[] = {
4215         "drif0_ctrl_a",
4216         "drif0_data0_a",
4217         "drif0_data1_a",
4218         "drif0_ctrl_b",
4219         "drif0_data0_b",
4220         "drif0_data1_b",
4221         "drif0_ctrl_c",
4222         "drif0_data0_c",
4223         "drif0_data1_c",
4224 };
4225
4226 static const char * const drif1_groups[] = {
4227         "drif1_ctrl_a",
4228         "drif1_data0_a",
4229         "drif1_data1_a",
4230         "drif1_ctrl_b",
4231         "drif1_data0_b",
4232         "drif1_data1_b",
4233         "drif1_ctrl_c",
4234         "drif1_data0_c",
4235         "drif1_data1_c",
4236 };
4237
4238 static const char * const drif2_groups[] = {
4239         "drif2_ctrl_a",
4240         "drif2_data0_a",
4241         "drif2_data1_a",
4242         "drif2_ctrl_b",
4243         "drif2_data0_b",
4244         "drif2_data1_b",
4245 };
4246
4247 static const char * const drif3_groups[] = {
4248         "drif3_ctrl_a",
4249         "drif3_data0_a",
4250         "drif3_data1_a",
4251         "drif3_ctrl_b",
4252         "drif3_data0_b",
4253         "drif3_data1_b",
4254 };
4255
4256 static const char * const du_groups[] = {
4257         "du_rgb666",
4258         "du_rgb888",
4259         "du_clk_out_0",
4260         "du_clk_out_1",
4261         "du_sync",
4262         "du_oddf",
4263         "du_cde",
4264         "du_disp",
4265 };
4266
4267 static const char * const hdmi0_groups[] = {
4268         "hdmi0_cec",
4269 };
4270
4271 static const char * const hdmi1_groups[] = {
4272         "hdmi1_cec",
4273 };
4274
4275 static const char * const hscif0_groups[] = {
4276         "hscif0_data",
4277         "hscif0_clk",
4278         "hscif0_ctrl",
4279 };
4280
4281 static const char * const hscif1_groups[] = {
4282         "hscif1_data_a",
4283         "hscif1_clk_a",
4284         "hscif1_ctrl_a",
4285         "hscif1_data_b",
4286         "hscif1_clk_b",
4287         "hscif1_ctrl_b",
4288 };
4289
4290 static const char * const hscif2_groups[] = {
4291         "hscif2_data_a",
4292         "hscif2_clk_a",
4293         "hscif2_ctrl_a",
4294         "hscif2_data_b",
4295         "hscif2_clk_b",
4296         "hscif2_ctrl_b",
4297 };
4298
4299 static const char * const hscif3_groups[] = {
4300         "hscif3_data_a",
4301         "hscif3_clk",
4302         "hscif3_ctrl",
4303         "hscif3_data_b",
4304         "hscif3_data_c",
4305         "hscif3_data_d",
4306 };
4307
4308 static const char * const hscif4_groups[] = {
4309         "hscif4_data_a",
4310         "hscif4_clk",
4311         "hscif4_ctrl",
4312         "hscif4_data_b",
4313 };
4314
4315 static const char * const i2c1_groups[] = {
4316         "i2c1_a",
4317         "i2c1_b",
4318 };
4319
4320 static const char * const i2c2_groups[] = {
4321         "i2c2_a",
4322         "i2c2_b",
4323 };
4324
4325 static const char * const i2c6_groups[] = {
4326         "i2c6_a",
4327         "i2c6_b",
4328         "i2c6_c",
4329 };
4330
4331 static const char * const intc_ex_groups[] = {
4332         "intc_ex_irq0",
4333         "intc_ex_irq1",
4334         "intc_ex_irq2",
4335         "intc_ex_irq3",
4336         "intc_ex_irq4",
4337         "intc_ex_irq5",
4338 };
4339
4340 static const char * const msiof0_groups[] = {
4341         "msiof0_clk",
4342         "msiof0_sync",
4343         "msiof0_ss1",
4344         "msiof0_ss2",
4345         "msiof0_txd",
4346         "msiof0_rxd",
4347 };
4348
4349 static const char * const msiof1_groups[] = {
4350         "msiof1_clk_a",
4351         "msiof1_sync_a",
4352         "msiof1_ss1_a",
4353         "msiof1_ss2_a",
4354         "msiof1_txd_a",
4355         "msiof1_rxd_a",
4356         "msiof1_clk_b",
4357         "msiof1_sync_b",
4358         "msiof1_ss1_b",
4359         "msiof1_ss2_b",
4360         "msiof1_txd_b",
4361         "msiof1_rxd_b",
4362         "msiof1_clk_c",
4363         "msiof1_sync_c",
4364         "msiof1_ss1_c",
4365         "msiof1_ss2_c",
4366         "msiof1_txd_c",
4367         "msiof1_rxd_c",
4368         "msiof1_clk_d",
4369         "msiof1_sync_d",
4370         "msiof1_ss1_d",
4371         "msiof1_ss2_d",
4372         "msiof1_txd_d",
4373         "msiof1_rxd_d",
4374         "msiof1_clk_e",
4375         "msiof1_sync_e",
4376         "msiof1_ss1_e",
4377         "msiof1_ss2_e",
4378         "msiof1_txd_e",
4379         "msiof1_rxd_e",
4380         "msiof1_clk_f",
4381         "msiof1_sync_f",
4382         "msiof1_ss1_f",
4383         "msiof1_ss2_f",
4384         "msiof1_txd_f",
4385         "msiof1_rxd_f",
4386         "msiof1_clk_g",
4387         "msiof1_sync_g",
4388         "msiof1_ss1_g",
4389         "msiof1_ss2_g",
4390         "msiof1_txd_g",
4391         "msiof1_rxd_g",
4392 };
4393
4394 static const char * const msiof2_groups[] = {
4395         "msiof2_clk_a",
4396         "msiof2_sync_a",
4397         "msiof2_ss1_a",
4398         "msiof2_ss2_a",
4399         "msiof2_txd_a",
4400         "msiof2_rxd_a",
4401         "msiof2_clk_b",
4402         "msiof2_sync_b",
4403         "msiof2_ss1_b",
4404         "msiof2_ss2_b",
4405         "msiof2_txd_b",
4406         "msiof2_rxd_b",
4407         "msiof2_clk_c",
4408         "msiof2_sync_c",
4409         "msiof2_ss1_c",
4410         "msiof2_ss2_c",
4411         "msiof2_txd_c",
4412         "msiof2_rxd_c",
4413         "msiof2_clk_d",
4414         "msiof2_sync_d",
4415         "msiof2_ss1_d",
4416         "msiof2_ss2_d",
4417         "msiof2_txd_d",
4418         "msiof2_rxd_d",
4419 };
4420
4421 static const char * const msiof3_groups[] = {
4422         "msiof3_clk_a",
4423         "msiof3_sync_a",
4424         "msiof3_ss1_a",
4425         "msiof3_ss2_a",
4426         "msiof3_txd_a",
4427         "msiof3_rxd_a",
4428         "msiof3_clk_b",
4429         "msiof3_sync_b",
4430         "msiof3_ss1_b",
4431         "msiof3_ss2_b",
4432         "msiof3_txd_b",
4433         "msiof3_rxd_b",
4434         "msiof3_clk_c",
4435         "msiof3_sync_c",
4436         "msiof3_txd_c",
4437         "msiof3_rxd_c",
4438         "msiof3_clk_d",
4439         "msiof3_sync_d",
4440         "msiof3_ss1_d",
4441         "msiof3_txd_d",
4442         "msiof3_rxd_d",
4443 };
4444
4445 static const char * const pwm0_groups[] = {
4446         "pwm0",
4447 };
4448
4449 static const char * const pwm1_groups[] = {
4450         "pwm1_a",
4451         "pwm1_b",
4452 };
4453
4454 static const char * const pwm2_groups[] = {
4455         "pwm2_a",
4456         "pwm2_b",
4457 };
4458
4459 static const char * const pwm3_groups[] = {
4460         "pwm3_a",
4461         "pwm3_b",
4462 };
4463
4464 static const char * const pwm4_groups[] = {
4465         "pwm4_a",
4466         "pwm4_b",
4467 };
4468
4469 static const char * const pwm5_groups[] = {
4470         "pwm5_a",
4471         "pwm5_b",
4472 };
4473
4474 static const char * const pwm6_groups[] = {
4475         "pwm6_a",
4476         "pwm6_b",
4477 };
4478
4479 static const char * const qspi0_groups[] = {
4480         "qspi0_ctrl",
4481         "qspi0_data2",
4482         "qspi0_data4",
4483 };
4484
4485 static const char * const qspi1_groups[] = {
4486         "qspi1_ctrl",
4487         "qspi1_data2",
4488         "qspi1_data4",
4489 };
4490
4491 static const char * const sata0_groups[] = {
4492         "sata0_devslp_a",
4493         "sata0_devslp_b",
4494 };
4495
4496 static const char * const scif0_groups[] = {
4497         "scif0_data",
4498         "scif0_clk",
4499         "scif0_ctrl",
4500 };
4501
4502 static const char * const scif1_groups[] = {
4503         "scif1_data_a",
4504         "scif1_clk",
4505         "scif1_ctrl",
4506         "scif1_data_b",
4507 };
4508
4509 static const char * const scif2_groups[] = {
4510         "scif2_data_a",
4511         "scif2_clk",
4512         "scif2_data_b",
4513 };
4514
4515 static const char * const scif3_groups[] = {
4516         "scif3_data_a",
4517         "scif3_clk",
4518         "scif3_ctrl",
4519         "scif3_data_b",
4520 };
4521
4522 static const char * const scif4_groups[] = {
4523         "scif4_data_a",
4524         "scif4_clk_a",
4525         "scif4_ctrl_a",
4526         "scif4_data_b",
4527         "scif4_clk_b",
4528         "scif4_ctrl_b",
4529         "scif4_data_c",
4530         "scif4_clk_c",
4531         "scif4_ctrl_c",
4532 };
4533
4534 static const char * const scif5_groups[] = {
4535         "scif5_data",
4536         "scif5_clk",
4537 };
4538
4539 static const char * const scif_clk_groups[] = {
4540         "scif_clk_a",
4541         "scif_clk_b",
4542 };
4543
4544 static const char * const sdhi0_groups[] = {
4545         "sdhi0_data1",
4546         "sdhi0_data4",
4547         "sdhi0_ctrl",
4548         "sdhi0_cd",
4549         "sdhi0_wp",
4550 };
4551
4552 static const char * const sdhi1_groups[] = {
4553         "sdhi1_data1",
4554         "sdhi1_data4",
4555         "sdhi1_ctrl",
4556         "sdhi1_cd",
4557         "sdhi1_wp",
4558 };
4559
4560 static const char * const sdhi2_groups[] = {
4561         "sdhi2_data1",
4562         "sdhi2_data4",
4563         "sdhi2_data8",
4564         "sdhi2_ctrl",
4565         "sdhi2_cd_a",
4566         "sdhi2_wp_a",
4567         "sdhi2_cd_b",
4568         "sdhi2_wp_b",
4569         "sdhi2_ds",
4570 };
4571
4572 static const char * const sdhi3_groups[] = {
4573         "sdhi3_data1",
4574         "sdhi3_data4",
4575         "sdhi3_data8",
4576         "sdhi3_ctrl",
4577         "sdhi3_cd",
4578         "sdhi3_wp",
4579         "sdhi3_ds",
4580 };
4581
4582 static const char * const ssi_groups[] = {
4583         "ssi0_data",
4584         "ssi01239_ctrl",
4585         "ssi1_data_a",
4586         "ssi1_data_b",
4587         "ssi1_ctrl_a",
4588         "ssi1_ctrl_b",
4589         "ssi2_data_a",
4590         "ssi2_data_b",
4591         "ssi2_ctrl_a",
4592         "ssi2_ctrl_b",
4593         "ssi3_data",
4594         "ssi349_ctrl",
4595         "ssi4_data",
4596         "ssi4_ctrl",
4597         "ssi5_data",
4598         "ssi5_ctrl",
4599         "ssi6_data",
4600         "ssi6_ctrl",
4601         "ssi7_data",
4602         "ssi78_ctrl",
4603         "ssi8_data",
4604         "ssi9_data_a",
4605         "ssi9_data_b",
4606         "ssi9_ctrl_a",
4607         "ssi9_ctrl_b",
4608 };
4609
4610 static const char * const tmu_groups[] = {
4611         "tmu_tclk1_a",
4612         "tmu_tclk1_b",
4613         "tmu_tclk2_a",
4614         "tmu_tclk2_b",
4615 };
4616
4617 static const char * const usb0_groups[] = {
4618         "usb0",
4619 };
4620
4621 static const char * const usb1_groups[] = {
4622         "usb1",
4623 };
4624
4625 static const char * const usb2_groups[] = {
4626         "usb2",
4627 };
4628
4629 static const char * const usb30_groups[] = {
4630         "usb30",
4631 };
4632
4633 static const char * const usb31_groups[] = {
4634         "usb31",
4635 };
4636
4637 static const struct sh_pfc_function pinmux_functions[] = {
4638         SH_PFC_FUNCTION(audio_clk),
4639         SH_PFC_FUNCTION(avb),
4640         SH_PFC_FUNCTION(can0),
4641         SH_PFC_FUNCTION(can1),
4642         SH_PFC_FUNCTION(can_clk),
4643         SH_PFC_FUNCTION(canfd0),
4644         SH_PFC_FUNCTION(canfd1),
4645         SH_PFC_FUNCTION(drif0),
4646         SH_PFC_FUNCTION(drif1),
4647         SH_PFC_FUNCTION(drif2),
4648         SH_PFC_FUNCTION(drif3),
4649         SH_PFC_FUNCTION(du),
4650         SH_PFC_FUNCTION(hdmi0),
4651         SH_PFC_FUNCTION(hdmi1),
4652         SH_PFC_FUNCTION(hscif0),
4653         SH_PFC_FUNCTION(hscif1),
4654         SH_PFC_FUNCTION(hscif2),
4655         SH_PFC_FUNCTION(hscif3),
4656         SH_PFC_FUNCTION(hscif4),
4657         SH_PFC_FUNCTION(i2c1),
4658         SH_PFC_FUNCTION(i2c2),
4659         SH_PFC_FUNCTION(i2c6),
4660         SH_PFC_FUNCTION(intc_ex),
4661         SH_PFC_FUNCTION(msiof0),
4662         SH_PFC_FUNCTION(msiof1),
4663         SH_PFC_FUNCTION(msiof2),
4664         SH_PFC_FUNCTION(msiof3),
4665         SH_PFC_FUNCTION(pwm0),
4666         SH_PFC_FUNCTION(pwm1),
4667         SH_PFC_FUNCTION(pwm2),
4668         SH_PFC_FUNCTION(pwm3),
4669         SH_PFC_FUNCTION(pwm4),
4670         SH_PFC_FUNCTION(pwm5),
4671         SH_PFC_FUNCTION(pwm6),
4672         SH_PFC_FUNCTION(qspi0),
4673         SH_PFC_FUNCTION(qspi1),
4674         SH_PFC_FUNCTION(sata0),
4675         SH_PFC_FUNCTION(scif0),
4676         SH_PFC_FUNCTION(scif1),
4677         SH_PFC_FUNCTION(scif2),
4678         SH_PFC_FUNCTION(scif3),
4679         SH_PFC_FUNCTION(scif4),
4680         SH_PFC_FUNCTION(scif5),
4681         SH_PFC_FUNCTION(scif_clk),
4682         SH_PFC_FUNCTION(sdhi0),
4683         SH_PFC_FUNCTION(sdhi1),
4684         SH_PFC_FUNCTION(sdhi2),
4685         SH_PFC_FUNCTION(sdhi3),
4686         SH_PFC_FUNCTION(ssi),
4687         SH_PFC_FUNCTION(tmu),
4688         SH_PFC_FUNCTION(usb0),
4689         SH_PFC_FUNCTION(usb1),
4690         SH_PFC_FUNCTION(usb2),
4691         SH_PFC_FUNCTION(usb30),
4692         SH_PFC_FUNCTION(usb31),
4693 };
4694
4695 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4696 #define F_(x, y)        FN_##y
4697 #define FM(x)           FN_##x
4698         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4699                 0, 0,
4700                 0, 0,
4701                 0, 0,
4702                 0, 0,
4703                 0, 0,
4704                 0, 0,
4705                 0, 0,
4706                 0, 0,
4707                 0, 0,
4708                 0, 0,
4709                 0, 0,
4710                 0, 0,
4711                 0, 0,
4712                 0, 0,
4713                 0, 0,
4714                 0, 0,
4715                 GP_0_15_FN,     GPSR0_15,
4716                 GP_0_14_FN,     GPSR0_14,
4717                 GP_0_13_FN,     GPSR0_13,
4718                 GP_0_12_FN,     GPSR0_12,
4719                 GP_0_11_FN,     GPSR0_11,
4720                 GP_0_10_FN,     GPSR0_10,
4721                 GP_0_9_FN,      GPSR0_9,
4722                 GP_0_8_FN,      GPSR0_8,
4723                 GP_0_7_FN,      GPSR0_7,
4724                 GP_0_6_FN,      GPSR0_6,
4725                 GP_0_5_FN,      GPSR0_5,
4726                 GP_0_4_FN,      GPSR0_4,
4727                 GP_0_3_FN,      GPSR0_3,
4728                 GP_0_2_FN,      GPSR0_2,
4729                 GP_0_1_FN,      GPSR0_1,
4730                 GP_0_0_FN,      GPSR0_0, }
4731         },
4732         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4733                 0, 0,
4734                 0, 0,
4735                 0, 0,
4736                 0, 0,
4737                 GP_1_27_FN,     GPSR1_27,
4738                 GP_1_26_FN,     GPSR1_26,
4739                 GP_1_25_FN,     GPSR1_25,
4740                 GP_1_24_FN,     GPSR1_24,
4741                 GP_1_23_FN,     GPSR1_23,
4742                 GP_1_22_FN,     GPSR1_22,
4743                 GP_1_21_FN,     GPSR1_21,
4744                 GP_1_20_FN,     GPSR1_20,
4745                 GP_1_19_FN,     GPSR1_19,
4746                 GP_1_18_FN,     GPSR1_18,
4747                 GP_1_17_FN,     GPSR1_17,
4748                 GP_1_16_FN,     GPSR1_16,
4749                 GP_1_15_FN,     GPSR1_15,
4750                 GP_1_14_FN,     GPSR1_14,
4751                 GP_1_13_FN,     GPSR1_13,
4752                 GP_1_12_FN,     GPSR1_12,
4753                 GP_1_11_FN,     GPSR1_11,
4754                 GP_1_10_FN,     GPSR1_10,
4755                 GP_1_9_FN,      GPSR1_9,
4756                 GP_1_8_FN,      GPSR1_8,
4757                 GP_1_7_FN,      GPSR1_7,
4758                 GP_1_6_FN,      GPSR1_6,
4759                 GP_1_5_FN,      GPSR1_5,
4760                 GP_1_4_FN,      GPSR1_4,
4761                 GP_1_3_FN,      GPSR1_3,
4762                 GP_1_2_FN,      GPSR1_2,
4763                 GP_1_1_FN,      GPSR1_1,
4764                 GP_1_0_FN,      GPSR1_0, }
4765         },
4766         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4767                 0, 0,
4768                 0, 0,
4769                 0, 0,
4770                 0, 0,
4771                 0, 0,
4772                 0, 0,
4773                 0, 0,
4774                 0, 0,
4775                 0, 0,
4776                 0, 0,
4777                 0, 0,
4778                 0, 0,
4779                 0, 0,
4780                 0, 0,
4781                 0, 0,
4782                 0, 0,
4783                 0, 0,
4784                 GP_2_14_FN,     GPSR2_14,
4785                 GP_2_13_FN,     GPSR2_13,
4786                 GP_2_12_FN,     GPSR2_12,
4787                 GP_2_11_FN,     GPSR2_11,
4788                 GP_2_10_FN,     GPSR2_10,
4789                 GP_2_9_FN,      GPSR2_9,
4790                 GP_2_8_FN,      GPSR2_8,
4791                 GP_2_7_FN,      GPSR2_7,
4792                 GP_2_6_FN,      GPSR2_6,
4793                 GP_2_5_FN,      GPSR2_5,
4794                 GP_2_4_FN,      GPSR2_4,
4795                 GP_2_3_FN,      GPSR2_3,
4796                 GP_2_2_FN,      GPSR2_2,
4797                 GP_2_1_FN,      GPSR2_1,
4798                 GP_2_0_FN,      GPSR2_0, }
4799         },
4800         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4801                 0, 0,
4802                 0, 0,
4803                 0, 0,
4804                 0, 0,
4805                 0, 0,
4806                 0, 0,
4807                 0, 0,
4808                 0, 0,
4809                 0, 0,
4810                 0, 0,
4811                 0, 0,
4812                 0, 0,
4813                 0, 0,
4814                 0, 0,
4815                 0, 0,
4816                 0, 0,
4817                 GP_3_15_FN,     GPSR3_15,
4818                 GP_3_14_FN,     GPSR3_14,
4819                 GP_3_13_FN,     GPSR3_13,
4820                 GP_3_12_FN,     GPSR3_12,
4821                 GP_3_11_FN,     GPSR3_11,
4822                 GP_3_10_FN,     GPSR3_10,
4823                 GP_3_9_FN,      GPSR3_9,
4824                 GP_3_8_FN,      GPSR3_8,
4825                 GP_3_7_FN,      GPSR3_7,
4826                 GP_3_6_FN,      GPSR3_6,
4827                 GP_3_5_FN,      GPSR3_5,
4828                 GP_3_4_FN,      GPSR3_4,
4829                 GP_3_3_FN,      GPSR3_3,
4830                 GP_3_2_FN,      GPSR3_2,
4831                 GP_3_1_FN,      GPSR3_1,
4832                 GP_3_0_FN,      GPSR3_0, }
4833         },
4834         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4835                 0, 0,
4836                 0, 0,
4837                 0, 0,
4838                 0, 0,
4839                 0, 0,
4840                 0, 0,
4841                 0, 0,
4842                 0, 0,
4843                 0, 0,
4844                 0, 0,
4845                 0, 0,
4846                 0, 0,
4847                 0, 0,
4848                 0, 0,
4849                 GP_4_17_FN,     GPSR4_17,
4850                 GP_4_16_FN,     GPSR4_16,
4851                 GP_4_15_FN,     GPSR4_15,
4852                 GP_4_14_FN,     GPSR4_14,
4853                 GP_4_13_FN,     GPSR4_13,
4854                 GP_4_12_FN,     GPSR4_12,
4855                 GP_4_11_FN,     GPSR4_11,
4856                 GP_4_10_FN,     GPSR4_10,
4857                 GP_4_9_FN,      GPSR4_9,
4858                 GP_4_8_FN,      GPSR4_8,
4859                 GP_4_7_FN,      GPSR4_7,
4860                 GP_4_6_FN,      GPSR4_6,
4861                 GP_4_5_FN,      GPSR4_5,
4862                 GP_4_4_FN,      GPSR4_4,
4863                 GP_4_3_FN,      GPSR4_3,
4864                 GP_4_2_FN,      GPSR4_2,
4865                 GP_4_1_FN,      GPSR4_1,
4866                 GP_4_0_FN,      GPSR4_0, }
4867         },
4868         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4869                 0, 0,
4870                 0, 0,
4871                 0, 0,
4872                 0, 0,
4873                 0, 0,
4874                 0, 0,
4875                 GP_5_25_FN,     GPSR5_25,
4876                 GP_5_24_FN,     GPSR5_24,
4877                 GP_5_23_FN,     GPSR5_23,
4878                 GP_5_22_FN,     GPSR5_22,
4879                 GP_5_21_FN,     GPSR5_21,
4880                 GP_5_20_FN,     GPSR5_20,
4881                 GP_5_19_FN,     GPSR5_19,
4882                 GP_5_18_FN,     GPSR5_18,
4883                 GP_5_17_FN,     GPSR5_17,
4884                 GP_5_16_FN,     GPSR5_16,
4885                 GP_5_15_FN,     GPSR5_15,
4886                 GP_5_14_FN,     GPSR5_14,
4887                 GP_5_13_FN,     GPSR5_13,
4888                 GP_5_12_FN,     GPSR5_12,
4889                 GP_5_11_FN,     GPSR5_11,
4890                 GP_5_10_FN,     GPSR5_10,
4891                 GP_5_9_FN,      GPSR5_9,
4892                 GP_5_8_FN,      GPSR5_8,
4893                 GP_5_7_FN,      GPSR5_7,
4894                 GP_5_6_FN,      GPSR5_6,
4895                 GP_5_5_FN,      GPSR5_5,
4896                 GP_5_4_FN,      GPSR5_4,
4897                 GP_5_3_FN,      GPSR5_3,
4898                 GP_5_2_FN,      GPSR5_2,
4899                 GP_5_1_FN,      GPSR5_1,
4900                 GP_5_0_FN,      GPSR5_0, }
4901         },
4902         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4903                 GP_6_31_FN,     GPSR6_31,
4904                 GP_6_30_FN,     GPSR6_30,
4905                 GP_6_29_FN,     GPSR6_29,
4906                 GP_6_28_FN,     GPSR6_28,
4907                 GP_6_27_FN,     GPSR6_27,
4908                 GP_6_26_FN,     GPSR6_26,
4909                 GP_6_25_FN,     GPSR6_25,
4910                 GP_6_24_FN,     GPSR6_24,
4911                 GP_6_23_FN,     GPSR6_23,
4912                 GP_6_22_FN,     GPSR6_22,
4913                 GP_6_21_FN,     GPSR6_21,
4914                 GP_6_20_FN,     GPSR6_20,
4915                 GP_6_19_FN,     GPSR6_19,
4916                 GP_6_18_FN,     GPSR6_18,
4917                 GP_6_17_FN,     GPSR6_17,
4918                 GP_6_16_FN,     GPSR6_16,
4919                 GP_6_15_FN,     GPSR6_15,
4920                 GP_6_14_FN,     GPSR6_14,
4921                 GP_6_13_FN,     GPSR6_13,
4922                 GP_6_12_FN,     GPSR6_12,
4923                 GP_6_11_FN,     GPSR6_11,
4924                 GP_6_10_FN,     GPSR6_10,
4925                 GP_6_9_FN,      GPSR6_9,
4926                 GP_6_8_FN,      GPSR6_8,
4927                 GP_6_7_FN,      GPSR6_7,
4928                 GP_6_6_FN,      GPSR6_6,
4929                 GP_6_5_FN,      GPSR6_5,
4930                 GP_6_4_FN,      GPSR6_4,
4931                 GP_6_3_FN,      GPSR6_3,
4932                 GP_6_2_FN,      GPSR6_2,
4933                 GP_6_1_FN,      GPSR6_1,
4934                 GP_6_0_FN,      GPSR6_0, }
4935         },
4936         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4937                 0, 0,
4938                 0, 0,
4939                 0, 0,
4940                 0, 0,
4941                 0, 0,
4942                 0, 0,
4943                 0, 0,
4944                 0, 0,
4945                 0, 0,
4946                 0, 0,
4947                 0, 0,
4948                 0, 0,
4949                 0, 0,
4950                 0, 0,
4951                 0, 0,
4952                 0, 0,
4953                 0, 0,
4954                 0, 0,
4955                 0, 0,
4956                 0, 0,
4957                 0, 0,
4958                 0, 0,
4959                 0, 0,
4960                 0, 0,
4961                 0, 0,
4962                 0, 0,
4963                 0, 0,
4964                 0, 0,
4965                 GP_7_3_FN, GPSR7_3,
4966                 GP_7_2_FN, GPSR7_2,
4967                 GP_7_1_FN, GPSR7_1,
4968                 GP_7_0_FN, GPSR7_0, }
4969         },
4970 #undef F_
4971 #undef FM
4972
4973 #define F_(x, y)        x,
4974 #define FM(x)           FN_##x,
4975         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4976                 IP0_31_28
4977                 IP0_27_24
4978                 IP0_23_20
4979                 IP0_19_16
4980                 IP0_15_12
4981                 IP0_11_8
4982                 IP0_7_4
4983                 IP0_3_0 }
4984         },
4985         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4986                 IP1_31_28
4987                 IP1_27_24
4988                 IP1_23_20
4989                 IP1_19_16
4990                 IP1_15_12
4991                 IP1_11_8
4992                 IP1_7_4
4993                 IP1_3_0 }
4994         },
4995         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4996                 IP2_31_28
4997                 IP2_27_24
4998                 IP2_23_20
4999                 IP2_19_16
5000                 IP2_15_12
5001                 IP2_11_8
5002                 IP2_7_4
5003                 IP2_3_0 }
5004         },
5005         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5006                 IP3_31_28
5007                 IP3_27_24
5008                 IP3_23_20
5009                 IP3_19_16
5010                 IP3_15_12
5011                 IP3_11_8
5012                 IP3_7_4
5013                 IP3_3_0 }
5014         },
5015         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5016                 IP4_31_28
5017                 IP4_27_24
5018                 IP4_23_20
5019                 IP4_19_16
5020                 IP4_15_12
5021                 IP4_11_8
5022                 IP4_7_4
5023                 IP4_3_0 }
5024         },
5025         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5026                 IP5_31_28
5027                 IP5_27_24
5028                 IP5_23_20
5029                 IP5_19_16
5030                 IP5_15_12
5031                 IP5_11_8
5032                 IP5_7_4
5033                 IP5_3_0 }
5034         },
5035         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5036                 IP6_31_28
5037                 IP6_27_24
5038                 IP6_23_20
5039                 IP6_19_16
5040                 IP6_15_12
5041                 IP6_11_8
5042                 IP6_7_4
5043                 IP6_3_0 }
5044         },
5045         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5046                 IP7_31_28
5047                 IP7_27_24
5048                 IP7_23_20
5049                 IP7_19_16
5050                 IP7_15_12
5051                 IP7_11_8
5052                 IP7_7_4
5053                 IP7_3_0 }
5054         },
5055         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5056                 IP8_31_28
5057                 IP8_27_24
5058                 IP8_23_20
5059                 IP8_19_16
5060                 IP8_15_12
5061                 IP8_11_8
5062                 IP8_7_4
5063                 IP8_3_0 }
5064         },
5065         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5066                 IP9_31_28
5067                 IP9_27_24
5068                 IP9_23_20
5069                 IP9_19_16
5070                 IP9_15_12
5071                 IP9_11_8
5072                 IP9_7_4
5073                 IP9_3_0 }
5074         },
5075         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5076                 IP10_31_28
5077                 IP10_27_24
5078                 IP10_23_20
5079                 IP10_19_16
5080                 IP10_15_12
5081                 IP10_11_8
5082                 IP10_7_4
5083                 IP10_3_0 }
5084         },
5085         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5086                 IP11_31_28
5087                 IP11_27_24
5088                 IP11_23_20
5089                 IP11_19_16
5090                 IP11_15_12
5091                 IP11_11_8
5092                 IP11_7_4
5093                 IP11_3_0 }
5094         },
5095         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5096                 IP12_31_28
5097                 IP12_27_24
5098                 IP12_23_20
5099                 IP12_19_16
5100                 IP12_15_12
5101                 IP12_11_8
5102                 IP12_7_4
5103                 IP12_3_0 }
5104         },
5105         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5106                 IP13_31_28
5107                 IP13_27_24
5108                 IP13_23_20
5109                 IP13_19_16
5110                 IP13_15_12
5111                 IP13_11_8
5112                 IP13_7_4
5113                 IP13_3_0 }
5114         },
5115         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5116                 IP14_31_28
5117                 IP14_27_24
5118                 IP14_23_20
5119                 IP14_19_16
5120                 IP14_15_12
5121                 IP14_11_8
5122                 IP14_7_4
5123                 IP14_3_0 }
5124         },
5125         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5126                 IP15_31_28
5127                 IP15_27_24
5128                 IP15_23_20
5129                 IP15_19_16
5130                 IP15_15_12
5131                 IP15_11_8
5132                 IP15_7_4
5133                 IP15_3_0 }
5134         },
5135         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5136                 IP16_31_28
5137                 IP16_27_24
5138                 IP16_23_20
5139                 IP16_19_16
5140                 IP16_15_12
5141                 IP16_11_8
5142                 IP16_7_4
5143                 IP16_3_0 }
5144         },
5145         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5146                 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5147                 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5148                 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5149                 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5150                 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5151                 /* IP17_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5152                 IP17_7_4
5153                 IP17_3_0 }
5154         },
5155 #undef F_
5156 #undef FM
5157
5158 #define F_(x, y)        x,
5159 #define FM(x)           FN_##x,
5160         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5161                              1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
5162                              2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
5163                 0, 0, /* RESERVED 31 */
5164                 MOD_SEL0_30_29
5165                 MOD_SEL0_28_27
5166                 MOD_SEL0_26_25_24
5167                 MOD_SEL0_23
5168                 MOD_SEL0_22
5169                 MOD_SEL0_21_20
5170                 MOD_SEL0_19
5171                 MOD_SEL0_18
5172                 MOD_SEL0_17
5173                 MOD_SEL0_16_15
5174                 MOD_SEL0_14
5175                 MOD_SEL0_13
5176                 MOD_SEL0_12
5177                 MOD_SEL0_11
5178                 MOD_SEL0_10
5179                 MOD_SEL0_9
5180                 MOD_SEL0_8
5181                 MOD_SEL0_7_6
5182                 MOD_SEL0_5_4
5183                 MOD_SEL0_3
5184                 MOD_SEL0_2_1
5185                 0, 0, /* RESERVED 0 */ }
5186         },
5187         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5188                              2, 3, 1, 2, 3, 1, 1, 2, 1,
5189                              2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5190                 MOD_SEL1_31_30
5191                 MOD_SEL1_29_28_27
5192                 MOD_SEL1_26
5193                 MOD_SEL1_25_24
5194                 MOD_SEL1_23_22_21
5195                 MOD_SEL1_20
5196                 MOD_SEL1_19
5197                 MOD_SEL1_18_17
5198                 MOD_SEL1_16
5199                 MOD_SEL1_15_14
5200                 MOD_SEL1_13
5201                 MOD_SEL1_12
5202                 MOD_SEL1_11
5203                 MOD_SEL1_10
5204                 MOD_SEL1_9
5205                 0, 0, 0, 0, /* RESERVED 8, 7 */
5206                 MOD_SEL1_6
5207                 MOD_SEL1_5
5208                 MOD_SEL1_4
5209                 MOD_SEL1_3
5210                 MOD_SEL1_2
5211                 MOD_SEL1_1
5212                 MOD_SEL1_0 }
5213         },
5214         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5215                              1, 1, 1, 1, 4, 4, 4,
5216                              4, 4, 4, 1, 2, 1) {
5217                 MOD_SEL2_31
5218                 MOD_SEL2_30
5219                 MOD_SEL2_29
5220                 /* RESERVED 28 */
5221                 0, 0,
5222                 /* RESERVED 27, 26, 25, 24 */
5223                 0, 0, 0, 0, 0, 0, 0, 0,
5224                 0, 0, 0, 0, 0, 0, 0, 0,
5225                 /* RESERVED 23, 22, 21, 20 */
5226                 0, 0, 0, 0, 0, 0, 0, 0,
5227                 0, 0, 0, 0, 0, 0, 0, 0,
5228                 /* RESERVED 19, 18, 17, 16 */
5229                 0, 0, 0, 0, 0, 0, 0, 0,
5230                 0, 0, 0, 0, 0, 0, 0, 0,
5231                 /* RESERVED 15, 14, 13, 12 */
5232                 0, 0, 0, 0, 0, 0, 0, 0,
5233                 0, 0, 0, 0, 0, 0, 0, 0,
5234                 /* RESERVED 11, 10, 9, 8 */
5235                 0, 0, 0, 0, 0, 0, 0, 0,
5236                 0, 0, 0, 0, 0, 0, 0, 0,
5237                 /* RESERVED 7, 6, 5, 4 */
5238                 0, 0, 0, 0, 0, 0, 0, 0,
5239                 0, 0, 0, 0, 0, 0, 0, 0,
5240                 /* RESERVED 3 */
5241                 0, 0,
5242                 /* RESERVED 2, 1 */
5243                 0, 0, 0, 0,
5244                 MOD_SEL2_0 }
5245         },
5246         { },
5247 };
5248
5249 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5250         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5251                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5252                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5253                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5254                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5255                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5256                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5257                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5258                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5259         } },
5260         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5261                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5262                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5263                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5264                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5265                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5266                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5267                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5268                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5269         } },
5270         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5271                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5272                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5273                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5274                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5275                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5276                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5277                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5278                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5279         } },
5280         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5281                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5282                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5283                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5284                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5285                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5286                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5287                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5288                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5289         } },
5290         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5291                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5292                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5293                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5294                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5295                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5296                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5297                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5298                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5299         } },
5300         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5301                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5302                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5303                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5304                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5305                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5306                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5307                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5308                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5309         } },
5310         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5311                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5312                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5313                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5314                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5315                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5316                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5317                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5318                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5319         } },
5320         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5321                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5322                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5323                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5324                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5325                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5326                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5327                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5328                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5329         } },
5330         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5331                 { PIN_NUMBER('F', 1), 28, 3 },  /* CLKOUT */
5332                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5333                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5334                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5335                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5336                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5337                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5338                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5339         } },
5340         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5341                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5342                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5343                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5344                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5345                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5346                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5347                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5348                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5349         } },
5350         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5351                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5352                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5353                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5354                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5355                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5356                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5357                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5358                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5359         } },
5360         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5361                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5362                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5363                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5364                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5365                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* HDMI0_CEC */
5366                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* HDMI1_CEC */
5367                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5368                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5369         } },
5370         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5371                 { PIN_A_NUMBER('R', 7),  28, 2 },       /* DU_DOTCLKIN2 */
5372                 { PIN_A_NUMBER('R', 8),  24, 2 },       /* DU_DOTCLKIN3 */
5373                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST# */
5374                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5375         } },
5376         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5377                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5378                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5379                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5380                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5381                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5382                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5383                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5384                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5385         } },
5386         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5387                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5388                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5389                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5390                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5391                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5392                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5393                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5394                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5395         } },
5396         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5397                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5398                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5399                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5400                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5401                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5402                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5403                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5404                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5405         } },
5406         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5407                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5408                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5409                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5410                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5411                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5412                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5413                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5414                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5415         } },
5416         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5417                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5418                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5419                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5420                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5421                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5422                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5423                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5424                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5425         } },
5426         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5427                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0_TANS */
5428                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5429                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5430                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5431                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1_TANS */
5432                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5433                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5434                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5435         } },
5436         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5437                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5438                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5439                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5440                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5441                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5442                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5443                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5444                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5445         } },
5446         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5447                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5448                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5449                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5450                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5451                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5452                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5453                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5454                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5455         } },
5456         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5457                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5458                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5459                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5460                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5461                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5462                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5463                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5464                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5465         } },
5466         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5467                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5468                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5469                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5470                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5471                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5472                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5473                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5474                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5475         } },
5476         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5477                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5478                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5479                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5480                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5481                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5482                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5483                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5484                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5485         } },
5486         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5487                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5488                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5489                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5490                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5491                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5492                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* USB31_PWEN */
5493                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* USB31_OVC */
5494         } },
5495         { },
5496 };
5497
5498 enum ioctrl_regs {
5499         POCCTRL,
5500 };
5501
5502 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5503         [POCCTRL] = { 0xe6060380, },
5504         { /* sentinel */ },
5505 };
5506
5507 static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5508                                      u32 *pocctrl)
5509 {
5510         int bit = -EINVAL;
5511
5512         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5513
5514         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5515                 bit = pin & 0x1f;
5516
5517         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5518                 bit = (pin & 0x1f) + 12;
5519
5520         return bit;
5521 }
5522
5523 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5524         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5525                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
5526                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
5527                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
5528                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
5529                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
5530                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
5531                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
5532                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
5533                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
5534                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
5535                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
5536                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
5537                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
5538                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
5539                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
5540                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
5541                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
5542                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
5543                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
5544                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
5545                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
5546                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
5547                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
5548                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
5549                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
5550                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
5551                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
5552                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
5553                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
5554                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
5555                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
5556                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
5557         } },
5558         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5559                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
5560                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
5561                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
5562                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
5563                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
5564                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
5565                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
5566                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
5567                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
5568                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
5569                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
5570                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
5571                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
5572                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
5573                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
5574                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
5575                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
5576                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
5577                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
5578                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
5579                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
5580                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
5581                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
5582                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
5583                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
5584                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
5585                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
5586                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
5587                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
5588                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
5589                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
5590                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
5591         } },
5592         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5593                 [ 0] = PIN_NUMBER('F', 1),      /* CLKOUT */
5594                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
5595                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N_A26 */
5596                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
5597                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
5598                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
5599                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
5600                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
5601                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
5602                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
5603                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
5604                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
5605                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
5606                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
5607                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
5608                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
5609                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
5610                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
5611                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
5612                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
5613                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
5614                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
5615                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
5616                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
5617                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
5618                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
5619                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
5620                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
5621                 [28] = RCAR_GP_PIN(7,  2),      /* HDMI0_CEC */
5622                 [29] = RCAR_GP_PIN(7,  3),      /* HDMI1_CEC */
5623                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
5624                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
5625         } },
5626         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5627                 [ 0] = PIN_A_NUMBER('R', 7),    /* DU_DOTCLKIN2 */
5628                 [ 1] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN3 */
5629                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST# */
5630                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
5631                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
5632                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
5633                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
5634                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
5635                 [ 8] = PIN_NONE,
5636                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
5637                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
5638                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
5639                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
5640                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
5641                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
5642                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
5643                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
5644                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
5645                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
5646                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
5647                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
5648                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
5649                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
5650                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
5651                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
5652                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
5653                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
5654                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
5655                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
5656                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
5657                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
5658                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
5659         } },
5660         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5661                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
5662                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
5663                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
5664                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
5665                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
5666                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
5667                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
5668                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
5669                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
5670                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
5671                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
5672                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
5673                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
5674                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
5675                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
5676                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
5677                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N_TANS */
5678                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
5679                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
5680                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
5681                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N_TANS */
5682                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
5683                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
5684                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
5685                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
5686                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
5687                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
5688                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
5689                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
5690                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
5691                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
5692                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
5693         } },
5694         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5695                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
5696                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
5697                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
5698                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
5699                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
5700                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
5701                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
5702                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
5703                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
5704                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
5705                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
5706                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
5707                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
5708                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
5709                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
5710                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
5711                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
5712                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
5713                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
5714                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
5715                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
5716                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
5717                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
5718                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
5719                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
5720                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
5721                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
5722                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
5723                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
5724                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
5725                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
5726                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
5727         } },
5728         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5729                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
5730                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
5731                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
5732                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
5733                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
5734                 [ 5] = RCAR_GP_PIN(6, 30),      /* USB31_PWEN */
5735                 [ 6] = RCAR_GP_PIN(6, 31),      /* USB31_OVC */
5736                 [ 7] = PIN_NONE,
5737                 [ 8] = PIN_NONE,
5738                 [ 9] = PIN_NONE,
5739                 [10] = PIN_NONE,
5740                 [11] = PIN_NONE,
5741                 [12] = PIN_NONE,
5742                 [13] = PIN_NONE,
5743                 [14] = PIN_NONE,
5744                 [15] = PIN_NONE,
5745                 [16] = PIN_NONE,
5746                 [17] = PIN_NONE,
5747                 [18] = PIN_NONE,
5748                 [19] = PIN_NONE,
5749                 [20] = PIN_NONE,
5750                 [21] = PIN_NONE,
5751                 [22] = PIN_NONE,
5752                 [23] = PIN_NONE,
5753                 [24] = PIN_NONE,
5754                 [25] = PIN_NONE,
5755                 [26] = PIN_NONE,
5756                 [27] = PIN_NONE,
5757                 [28] = PIN_NONE,
5758                 [29] = PIN_NONE,
5759                 [30] = PIN_NONE,
5760                 [31] = PIN_NONE,
5761         } },
5762         { /* sentinel */ },
5763 };
5764
5765 static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
5766                                                unsigned int pin)
5767 {
5768         const struct pinmux_bias_reg *reg;
5769         unsigned int bit;
5770
5771         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5772         if (!reg)
5773                 return PIN_CONFIG_BIAS_DISABLE;
5774
5775         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5776                 return PIN_CONFIG_BIAS_DISABLE;
5777         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5778                 return PIN_CONFIG_BIAS_PULL_UP;
5779         else
5780                 return PIN_CONFIG_BIAS_PULL_DOWN;
5781 }
5782
5783 static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5784                                        unsigned int bias)
5785 {
5786         const struct pinmux_bias_reg *reg;
5787         u32 enable, updown;
5788         unsigned int bit;
5789
5790         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5791         if (!reg)
5792                 return;
5793
5794         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5795         if (bias != PIN_CONFIG_BIAS_DISABLE)
5796                 enable |= BIT(bit);
5797
5798         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5799         if (bias == PIN_CONFIG_BIAS_PULL_UP)
5800                 updown |= BIT(bit);
5801
5802         sh_pfc_write(pfc, reg->pud, updown);
5803         sh_pfc_write(pfc, reg->puen, enable);
5804 }
5805
5806 static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = {
5807         .pin_to_pocctrl = r8a7795es1_pin_to_pocctrl,
5808         .get_bias = r8a7795es1_pinmux_get_bias,
5809         .set_bias = r8a7795es1_pinmux_set_bias,
5810 };
5811
5812 const struct sh_pfc_soc_info r8a7795es1_pinmux_info = {
5813         .name = "r8a77950_pfc",
5814         .ops = &r8a7795es1_pinmux_ops,
5815         .unlock_reg = 0xe6060000, /* PMMR */
5816
5817         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5818
5819         .pins = pinmux_pins,
5820         .nr_pins = ARRAY_SIZE(pinmux_pins),
5821         .groups = pinmux_groups,
5822         .nr_groups = ARRAY_SIZE(pinmux_groups),
5823         .functions = pinmux_functions,
5824         .nr_functions = ARRAY_SIZE(pinmux_functions),
5825
5826         .cfg_regs = pinmux_config_regs,
5827         .drive_regs = pinmux_drive_regs,
5828         .bias_regs = pinmux_bias_regs,
5829         .ioctrl_regs = pinmux_ioctrl_regs,
5830
5831         .pinmux_data = pinmux_data,
5832         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5833 };