drivers/pinctrl/sh-pfc/pfc-sh73a0.c

   1 /*
   2  * sh73a0 processor support - PFC hardware block
   3  *
   4  * Copyright (C) 2010 Renesas Solutions Corp.
   5  * Copyright (C) 2010 NISHIMOTO Hiroki
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of the
  10  * License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25 #include <linux/regulator/driver.h>
  26 #include <linux/regulator/machine.h>
  27 #include <linux/slab.h>
  28
  29 #include "core.h"
  30 #include "sh_pfc.h"
  31
  32 #define CPU_ALL_PORT(fn, pfx, sfx)                                      \
  33         PORT_10(0,  fn, pfx, sfx), PORT_90(0, fn, pfx, sfx),            \
  34         PORT_10(100, fn, pfx##10, sfx),                                 \
  35         PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
  36         PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
  37         PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
  38         PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \
  39         PORT_1(118, fn, pfx##118, sfx),                                 \
  40         PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
  41         PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \
  42         PORT_10(150, fn, pfx##15, sfx),                                 \
  43         PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \
  44         PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \
  45         PORT_1(164, fn, pfx##164, sfx),                                 \
  46         PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
  47         PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
  48         PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
  49         PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
  50         PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \
  51         PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \
  52         PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \
  53         PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \
  54         PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
  55         PORT_1(282, fn, pfx##282, sfx),                                 \
  56         PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
  57         PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
  58
  59 enum {
  60         PINMUX_RESERVED = 0,
  61
  62         PINMUX_DATA_BEGIN,
  63         PORT_ALL(DATA),                 /* PORT0_DATA -> PORT309_DATA */
  64         PINMUX_DATA_END,
  65
  66         PINMUX_INPUT_BEGIN,
  67         PORT_ALL(IN),                   /* PORT0_IN -> PORT309_IN */
  68         PINMUX_INPUT_END,
  69
  70         PINMUX_OUTPUT_BEGIN,
  71         PORT_ALL(OUT),                  /* PORT0_OUT -> PORT309_OUT */
  72         PINMUX_OUTPUT_END,
  73
  74         PINMUX_FUNCTION_BEGIN,
  75         PORT_ALL(FN_IN),                /* PORT0_FN_IN -> PORT309_FN_IN */
  76         PORT_ALL(FN_OUT),               /* PORT0_FN_OUT -> PORT309_FN_OUT */
  77         PORT_ALL(FN0),                  /* PORT0_FN0 -> PORT309_FN0 */
  78         PORT_ALL(FN1),                  /* PORT0_FN1 -> PORT309_FN1 */
  79         PORT_ALL(FN2),                  /* PORT0_FN2 -> PORT309_FN2 */
  80         PORT_ALL(FN3),                  /* PORT0_FN3 -> PORT309_FN3 */
  81         PORT_ALL(FN4),                  /* PORT0_FN4 -> PORT309_FN4 */
  82         PORT_ALL(FN5),                  /* PORT0_FN5 -> PORT309_FN5 */
  83         PORT_ALL(FN6),                  /* PORT0_FN6 -> PORT309_FN6 */
  84         PORT_ALL(FN7),                  /* PORT0_FN7 -> PORT309_FN7 */
  85
  86         MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
  87         MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
  88         MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
  89         MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
  90         MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
  91         MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
  92         MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
  93         MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
  94         MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
  95         MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
  96         MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
  97         MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
  98         MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
  99         MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
 100         MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
 101         MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
 102         MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
 103         MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
 104         MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
 105         MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
 106         MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
 107         MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
 108         MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
 109         MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
 110         MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
 111         MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
 112         MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
 113         MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
 114         MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
 115         MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
 116         MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
 117         MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
 118         MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
 119         MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
 120         MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
 121         MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
 122         MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
 123         MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
 124         MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
 125         MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
 126         MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
 127         MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
 128         PINMUX_FUNCTION_END,
 129
 130         PINMUX_MARK_BEGIN,
 131         /* Hardware manual Table 25-1 (Function 0-7) */
 132         VBUS_0_MARK,
 133         GPI0_MARK,
 134         GPI1_MARK,
 135         GPI2_MARK,
 136         GPI3_MARK,
 137         GPI4_MARK,
 138         GPI5_MARK,
 139         GPI6_MARK,
 140         GPI7_MARK,
 141         SCIFA7_RXD_MARK,
 142         SCIFA7_CTS__MARK,
 143         GPO7_MARK, MFG0_OUT2_MARK,
 144         GPO6_MARK, MFG1_OUT2_MARK,
 145         GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
 146         SCIFA0_TXD_MARK,
 147         SCIFA7_TXD_MARK,
 148         SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
 149         GPO0_MARK,
 150         GPO1_MARK,
 151         GPO2_MARK, STATUS0_MARK,
 152         GPO3_MARK, STATUS1_MARK,
 153         GPO4_MARK, STATUS2_MARK,
 154         VINT_MARK,
 155         TCKON_MARK,
 156         XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
 157         MFG0_OUT1_MARK, PORT27_IROUT_MARK,
 158         XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
 159         PORT28_TPU1TO1_MARK,
 160         SIM_RST_MARK, PORT29_TPU1TO1_MARK,
 161         SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
 162         SIM_D_MARK, PORT31_IROUT_MARK,
 163         SCIFA4_TXD_MARK,
 164         SCIFA4_RXD_MARK, XWUP_MARK,
 165         SCIFA4_RTS__MARK,
 166         SCIFA4_CTS__MARK,
 167         FSIBOBT_MARK, FSIBIBT_MARK,
 168         FSIBOLR_MARK, FSIBILR_MARK,
 169         FSIBOSLD_MARK,
 170         FSIBISLD_MARK,
 171         VACK_MARK,
 172         XTAL1L_MARK,
 173         SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
 174         SCIFA0_RXD_MARK,
 175         SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
 176         FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
 177         FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
 178         FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
 179         FSICISLD_MARK, FSIDISLD_MARK,
 180         FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
 181         FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
 182
 183         FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
 184         FSIAOSLD_MARK, BBIF2_TXD2_MARK,
 185         FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
 186         PORT53_FSICSPDIF_MARK,
 187         FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
 188         FSICCK_MARK, FSICOMC_MARK,
 189         FSIAISLD_MARK, TPU0TO0_MARK,
 190         A0_MARK, BS__MARK,
 191         A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
 192         A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
 193         A14_MARK, KEYOUT5_MARK,
 194         A15_MARK, KEYOUT4_MARK,
 195         A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
 196         A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
 197         A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
 198         A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
 199         A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
 200         A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
 201         A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
 202         A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
 203         A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
 204         A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
 205         A26_MARK, KEYIN6_MARK,
 206         KEYIN7_MARK,
 207         D0_NAF0_MARK,
 208         D1_NAF1_MARK,
 209         D2_NAF2_MARK,
 210         D3_NAF3_MARK,
 211         D4_NAF4_MARK,
 212         D5_NAF5_MARK,
 213         D6_NAF6_MARK,
 214         D7_NAF7_MARK,
 215         D8_NAF8_MARK,
 216         D9_NAF9_MARK,
 217         D10_NAF10_MARK,
 218         D11_NAF11_MARK,
 219         D12_NAF12_MARK,
 220         D13_NAF13_MARK,
 221         D14_NAF14_MARK,
 222         D15_NAF15_MARK,
 223         CS4__MARK,
 224         CS5A__MARK, PORT91_RDWR_MARK,
 225         CS5B__MARK, FCE1__MARK,
 226         CS6B__MARK, DACK0_MARK,
 227         FCE0__MARK, CS6A__MARK,
 228         WAIT__MARK, DREQ0_MARK,
 229         RD__FSC_MARK,
 230         WE0__FWE_MARK, RDWR_FWE_MARK,
 231         WE1__MARK,
 232         FRB_MARK,
 233         CKO_MARK,
 234         NBRSTOUT__MARK,
 235         NBRST__MARK,
 236         BBIF2_TXD_MARK,
 237         BBIF2_RXD_MARK,
 238         BBIF2_SYNC_MARK,
 239         BBIF2_SCK_MARK,
 240         SCIFA3_CTS__MARK, MFG3_IN2_MARK,
 241         SCIFA3_RXD_MARK, MFG3_IN1_MARK,
 242         BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
 243         SCIFA3_TXD_MARK,
 244         HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
 245         HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
 246         HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
 247         HSI_TX_READY_MARK, BBIF1_TXD_MARK,
 248         HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
 249         PORT115_I2C_SCL3_MARK,
 250         HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
 251         PORT116_I2C_SDA3_MARK,
 252         HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
 253         HSI_TX_FLAG_MARK,
 254         VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
 255
 256         VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
 257         VIO2_HD_MARK, LCD2D1_MARK,
 258         VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
 259         VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
 260         PORT131_KEYOUT11_MARK, LCD2D11_MARK,
 261         VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
 262         PORT132_KEYOUT10_MARK, LCD2D12_MARK,
 263         VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
 264         VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
 265         VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
 266         VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
 267         VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
 268         VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
 269         VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
 270         VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
 271         VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
 272         VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
 273         VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
 274         VIO2_D5_MARK, LCD2D3_MARK,
 275         VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
 276         VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
 277         PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
 278         VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
 279         LCD2D18_MARK,
 280         VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
 281         VIO_CKO_MARK,
 282         A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
 283         MFG0_IN2_MARK,
 284         TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
 285         TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
 286         TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
 287         SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
 288         SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
 289         SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
 290         SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
 291         DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
 292         PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
 293         PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
 294         PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
 295         PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
 296         PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
 297         LCDD0_MARK,
 298         LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
 299         LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
 300         LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
 301         LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
 302         LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
 303         LCDD6_MARK,
 304         LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
 305         LCDD8_MARK, D16_MARK,
 306         LCDD9_MARK, D17_MARK,
 307         LCDD10_MARK, D18_MARK,
 308         LCDD11_MARK, D19_MARK,
 309         LCDD12_MARK, D20_MARK,
 310         LCDD13_MARK, D21_MARK,
 311         LCDD14_MARK, D22_MARK,
 312         LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
 313         LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
 314         LCDD17_MARK, D25_MARK,
 315         LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
 316         LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
 317         LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
 318         LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
 319         LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
 320         LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
 321         LCDDCK_MARK, LCDWR__MARK,
 322         LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
 323         VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
 324         LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
 325         PORT218_VIO_CKOR_MARK,
 326         LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
 327         MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
 328         LCDVSYN_MARK, LCDVSYN2_MARK,
 329         LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
 330         MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
 331         LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
 332         VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
 333
 334         SCIFA1_TXD_MARK, OVCN2_MARK,
 335         EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
 336         SCIFA1_RTS__MARK, IDIN_MARK,
 337         SCIFA1_RXD_MARK,
 338         SCIFA1_CTS__MARK, MFG1_IN1_MARK,
 339         MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
 340         MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
 341         MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
 342         MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
 343         MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
 344         MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
 345         MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
 346         MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
 347         MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
 348         MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
 349         SCIFA6_TXD_MARK,
 350         PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
 351         PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
 352         PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
 353         PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
 354         MSIOF2R_RXD_MARK,
 355         PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
 356         MSIOF2R_TXD_MARK,
 357         PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
 358         TPU1TO0_MARK,
 359         PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
 360         TPU3TO1_MARK,
 361         PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
 362         TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
 363         PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
 364         MSIOF2R_TSYNC_MARK,
 365         SDHICLK0_MARK,
 366         SDHICD0_MARK,
 367         SDHID0_0_MARK,
 368         SDHID0_1_MARK,
 369         SDHID0_2_MARK,
 370         SDHID0_3_MARK,
 371         SDHICMD0_MARK,
 372         SDHIWP0_MARK,
 373         SDHICLK1_MARK,
 374         SDHID1_0_MARK, TS_SPSYNC2_MARK,
 375         SDHID1_1_MARK, TS_SDAT2_MARK,
 376         SDHID1_2_MARK, TS_SDEN2_MARK,
 377         SDHID1_3_MARK, TS_SCK2_MARK,
 378         SDHICMD1_MARK,
 379         SDHICLK2_MARK,
 380         SDHID2_0_MARK, TS_SPSYNC4_MARK,
 381         SDHID2_1_MARK, TS_SDAT4_MARK,
 382         SDHID2_2_MARK, TS_SDEN4_MARK,
 383         SDHID2_3_MARK, TS_SCK4_MARK,
 384         SDHICMD2_MARK,
 385         MMCCLK0_MARK,
 386         MMCD0_0_MARK,
 387         MMCD0_1_MARK,
 388         MMCD0_2_MARK,
 389         MMCD0_3_MARK,
 390         MMCD0_4_MARK, TS_SPSYNC5_MARK,
 391         MMCD0_5_MARK, TS_SDAT5_MARK,
 392         MMCD0_6_MARK, TS_SDEN5_MARK,
 393         MMCD0_7_MARK, TS_SCK5_MARK,
 394         MMCCMD0_MARK,
 395         RESETOUTS__MARK, EXTAL2OUT_MARK,
 396         MCP_WAIT__MCP_FRB_MARK,
 397         MCP_CKO_MARK, MMCCLK1_MARK,
 398         MCP_D15_MCP_NAF15_MARK,
 399         MCP_D14_MCP_NAF14_MARK,
 400         MCP_D13_MCP_NAF13_MARK,
 401         MCP_D12_MCP_NAF12_MARK,
 402         MCP_D11_MCP_NAF11_MARK,
 403         MCP_D10_MCP_NAF10_MARK,
 404         MCP_D9_MCP_NAF9_MARK,
 405         MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
 406         MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
 407
 408         MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
 409         MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
 410         MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
 411         MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
 412         MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
 413         MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
 414         MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
 415         MCP_NBRSTOUT__MARK,
 416         MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
 417
 418         /* MSEL2 special cases */
 419         TSIF2_TS_XX1_MARK,
 420         TSIF2_TS_XX2_MARK,
 421         TSIF2_TS_XX3_MARK,
 422         TSIF2_TS_XX4_MARK,
 423         TSIF2_TS_XX5_MARK,
 424         TSIF1_TS_XX1_MARK,
 425         TSIF1_TS_XX2_MARK,
 426         TSIF1_TS_XX3_MARK,
 427         TSIF1_TS_XX4_MARK,
 428         TSIF1_TS_XX5_MARK,
 429         TSIF0_TS_XX1_MARK,
 430         TSIF0_TS_XX2_MARK,
 431         TSIF0_TS_XX3_MARK,
 432         TSIF0_TS_XX4_MARK,
 433         TSIF0_TS_XX5_MARK,
 434         MST1_TS_XX1_MARK,
 435         MST1_TS_XX2_MARK,
 436         MST1_TS_XX3_MARK,
 437         MST1_TS_XX4_MARK,
 438         MST1_TS_XX5_MARK,
 439         MST0_TS_XX1_MARK,
 440         MST0_TS_XX2_MARK,
 441         MST0_TS_XX3_MARK,
 442         MST0_TS_XX4_MARK,
 443         MST0_TS_XX5_MARK,
 444
 445         /* MSEL3 special cases */
 446         SDHI0_VCCQ_MC0_ON_MARK,
 447         SDHI0_VCCQ_MC0_OFF_MARK,
 448         DEBUG_MON_VIO_MARK,
 449         DEBUG_MON_LCDD_MARK,
 450         LCDC_LCDC0_MARK,
 451         LCDC_LCDC1_MARK,
 452
 453         /* MSEL4 special cases */
 454         IRQ9_MEM_INT_MARK,
 455         IRQ9_MCP_INT_MARK,
 456         A11_MARK,
 457         KEYOUT8_MARK,
 458         TPU4TO3_MARK,
 459         RESETA_N_PU_ON_MARK,
 460         RESETA_N_PU_OFF_MARK,
 461         EDBGREQ_PD_MARK,
 462         EDBGREQ_PU_MARK,
 463
 464         PINMUX_MARK_END,
 465 };
 466
 467 static const u16 pinmux_data[] = {
 468         /* specify valid pin states for each pin in GPIO mode */
 469         PINMUX_DATA_ALL(),
 470
 471         /* Table 25-1 (Function 0-7) */
 472         PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
 473         PINMUX_DATA(GPI0_MARK, PORT1_FN1),
 474         PINMUX_DATA(GPI1_MARK, PORT2_FN1),
 475         PINMUX_DATA(GPI2_MARK, PORT3_FN1),
 476         PINMUX_DATA(GPI3_MARK, PORT4_FN1),
 477         PINMUX_DATA(GPI4_MARK, PORT5_FN1),
 478         PINMUX_DATA(GPI5_MARK, PORT6_FN1),
 479         PINMUX_DATA(GPI6_MARK, PORT7_FN1),
 480         PINMUX_DATA(GPI7_MARK, PORT8_FN1),
 481         PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
 482         PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
 483         PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
 484         PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
 485         PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
 486         PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
 487         PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
 488         PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
 489         PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
 490         PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
 491         PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
 492         PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
 493         PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
 494         PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
 495         PINMUX_DATA(GPO0_MARK, PORT20_FN1),
 496         PINMUX_DATA(GPO1_MARK, PORT21_FN1),
 497         PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
 498         PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
 499         PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
 500         PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
 501         PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
 502         PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
 503         PINMUX_DATA(VINT_MARK, PORT25_FN1),
 504         PINMUX_DATA(TCKON_MARK, PORT26_FN1),
 505         PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
 506         PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
 507                 MSEL2CR_MSEL16_1), \
 508         PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
 509                 MSEL2CR_MSEL18_1), \
 510         PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
 511         PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
 512         PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
 513         PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
 514                 MSEL2CR_MSEL16_1), \
 515         PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
 516                 MSEL2CR_MSEL18_1), \
 517         PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
 518         PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
 519         PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
 520         PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
 521         PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
 522         PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
 523         PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
 524         PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
 525         PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
 526         PINMUX_DATA(XWUP_MARK, PORT33_FN3),
 527         PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
 528         PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
 529         PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
 530         PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
 531         PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
 532         PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
 533         PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
 534         PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
 535         PINMUX_DATA(VACK_MARK, PORT40_FN1),
 536         PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
 537         PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
 538         PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
 539         PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
 540         PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
 541         PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
 542         PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
 543         PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
 544         PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
 545         PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
 546         PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
 547         PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
 548         PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
 549         PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
 550         PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
 551         PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
 552         PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
 553         PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
 554         PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
 555         PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
 556         PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
 557         PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
 558         PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
 559         PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
 560         PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
 561         PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
 562
 563         PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
 564         PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
 565         PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
 566         PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
 567         PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
 568         PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
 569         PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
 570         PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
 571         PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
 572         PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
 573         PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
 574         PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
 575         PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
 576         PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
 577         PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
 578         PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
 579         PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
 580         PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
 581         PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
 582         PINMUX_DATA(A0_MARK, PORT57_FN1), \
 583         PINMUX_DATA(BS__MARK, PORT57_FN2),
 584         PINMUX_DATA(A12_MARK, PORT58_FN1), \
 585         PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
 586         PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
 587         PINMUX_DATA(A13_MARK, PORT59_FN1), \
 588         PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
 589         PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
 590         PINMUX_DATA(A14_MARK, PORT60_FN1), \
 591         PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
 592         PINMUX_DATA(A15_MARK, PORT61_FN1), \
 593         PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
 594         PINMUX_DATA(A16_MARK, PORT62_FN1), \
 595         PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
 596         PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
 597         PINMUX_DATA(A17_MARK, PORT63_FN1), \
 598         PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
 599         PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
 600         PINMUX_DATA(A18_MARK, PORT64_FN1), \
 601         PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
 602         PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
 603         PINMUX_DATA(A19_MARK, PORT65_FN1), \
 604         PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
 605         PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
 606         PINMUX_DATA(A20_MARK, PORT66_FN1), \
 607         PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
 608         PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
 609         PINMUX_DATA(A21_MARK, PORT67_FN1), \
 610         PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
 611         PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
 612         PINMUX_DATA(A22_MARK, PORT68_FN1), \
 613         PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
 614         PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
 615         PINMUX_DATA(A23_MARK, PORT69_FN1), \
 616         PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
 617         PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
 618         PINMUX_DATA(A24_MARK, PORT70_FN1), \
 619         PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
 620         PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
 621         PINMUX_DATA(A25_MARK, PORT71_FN1), \
 622         PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
 623         PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
 624         PINMUX_DATA(A26_MARK, PORT72_FN1), \
 625         PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
 626         PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
 627         PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
 628         PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
 629         PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
 630         PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
 631         PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
 632         PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
 633         PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
 634         PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
 635         PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
 636         PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
 637         PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
 638         PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
 639         PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
 640         PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
 641         PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
 642         PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
 643         PINMUX_DATA(CS4__MARK, PORT90_FN1),
 644         PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
 645         PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
 646         PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
 647         PINMUX_DATA(FCE1__MARK, PORT92_FN2),
 648         PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
 649         PINMUX_DATA(DACK0_MARK, PORT93_FN4),
 650         PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
 651         PINMUX_DATA(CS6A__MARK, PORT94_FN2),
 652         PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
 653         PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
 654         PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
 655         PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
 656         PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
 657         PINMUX_DATA(WE1__MARK, PORT98_FN1),
 658         PINMUX_DATA(FRB_MARK, PORT99_FN1),
 659         PINMUX_DATA(CKO_MARK, PORT100_FN1),
 660         PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
 661         PINMUX_DATA(NBRST__MARK, PORT102_FN1),
 662         PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
 663         PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
 664         PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
 665         PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
 666         PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
 667         PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
 668         PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
 669         PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
 670         PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
 671         PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
 672         PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
 673         PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
 674         PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
 675         PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
 676         PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
 677         PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
 678         PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
 679         PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
 680         PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
 681         PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
 682         PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
 683         PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
 684         PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
 685         PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
 686         PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
 687         PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
 688         PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
 689         PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
 690         PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
 691         PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
 692         PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
 693         PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
 694         PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
 695         PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
 696         PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
 697         PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
 698
 699         PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
 700         PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
 701         PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
 702         PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
 703         PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
 704         PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
 705         PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
 706                 MSEL4CR_MSEL10_1), \
 707         PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
 708         PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
 709         PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
 710         PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
 711         PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
 712         PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
 713         PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
 714         PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
 715         PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
 716         PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
 717         PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
 718         PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
 719         PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
 720         PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
 721         PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
 722         PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
 723         PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
 724         PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
 725         PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
 726         PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
 727         PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
 728         PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
 729         PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
 730         PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
 731         PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
 732         PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
 733         PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
 734         PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
 735         PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
 736         PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
 737         PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
 738         PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
 739         PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
 740         PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
 741         PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
 742         PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
 743         PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
 744         PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
 745         PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
 746         PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
 747         PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
 748         PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
 749         PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
 750         PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
 751         PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
 752         PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
 753         PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
 754         PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
 755         PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
 756         PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
 757         PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
 758         PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
 759         PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
 760         PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
 761         PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
 762         PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
 763         PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
 764         PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
 765         PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
 766         PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
 767         PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
 768         PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
 769         PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
 770         PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
 771         PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
 772         PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
 773         PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
 774         PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
 775         PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
 776         PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
 777         PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
 778         PINMUX_DATA(A27_MARK, PORT149_FN1), \
 779         PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
 780         PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
 781         PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
 782         PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
 783         PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
 784         PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
 785         PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
 786         PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
 787         PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
 788         PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
 789         PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
 790         PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
 791         PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
 792         PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
 793         PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
 794         PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
 795         PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
 796         PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
 797         PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
 798                 MSEL4CR_MSEL10_0),
 799         PINMUX_DATA(DINT__MARK, PORT158_FN1), \
 800         PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
 801         PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
 802         PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
 803         PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
 804         PINMUX_DATA(NMI_MARK, PORT159_FN3),
 805         PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
 806         PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
 807         PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
 808         PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
 809         PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
 810         PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
 811         PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
 812         PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
 813         PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
 814         PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
 815         PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
 816         PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
 817                 MSEL4CR_MSEL20_1), \
 818         PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
 819         PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
 820         PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
 821                 MSEL4CR_MSEL20_1), \
 822         PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
 823         PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
 824         PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
 825                 MSEL4CR_MSEL20_1), \
 826         PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
 827         PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
 828         PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
 829                 MSEL4CR_MSEL20_1),
 830         PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
 831         PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
 832                 MSEL4CR_MSEL20_1), \
 833         PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
 834         PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
 835         PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
 836         PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
 837         PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
 838         PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
 839         PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
 840         PINMUX_DATA(D16_MARK, PORT200_FN6),
 841         PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
 842         PINMUX_DATA(D17_MARK, PORT201_FN6),
 843         PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
 844         PINMUX_DATA(D18_MARK, PORT202_FN6),
 845         PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
 846         PINMUX_DATA(D19_MARK, PORT203_FN6),
 847         PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
 848         PINMUX_DATA(D20_MARK, PORT204_FN6),
 849         PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
 850         PINMUX_DATA(D21_MARK, PORT205_FN6),
 851         PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
 852         PINMUX_DATA(D22_MARK, PORT206_FN6),
 853         PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
 854         PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
 855         PINMUX_DATA(D23_MARK, PORT207_FN6),
 856         PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
 857         PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
 858         PINMUX_DATA(D24_MARK, PORT208_FN6),
 859         PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
 860         PINMUX_DATA(D25_MARK, PORT209_FN6),
 861         PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
 862         PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
 863         PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
 864         PINMUX_DATA(D26_MARK, PORT210_FN6),
 865         PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
 866         PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
 867         PINMUX_DATA(D27_MARK, PORT211_FN6),
 868         PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
 869         PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
 870         PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
 871         PINMUX_DATA(D28_MARK, PORT212_FN6),
 872         PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
 873         PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
 874         PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
 875         PINMUX_DATA(D29_MARK, PORT213_FN6),
 876         PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
 877         PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
 878         PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
 879         PINMUX_DATA(D30_MARK, PORT214_FN6),
 880         PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
 881         PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
 882         PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
 883         PINMUX_DATA(D31_MARK, PORT215_FN6),
 884         PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
 885         PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
 886         PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
 887         PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
 888         PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
 889         PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
 890         PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
 891                 MSEL4CR_MSEL26_1), \
 892         PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
 893         PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
 894         PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
 895         PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
 896         PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
 897         PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
 898         PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
 899         PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
 900         PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
 901         PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
 902         PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
 903         PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
 904                 MSEL4CR_MSEL26_1), \
 905         PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
 906         PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
 907         PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
 908         PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
 909         PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
 910         PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
 911         PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
 912         PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
 913         PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
 914                 MSEL4CR_MSEL26_1), \
 915         PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
 916         PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
 917         PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
 918         PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
 919         PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
 920         PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
 921         PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
 922                 MSEL4CR_MSEL26_1), \
 923         PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
 924
 925         PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
 926         PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
 927         PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
 928         PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
 929         PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
 930         PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
 931         PINMUX_DATA(IDIN_MARK, PORT227_FN4),
 932         PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
 933         PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
 934         PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
 935         PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
 936         PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
 937         PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
 938         PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
 939         PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
 940         PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
 941         PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
 942         PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
 943         PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
 944         PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
 945         PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
 946                 MSEL4CR_MSEL26_0), \
 947         PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
 948         PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
 949         PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
 950         PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
 951                 MSEL4CR_MSEL26_0), \
 952         PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
 953         PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
 954         PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
 955                 MSEL2CR_MSEL16_0),
 956         PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
 957         PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
 958                 MSEL2CR_MSEL16_0),
 959         PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
 960         PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
 961                 MSEL4CR_MSEL26_0), \
 962         PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
 963         PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
 964         PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
 965                 MSEL4CR_MSEL26_0), \
 966         PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
 967         PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
 968         PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
 969         PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
 970         PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
 971         PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
 972         PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
 973         PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
 974         PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
 975         PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
 976         PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
 977                 MSEL4CR_MSEL20_0), \
 978         PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
 979         PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
 980         PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
 981         PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
 982                 MSEL4CR_MSEL20_0), \
 983         PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
 984         PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
 985         PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
 986         PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
 987                 MSEL4CR_MSEL20_0), \
 988         PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
 989         PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
 990         PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
 991         PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
 992                 MSEL4CR_MSEL20_0), \
 993         PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
 994         PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
 995         PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
 996         PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
 997                 MSEL4CR_MSEL20_0), \
 998         PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
 999         PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
1000         PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
1001         PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
1002                 MSEL2CR_MSEL18_0), \
1003         PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
1004         PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
1005         PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
1006         PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
1007                 MSEL2CR_MSEL18_0), \
1008         PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
1009         PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
1010         PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
1011         PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
1012         PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
1013         PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
1014         PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
1015         PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
1016         PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
1017         PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
1018         PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
1019         PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
1020         PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
1021         PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
1022         PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
1023         PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
1024         PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
1025         PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
1026         PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
1027         PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
1028         PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
1029         PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
1030         PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
1031         PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
1032         PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
1033         PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
1034         PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
1035         PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1036         PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1037         PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
1038         PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
1039         PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
1040         PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
1041         PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
1042         PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
1043         PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
1044         PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
1045         PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
1046         PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
1047         PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
1048         PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
1049         PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
1050         PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
1051         PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1052         PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1053         PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
1054         PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
1055         PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
1056         PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
1057         PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
1058         PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
1059         PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
1060         PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
1061         PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
1062         PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
1063         PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
1064         PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
1065         PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
1066         PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
1067
1068         PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
1069         PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
1070         PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
1071         PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
1072         PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
1073         PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
1074         PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
1075         PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
1076         PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
1077         PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
1078         PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
1079         PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
1080         PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
1081         PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
1082         PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
1083         PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
1084         PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
1085
1086         /* MSEL2 special cases */
1087         PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1088                 MSEL2CR_MSEL12_0),
1089         PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1090                 MSEL2CR_MSEL12_1),
1091         PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1092                 MSEL2CR_MSEL12_0),
1093         PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1094                 MSEL2CR_MSEL12_1),
1095         PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
1096                 MSEL2CR_MSEL12_0),
1097         PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1098                 MSEL2CR_MSEL9_0),
1099         PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1100                 MSEL2CR_MSEL9_1),
1101         PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1102                 MSEL2CR_MSEL9_0),
1103         PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1104                 MSEL2CR_MSEL9_1),
1105         PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
1106                 MSEL2CR_MSEL9_0),
1107         PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1108                 MSEL2CR_MSEL6_0),
1109         PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1110                 MSEL2CR_MSEL6_1),
1111         PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1112                 MSEL2CR_MSEL6_0),
1113         PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1114                 MSEL2CR_MSEL6_1),
1115         PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
1116                 MSEL2CR_MSEL6_0),
1117         PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1118                 MSEL2CR_MSEL3_0),
1119         PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1120                 MSEL2CR_MSEL3_1),
1121         PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1122                 MSEL2CR_MSEL3_0),
1123         PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1124                 MSEL2CR_MSEL3_1),
1125         PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
1126                 MSEL2CR_MSEL3_0),
1127         PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1128                 MSEL2CR_MSEL0_0),
1129         PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1130                 MSEL2CR_MSEL0_1),
1131         PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1132                 MSEL2CR_MSEL0_0),
1133         PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1134                 MSEL2CR_MSEL0_1),
1135         PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
1136                 MSEL2CR_MSEL0_0),
1137
1138         /* MSEL3 special cases */
1139         PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
1140         PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
1141         PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
1142         PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
1143         PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
1144         PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
1145
1146         /* MSEL4 special cases */
1147         PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
1148         PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
1149         PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
1150         PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
1151         PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
1152         PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
1153         PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
1154         PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
1155         PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
1156 };
1157
1158 #define __I             (SH_PFC_PIN_CFG_INPUT)
1159 #define __O             (SH_PFC_PIN_CFG_OUTPUT)
1160 #define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1161 #define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
1162 #define __PU            (SH_PFC_PIN_CFG_PULL_UP)
1163 #define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1164
1165 #define SH73A0_PIN_I_PD(pin)            SH_PFC_PIN_CFG(pin, __I | __PD)
1166 #define SH73A0_PIN_I_PU(pin)            SH_PFC_PIN_CFG(pin, __I | __PU)
1167 #define SH73A0_PIN_I_PU_PD(pin)         SH_PFC_PIN_CFG(pin, __I | __PUD)
1168 #define SH73A0_PIN_IO(pin)              SH_PFC_PIN_CFG(pin, __IO)
1169 #define SH73A0_PIN_IO_PD(pin)           SH_PFC_PIN_CFG(pin, __IO | __PD)
1170 #define SH73A0_PIN_IO_PU(pin)           SH_PFC_PIN_CFG(pin, __IO | __PU)
1171 #define SH73A0_PIN_IO_PU_PD(pin)        SH_PFC_PIN_CFG(pin, __IO | __PUD)
1172 #define SH73A0_PIN_O(pin)               SH_PFC_PIN_CFG(pin, __O)
1173
1174 /* Pin numbers for pins without a corresponding GPIO port number are computed
1175  * from the row and column numbers with a 1000 offset to avoid collisions with
1176  * GPIO port numbers.
1177  */
1178 #define PIN_NUMBER(row, col)            (1000+((row)-1)*34+(col)-1)
1179
1180 static const struct sh_pfc_pin pinmux_pins[] = {
1181         /* Table 25-1 (I/O and Pull U/D) */
1182         SH73A0_PIN_I_PD(0),
1183         SH73A0_PIN_I_PU(1),
1184         SH73A0_PIN_I_PU(2),
1185         SH73A0_PIN_I_PU(3),
1186         SH73A0_PIN_I_PU(4),
1187         SH73A0_PIN_I_PU(5),
1188         SH73A0_PIN_I_PU(6),
1189         SH73A0_PIN_I_PU(7),
1190         SH73A0_PIN_I_PU(8),
1191         SH73A0_PIN_I_PD(9),
1192         SH73A0_PIN_I_PD(10),
1193         SH73A0_PIN_I_PU_PD(11),
1194         SH73A0_PIN_IO_PU_PD(12),
1195         SH73A0_PIN_IO_PU_PD(13),
1196         SH73A0_PIN_IO_PU_PD(14),
1197         SH73A0_PIN_IO_PU_PD(15),
1198         SH73A0_PIN_IO_PD(16),
1199         SH73A0_PIN_IO_PD(17),
1200         SH73A0_PIN_IO_PU(18),
1201         SH73A0_PIN_IO_PU(19),
1202         SH73A0_PIN_O(20),
1203         SH73A0_PIN_O(21),
1204         SH73A0_PIN_O(22),
1205         SH73A0_PIN_O(23),
1206         SH73A0_PIN_O(24),
1207         SH73A0_PIN_I_PD(25),
1208         SH73A0_PIN_I_PD(26),
1209         SH73A0_PIN_IO_PU(27),
1210         SH73A0_PIN_IO_PU(28),
1211         SH73A0_PIN_IO_PD(29),
1212         SH73A0_PIN_IO_PD(30),
1213         SH73A0_PIN_IO_PU(31),
1214         SH73A0_PIN_IO_PD(32),
1215         SH73A0_PIN_I_PU_PD(33),
1216         SH73A0_PIN_IO_PD(34),
1217         SH73A0_PIN_I_PU_PD(35),
1218         SH73A0_PIN_IO_PD(36),
1219         SH73A0_PIN_IO(37),
1220         SH73A0_PIN_O(38),
1221         SH73A0_PIN_I_PU(39),
1222         SH73A0_PIN_I_PU_PD(40),
1223         SH73A0_PIN_O(41),
1224         SH73A0_PIN_IO_PD(42),
1225         SH73A0_PIN_IO_PU_PD(43),
1226         SH73A0_PIN_IO_PU_PD(44),
1227         SH73A0_PIN_IO_PD(45),
1228         SH73A0_PIN_IO_PD(46),
1229         SH73A0_PIN_IO_PD(47),
1230         SH73A0_PIN_I_PD(48),
1231         SH73A0_PIN_IO_PU_PD(49),
1232         SH73A0_PIN_IO_PD(50),
1233         SH73A0_PIN_IO_PD(51),
1234         SH73A0_PIN_O(52),
1235         SH73A0_PIN_IO_PU_PD(53),
1236         SH73A0_PIN_IO_PU_PD(54),
1237         SH73A0_PIN_IO_PD(55),
1238         SH73A0_PIN_I_PU_PD(56),
1239         SH73A0_PIN_IO(57),
1240         SH73A0_PIN_IO(58),
1241         SH73A0_PIN_IO(59),
1242         SH73A0_PIN_IO(60),
1243         SH73A0_PIN_IO(61),
1244         SH73A0_PIN_IO_PD(62),
1245         SH73A0_PIN_IO_PD(63),
1246         SH73A0_PIN_IO_PU_PD(64),
1247         SH73A0_PIN_IO_PD(65),
1248         SH73A0_PIN_IO_PU_PD(66),
1249         SH73A0_PIN_IO_PU_PD(67),
1250         SH73A0_PIN_IO_PU_PD(68),
1251         SH73A0_PIN_IO_PU_PD(69),
1252         SH73A0_PIN_IO_PU_PD(70),
1253         SH73A0_PIN_IO_PU_PD(71),
1254         SH73A0_PIN_IO_PU_PD(72),
1255         SH73A0_PIN_I_PU_PD(73),
1256         SH73A0_PIN_IO_PU(74),
1257         SH73A0_PIN_IO_PU(75),
1258         SH73A0_PIN_IO_PU(76),
1259         SH73A0_PIN_IO_PU(77),
1260         SH73A0_PIN_IO_PU(78),
1261         SH73A0_PIN_IO_PU(79),
1262         SH73A0_PIN_IO_PU(80),
1263         SH73A0_PIN_IO_PU(81),
1264         SH73A0_PIN_IO_PU(82),
1265         SH73A0_PIN_IO_PU(83),
1266         SH73A0_PIN_IO_PU(84),
1267         SH73A0_PIN_IO_PU(85),
1268         SH73A0_PIN_IO_PU(86),
1269         SH73A0_PIN_IO_PU(87),
1270         SH73A0_PIN_IO_PU(88),
1271         SH73A0_PIN_IO_PU(89),
1272         SH73A0_PIN_O(90),
1273         SH73A0_PIN_IO_PU(91),
1274         SH73A0_PIN_O(92),
1275         SH73A0_PIN_IO_PU(93),
1276         SH73A0_PIN_O(94),
1277         SH73A0_PIN_I_PU_PD(95),
1278         SH73A0_PIN_IO(96),
1279         SH73A0_PIN_IO(97),
1280         SH73A0_PIN_IO(98),
1281         SH73A0_PIN_I_PU(99),
1282         SH73A0_PIN_O(100),
1283         SH73A0_PIN_O(101),
1284         SH73A0_PIN_I_PU(102),
1285         SH73A0_PIN_IO_PD(103),
1286         SH73A0_PIN_I_PU_PD(104),
1287         SH73A0_PIN_I_PD(105),
1288         SH73A0_PIN_I_PD(106),
1289         SH73A0_PIN_I_PU_PD(107),
1290         SH73A0_PIN_I_PU_PD(108),
1291         SH73A0_PIN_IO_PD(109),
1292         SH73A0_PIN_IO_PD(110),
1293         SH73A0_PIN_IO_PU_PD(111),
1294         SH73A0_PIN_IO_PU_PD(112),
1295         SH73A0_PIN_IO_PU_PD(113),
1296         SH73A0_PIN_IO_PD(114),
1297         SH73A0_PIN_IO_PU(115),
1298         SH73A0_PIN_IO_PU(116),
1299         SH73A0_PIN_IO_PU_PD(117),
1300         SH73A0_PIN_IO_PU_PD(118),
1301         SH73A0_PIN_IO_PD(128),
1302         SH73A0_PIN_IO_PD(129),
1303         SH73A0_PIN_IO_PU_PD(130),
1304         SH73A0_PIN_IO_PD(131),
1305         SH73A0_PIN_IO_PD(132),
1306         SH73A0_PIN_IO_PD(133),
1307         SH73A0_PIN_IO_PU_PD(134),
1308         SH73A0_PIN_IO_PU_PD(135),
1309         SH73A0_PIN_IO_PU_PD(136),
1310         SH73A0_PIN_IO_PU_PD(137),
1311         SH73A0_PIN_IO_PD(138),
1312         SH73A0_PIN_IO_PD(139),
1313         SH73A0_PIN_IO_PD(140),
1314         SH73A0_PIN_IO_PD(141),
1315         SH73A0_PIN_IO_PD(142),
1316         SH73A0_PIN_IO_PD(143),
1317         SH73A0_PIN_IO_PU_PD(144),
1318         SH73A0_PIN_IO_PD(145),
1319         SH73A0_PIN_IO_PU_PD(146),
1320         SH73A0_PIN_IO_PU_PD(147),
1321         SH73A0_PIN_IO_PU_PD(148),
1322         SH73A0_PIN_IO_PU_PD(149),
1323         SH73A0_PIN_I_PU_PD(150),
1324         SH73A0_PIN_IO_PU_PD(151),
1325         SH73A0_PIN_IO_PU_PD(152),
1326         SH73A0_PIN_IO_PD(153),
1327         SH73A0_PIN_IO_PD(154),
1328         SH73A0_PIN_I_PU_PD(155),
1329         SH73A0_PIN_IO_PU_PD(156),
1330         SH73A0_PIN_I_PD(157),
1331         SH73A0_PIN_IO_PD(158),
1332         SH73A0_PIN_IO_PU_PD(159),
1333         SH73A0_PIN_IO_PU_PD(160),
1334         SH73A0_PIN_I_PU_PD(161),
1335         SH73A0_PIN_I_PU_PD(162),
1336         SH73A0_PIN_IO_PU_PD(163),
1337         SH73A0_PIN_I_PU_PD(164),
1338         SH73A0_PIN_IO_PD(192),
1339         SH73A0_PIN_IO_PU_PD(193),
1340         SH73A0_PIN_IO_PD(194),
1341         SH73A0_PIN_IO_PU_PD(195),
1342         SH73A0_PIN_IO_PD(196),
1343         SH73A0_PIN_IO_PD(197),
1344         SH73A0_PIN_IO_PD(198),
1345         SH73A0_PIN_IO_PD(199),
1346         SH73A0_PIN_IO_PU_PD(200),
1347         SH73A0_PIN_IO_PU_PD(201),
1348         SH73A0_PIN_IO_PU_PD(202),
1349         SH73A0_PIN_IO_PU_PD(203),
1350         SH73A0_PIN_IO_PU_PD(204),
1351         SH73A0_PIN_IO_PU_PD(205),
1352         SH73A0_PIN_IO_PU_PD(206),
1353         SH73A0_PIN_IO_PD(207),
1354         SH73A0_PIN_IO_PD(208),
1355         SH73A0_PIN_IO_PD(209),
1356         SH73A0_PIN_IO_PD(210),
1357         SH73A0_PIN_IO_PD(211),
1358         SH73A0_PIN_IO_PD(212),
1359         SH73A0_PIN_IO_PD(213),
1360         SH73A0_PIN_IO_PU_PD(214),
1361         SH73A0_PIN_IO_PU_PD(215),
1362         SH73A0_PIN_IO_PD(216),
1363         SH73A0_PIN_IO_PD(217),
1364         SH73A0_PIN_O(218),
1365         SH73A0_PIN_IO_PD(219),
1366         SH73A0_PIN_IO_PD(220),
1367         SH73A0_PIN_IO_PU_PD(221),
1368         SH73A0_PIN_IO_PU_PD(222),
1369         SH73A0_PIN_I_PU_PD(223),
1370         SH73A0_PIN_I_PU_PD(224),
1371         SH73A0_PIN_IO_PU_PD(225),
1372         SH73A0_PIN_O(226),
1373         SH73A0_PIN_IO_PU_PD(227),
1374         SH73A0_PIN_I_PU_PD(228),
1375         SH73A0_PIN_I_PD(229),
1376         SH73A0_PIN_IO(230),
1377         SH73A0_PIN_IO_PU_PD(231),
1378         SH73A0_PIN_IO_PU_PD(232),
1379         SH73A0_PIN_I_PU_PD(233),
1380         SH73A0_PIN_IO_PU_PD(234),
1381         SH73A0_PIN_IO_PU_PD(235),
1382         SH73A0_PIN_IO_PU_PD(236),
1383         SH73A0_PIN_IO_PD(237),
1384         SH73A0_PIN_IO_PU_PD(238),
1385         SH73A0_PIN_IO_PU_PD(239),
1386         SH73A0_PIN_IO_PU_PD(240),
1387         SH73A0_PIN_O(241),
1388         SH73A0_PIN_I_PD(242),
1389         SH73A0_PIN_IO_PU_PD(243),
1390         SH73A0_PIN_IO_PU_PD(244),
1391         SH73A0_PIN_IO_PU_PD(245),
1392         SH73A0_PIN_IO_PU_PD(246),
1393         SH73A0_PIN_IO_PU_PD(247),
1394         SH73A0_PIN_IO_PU_PD(248),
1395         SH73A0_PIN_IO_PU_PD(249),
1396         SH73A0_PIN_IO_PU_PD(250),
1397         SH73A0_PIN_IO_PU_PD(251),
1398         SH73A0_PIN_IO_PU_PD(252),
1399         SH73A0_PIN_IO_PU_PD(253),
1400         SH73A0_PIN_IO_PU_PD(254),
1401         SH73A0_PIN_IO_PU_PD(255),
1402         SH73A0_PIN_IO_PU_PD(256),
1403         SH73A0_PIN_IO_PU_PD(257),
1404         SH73A0_PIN_IO_PU_PD(258),
1405         SH73A0_PIN_IO_PU_PD(259),
1406         SH73A0_PIN_IO_PU_PD(260),
1407         SH73A0_PIN_IO_PU_PD(261),
1408         SH73A0_PIN_IO_PU_PD(262),
1409         SH73A0_PIN_IO_PU_PD(263),
1410         SH73A0_PIN_IO_PU_PD(264),
1411         SH73A0_PIN_IO_PU_PD(265),
1412         SH73A0_PIN_IO_PU_PD(266),
1413         SH73A0_PIN_IO_PU_PD(267),
1414         SH73A0_PIN_IO_PU_PD(268),
1415         SH73A0_PIN_IO_PU_PD(269),
1416         SH73A0_PIN_IO_PU_PD(270),
1417         SH73A0_PIN_IO_PU_PD(271),
1418         SH73A0_PIN_IO_PU_PD(272),
1419         SH73A0_PIN_IO_PU_PD(273),
1420         SH73A0_PIN_IO_PU_PD(274),
1421         SH73A0_PIN_IO_PU_PD(275),
1422         SH73A0_PIN_IO_PU_PD(276),
1423         SH73A0_PIN_IO_PU_PD(277),
1424         SH73A0_PIN_IO_PU_PD(278),
1425         SH73A0_PIN_IO_PU_PD(279),
1426         SH73A0_PIN_IO_PU_PD(280),
1427         SH73A0_PIN_O(281),
1428         SH73A0_PIN_O(282),
1429         SH73A0_PIN_I_PU(288),
1430         SH73A0_PIN_IO_PU_PD(289),
1431         SH73A0_PIN_IO_PU_PD(290),
1432         SH73A0_PIN_IO_PU_PD(291),
1433         SH73A0_PIN_IO_PU_PD(292),
1434         SH73A0_PIN_IO_PU_PD(293),
1435         SH73A0_PIN_IO_PU_PD(294),
1436         SH73A0_PIN_IO_PU_PD(295),
1437         SH73A0_PIN_IO_PU_PD(296),
1438         SH73A0_PIN_IO_PU_PD(297),
1439         SH73A0_PIN_IO_PU_PD(298),
1440         SH73A0_PIN_IO_PU_PD(299),
1441         SH73A0_PIN_IO_PU_PD(300),
1442         SH73A0_PIN_IO_PU_PD(301),
1443         SH73A0_PIN_IO_PU_PD(302),
1444         SH73A0_PIN_IO_PU_PD(303),
1445         SH73A0_PIN_IO_PU_PD(304),
1446         SH73A0_PIN_IO_PU_PD(305),
1447         SH73A0_PIN_O(306),
1448         SH73A0_PIN_O(307),
1449         SH73A0_PIN_I_PU(308),
1450         SH73A0_PIN_O(309),
1451
1452         /* Pins not associated with a GPIO port */
1453         SH_PFC_PIN_NAMED(6, 26, F26),
1454 };
1455
1456 /* - BSC -------------------------------------------------------------------- */
1457 static const unsigned int bsc_data_0_7_pins[] = {
1458         /* D[0:7] */
1459         74, 75, 76, 77, 78, 79, 80, 81,
1460 };
1461 static const unsigned int bsc_data_0_7_mux[] = {
1462         D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1463         D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1464 };
1465 static const unsigned int bsc_data_8_15_pins[] = {
1466         /* D[8:15] */
1467         82, 83, 84, 85, 86, 87, 88, 89,
1468 };
1469 static const unsigned int bsc_data_8_15_mux[] = {
1470         D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1471         D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1472 };
1473 static const unsigned int bsc_cs4_pins[] = {
1474         /* CS */
1475         90,
1476 };
1477 static const unsigned int bsc_cs4_mux[] = {
1478         CS4__MARK,
1479 };
1480 static const unsigned int bsc_cs5_a_pins[] = {
1481         /* CS */
1482         91,
1483 };
1484 static const unsigned int bsc_cs5_a_mux[] = {
1485         CS5A__MARK,
1486 };
1487 static const unsigned int bsc_cs5_b_pins[] = {
1488         /* CS */
1489         92,
1490 };
1491 static const unsigned int bsc_cs5_b_mux[] = {
1492         CS5B__MARK,
1493 };
1494 static const unsigned int bsc_cs6_a_pins[] = {
1495         /* CS */
1496         94,
1497 };
1498 static const unsigned int bsc_cs6_a_mux[] = {
1499         CS6A__MARK,
1500 };
1501 static const unsigned int bsc_cs6_b_pins[] = {
1502         /* CS */
1503         93,
1504 };
1505 static const unsigned int bsc_cs6_b_mux[] = {
1506         CS6B__MARK,
1507 };
1508 static const unsigned int bsc_rd_pins[] = {
1509         /* RD */
1510         96,
1511 };
1512 static const unsigned int bsc_rd_mux[] = {
1513         RD__FSC_MARK,
1514 };
1515 static const unsigned int bsc_rdwr_0_pins[] = {
1516         /* RDWR */
1517         91,
1518 };
1519 static const unsigned int bsc_rdwr_0_mux[] = {
1520         PORT91_RDWR_MARK,
1521 };
1522 static const unsigned int bsc_rdwr_1_pins[] = {
1523         /* RDWR */
1524         97,
1525 };
1526 static const unsigned int bsc_rdwr_1_mux[] = {
1527         RDWR_FWE_MARK,
1528 };
1529 static const unsigned int bsc_rdwr_2_pins[] = {
1530         /* RDWR */
1531         149,
1532 };
1533 static const unsigned int bsc_rdwr_2_mux[] = {
1534         PORT149_RDWR_MARK,
1535 };
1536 static const unsigned int bsc_we0_pins[] = {
1537         /* WE0 */
1538         97,
1539 };
1540 static const unsigned int bsc_we0_mux[] = {
1541         WE0__FWE_MARK,
1542 };
1543 static const unsigned int bsc_we1_pins[] = {
1544         /* WE1 */
1545         98,
1546 };
1547 static const unsigned int bsc_we1_mux[] = {
1548         WE1__MARK,
1549 };
1550 /* - FSIA ------------------------------------------------------------------- */
1551 static const unsigned int fsia_mclk_in_pins[] = {
1552         /* CK */
1553         49,
1554 };
1555 static const unsigned int fsia_mclk_in_mux[] = {
1556         FSIACK_MARK,
1557 };
1558 static const unsigned int fsia_mclk_out_pins[] = {
1559         /* OMC */
1560         49,
1561 };
1562 static const unsigned int fsia_mclk_out_mux[] = {
1563         FSIAOMC_MARK,
1564 };
1565 static const unsigned int fsia_sclk_in_pins[] = {
1566         /* ILR, IBT */
1567         50, 51,
1568 };
1569 static const unsigned int fsia_sclk_in_mux[] = {
1570         FSIAILR_MARK, FSIAIBT_MARK,
1571 };
1572 static const unsigned int fsia_sclk_out_pins[] = {
1573         /* OLR, OBT */
1574         50, 51,
1575 };
1576 static const unsigned int fsia_sclk_out_mux[] = {
1577         FSIAOLR_MARK, FSIAOBT_MARK,
1578 };
1579 static const unsigned int fsia_data_in_pins[] = {
1580         /* ISLD */
1581         55,
1582 };
1583 static const unsigned int fsia_data_in_mux[] = {
1584         FSIAISLD_MARK,
1585 };
1586 static const unsigned int fsia_data_out_pins[] = {
1587         /* OSLD */
1588         52,
1589 };
1590 static const unsigned int fsia_data_out_mux[] = {
1591         FSIAOSLD_MARK,
1592 };
1593 static const unsigned int fsia_spdif_pins[] = {
1594         /* SPDIF */
1595         53,
1596 };
1597 static const unsigned int fsia_spdif_mux[] = {
1598         FSIASPDIF_MARK,
1599 };
1600 /* - FSIB ------------------------------------------------------------------- */
1601 static const unsigned int fsib_mclk_in_pins[] = {
1602         /* CK */
1603         54,
1604 };
1605 static const unsigned int fsib_mclk_in_mux[] = {
1606         FSIBCK_MARK,
1607 };
1608 static const unsigned int fsib_mclk_out_pins[] = {
1609         /* OMC */
1610         54,
1611 };
1612 static const unsigned int fsib_mclk_out_mux[] = {
1613         FSIBOMC_MARK,
1614 };
1615 static const unsigned int fsib_sclk_in_pins[] = {
1616         /* ILR, IBT */
1617         37, 36,
1618 };
1619 static const unsigned int fsib_sclk_in_mux[] = {
1620         FSIBILR_MARK, FSIBIBT_MARK,
1621 };
1622 static const unsigned int fsib_sclk_out_pins[] = {
1623         /* OLR, OBT */
1624         37, 36,
1625 };
1626 static const unsigned int fsib_sclk_out_mux[] = {
1627         FSIBOLR_MARK, FSIBOBT_MARK,
1628 };
1629 static const unsigned int fsib_data_in_pins[] = {
1630         /* ISLD */
1631         39,
1632 };
1633 static const unsigned int fsib_data_in_mux[] = {
1634         FSIBISLD_MARK,
1635 };
1636 static const unsigned int fsib_data_out_pins[] = {
1637         /* OSLD */
1638         38,
1639 };
1640 static const unsigned int fsib_data_out_mux[] = {
1641         FSIBOSLD_MARK,
1642 };
1643 static const unsigned int fsib_spdif_pins[] = {
1644         /* SPDIF */
1645         53,
1646 };
1647 static const unsigned int fsib_spdif_mux[] = {
1648         FSIBSPDIF_MARK,
1649 };
1650 /* - FSIC ------------------------------------------------------------------- */
1651 static const unsigned int fsic_mclk_in_pins[] = {
1652         /* CK */
1653         54,
1654 };
1655 static const unsigned int fsic_mclk_in_mux[] = {
1656         FSICCK_MARK,
1657 };
1658 static const unsigned int fsic_mclk_out_pins[] = {
1659         /* OMC */
1660         54,
1661 };
1662 static const unsigned int fsic_mclk_out_mux[] = {
1663         FSICOMC_MARK,
1664 };
1665 static const unsigned int fsic_sclk_in_pins[] = {
1666         /* ILR, IBT */
1667         46, 45,
1668 };
1669 static const unsigned int fsic_sclk_in_mux[] = {
1670         FSICILR_MARK, FSICIBT_MARK,
1671 };
1672 static const unsigned int fsic_sclk_out_pins[] = {
1673         /* OLR, OBT */
1674         46, 45,
1675 };
1676 static const unsigned int fsic_sclk_out_mux[] = {
1677         FSICOLR_MARK, FSICOBT_MARK,
1678 };
1679 static const unsigned int fsic_data_in_pins[] = {
1680         /* ISLD */
1681         48,
1682 };
1683 static const unsigned int fsic_data_in_mux[] = {
1684         FSICISLD_MARK,
1685 };
1686 static const unsigned int fsic_data_out_pins[] = {
1687         /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
1688         47, 44, 42, 16,
1689 };
1690 static const unsigned int fsic_data_out_mux[] = {
1691         FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
1692 };
1693 static const unsigned int fsic_spdif_0_pins[] = {
1694         /* SPDIF */
1695         53,
1696 };
1697 static const unsigned int fsic_spdif_0_mux[] = {
1698         PORT53_FSICSPDIF_MARK,
1699 };
1700 static const unsigned int fsic_spdif_1_pins[] = {
1701         /* SPDIF */
1702         47,
1703 };
1704 static const unsigned int fsic_spdif_1_mux[] = {
1705         PORT47_FSICSPDIF_MARK,
1706 };
1707 /* - FSID ------------------------------------------------------------------- */
1708 static const unsigned int fsid_sclk_in_pins[] = {
1709         /* ILR, IBT */
1710         46, 45,
1711 };
1712 static const unsigned int fsid_sclk_in_mux[] = {
1713         FSIDILR_MARK, FSIDIBT_MARK,
1714 };
1715 static const unsigned int fsid_sclk_out_pins[] = {
1716         /* OLR, OBT */
1717         46, 45,
1718 };
1719 static const unsigned int fsid_sclk_out_mux[] = {
1720         FSIDOLR_MARK, FSIDOBT_MARK,
1721 };
1722 static const unsigned int fsid_data_in_pins[] = {
1723         /* ISLD */
1724         48,
1725 };
1726 static const unsigned int fsid_data_in_mux[] = {
1727         FSIDISLD_MARK,
1728 };
1729 /* - I2C2 ------------------------------------------------------------------- */
1730 static const unsigned int i2c2_0_pins[] = {
1731         /* SCL, SDA */
1732         237, 236,
1733 };
1734 static const unsigned int i2c2_0_mux[] = {
1735         PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
1736 };
1737 static const unsigned int i2c2_1_pins[] = {
1738         /* SCL, SDA */
1739         27, 28,
1740 };
1741 static const unsigned int i2c2_1_mux[] = {
1742         PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
1743 };
1744 static const unsigned int i2c2_2_pins[] = {
1745         /* SCL, SDA */
1746         115, 116,
1747 };
1748 static const unsigned int i2c2_2_mux[] = {
1749         PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
1750 };
1751 /* - I2C3 ------------------------------------------------------------------- */
1752 static const unsigned int i2c3_0_pins[] = {
1753         /* SCL, SDA */
1754         248, 249,
1755 };
1756 static const unsigned int i2c3_0_mux[] = {
1757         PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
1758 };
1759 static const unsigned int i2c3_1_pins[] = {
1760         /* SCL, SDA */
1761         27, 28,
1762 };
1763 static const unsigned int i2c3_1_mux[] = {
1764         PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
1765 };
1766 static const unsigned int i2c3_2_pins[] = {
1767         /* SCL, SDA */
1768         115, 116,
1769 };
1770 static const unsigned int i2c3_2_mux[] = {
1771         PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
1772 };
1773 /* - IrDA ------------------------------------------------------------------- */
1774 static const unsigned int irda_0_pins[] = {
1775         /* OUT, IN, FIRSEL */
1776         241, 242, 243,
1777 };
1778 static const unsigned int irda_0_mux[] = {
1779         PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
1780 };
1781 static const unsigned int irda_1_pins[] = {
1782         /* OUT, IN, FIRSEL */
1783         49, 53, 54,
1784 };
1785 static const unsigned int irda_1_mux[] = {
1786         PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
1787 };
1788 /* - KEYSC ------------------------------------------------------------------ */
1789 static const unsigned int keysc_in5_pins[] = {
1790         /* KEYIN[0:4] */
1791         66, 67, 68, 69, 70,
1792 };
1793 static const unsigned int keysc_in5_mux[] = {
1794         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1795         KEYIN4_MARK,
1796 };
1797 static const unsigned int keysc_in6_pins[] = {
1798         /* KEYIN[0:5] */
1799         66, 67, 68, 69, 70, 71,
1800 };
1801 static const unsigned int keysc_in6_mux[] = {
1802         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1803         KEYIN4_MARK, KEYIN5_MARK,
1804 };
1805 static const unsigned int keysc_in7_pins[] = {
1806         /* KEYIN[0:6] */
1807         66, 67, 68, 69, 70, 71, 72,
1808 };
1809 static const unsigned int keysc_in7_mux[] = {
1810         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1811         KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
1812 };
1813 static const unsigned int keysc_in8_pins[] = {
1814         /* KEYIN[0:7] */
1815         66, 67, 68, 69, 70, 71, 72, 73,
1816 };
1817 static const unsigned int keysc_in8_mux[] = {
1818         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1819         KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
1820 };
1821 static const unsigned int keysc_out04_pins[] = {
1822         /* KEYOUT[0:4] */
1823         65, 64, 63, 62, 61,
1824 };
1825 static const unsigned int keysc_out04_mux[] = {
1826         KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
1827 };
1828 static const unsigned int keysc_out5_pins[] = {
1829         /* KEYOUT5 */
1830         60,
1831 };
1832 static const unsigned int keysc_out5_mux[] = {
1833         KEYOUT5_MARK,
1834 };
1835 static const unsigned int keysc_out6_0_pins[] = {
1836         /* KEYOUT6 */
1837         59,
1838 };
1839 static const unsigned int keysc_out6_0_mux[] = {
1840         PORT59_KEYOUT6_MARK,
1841 };
1842 static const unsigned int keysc_out6_1_pins[] = {
1843         /* KEYOUT6 */
1844         131,
1845 };
1846 static const unsigned int keysc_out6_1_mux[] = {
1847         PORT131_KEYOUT6_MARK,
1848 };
1849 static const unsigned int keysc_out6_2_pins[] = {
1850         /* KEYOUT6 */
1851         143,
1852 };
1853 static const unsigned int keysc_out6_2_mux[] = {
1854         PORT143_KEYOUT6_MARK,
1855 };
1856 static const unsigned int keysc_out7_0_pins[] = {
1857         /* KEYOUT7 */
1858         58,
1859 };
1860 static const unsigned int keysc_out7_0_mux[] = {
1861         PORT58_KEYOUT7_MARK,
1862 };
1863 static const unsigned int keysc_out7_1_pins[] = {
1864         /* KEYOUT7 */
1865         132,
1866 };
1867 static const unsigned int keysc_out7_1_mux[] = {
1868         PORT132_KEYOUT7_MARK,
1869 };
1870 static const unsigned int keysc_out7_2_pins[] = {
1871         /* KEYOUT7 */
1872         144,
1873 };
1874 static const unsigned int keysc_out7_2_mux[] = {
1875         PORT144_KEYOUT7_MARK,
1876 };
1877 static const unsigned int keysc_out8_0_pins[] = {
1878         /* KEYOUT8 */
1879         PIN_NUMBER(6, 26),
1880 };
1881 static const unsigned int keysc_out8_0_mux[] = {
1882         KEYOUT8_MARK,
1883 };
1884 static const unsigned int keysc_out8_1_pins[] = {
1885         /* KEYOUT8 */
1886         136,
1887 };
1888 static const unsigned int keysc_out8_1_mux[] = {
1889         PORT136_KEYOUT8_MARK,
1890 };
1891 static const unsigned int keysc_out8_2_pins[] = {
1892         /* KEYOUT8 */
1893         138,
1894 };
1895 static const unsigned int keysc_out8_2_mux[] = {
1896         PORT138_KEYOUT8_MARK,
1897 };
1898 static const unsigned int keysc_out9_0_pins[] = {
1899         /* KEYOUT9 */
1900         137,
1901 };
1902 static const unsigned int keysc_out9_0_mux[] = {
1903         PORT137_KEYOUT9_MARK,
1904 };
1905 static const unsigned int keysc_out9_1_pins[] = {
1906         /* KEYOUT9 */
1907         139,
1908 };
1909 static const unsigned int keysc_out9_1_mux[] = {
1910         PORT139_KEYOUT9_MARK,
1911 };
1912 static const unsigned int keysc_out9_2_pins[] = {
1913         /* KEYOUT9 */
1914         149,
1915 };
1916 static const unsigned int keysc_out9_2_mux[] = {
1917         PORT149_KEYOUT9_MARK,
1918 };
1919 static const unsigned int keysc_out10_0_pins[] = {
1920         /* KEYOUT10 */
1921         132,
1922 };
1923 static const unsigned int keysc_out10_0_mux[] = {
1924         PORT132_KEYOUT10_MARK,
1925 };
1926 static const unsigned int keysc_out10_1_pins[] = {
1927         /* KEYOUT10 */
1928         142,
1929 };
1930 static const unsigned int keysc_out10_1_mux[] = {
1931         PORT142_KEYOUT10_MARK,
1932 };
1933 static const unsigned int keysc_out11_0_pins[] = {
1934         /* KEYOUT11 */
1935         131,
1936 };
1937 static const unsigned int keysc_out11_0_mux[] = {
1938         PORT131_KEYOUT11_MARK,
1939 };
1940 static const unsigned int keysc_out11_1_pins[] = {
1941         /* KEYOUT11 */
1942         143,
1943 };
1944 static const unsigned int keysc_out11_1_mux[] = {
1945         PORT143_KEYOUT11_MARK,
1946 };
1947 /* - LCD -------------------------------------------------------------------- */
1948 static const unsigned int lcd_data8_pins[] = {
1949         /* D[0:7] */
1950         192, 193, 194, 195, 196, 197, 198, 199,
1951 };
1952 static const unsigned int lcd_data8_mux[] = {
1953         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1954         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1955 };
1956 static const unsigned int lcd_data9_pins[] = {
1957         /* D[0:8] */
1958         192, 193, 194, 195, 196, 197, 198, 199,
1959         200,
1960 };
1961 static const unsigned int lcd_data9_mux[] = {
1962         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1963         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1964         LCDD8_MARK,
1965 };
1966 static const unsigned int lcd_data12_pins[] = {
1967         /* D[0:11] */
1968         192, 193, 194, 195, 196, 197, 198, 199,
1969         200, 201, 202, 203,
1970 };
1971 static const unsigned int lcd_data12_mux[] = {
1972         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1973         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1974         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1975 };
1976 static const unsigned int lcd_data16_pins[] = {
1977         /* D[0:15] */
1978         192, 193, 194, 195, 196, 197, 198, 199,
1979         200, 201, 202, 203, 204, 205, 206, 207,
1980 };
1981 static const unsigned int lcd_data16_mux[] = {
1982         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1983         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1984         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1985         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1986 };
1987 static const unsigned int lcd_data18_pins[] = {
1988         /* D[0:17] */
1989         192, 193, 194, 195, 196, 197, 198, 199,
1990         200, 201, 202, 203, 204, 205, 206, 207,
1991         208, 209,
1992 };
1993 static const unsigned int lcd_data18_mux[] = {
1994         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1995         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1996         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1997         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1998         LCDD16_MARK, LCDD17_MARK,
1999 };
2000 static const unsigned int lcd_data24_pins[] = {
2001         /* D[0:23] */
2002         192, 193, 194, 195, 196, 197, 198, 199,
2003         200, 201, 202, 203, 204, 205, 206, 207,
2004         208, 209, 210, 211, 212, 213, 214, 215
2005 };
2006 static const unsigned int lcd_data24_mux[] = {
2007         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2008         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2009         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2010         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2011         LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
2012         LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
2013 };
2014 static const unsigned int lcd_display_pins[] = {
2015         /* DON */
2016         222,
2017 };
2018 static const unsigned int lcd_display_mux[] = {
2019         LCDDON_MARK,
2020 };
2021 static const unsigned int lcd_lclk_pins[] = {
2022         /* LCLK */
2023         221,
2024 };
2025 static const unsigned int lcd_lclk_mux[] = {
2026         LCDLCLK_MARK,
2027 };
2028 static const unsigned int lcd_sync_pins[] = {
2029         /* VSYN, HSYN, DCK, DISP */
2030         220, 218, 216, 219,
2031 };
2032 static const unsigned int lcd_sync_mux[] = {
2033         LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
2034 };
2035 static const unsigned int lcd_sys_pins[] = {
2036         /* CS, WR, RD, RS */
2037         218, 216, 217, 219,
2038 };
2039 static const unsigned int lcd_sys_mux[] = {
2040         LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
2041 };
2042 /* - LCD2 ------------------------------------------------------------------- */
2043 static const unsigned int lcd2_data8_pins[] = {
2044         /* D[0:7] */
2045         128, 129, 142, 143, 144, 145, 138, 139,
2046 };
2047 static const unsigned int lcd2_data8_mux[] = {
2048         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2049         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2050 };
2051 static const unsigned int lcd2_data9_pins[] = {
2052         /* D[0:8] */
2053         128, 129, 142, 143, 144, 145, 138, 139,
2054         140,
2055 };
2056 static const unsigned int lcd2_data9_mux[] = {
2057         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2058         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2059         LCD2D8_MARK,
2060 };
2061 static const unsigned int lcd2_data12_pins[] = {
2062         /* D[0:11] */
2063         128, 129, 142, 143, 144, 145, 138, 139,
2064         140, 141, 130, 131,
2065 };
2066 static const unsigned int lcd2_data12_mux[] = {
2067         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2068         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2069         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2070 };
2071 static const unsigned int lcd2_data16_pins[] = {
2072         /* D[0:15] */
2073         128, 129, 142, 143, 144, 145, 138, 139,
2074         140, 141, 130, 131, 132, 133, 134, 135,
2075 };
2076 static const unsigned int lcd2_data16_mux[] = {
2077         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2078         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2079         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2080         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2081 };
2082 static const unsigned int lcd2_data18_pins[] = {
2083         /* D[0:17] */
2084         128, 129, 142, 143, 144, 145, 138, 139,
2085         140, 141, 130, 131, 132, 133, 134, 135,
2086         136, 137,
2087 };
2088 static const unsigned int lcd2_data18_mux[] = {
2089         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2090         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2091         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2092         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2093         LCD2D16_MARK, LCD2D17_MARK,
2094 };
2095 static const unsigned int lcd2_data24_pins[] = {
2096         /* D[0:23] */
2097         128, 129, 142, 143, 144, 145, 138, 139,
2098         140, 141, 130, 131, 132, 133, 134, 135,
2099         136, 137, 146, 147, 234, 235, 238, 239
2100 };
2101 static const unsigned int lcd2_data24_mux[] = {
2102         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2103         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2104         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2105         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2106         LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
2107         LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
2108 };
2109 static const unsigned int lcd2_sync_0_pins[] = {
2110         /* VSYN, HSYN, DCK, DISP */
2111         128, 129, 146, 145,
2112 };
2113 static const unsigned int lcd2_sync_0_mux[] = {
2114         PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
2115         LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
2116 };
2117 static const unsigned int lcd2_sync_1_pins[] = {
2118         /* VSYN, HSYN, DCK, DISP */
2119         222, 221, 219, 217,
2120 };
2121 static const unsigned int lcd2_sync_1_mux[] = {
2122         PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
2123         LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
2124 };
2125 static const unsigned int lcd2_sys_0_pins[] = {
2126         /* CS, WR, RD, RS */
2127         129, 146, 147, 145,
2128 };
2129 static const unsigned int lcd2_sys_0_mux[] = {
2130         PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
2131         LCD2RD__MARK, PORT145_LCD2RS_MARK,
2132 };
2133 static const unsigned int lcd2_sys_1_pins[] = {
2134         /* CS, WR, RD, RS */
2135         221, 219, 147, 217,
2136 };
2137 static const unsigned int lcd2_sys_1_mux[] = {
2138         PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
2139         LCD2RD__MARK, PORT217_LCD2RS_MARK,
2140 };
2141 /* - MMCIF ------------------------------------------------------------------ */
2142 static const unsigned int mmc0_data1_0_pins[] = {
2143         /* D[0] */
2144         271,
2145 };
2146 static const unsigned int mmc0_data1_0_mux[] = {
2147         MMCD0_0_MARK,
2148 };
2149 static const unsigned int mmc0_data4_0_pins[] = {
2150         /* D[0:3] */
2151         271, 272, 273, 274,
2152 };
2153 static const unsigned int mmc0_data4_0_mux[] = {
2154         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2155 };
2156 static const unsigned int mmc0_data8_0_pins[] = {
2157         /* D[0:7] */
2158         271, 272, 273, 274, 275, 276, 277, 278,
2159 };
2160 static const unsigned int mmc0_data8_0_mux[] = {
2161         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2162         MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
2163 };
2164 static const unsigned int mmc0_ctrl_0_pins[] = {
2165         /* CMD, CLK */
2166         279, 270,
2167 };
2168 static const unsigned int mmc0_ctrl_0_mux[] = {
2169         MMCCMD0_MARK, MMCCLK0_MARK,
2170 };
2171
2172 static const unsigned int mmc0_data1_1_pins[] = {
2173         /* D[0] */
2174         305,
2175 };
2176 static const unsigned int mmc0_data1_1_mux[] = {
2177         MMCD1_0_MARK,
2178 };
2179 static const unsigned int mmc0_data4_1_pins[] = {
2180         /* D[0:3] */
2181         305, 304, 303, 302,
2182 };
2183 static const unsigned int mmc0_data4_1_mux[] = {
2184         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2185 };
2186 static const unsigned int mmc0_data8_1_pins[] = {
2187         /* D[0:7] */
2188         305, 304, 303, 302, 301, 300, 299, 298,
2189 };
2190 static const unsigned int mmc0_data8_1_mux[] = {
2191         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2192         MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
2193 };
2194 static const unsigned int mmc0_ctrl_1_pins[] = {
2195         /* CMD, CLK */
2196         297, 289,
2197 };
2198 static const unsigned int mmc0_ctrl_1_mux[] = {
2199         MMCCMD1_MARK, MMCCLK1_MARK,
2200 };
2201 /* - MSIOF0 ----------------------------------------------------------------- */
2202 static const unsigned int msiof0_rsck_pins[] = {
2203         /* RSCK */
2204         66,
2205 };
2206 static const unsigned int msiof0_rsck_mux[] = {
2207         MSIOF0_RSCK_MARK,
2208 };
2209 static const unsigned int msiof0_tsck_pins[] = {
2210         /* TSCK */
2211         64,
2212 };
2213 static const unsigned int msiof0_tsck_mux[] = {
2214         MSIOF0_TSCK_MARK,
2215 };
2216 static const unsigned int msiof0_rsync_pins[] = {
2217         /* RSYNC */
2218         67,
2219 };
2220 static const unsigned int msiof0_rsync_mux[] = {
2221         MSIOF0_RSYNC_MARK,
2222 };
2223 static const unsigned int msiof0_tsync_pins[] = {
2224         /* TSYNC */
2225         63,
2226 };
2227 static const unsigned int msiof0_tsync_mux[] = {
2228         MSIOF0_TSYNC_MARK,
2229 };
2230 static const unsigned int msiof0_ss1_pins[] = {
2231         /* SS1 */
2232         62,
2233 };
2234 static const unsigned int msiof0_ss1_mux[] = {
2235         MSIOF0_SS1_MARK,
2236 };
2237 static const unsigned int msiof0_ss2_pins[] = {
2238         /* SS2 */
2239         71,
2240 };
2241 static const unsigned int msiof0_ss2_mux[] = {
2242         MSIOF0_SS2_MARK,
2243 };
2244 static const unsigned int msiof0_rxd_pins[] = {
2245         /* RXD */
2246         70,
2247 };
2248 static const unsigned int msiof0_rxd_mux[] = {
2249         MSIOF0_RXD_MARK,
2250 };
2251 static const unsigned int msiof0_txd_pins[] = {
2252         /* TXD */
2253         65,
2254 };
2255 static const unsigned int msiof0_txd_mux[] = {
2256         MSIOF0_TXD_MARK,
2257 };
2258 static const unsigned int msiof0_mck0_pins[] = {
2259         /* MSCK0 */
2260         68,
2261 };
2262 static const unsigned int msiof0_mck0_mux[] = {
2263         MSIOF0_MCK0_MARK,
2264 };
2265
2266 static const unsigned int msiof0_mck1_pins[] = {
2267         /* MSCK1 */
2268         69,
2269 };
2270 static const unsigned int msiof0_mck1_mux[] = {
2271         MSIOF0_MCK1_MARK,
2272 };
2273
2274 static const unsigned int msiof0l_rsck_pins[] = {
2275         /* RSCK */
2276         214,
2277 };
2278 static const unsigned int msiof0l_rsck_mux[] = {
2279         MSIOF0L_RSCK_MARK,
2280 };
2281 static const unsigned int msiof0l_tsck_pins[] = {
2282         /* TSCK */
2283         219,
2284 };
2285 static const unsigned int msiof0l_tsck_mux[] = {
2286         MSIOF0L_TSCK_MARK,
2287 };
2288 static const unsigned int msiof0l_rsync_pins[] = {
2289         /* RSYNC */
2290         215,
2291 };
2292 static const unsigned int msiof0l_rsync_mux[] = {
2293         MSIOF0L_RSYNC_MARK,
2294 };
2295 static const unsigned int msiof0l_tsync_pins[] = {
2296         /* TSYNC */
2297         217,
2298 };
2299 static const unsigned int msiof0l_tsync_mux[] = {
2300         MSIOF0L_TSYNC_MARK,
2301 };
2302 static const unsigned int msiof0l_ss1_a_pins[] = {
2303         /* SS1 */
2304         207,
2305 };
2306 static const unsigned int msiof0l_ss1_a_mux[] = {
2307         PORT207_MSIOF0L_SS1_MARK,
2308 };
2309 static const unsigned int msiof0l_ss1_b_pins[] = {
2310         /* SS1 */
2311         210,
2312 };
2313 static const unsigned int msiof0l_ss1_b_mux[] = {
2314         PORT210_MSIOF0L_SS1_MARK,
2315 };
2316 static const unsigned int msiof0l_ss2_a_pins[] = {
2317         /* SS2 */
2318         208,
2319 };
2320 static const unsigned int msiof0l_ss2_a_mux[] = {
2321         PORT208_MSIOF0L_SS2_MARK,
2322 };
2323 static const unsigned int msiof0l_ss2_b_pins[] = {
2324         /* SS2 */
2325         211,
2326 };
2327 static const unsigned int msiof0l_ss2_b_mux[] = {
2328         PORT211_MSIOF0L_SS2_MARK,
2329 };
2330 static const unsigned int msiof0l_rxd_pins[] = {
2331         /* RXD */
2332         221,
2333 };
2334 static const unsigned int msiof0l_rxd_mux[] = {
2335         MSIOF0L_RXD_MARK,
2336 };
2337 static const unsigned int msiof0l_txd_pins[] = {
2338         /* TXD */
2339         222,
2340 };
2341 static const unsigned int msiof0l_txd_mux[] = {
2342         MSIOF0L_TXD_MARK,
2343 };
2344 static const unsigned int msiof0l_mck0_pins[] = {
2345         /* MSCK0 */
2346         212,
2347 };
2348 static const unsigned int msiof0l_mck0_mux[] = {
2349         MSIOF0L_MCK0_MARK,
2350 };
2351 static const unsigned int msiof0l_mck1_pins[] = {
2352         /* MSCK1 */
2353         213,
2354 };
2355 static const unsigned int msiof0l_mck1_mux[] = {
2356         MSIOF0L_MCK1_MARK,
2357 };
2358 /* - MSIOF1 ----------------------------------------------------------------- */
2359 static const unsigned int msiof1_rsck_pins[] = {
2360         /* RSCK */
2361         234,
2362 };
2363 static const unsigned int msiof1_rsck_mux[] = {
2364         MSIOF1_RSCK_MARK,
2365 };
2366 static const unsigned int msiof1_tsck_pins[] = {
2367         /* TSCK */
2368         232,
2369 };
2370 static const unsigned int msiof1_tsck_mux[] = {
2371         MSIOF1_TSCK_MARK,
2372 };
2373 static const unsigned int msiof1_rsync_pins[] = {
2374         /* RSYNC */
2375         235,
2376 };
2377 static const unsigned int msiof1_rsync_mux[] = {
2378         MSIOF1_RSYNC_MARK,
2379 };
2380 static const unsigned int msiof1_tsync_pins[] = {
2381         /* TSYNC */
2382         231,
2383 };
2384 static const unsigned int msiof1_tsync_mux[] = {
2385         MSIOF1_TSYNC_MARK,
2386 };
2387 static const unsigned int msiof1_ss1_pins[] = {
2388         /* SS1 */
2389         238,
2390 };
2391 static const unsigned int msiof1_ss1_mux[] = {
2392         MSIOF1_SS1_MARK,
2393 };
2394 static const unsigned int msiof1_ss2_pins[] = {
2395         /* SS2 */
2396         239,
2397 };
2398 static const unsigned int msiof1_ss2_mux[] = {
2399         MSIOF1_SS2_MARK,
2400 };
2401 static const unsigned int msiof1_rxd_pins[] = {
2402         /* RXD */
2403         233,
2404 };
2405 static const unsigned int msiof1_rxd_mux[] = {
2406         MSIOF1_RXD_MARK,
2407 };
2408 static const unsigned int msiof1_txd_pins[] = {
2409         /* TXD */
2410         230,
2411 };
2412 static const unsigned int msiof1_txd_mux[] = {
2413         MSIOF1_TXD_MARK,
2414 };
2415 static const unsigned int msiof1_mck0_pins[] = {
2416         /* MSCK0 */
2417         236,
2418 };
2419 static const unsigned int msiof1_mck0_mux[] = {
2420         MSIOF1_MCK0_MARK,
2421 };
2422 static const unsigned int msiof1_mck1_pins[] = {
2423         /* MSCK1 */
2424         237,
2425 };
2426 static const unsigned int msiof1_mck1_mux[] = {
2427         MSIOF1_MCK1_MARK,
2428 };
2429 /* - MSIOF2 ----------------------------------------------------------------- */
2430 static const unsigned int msiof2_rsck_pins[] = {
2431         /* RSCK */
2432         151,
2433 };
2434 static const unsigned int msiof2_rsck_mux[] = {
2435         MSIOF2_RSCK_MARK,
2436 };
2437 static const unsigned int msiof2_tsck_pins[] = {
2438         /* TSCK */
2439         135,
2440 };
2441 static const unsigned int msiof2_tsck_mux[] = {
2442         MSIOF2_TSCK_MARK,
2443 };
2444 static const unsigned int msiof2_rsync_pins[] = {
2445         /* RSYNC */
2446         152,
2447 };
2448 static const unsigned int msiof2_rsync_mux[] = {
2449         MSIOF2_RSYNC_MARK,
2450 };
2451 static const unsigned int msiof2_tsync_pins[] = {
2452         /* TSYNC */
2453         133,
2454 };
2455 static const unsigned int msiof2_tsync_mux[] = {
2456         MSIOF2_TSYNC_MARK,
2457 };
2458 static const unsigned int msiof2_ss1_a_pins[] = {
2459         /* SS1 */
2460         131,
2461 };
2462 static const unsigned int msiof2_ss1_a_mux[] = {
2463         PORT131_MSIOF2_SS1_MARK,
2464 };
2465 static const unsigned int msiof2_ss1_b_pins[] = {
2466         /* SS1 */
2467         153,
2468 };
2469 static const unsigned int msiof2_ss1_b_mux[] = {
2470         PORT153_MSIOF2_SS1_MARK,
2471 };
2472 static const unsigned int msiof2_ss2_a_pins[] = {
2473         /* SS2 */
2474         132,
2475 };
2476 static const unsigned int msiof2_ss2_a_mux[] = {
2477         PORT132_MSIOF2_SS2_MARK,
2478 };
2479 static const unsigned int msiof2_ss2_b_pins[] = {
2480         /* SS2 */
2481         156,
2482 };
2483 static const unsigned int msiof2_ss2_b_mux[] = {
2484         PORT156_MSIOF2_SS2_MARK,
2485 };
2486 static const unsigned int msiof2_rxd_a_pins[] = {
2487         /* RXD */
2488         130,
2489 };
2490 static const unsigned int msiof2_rxd_a_mux[] = {
2491         PORT130_MSIOF2_RXD_MARK,
2492 };
2493 static const unsigned int msiof2_rxd_b_pins[] = {
2494         /* RXD */
2495         157,
2496 };
2497 static const unsigned int msiof2_rxd_b_mux[] = {
2498         PORT157_MSIOF2_RXD_MARK,
2499 };
2500 static const unsigned int msiof2_txd_pins[] = {
2501         /* TXD */
2502         134,
2503 };
2504 static const unsigned int msiof2_txd_mux[] = {
2505         MSIOF2_TXD_MARK,
2506 };
2507 static const unsigned int msiof2_mck0_pins[] = {
2508         /* MSCK0 */
2509         154,
2510 };
2511 static const unsigned int msiof2_mck0_mux[] = {
2512         MSIOF2_MCK0_MARK,
2513 };
2514 static const unsigned int msiof2_mck1_pins[] = {
2515         /* MSCK1 */
2516         155,
2517 };
2518 static const unsigned int msiof2_mck1_mux[] = {
2519         MSIOF2_MCK1_MARK,
2520 };
2521
2522 static const unsigned int msiof2r_tsck_pins[] = {
2523         /* TSCK */
2524         248,
2525 };
2526 static const unsigned int msiof2r_tsck_mux[] = {
2527         MSIOF2R_TSCK_MARK,
2528 };
2529 static const unsigned int msiof2r_tsync_pins[] = {
2530         /* TSYNC */
2531         249,
2532 };
2533 static const unsigned int msiof2r_tsync_mux[] = {
2534         MSIOF2R_TSYNC_MARK,
2535 };
2536 static const unsigned int msiof2r_rxd_pins[] = {
2537         /* RXD */
2538         244,
2539 };
2540 static const unsigned int msiof2r_rxd_mux[] = {
2541         MSIOF2R_RXD_MARK,
2542 };
2543 static const unsigned int msiof2r_txd_pins[] = {
2544         /* TXD */
2545         245,
2546 };
2547 static const unsigned int msiof2r_txd_mux[] = {
2548         MSIOF2R_TXD_MARK,
2549 };
2550 /* - MSIOF3 (Pin function name of MSIOF3 is named BBIF1) -------------------- */
2551 static const unsigned int msiof3_rsck_pins[] = {
2552         /* RSCK */
2553         115,
2554 };
2555 static const unsigned int msiof3_rsck_mux[] = {
2556         BBIF1_RSCK_MARK,
2557 };
2558 static const unsigned int msiof3_tsck_pins[] = {
2559         /* TSCK */
2560         112,
2561 };
2562 static const unsigned int msiof3_tsck_mux[] = {
2563         BBIF1_TSCK_MARK,
2564 };
2565 static const unsigned int msiof3_rsync_pins[] = {
2566         /* RSYNC */
2567         116,
2568 };
2569 static const unsigned int msiof3_rsync_mux[] = {
2570         BBIF1_RSYNC_MARK,
2571 };
2572 static const unsigned int msiof3_tsync_pins[] = {
2573         /* TSYNC */
2574         113,
2575 };
2576 static const unsigned int msiof3_tsync_mux[] = {
2577         BBIF1_TSYNC_MARK,
2578 };
2579 static const unsigned int msiof3_ss1_pins[] = {
2580         /* SS1 */
2581         117,
2582 };
2583 static const unsigned int msiof3_ss1_mux[] = {
2584         BBIF1_SS1_MARK,
2585 };
2586 static const unsigned int msiof3_ss2_pins[] = {
2587         /* SS2 */
2588         109,
2589 };
2590 static const unsigned int msiof3_ss2_mux[] = {
2591         BBIF1_SS2_MARK,
2592 };
2593 static const unsigned int msiof3_rxd_pins[] = {
2594         /* RXD */
2595         111,
2596 };
2597 static const unsigned int msiof3_rxd_mux[] = {
2598         BBIF1_RXD_MARK,
2599 };
2600 static const unsigned int msiof3_txd_pins[] = {
2601         /* TXD */
2602         114,
2603 };
2604 static const unsigned int msiof3_txd_mux[] = {
2605         BBIF1_TXD_MARK,
2606 };
2607 static const unsigned int msiof3_flow_pins[] = {
2608         /* FLOW */
2609         117,
2610 };
2611 static const unsigned int msiof3_flow_mux[] = {
2612         BBIF1_FLOW_MARK,
2613 };
2614
2615 /* - SCIFA0 ----------------------------------------------------------------- */
2616 static const unsigned int scifa0_data_pins[] = {
2617         /* RXD, TXD */
2618         43, 17,
2619 };
2620 static const unsigned int scifa0_data_mux[] = {
2621         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2622 };
2623 static const unsigned int scifa0_clk_pins[] = {
2624         /* SCK */
2625         16,
2626 };
2627 static const unsigned int scifa0_clk_mux[] = {
2628         SCIFA0_SCK_MARK,
2629 };
2630 static const unsigned int scifa0_ctrl_pins[] = {
2631         /* RTS, CTS */
2632         42, 44,
2633 };
2634 static const unsigned int scifa0_ctrl_mux[] = {
2635         SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
2636 };
2637 /* - SCIFA1 ----------------------------------------------------------------- */
2638 static const unsigned int scifa1_data_pins[] = {
2639         /* RXD, TXD */
2640         228, 225,
2641 };
2642 static const unsigned int scifa1_data_mux[] = {
2643         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2644 };
2645 static const unsigned int scifa1_clk_pins[] = {
2646         /* SCK */
2647         226,
2648 };
2649 static const unsigned int scifa1_clk_mux[] = {
2650         SCIFA1_SCK_MARK,
2651 };
2652 static const unsigned int scifa1_ctrl_pins[] = {
2653         /* RTS, CTS */
2654         227, 229,
2655 };
2656 static const unsigned int scifa1_ctrl_mux[] = {
2657         SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
2658 };
2659 /* - SCIFA2 ----------------------------------------------------------------- */
2660 static const unsigned int scifa2_data_0_pins[] = {
2661         /* RXD, TXD */
2662         155, 154,
2663 };
2664 static const unsigned int scifa2_data_0_mux[] = {
2665         SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
2666 };
2667 static const unsigned int scifa2_clk_0_pins[] = {
2668         /* SCK */
2669         158,
2670 };
2671 static const unsigned int scifa2_clk_0_mux[] = {
2672         SCIFA2_SCK1_MARK,
2673 };
2674 static const unsigned int scifa2_ctrl_0_pins[] = {
2675         /* RTS, CTS */
2676         156, 157,
2677 };
2678 static const unsigned int scifa2_ctrl_0_mux[] = {
2679         SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
2680 };
2681 static const unsigned int scifa2_data_1_pins[] = {
2682         /* RXD, TXD */
2683         233, 230,
2684 };
2685 static const unsigned int scifa2_data_1_mux[] = {
2686         SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
2687 };
2688 static const unsigned int scifa2_clk_1_pins[] = {
2689         /* SCK */
2690         232,
2691 };
2692 static const unsigned int scifa2_clk_1_mux[] = {
2693         SCIFA2_SCK2_MARK,
2694 };
2695 static const unsigned int scifa2_ctrl_1_pins[] = {
2696         /* RTS, CTS */
2697         234, 231,
2698 };
2699 static const unsigned int scifa2_ctrl_1_mux[] = {
2700         SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
2701 };
2702 /* - SCIFA3 ----------------------------------------------------------------- */
2703 static const unsigned int scifa3_data_pins[] = {
2704         /* RXD, TXD */
2705         108, 110,
2706 };
2707 static const unsigned int scifa3_data_mux[] = {
2708         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2709 };
2710 static const unsigned int scifa3_ctrl_pins[] = {
2711         /* RTS, CTS */
2712         109, 107,
2713 };
2714 static const unsigned int scifa3_ctrl_mux[] = {
2715         SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
2716 };
2717 /* - SCIFA4 ----------------------------------------------------------------- */
2718 static const unsigned int scifa4_data_pins[] = {
2719         /* RXD, TXD */
2720         33, 32,
2721 };
2722 static const unsigned int scifa4_data_mux[] = {
2723         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2724 };
2725 static const unsigned int scifa4_ctrl_pins[] = {
2726         /* RTS, CTS */
2727         34, 35,
2728 };
2729 static const unsigned int scifa4_ctrl_mux[] = {
2730         SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
2731 };
2732 /* - SCIFA5 ----------------------------------------------------------------- */
2733 static const unsigned int scifa5_data_0_pins[] = {
2734         /* RXD, TXD */
2735         246, 247,
2736 };
2737 static const unsigned int scifa5_data_0_mux[] = {
2738         PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
2739 };
2740 static const unsigned int scifa5_clk_0_pins[] = {
2741         /* SCK */
2742         248,
2743 };
2744 static const unsigned int scifa5_clk_0_mux[] = {
2745         PORT248_SCIFA5_SCK_MARK,
2746 };
2747 static const unsigned int scifa5_ctrl_0_pins[] = {
2748         /* RTS, CTS */
2749         245, 244,
2750 };
2751 static const unsigned int scifa5_ctrl_0_mux[] = {
2752         PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
2753 };
2754 static const unsigned int scifa5_data_1_pins[] = {
2755         /* RXD, TXD */
2756         195, 196,
2757 };
2758 static const unsigned int scifa5_data_1_mux[] = {
2759         PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
2760 };
2761 static const unsigned int scifa5_clk_1_pins[] = {
2762         /* SCK */
2763         197,
2764 };
2765 static const unsigned int scifa5_clk_1_mux[] = {
2766         PORT197_SCIFA5_SCK_MARK,
2767 };
2768 static const unsigned int scifa5_ctrl_1_pins[] = {
2769         /* RTS, CTS */
2770         194, 193,
2771 };
2772 static const unsigned int scifa5_ctrl_1_mux[] = {
2773         PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
2774 };
2775 static const unsigned int scifa5_data_2_pins[] = {
2776         /* RXD, TXD */
2777         162, 160,
2778 };
2779 static const unsigned int scifa5_data_2_mux[] = {
2780         PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
2781 };
2782 static const unsigned int scifa5_clk_2_pins[] = {
2783         /* SCK */
2784         159,
2785 };
2786 static const unsigned int scifa5_clk_2_mux[] = {
2787         PORT159_SCIFA5_SCK_MARK,
2788 };
2789 static const unsigned int scifa5_ctrl_2_pins[] = {
2790         /* RTS, CTS */
2791         163, 161,
2792 };
2793 static const unsigned int scifa5_ctrl_2_mux[] = {
2794         PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
2795 };
2796 /* - SCIFA6 ----------------------------------------------------------------- */
2797 static const unsigned int scifa6_pins[] = {
2798         /* TXD */
2799         240,
2800 };
2801 static const unsigned int scifa6_mux[] = {
2802         SCIFA6_TXD_MARK,
2803 };
2804 /* - SCIFA7 ----------------------------------------------------------------- */
2805 static const unsigned int scifa7_data_pins[] = {
2806         /* RXD, TXD */
2807         12, 18,
2808 };
2809 static const unsigned int scifa7_data_mux[] = {
2810         SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2811 };
2812 static const unsigned int scifa7_ctrl_pins[] = {
2813         /* RTS, CTS */
2814         19, 13,
2815 };
2816 static const unsigned int scifa7_ctrl_mux[] = {
2817         SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
2818 };
2819 /* - SCIFB ------------------------------------------------------------------ */
2820 static const unsigned int scifb_data_0_pins[] = {
2821         /* RXD, TXD */
2822         162, 160,
2823 };
2824 static const unsigned int scifb_data_0_mux[] = {
2825         PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
2826 };
2827 static const unsigned int scifb_clk_0_pins[] = {
2828         /* SCK */
2829         159,
2830 };
2831 static const unsigned int scifb_clk_0_mux[] = {
2832         PORT159_SCIFB_SCK_MARK,
2833 };
2834 static const unsigned int scifb_ctrl_0_pins[] = {
2835         /* RTS, CTS */
2836         163, 161,
2837 };
2838 static const unsigned int scifb_ctrl_0_mux[] = {
2839         PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
2840 };
2841 static const unsigned int scifb_data_1_pins[] = {
2842         /* RXD, TXD */
2843         246, 247,
2844 };
2845 static const unsigned int scifb_data_1_mux[] = {
2846         PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
2847 };
2848 static const unsigned int scifb_clk_1_pins[] = {
2849         /* SCK */
2850         248,
2851 };
2852 static const unsigned int scifb_clk_1_mux[] = {
2853         PORT248_SCIFB_SCK_MARK,
2854 };
2855 static const unsigned int scifb_ctrl_1_pins[] = {
2856         /* RTS, CTS */
2857         245, 244,
2858 };
2859 static const unsigned int scifb_ctrl_1_mux[] = {
2860         PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
2861 };
2862 /* - SDHI0 ------------------------------------------------------------------ */
2863 static const unsigned int sdhi0_data1_pins[] = {
2864         /* D0 */
2865         252,
2866 };
2867 static const unsigned int sdhi0_data1_mux[] = {
2868         SDHID0_0_MARK,
2869 };
2870 static const unsigned int sdhi0_data4_pins[] = {
2871         /* D[0:3] */
2872         252, 253, 254, 255,
2873 };
2874 static const unsigned int sdhi0_data4_mux[] = {
2875         SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
2876 };
2877 static const unsigned int sdhi0_ctrl_pins[] = {
2878         /* CMD, CLK */
2879         256, 250,
2880 };
2881 static const unsigned int sdhi0_ctrl_mux[] = {
2882         SDHICMD0_MARK, SDHICLK0_MARK,
2883 };
2884 static const unsigned int sdhi0_cd_pins[] = {
2885         /* CD */
2886         251,
2887 };
2888 static const unsigned int sdhi0_cd_mux[] = {
2889         SDHICD0_MARK,
2890 };
2891 static const unsigned int sdhi0_wp_pins[] = {
2892         /* WP */
2893         257,
2894 };
2895 static const unsigned int sdhi0_wp_mux[] = {
2896         SDHIWP0_MARK,
2897 };
2898 /* - SDHI1 ------------------------------------------------------------------ */
2899 static const unsigned int sdhi1_data1_pins[] = {
2900         /* D0 */
2901         259,
2902 };
2903 static const unsigned int sdhi1_data1_mux[] = {
2904         SDHID1_0_MARK,
2905 };
2906 static const unsigned int sdhi1_data4_pins[] = {
2907         /* D[0:3] */
2908         259, 260, 261, 262,
2909 };
2910 static const unsigned int sdhi1_data4_mux[] = {
2911         SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
2912 };
2913 static const unsigned int sdhi1_ctrl_pins[] = {
2914         /* CMD, CLK */
2915         263, 258,
2916 };
2917 static const unsigned int sdhi1_ctrl_mux[] = {
2918         SDHICMD1_MARK, SDHICLK1_MARK,
2919 };
2920 /* - SDHI2 ------------------------------------------------------------------ */
2921 static const unsigned int sdhi2_data1_pins[] = {
2922         /* D0 */
2923         265,
2924 };
2925 static const unsigned int sdhi2_data1_mux[] = {
2926         SDHID2_0_MARK,
2927 };
2928 static const unsigned int sdhi2_data4_pins[] = {
2929         /* D[0:3] */
2930         265, 266, 267, 268,
2931 };
2932 static const unsigned int sdhi2_data4_mux[] = {
2933         SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
2934 };
2935 static const unsigned int sdhi2_ctrl_pins[] = {
2936         /* CMD, CLK */
2937         269, 264,
2938 };
2939 static const unsigned int sdhi2_ctrl_mux[] = {
2940         SDHICMD2_MARK, SDHICLK2_MARK,
2941 };
2942 /* - TPU0 ------------------------------------------------------------------- */
2943 static const unsigned int tpu0_to0_pins[] = {
2944         /* TO */
2945         55,
2946 };
2947 static const unsigned int tpu0_to0_mux[] = {
2948         TPU0TO0_MARK,
2949 };
2950 static const unsigned int tpu0_to1_pins[] = {
2951         /* TO */
2952         59,
2953 };
2954 static const unsigned int tpu0_to1_mux[] = {
2955         TPU0TO1_MARK,
2956 };
2957 static const unsigned int tpu0_to2_pins[] = {
2958         /* TO */
2959         140,
2960 };
2961 static const unsigned int tpu0_to2_mux[] = {
2962         TPU0TO2_MARK,
2963 };
2964 static const unsigned int tpu0_to3_pins[] = {
2965         /* TO */
2966         141,
2967 };
2968 static const unsigned int tpu0_to3_mux[] = {
2969         TPU0TO3_MARK,
2970 };
2971 /* - TPU1 ------------------------------------------------------------------- */
2972 static const unsigned int tpu1_to0_pins[] = {
2973         /* TO */
2974         246,
2975 };
2976 static const unsigned int tpu1_to0_mux[] = {
2977         TPU1TO0_MARK,
2978 };
2979 static const unsigned int tpu1_to1_0_pins[] = {
2980         /* TO */
2981         28,
2982 };
2983 static const unsigned int tpu1_to1_0_mux[] = {
2984         PORT28_TPU1TO1_MARK,
2985 };
2986 static const unsigned int tpu1_to1_1_pins[] = {
2987         /* TO */
2988         29,
2989 };
2990 static const unsigned int tpu1_to1_1_mux[] = {
2991         PORT29_TPU1TO1_MARK,
2992 };
2993 static const unsigned int tpu1_to2_pins[] = {
2994         /* TO */
2995         153,
2996 };
2997 static const unsigned int tpu1_to2_mux[] = {
2998         TPU1TO2_MARK,
2999 };
3000 static const unsigned int tpu1_to3_pins[] = {
3001         /* TO */
3002         145,
3003 };
3004 static const unsigned int tpu1_to3_mux[] = {
3005         TPU1TO3_MARK,
3006 };
3007 /* - TPU2 ------------------------------------------------------------------- */
3008 static const unsigned int tpu2_to0_pins[] = {
3009         /* TO */
3010         248,
3011 };
3012 static const unsigned int tpu2_to0_mux[] = {
3013         TPU2TO0_MARK,
3014 };
3015 static const unsigned int tpu2_to1_pins[] = {
3016         /* TO */
3017         197,
3018 };
3019 static const unsigned int tpu2_to1_mux[] = {
3020         TPU2TO1_MARK,
3021 };
3022 static const unsigned int tpu2_to2_pins[] = {
3023         /* TO */
3024         50,
3025 };
3026 static const unsigned int tpu2_to2_mux[] = {
3027         TPU2TO2_MARK,
3028 };
3029 static const unsigned int tpu2_to3_pins[] = {
3030         /* TO */
3031         51,
3032 };
3033 static const unsigned int tpu2_to3_mux[] = {
3034         TPU2TO3_MARK,
3035 };
3036 /* - TPU3 ------------------------------------------------------------------- */
3037 static const unsigned int tpu3_to0_pins[] = {
3038         /* TO */
3039         163,
3040 };
3041 static const unsigned int tpu3_to0_mux[] = {
3042         TPU3TO0_MARK,
3043 };
3044 static const unsigned int tpu3_to1_pins[] = {
3045         /* TO */
3046         247,
3047 };
3048 static const unsigned int tpu3_to1_mux[] = {
3049         TPU3TO1_MARK,
3050 };
3051 static const unsigned int tpu3_to2_pins[] = {
3052         /* TO */
3053         54,
3054 };
3055 static const unsigned int tpu3_to2_mux[] = {
3056         TPU3TO2_MARK,
3057 };
3058 static const unsigned int tpu3_to3_pins[] = {
3059         /* TO */
3060         53,
3061 };
3062 static const unsigned int tpu3_to3_mux[] = {
3063         TPU3TO3_MARK,
3064 };
3065 /* - TPU4 ------------------------------------------------------------------- */
3066 static const unsigned int tpu4_to0_pins[] = {
3067         /* TO */
3068         241,
3069 };
3070 static const unsigned int tpu4_to0_mux[] = {
3071         TPU4TO0_MARK,
3072 };
3073 static const unsigned int tpu4_to1_pins[] = {
3074         /* TO */
3075         199,
3076 };
3077 static const unsigned int tpu4_to1_mux[] = {
3078         TPU4TO1_MARK,
3079 };
3080 static const unsigned int tpu4_to2_pins[] = {
3081         /* TO */
3082         58,
3083 };
3084 static const unsigned int tpu4_to2_mux[] = {
3085         TPU4TO2_MARK,
3086 };
3087 static const unsigned int tpu4_to3_pins[] = {
3088         /* TO */
3089         PIN_NUMBER(6, 26),
3090 };
3091 static const unsigned int tpu4_to3_mux[] = {
3092         TPU4TO3_MARK,
3093 };
3094 /* - USB -------------------------------------------------------------------- */
3095 static const unsigned int usb_vbus_pins[] = {
3096         /* VBUS */
3097         0,
3098 };
3099 static const unsigned int usb_vbus_mux[] = {
3100         VBUS_0_MARK,
3101 };
3102
3103 static const struct sh_pfc_pin_group pinmux_groups[] = {
3104         SH_PFC_PIN_GROUP(bsc_data_0_7),
3105         SH_PFC_PIN_GROUP(bsc_data_8_15),
3106         SH_PFC_PIN_GROUP(bsc_cs4),
3107         SH_PFC_PIN_GROUP(bsc_cs5_a),
3108         SH_PFC_PIN_GROUP(bsc_cs5_b),
3109         SH_PFC_PIN_GROUP(bsc_cs6_a),
3110         SH_PFC_PIN_GROUP(bsc_cs6_b),
3111         SH_PFC_PIN_GROUP(bsc_rd),
3112         SH_PFC_PIN_GROUP(bsc_rdwr_0),
3113         SH_PFC_PIN_GROUP(bsc_rdwr_1),
3114         SH_PFC_PIN_GROUP(bsc_rdwr_2),
3115         SH_PFC_PIN_GROUP(bsc_we0),
3116         SH_PFC_PIN_GROUP(bsc_we1),
3117         SH_PFC_PIN_GROUP(fsia_mclk_in),
3118         SH_PFC_PIN_GROUP(fsia_mclk_out),
3119         SH_PFC_PIN_GROUP(fsia_sclk_in),
3120         SH_PFC_PIN_GROUP(fsia_sclk_out),
3121         SH_PFC_PIN_GROUP(fsia_data_in),
3122         SH_PFC_PIN_GROUP(fsia_data_out),
3123         SH_PFC_PIN_GROUP(fsia_spdif),
3124         SH_PFC_PIN_GROUP(fsib_mclk_in),
3125         SH_PFC_PIN_GROUP(fsib_mclk_out),
3126         SH_PFC_PIN_GROUP(fsib_sclk_in),
3127         SH_PFC_PIN_GROUP(fsib_sclk_out),
3128         SH_PFC_PIN_GROUP(fsib_data_in),
3129         SH_PFC_PIN_GROUP(fsib_data_out),
3130         SH_PFC_PIN_GROUP(fsib_spdif),
3131         SH_PFC_PIN_GROUP(fsic_mclk_in),
3132         SH_PFC_PIN_GROUP(fsic_mclk_out),
3133         SH_PFC_PIN_GROUP(fsic_sclk_in),
3134         SH_PFC_PIN_GROUP(fsic_sclk_out),
3135         SH_PFC_PIN_GROUP(fsic_data_in),
3136         SH_PFC_PIN_GROUP(fsic_data_out),
3137         SH_PFC_PIN_GROUP(fsic_spdif_0),
3138         SH_PFC_PIN_GROUP(fsic_spdif_1),
3139         SH_PFC_PIN_GROUP(fsid_sclk_in),
3140         SH_PFC_PIN_GROUP(fsid_sclk_out),
3141         SH_PFC_PIN_GROUP(fsid_data_in),
3142         SH_PFC_PIN_GROUP(i2c2_0),
3143         SH_PFC_PIN_GROUP(i2c2_1),
3144         SH_PFC_PIN_GROUP(i2c2_2),
3145         SH_PFC_PIN_GROUP(i2c3_0),
3146         SH_PFC_PIN_GROUP(i2c3_1),
3147         SH_PFC_PIN_GROUP(i2c3_2),
3148         SH_PFC_PIN_GROUP(irda_0),
3149         SH_PFC_PIN_GROUP(irda_1),
3150         SH_PFC_PIN_GROUP(keysc_in5),
3151         SH_PFC_PIN_GROUP(keysc_in6),
3152         SH_PFC_PIN_GROUP(keysc_in7),
3153         SH_PFC_PIN_GROUP(keysc_in8),
3154         SH_PFC_PIN_GROUP(keysc_out04),
3155         SH_PFC_PIN_GROUP(keysc_out5),
3156         SH_PFC_PIN_GROUP(keysc_out6_0),
3157         SH_PFC_PIN_GROUP(keysc_out6_1),
3158         SH_PFC_PIN_GROUP(keysc_out6_2),
3159         SH_PFC_PIN_GROUP(keysc_out7_0),
3160         SH_PFC_PIN_GROUP(keysc_out7_1),
3161         SH_PFC_PIN_GROUP(keysc_out7_2),
3162         SH_PFC_PIN_GROUP(keysc_out8_0),
3163         SH_PFC_PIN_GROUP(keysc_out8_1),
3164         SH_PFC_PIN_GROUP(keysc_out8_2),
3165         SH_PFC_PIN_GROUP(keysc_out9_0),
3166         SH_PFC_PIN_GROUP(keysc_out9_1),
3167         SH_PFC_PIN_GROUP(keysc_out9_2),
3168         SH_PFC_PIN_GROUP(keysc_out10_0),
3169         SH_PFC_PIN_GROUP(keysc_out10_1),
3170         SH_PFC_PIN_GROUP(keysc_out11_0),
3171         SH_PFC_PIN_GROUP(keysc_out11_1),
3172         SH_PFC_PIN_GROUP(lcd_data8),
3173         SH_PFC_PIN_GROUP(lcd_data9),
3174         SH_PFC_PIN_GROUP(lcd_data12),
3175         SH_PFC_PIN_GROUP(lcd_data16),
3176         SH_PFC_PIN_GROUP(lcd_data18),
3177         SH_PFC_PIN_GROUP(lcd_data24),
3178         SH_PFC_PIN_GROUP(lcd_display),
3179         SH_PFC_PIN_GROUP(lcd_lclk),
3180         SH_PFC_PIN_GROUP(lcd_sync),
3181         SH_PFC_PIN_GROUP(lcd_sys),
3182         SH_PFC_PIN_GROUP(lcd2_data8),
3183         SH_PFC_PIN_GROUP(lcd2_data9),
3184         SH_PFC_PIN_GROUP(lcd2_data12),
3185         SH_PFC_PIN_GROUP(lcd2_data16),
3186         SH_PFC_PIN_GROUP(lcd2_data18),
3187         SH_PFC_PIN_GROUP(lcd2_data24),
3188         SH_PFC_PIN_GROUP(lcd2_sync_0),
3189         SH_PFC_PIN_GROUP(lcd2_sync_1),
3190         SH_PFC_PIN_GROUP(lcd2_sys_0),
3191         SH_PFC_PIN_GROUP(lcd2_sys_1),
3192         SH_PFC_PIN_GROUP(mmc0_data1_0),
3193         SH_PFC_PIN_GROUP(mmc0_data4_0),
3194         SH_PFC_PIN_GROUP(mmc0_data8_0),
3195         SH_PFC_PIN_GROUP(mmc0_ctrl_0),
3196         SH_PFC_PIN_GROUP(mmc0_data1_1),
3197         SH_PFC_PIN_GROUP(mmc0_data4_1),
3198         SH_PFC_PIN_GROUP(mmc0_data8_1),
3199         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
3200         SH_PFC_PIN_GROUP(msiof0_rsck),
3201         SH_PFC_PIN_GROUP(msiof0_tsck),
3202         SH_PFC_PIN_GROUP(msiof0_rsync),
3203         SH_PFC_PIN_GROUP(msiof0_tsync),
3204         SH_PFC_PIN_GROUP(msiof0_ss1),
3205         SH_PFC_PIN_GROUP(msiof0_ss2),
3206         SH_PFC_PIN_GROUP(msiof0_rxd),
3207         SH_PFC_PIN_GROUP(msiof0_txd),
3208         SH_PFC_PIN_GROUP(msiof0_mck0),
3209         SH_PFC_PIN_GROUP(msiof0_mck1),
3210         SH_PFC_PIN_GROUP(msiof0l_rsck),
3211         SH_PFC_PIN_GROUP(msiof0l_tsck),
3212         SH_PFC_PIN_GROUP(msiof0l_rsync),
3213         SH_PFC_PIN_GROUP(msiof0l_tsync),
3214         SH_PFC_PIN_GROUP(msiof0l_ss1_a),
3215         SH_PFC_PIN_GROUP(msiof0l_ss1_b),
3216         SH_PFC_PIN_GROUP(msiof0l_ss2_a),
3217         SH_PFC_PIN_GROUP(msiof0l_ss2_b),
3218         SH_PFC_PIN_GROUP(msiof0l_rxd),
3219         SH_PFC_PIN_GROUP(msiof0l_txd),
3220         SH_PFC_PIN_GROUP(msiof0l_mck0),
3221         SH_PFC_PIN_GROUP(msiof0l_mck1),
3222         SH_PFC_PIN_GROUP(msiof1_rsck),
3223         SH_PFC_PIN_GROUP(msiof1_tsck),
3224         SH_PFC_PIN_GROUP(msiof1_rsync),
3225         SH_PFC_PIN_GROUP(msiof1_tsync),
3226         SH_PFC_PIN_GROUP(msiof1_ss1),
3227         SH_PFC_PIN_GROUP(msiof1_ss2),
3228         SH_PFC_PIN_GROUP(msiof1_rxd),
3229         SH_PFC_PIN_GROUP(msiof1_txd),
3230         SH_PFC_PIN_GROUP(msiof1_mck0),
3231         SH_PFC_PIN_GROUP(msiof1_mck1),
3232         SH_PFC_PIN_GROUP(msiof2_rsck),
3233         SH_PFC_PIN_GROUP(msiof2_tsck),
3234         SH_PFC_PIN_GROUP(msiof2_rsync),
3235         SH_PFC_PIN_GROUP(msiof2_tsync),
3236         SH_PFC_PIN_GROUP(msiof2_ss1_a),
3237         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3238         SH_PFC_PIN_GROUP(msiof2_ss2_a),
3239         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3240         SH_PFC_PIN_GROUP(msiof2_rxd_a),
3241         SH_PFC_PIN_GROUP(msiof2_rxd_b),
3242         SH_PFC_PIN_GROUP(msiof2_txd),
3243         SH_PFC_PIN_GROUP(msiof2_mck0),
3244         SH_PFC_PIN_GROUP(msiof2_mck1),
3245         SH_PFC_PIN_GROUP(msiof2r_tsck),
3246         SH_PFC_PIN_GROUP(msiof2r_tsync),
3247         SH_PFC_PIN_GROUP(msiof2r_rxd),
3248         SH_PFC_PIN_GROUP(msiof2r_txd),
3249         SH_PFC_PIN_GROUP(msiof3_rsck),
3250         SH_PFC_PIN_GROUP(msiof3_tsck),
3251         SH_PFC_PIN_GROUP(msiof3_rsync),
3252         SH_PFC_PIN_GROUP(msiof3_tsync),
3253         SH_PFC_PIN_GROUP(msiof3_ss1),
3254         SH_PFC_PIN_GROUP(msiof3_ss2),
3255         SH_PFC_PIN_GROUP(msiof3_rxd),
3256         SH_PFC_PIN_GROUP(msiof3_txd),
3257         SH_PFC_PIN_GROUP(msiof3_flow),
3258         SH_PFC_PIN_GROUP(scifa0_data),
3259         SH_PFC_PIN_GROUP(scifa0_clk),
3260         SH_PFC_PIN_GROUP(scifa0_ctrl),
3261         SH_PFC_PIN_GROUP(scifa1_data),
3262         SH_PFC_PIN_GROUP(scifa1_clk),
3263         SH_PFC_PIN_GROUP(scifa1_ctrl),
3264         SH_PFC_PIN_GROUP(scifa2_data_0),
3265         SH_PFC_PIN_GROUP(scifa2_clk_0),
3266         SH_PFC_PIN_GROUP(scifa2_ctrl_0),
3267         SH_PFC_PIN_GROUP(scifa2_data_1),
3268         SH_PFC_PIN_GROUP(scifa2_clk_1),
3269         SH_PFC_PIN_GROUP(scifa2_ctrl_1),
3270         SH_PFC_PIN_GROUP(scifa3_data),
3271         SH_PFC_PIN_GROUP(scifa3_ctrl),
3272         SH_PFC_PIN_GROUP(scifa4_data),
3273         SH_PFC_PIN_GROUP(scifa4_ctrl),
3274         SH_PFC_PIN_GROUP(scifa5_data_0),
3275         SH_PFC_PIN_GROUP(scifa5_clk_0),
3276         SH_PFC_PIN_GROUP(scifa5_ctrl_0),
3277         SH_PFC_PIN_GROUP(scifa5_data_1),
3278         SH_PFC_PIN_GROUP(scifa5_clk_1),
3279         SH_PFC_PIN_GROUP(scifa5_ctrl_1),
3280         SH_PFC_PIN_GROUP(scifa5_data_2),
3281         SH_PFC_PIN_GROUP(scifa5_clk_2),
3282         SH_PFC_PIN_GROUP(scifa5_ctrl_2),
3283         SH_PFC_PIN_GROUP(scifa6),
3284         SH_PFC_PIN_GROUP(scifa7_data),
3285         SH_PFC_PIN_GROUP(scifa7_ctrl),
3286         SH_PFC_PIN_GROUP(scifb_data_0),
3287         SH_PFC_PIN_GROUP(scifb_clk_0),
3288         SH_PFC_PIN_GROUP(scifb_ctrl_0),
3289         SH_PFC_PIN_GROUP(scifb_data_1),
3290         SH_PFC_PIN_GROUP(scifb_clk_1),
3291         SH_PFC_PIN_GROUP(scifb_ctrl_1),
3292         SH_PFC_PIN_GROUP(sdhi0_data1),
3293         SH_PFC_PIN_GROUP(sdhi0_data4),
3294         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3295         SH_PFC_PIN_GROUP(sdhi0_cd),
3296         SH_PFC_PIN_GROUP(sdhi0_wp),
3297         SH_PFC_PIN_GROUP(sdhi1_data1),
3298         SH_PFC_PIN_GROUP(sdhi1_data4),
3299         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3300         SH_PFC_PIN_GROUP(sdhi2_data1),
3301         SH_PFC_PIN_GROUP(sdhi2_data4),
3302         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3303         SH_PFC_PIN_GROUP(tpu0_to0),
3304         SH_PFC_PIN_GROUP(tpu0_to1),
3305         SH_PFC_PIN_GROUP(tpu0_to2),
3306         SH_PFC_PIN_GROUP(tpu0_to3),
3307         SH_PFC_PIN_GROUP(tpu1_to0),
3308         SH_PFC_PIN_GROUP(tpu1_to1_0),
3309         SH_PFC_PIN_GROUP(tpu1_to1_1),
3310         SH_PFC_PIN_GROUP(tpu1_to2),
3311         SH_PFC_PIN_GROUP(tpu1_to3),
3312         SH_PFC_PIN_GROUP(tpu2_to0),
3313         SH_PFC_PIN_GROUP(tpu2_to1),
3314         SH_PFC_PIN_GROUP(tpu2_to2),
3315         SH_PFC_PIN_GROUP(tpu2_to3),
3316         SH_PFC_PIN_GROUP(tpu3_to0),
3317         SH_PFC_PIN_GROUP(tpu3_to1),
3318         SH_PFC_PIN_GROUP(tpu3_to2),
3319         SH_PFC_PIN_GROUP(tpu3_to3),
3320         SH_PFC_PIN_GROUP(tpu4_to0),
3321         SH_PFC_PIN_GROUP(tpu4_to1),
3322         SH_PFC_PIN_GROUP(tpu4_to2),
3323         SH_PFC_PIN_GROUP(tpu4_to3),
3324         SH_PFC_PIN_GROUP(usb_vbus),
3325 };
3326
3327 static const char * const bsc_groups[] = {
3328         "bsc_data_0_7",
3329         "bsc_data_8_15",
3330         "bsc_cs4",
3331         "bsc_cs5_a",
3332         "bsc_cs5_b",
3333         "bsc_cs6_a",
3334         "bsc_cs6_b",
3335         "bsc_rd",
3336         "bsc_rdwr_0",
3337         "bsc_rdwr_1",
3338         "bsc_rdwr_2",
3339         "bsc_we0",
3340         "bsc_we1",
3341 };
3342
3343 static const char * const fsia_groups[] = {
3344         "fsia_mclk_in",
3345         "fsia_mclk_out",
3346         "fsia_sclk_in",
3347         "fsia_sclk_out",
3348         "fsia_data_in",
3349         "fsia_data_out",
3350         "fsia_spdif",
3351 };
3352
3353 static const char * const fsib_groups[] = {
3354         "fsib_mclk_in",
3355         "fsib_mclk_out",
3356         "fsib_sclk_in",
3357         "fsib_sclk_out",
3358         "fsib_data_in",
3359         "fsib_data_out",
3360         "fsib_spdif",
3361 };
3362
3363 static const char * const fsic_groups[] = {
3364         "fsic_mclk_in",
3365         "fsic_mclk_out",
3366         "fsic_sclk_in",
3367         "fsic_sclk_out",
3368         "fsic_data_in",
3369         "fsic_data_out",
3370         "fsic_spdif_0",
3371         "fsic_spdif_1",
3372 };
3373
3374 static const char * const fsid_groups[] = {
3375         "fsid_sclk_in",
3376         "fsid_sclk_out",
3377         "fsid_data_in",
3378 };
3379
3380 static const char * const i2c2_groups[] = {
3381         "i2c2_0",
3382         "i2c2_1",
3383         "i2c2_2",
3384 };
3385
3386 static const char * const i2c3_groups[] = {
3387         "i2c3_0",
3388         "i2c3_1",
3389         "i2c3_2",
3390 };
3391
3392 static const char * const irda_groups[] = {
3393         "irda_0",
3394         "irda_1",
3395 };
3396
3397 static const char * const keysc_groups[] = {
3398         "keysc_in5",
3399         "keysc_in6",
3400         "keysc_in7",
3401         "keysc_in8",
3402         "keysc_out04",
3403         "keysc_out5",
3404         "keysc_out6_0",
3405         "keysc_out6_1",
3406         "keysc_out6_2",
3407         "keysc_out7_0",
3408         "keysc_out7_1",
3409         "keysc_out7_2",
3410         "keysc_out8_0",
3411         "keysc_out8_1",
3412         "keysc_out8_2",
3413         "keysc_out9_0",
3414         "keysc_out9_1",
3415         "keysc_out9_2",
3416         "keysc_out10_0",
3417         "keysc_out10_1",
3418         "keysc_out11_0",
3419         "keysc_out11_1",
3420 };
3421
3422 static const char * const lcd_groups[] = {
3423         "lcd_data8",
3424         "lcd_data9",
3425         "lcd_data12",
3426         "lcd_data16",
3427         "lcd_data18",
3428         "lcd_data24",
3429         "lcd_display",
3430         "lcd_lclk",
3431         "lcd_sync",
3432         "lcd_sys",
3433 };
3434
3435 static const char * const lcd2_groups[] = {
3436         "lcd2_data8",
3437         "lcd2_data9",
3438         "lcd2_data12",
3439         "lcd2_data16",
3440         "lcd2_data18",
3441         "lcd2_data24",
3442         "lcd2_sync_0",
3443         "lcd2_sync_1",
3444         "lcd2_sys_0",
3445         "lcd2_sys_1",
3446 };
3447
3448 static const char * const mmc0_groups[] = {
3449         "mmc0_data1_0",
3450         "mmc0_data4_0",
3451         "mmc0_data8_0",
3452         "mmc0_ctrl_0",
3453         "mmc0_data1_1",
3454         "mmc0_data4_1",
3455         "mmc0_data8_1",
3456         "mmc0_ctrl_1",
3457 };
3458
3459 static const char * const msiof0_groups[] = {
3460         "msiof0_rsck",
3461         "msiof0_tsck",
3462         "msiof0_rsync",
3463         "msiof0_tsync",
3464         "msiof0_ss1",
3465         "msiof0_ss2",
3466         "msiof0_rxd",
3467         "msiof0_txd",
3468         "msiof0_mck0",
3469         "msiof0_mck1",
3470         "msiof0l_rsck",
3471         "msiof0l_tsck",
3472         "msiof0l_rsync",
3473         "msiof0l_tsync",
3474         "msiof0l_ss1_a",
3475         "msiof0l_ss1_b",
3476         "msiof0l_ss2_a",
3477         "msiof0l_ss2_b",
3478         "msiof0l_rxd",
3479         "msiof0l_txd",
3480         "msiof0l_mck0",
3481         "msiof0l_mck1",
3482 };
3483
3484 static const char * const msiof1_groups[] = {
3485         "msiof1_rsck",
3486         "msiof1_tsck",
3487         "msiof1_rsync",
3488         "msiof1_tsync",
3489         "msiof1_ss1",
3490         "msiof1_ss2",
3491         "msiof1_rxd",
3492         "msiof1_txd",
3493         "msiof1_mck0",
3494         "msiof1_mck1",
3495 };
3496
3497 static const char * const msiof2_groups[] = {
3498         "msiof2_rsck",
3499         "msiof2_tsck",
3500         "msiof2_rsync",
3501         "msiof2_tsync",
3502         "msiof2_ss1_a",
3503         "msiof2_ss1_b",
3504         "msiof2_ss2_a",
3505         "msiof2_ss2_b",
3506         "msiof2_rxd_a",
3507         "msiof2_rxd_b",
3508         "msiof2_txd",
3509         "msiof2_mck0",
3510         "msiof2_mck1",
3511         "msiof2r_tsck",
3512         "msiof2r_tsync",
3513         "msiof2r_rxd",
3514         "msiof2r_txd",
3515 };
3516
3517 static const char * const msiof3_groups[] = {
3518         "msiof3_rsck",
3519         "msiof3_tsck",
3520         "msiof3_rsync",
3521         "msiof3_tsync",
3522         "msiof3_ss1",
3523         "msiof3_ss2",
3524         "msiof3_rxd",
3525         "msiof3_txd",
3526         "msiof3_flow",
3527 };
3528
3529 static const char * const scifa0_groups[] = {
3530         "scifa0_data",
3531         "scifa0_clk",
3532         "scifa0_ctrl",
3533 };
3534
3535 static const char * const scifa1_groups[] = {
3536         "scifa1_data",
3537         "scifa1_clk",
3538         "scifa1_ctrl",
3539 };
3540
3541 static const char * const scifa2_groups[] = {
3542         "scifa2_data_0",
3543         "scifa2_clk_0",
3544         "scifa2_ctrl_0",
3545         "scifa2_data_1",
3546         "scifa2_clk_1",
3547         "scifa2_ctrl_1",
3548 };
3549
3550 static const char * const scifa3_groups[] = {
3551         "scifa3_data",
3552         "scifa3_ctrl",
3553 };
3554
3555 static const char * const scifa4_groups[] = {
3556         "scifa4_data",
3557         "scifa4_ctrl",
3558 };
3559
3560 static const char * const scifa5_groups[] = {
3561         "scifa5_data_0",
3562         "scifa5_clk_0",
3563         "scifa5_ctrl_0",
3564         "scifa5_data_1",
3565         "scifa5_clk_1",
3566         "scifa5_ctrl_1",
3567         "scifa5_data_2",
3568         "scifa5_clk_2",
3569         "scifa5_ctrl_2",
3570 };
3571
3572 static const char * const scifa6_groups[] = {
3573         "scifa6",
3574 };
3575
3576 static const char * const scifa7_groups[] = {
3577         "scifa7_data",
3578         "scifa7_ctrl",
3579 };
3580
3581 static const char * const scifb_groups[] = {
3582         "scifb_data_0",
3583         "scifb_clk_0",
3584         "scifb_ctrl_0",
3585         "scifb_data_1",
3586         "scifb_clk_1",
3587         "scifb_ctrl_1",
3588 };
3589
3590 static const char * const sdhi0_groups[] = {
3591         "sdhi0_data1",
3592         "sdhi0_data4",
3593         "sdhi0_ctrl",
3594         "sdhi0_cd",
3595         "sdhi0_wp",
3596 };
3597
3598 static const char * const sdhi1_groups[] = {
3599         "sdhi1_data1",
3600         "sdhi1_data4",
3601         "sdhi1_ctrl",
3602 };
3603
3604 static const char * const sdhi2_groups[] = {
3605         "sdhi2_data1",
3606         "sdhi2_data4",
3607         "sdhi2_ctrl",
3608 };
3609
3610 static const char * const usb_groups[] = {
3611         "usb_vbus",
3612 };
3613
3614 static const char * const tpu0_groups[] = {
3615         "tpu0_to0",
3616         "tpu0_to1",
3617         "tpu0_to2",
3618         "tpu0_to3",
3619 };
3620
3621 static const char * const tpu1_groups[] = {
3622         "tpu1_to0",
3623         "tpu1_to1_0",
3624         "tpu1_to1_1",
3625         "tpu1_to2",
3626         "tpu1_to3",
3627 };
3628
3629 static const char * const tpu2_groups[] = {
3630         "tpu2_to0",
3631         "tpu2_to1",
3632         "tpu2_to2",
3633         "tpu2_to3",
3634 };
3635
3636 static const char * const tpu3_groups[] = {
3637         "tpu3_to0",
3638         "tpu3_to1",
3639         "tpu3_to2",
3640         "tpu3_to3",
3641 };
3642
3643 static const char * const tpu4_groups[] = {
3644         "tpu4_to0",
3645         "tpu4_to1",
3646         "tpu4_to2",
3647         "tpu4_to3",
3648 };
3649
3650 static const struct sh_pfc_function pinmux_functions[] = {
3651         SH_PFC_FUNCTION(bsc),
3652         SH_PFC_FUNCTION(fsia),
3653         SH_PFC_FUNCTION(fsib),
3654         SH_PFC_FUNCTION(fsic),
3655         SH_PFC_FUNCTION(fsid),
3656         SH_PFC_FUNCTION(i2c2),
3657         SH_PFC_FUNCTION(i2c3),
3658         SH_PFC_FUNCTION(irda),
3659         SH_PFC_FUNCTION(keysc),
3660         SH_PFC_FUNCTION(lcd),
3661         SH_PFC_FUNCTION(lcd2),
3662         SH_PFC_FUNCTION(mmc0),
3663         SH_PFC_FUNCTION(msiof0),
3664         SH_PFC_FUNCTION(msiof1),
3665         SH_PFC_FUNCTION(msiof2),
3666         SH_PFC_FUNCTION(msiof3),
3667         SH_PFC_FUNCTION(scifa0),
3668         SH_PFC_FUNCTION(scifa1),
3669         SH_PFC_FUNCTION(scifa2),
3670         SH_PFC_FUNCTION(scifa3),
3671         SH_PFC_FUNCTION(scifa4),
3672         SH_PFC_FUNCTION(scifa5),
3673         SH_PFC_FUNCTION(scifa6),
3674         SH_PFC_FUNCTION(scifa7),
3675         SH_PFC_FUNCTION(scifb),
3676         SH_PFC_FUNCTION(sdhi0),
3677         SH_PFC_FUNCTION(sdhi1),
3678         SH_PFC_FUNCTION(sdhi2),
3679         SH_PFC_FUNCTION(tpu0),
3680         SH_PFC_FUNCTION(tpu1),
3681         SH_PFC_FUNCTION(tpu2),
3682         SH_PFC_FUNCTION(tpu3),
3683         SH_PFC_FUNCTION(tpu4),
3684         SH_PFC_FUNCTION(usb),
3685 };
3686
3687 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3688         PORTCR(0, 0xe6050000), /* PORT0CR */
3689         PORTCR(1, 0xe6050001), /* PORT1CR */
3690         PORTCR(2, 0xe6050002), /* PORT2CR */
3691         PORTCR(3, 0xe6050003), /* PORT3CR */
3692         PORTCR(4, 0xe6050004), /* PORT4CR */
3693         PORTCR(5, 0xe6050005), /* PORT5CR */
3694         PORTCR(6, 0xe6050006), /* PORT6CR */
3695         PORTCR(7, 0xe6050007), /* PORT7CR */
3696         PORTCR(8, 0xe6050008), /* PORT8CR */
3697         PORTCR(9, 0xe6050009), /* PORT9CR */
3698
3699         PORTCR(10, 0xe605000a), /* PORT10CR */
3700         PORTCR(11, 0xe605000b), /* PORT11CR */
3701         PORTCR(12, 0xe605000c), /* PORT12CR */
3702         PORTCR(13, 0xe605000d), /* PORT13CR */
3703         PORTCR(14, 0xe605000e), /* PORT14CR */
3704         PORTCR(15, 0xe605000f), /* PORT15CR */
3705         PORTCR(16, 0xe6050010), /* PORT16CR */
3706         PORTCR(17, 0xe6050011), /* PORT17CR */
3707         PORTCR(18, 0xe6050012), /* PORT18CR */
3708         PORTCR(19, 0xe6050013), /* PORT19CR */
3709
3710         PORTCR(20, 0xe6050014), /* PORT20CR */
3711         PORTCR(21, 0xe6050015), /* PORT21CR */
3712         PORTCR(22, 0xe6050016), /* PORT22CR */
3713         PORTCR(23, 0xe6050017), /* PORT23CR */
3714         PORTCR(24, 0xe6050018), /* PORT24CR */
3715         PORTCR(25, 0xe6050019), /* PORT25CR */
3716         PORTCR(26, 0xe605001a), /* PORT26CR */
3717         PORTCR(27, 0xe605001b), /* PORT27CR */
3718         PORTCR(28, 0xe605001c), /* PORT28CR */
3719         PORTCR(29, 0xe605001d), /* PORT29CR */
3720
3721         PORTCR(30, 0xe605001e), /* PORT30CR */
3722         PORTCR(31, 0xe605001f), /* PORT31CR */
3723         PORTCR(32, 0xe6051020), /* PORT32CR */
3724         PORTCR(33, 0xe6051021), /* PORT33CR */
3725         PORTCR(34, 0xe6051022), /* PORT34CR */
3726         PORTCR(35, 0xe6051023), /* PORT35CR */
3727         PORTCR(36, 0xe6051024), /* PORT36CR */
3728         PORTCR(37, 0xe6051025), /* PORT37CR */
3729         PORTCR(38, 0xe6051026), /* PORT38CR */
3730         PORTCR(39, 0xe6051027), /* PORT39CR */
3731
3732         PORTCR(40, 0xe6051028), /* PORT40CR */
3733         PORTCR(41, 0xe6051029), /* PORT41CR */
3734         PORTCR(42, 0xe605102a), /* PORT42CR */
3735         PORTCR(43, 0xe605102b), /* PORT43CR */
3736         PORTCR(44, 0xe605102c), /* PORT44CR */
3737         PORTCR(45, 0xe605102d), /* PORT45CR */
3738         PORTCR(46, 0xe605102e), /* PORT46CR */
3739         PORTCR(47, 0xe605102f), /* PORT47CR */
3740         PORTCR(48, 0xe6051030), /* PORT48CR */
3741         PORTCR(49, 0xe6051031), /* PORT49CR */
3742
3743         PORTCR(50, 0xe6051032), /* PORT50CR */
3744         PORTCR(51, 0xe6051033), /* PORT51CR */
3745         PORTCR(52, 0xe6051034), /* PORT52CR */
3746         PORTCR(53, 0xe6051035), /* PORT53CR */
3747         PORTCR(54, 0xe6051036), /* PORT54CR */
3748         PORTCR(55, 0xe6051037), /* PORT55CR */
3749         PORTCR(56, 0xe6051038), /* PORT56CR */
3750         PORTCR(57, 0xe6051039), /* PORT57CR */
3751         PORTCR(58, 0xe605103a), /* PORT58CR */
3752         PORTCR(59, 0xe605103b), /* PORT59CR */
3753
3754         PORTCR(60, 0xe605103c), /* PORT60CR */
3755         PORTCR(61, 0xe605103d), /* PORT61CR */
3756         PORTCR(62, 0xe605103e), /* PORT62CR */
3757         PORTCR(63, 0xe605103f), /* PORT63CR */
3758         PORTCR(64, 0xe6051040), /* PORT64CR */
3759         PORTCR(65, 0xe6051041), /* PORT65CR */
3760         PORTCR(66, 0xe6051042), /* PORT66CR */
3761         PORTCR(67, 0xe6051043), /* PORT67CR */
3762         PORTCR(68, 0xe6051044), /* PORT68CR */
3763         PORTCR(69, 0xe6051045), /* PORT69CR */
3764
3765         PORTCR(70, 0xe6051046), /* PORT70CR */
3766         PORTCR(71, 0xe6051047), /* PORT71CR */
3767         PORTCR(72, 0xe6051048), /* PORT72CR */
3768         PORTCR(73, 0xe6051049), /* PORT73CR */
3769         PORTCR(74, 0xe605104a), /* PORT74CR */
3770         PORTCR(75, 0xe605104b), /* PORT75CR */
3771         PORTCR(76, 0xe605104c), /* PORT76CR */
3772         PORTCR(77, 0xe605104d), /* PORT77CR */
3773         PORTCR(78, 0xe605104e), /* PORT78CR */
3774         PORTCR(79, 0xe605104f), /* PORT79CR */
3775
3776         PORTCR(80, 0xe6051050), /* PORT80CR */
3777         PORTCR(81, 0xe6051051), /* PORT81CR */
3778         PORTCR(82, 0xe6051052), /* PORT82CR */
3779         PORTCR(83, 0xe6051053), /* PORT83CR */
3780         PORTCR(84, 0xe6051054), /* PORT84CR */
3781         PORTCR(85, 0xe6051055), /* PORT85CR */
3782         PORTCR(86, 0xe6051056), /* PORT86CR */
3783         PORTCR(87, 0xe6051057), /* PORT87CR */
3784         PORTCR(88, 0xe6051058), /* PORT88CR */
3785         PORTCR(89, 0xe6051059), /* PORT89CR */
3786
3787         PORTCR(90, 0xe605105a), /* PORT90CR */
3788         PORTCR(91, 0xe605105b), /* PORT91CR */
3789         PORTCR(92, 0xe605105c), /* PORT92CR */
3790         PORTCR(93, 0xe605105d), /* PORT93CR */
3791         PORTCR(94, 0xe605105e), /* PORT94CR */
3792         PORTCR(95, 0xe605105f), /* PORT95CR */
3793         PORTCR(96, 0xe6052060), /* PORT96CR */
3794         PORTCR(97, 0xe6052061), /* PORT97CR */
3795         PORTCR(98, 0xe6052062), /* PORT98CR */
3796         PORTCR(99, 0xe6052063), /* PORT99CR */
3797
3798         PORTCR(100, 0xe6052064), /* PORT100CR */
3799         PORTCR(101, 0xe6052065), /* PORT101CR */
3800         PORTCR(102, 0xe6052066), /* PORT102CR */
3801         PORTCR(103, 0xe6052067), /* PORT103CR */
3802         PORTCR(104, 0xe6052068), /* PORT104CR */
3803         PORTCR(105, 0xe6052069), /* PORT105CR */
3804         PORTCR(106, 0xe605206a), /* PORT106CR */
3805         PORTCR(107, 0xe605206b), /* PORT107CR */
3806         PORTCR(108, 0xe605206c), /* PORT108CR */
3807         PORTCR(109, 0xe605206d), /* PORT109CR */
3808
3809         PORTCR(110, 0xe605206e), /* PORT110CR */
3810         PORTCR(111, 0xe605206f), /* PORT111CR */
3811         PORTCR(112, 0xe6052070), /* PORT112CR */
3812         PORTCR(113, 0xe6052071), /* PORT113CR */
3813         PORTCR(114, 0xe6052072), /* PORT114CR */
3814         PORTCR(115, 0xe6052073), /* PORT115CR */
3815         PORTCR(116, 0xe6052074), /* PORT116CR */
3816         PORTCR(117, 0xe6052075), /* PORT117CR */
3817         PORTCR(118, 0xe6052076), /* PORT118CR */
3818
3819         PORTCR(128, 0xe6052080), /* PORT128CR */
3820         PORTCR(129, 0xe6052081), /* PORT129CR */
3821
3822         PORTCR(130, 0xe6052082), /* PORT130CR */
3823         PORTCR(131, 0xe6052083), /* PORT131CR */
3824         PORTCR(132, 0xe6052084), /* PORT132CR */
3825         PORTCR(133, 0xe6052085), /* PORT133CR */
3826         PORTCR(134, 0xe6052086), /* PORT134CR */
3827         PORTCR(135, 0xe6052087), /* PORT135CR */
3828         PORTCR(136, 0xe6052088), /* PORT136CR */
3829         PORTCR(137, 0xe6052089), /* PORT137CR */
3830         PORTCR(138, 0xe605208a), /* PORT138CR */
3831         PORTCR(139, 0xe605208b), /* PORT139CR */
3832
3833         PORTCR(140, 0xe605208c), /* PORT140CR */
3834         PORTCR(141, 0xe605208d), /* PORT141CR */
3835         PORTCR(142, 0xe605208e), /* PORT142CR */
3836         PORTCR(143, 0xe605208f), /* PORT143CR */
3837         PORTCR(144, 0xe6052090), /* PORT144CR */
3838         PORTCR(145, 0xe6052091), /* PORT145CR */
3839         PORTCR(146, 0xe6052092), /* PORT146CR */
3840         PORTCR(147, 0xe6052093), /* PORT147CR */
3841         PORTCR(148, 0xe6052094), /* PORT148CR */
3842         PORTCR(149, 0xe6052095), /* PORT149CR */
3843
3844         PORTCR(150, 0xe6052096), /* PORT150CR */
3845         PORTCR(151, 0xe6052097), /* PORT151CR */
3846         PORTCR(152, 0xe6052098), /* PORT152CR */
3847         PORTCR(153, 0xe6052099), /* PORT153CR */
3848         PORTCR(154, 0xe605209a), /* PORT154CR */
3849         PORTCR(155, 0xe605209b), /* PORT155CR */
3850         PORTCR(156, 0xe605209c), /* PORT156CR */
3851         PORTCR(157, 0xe605209d), /* PORT157CR */
3852         PORTCR(158, 0xe605209e), /* PORT158CR */
3853         PORTCR(159, 0xe605209f), /* PORT159CR */
3854
3855         PORTCR(160, 0xe60520a0), /* PORT160CR */
3856         PORTCR(161, 0xe60520a1), /* PORT161CR */
3857         PORTCR(162, 0xe60520a2), /* PORT162CR */
3858         PORTCR(163, 0xe60520a3), /* PORT163CR */
3859         PORTCR(164, 0xe60520a4), /* PORT164CR */
3860
3861         PORTCR(192, 0xe60520c0), /* PORT192CR */
3862         PORTCR(193, 0xe60520c1), /* PORT193CR */
3863         PORTCR(194, 0xe60520c2), /* PORT194CR */
3864         PORTCR(195, 0xe60520c3), /* PORT195CR */
3865         PORTCR(196, 0xe60520c4), /* PORT196CR */
3866         PORTCR(197, 0xe60520c5), /* PORT197CR */
3867         PORTCR(198, 0xe60520c6), /* PORT198CR */
3868         PORTCR(199, 0xe60520c7), /* PORT199CR */
3869
3870         PORTCR(200, 0xe60520c8), /* PORT200CR */
3871         PORTCR(201, 0xe60520c9), /* PORT201CR */
3872         PORTCR(202, 0xe60520ca), /* PORT202CR */
3873         PORTCR(203, 0xe60520cb), /* PORT203CR */
3874         PORTCR(204, 0xe60520cc), /* PORT204CR */
3875         PORTCR(205, 0xe60520cd), /* PORT205CR */
3876         PORTCR(206, 0xe60520ce), /* PORT206CR */
3877         PORTCR(207, 0xe60520cf), /* PORT207CR */
3878         PORTCR(208, 0xe60520d0), /* PORT208CR */
3879         PORTCR(209, 0xe60520d1), /* PORT209CR */
3880
3881         PORTCR(210, 0xe60520d2), /* PORT210CR */
3882         PORTCR(211, 0xe60520d3), /* PORT211CR */
3883         PORTCR(212, 0xe60520d4), /* PORT212CR */
3884         PORTCR(213, 0xe60520d5), /* PORT213CR */
3885         PORTCR(214, 0xe60520d6), /* PORT214CR */
3886         PORTCR(215, 0xe60520d7), /* PORT215CR */
3887         PORTCR(216, 0xe60520d8), /* PORT216CR */
3888         PORTCR(217, 0xe60520d9), /* PORT217CR */
3889         PORTCR(218, 0xe60520da), /* PORT218CR */
3890         PORTCR(219, 0xe60520db), /* PORT219CR */
3891
3892         PORTCR(220, 0xe60520dc), /* PORT220CR */
3893         PORTCR(221, 0xe60520dd), /* PORT221CR */
3894         PORTCR(222, 0xe60520de), /* PORT222CR */
3895         PORTCR(223, 0xe60520df), /* PORT223CR */
3896         PORTCR(224, 0xe60530e0), /* PORT224CR */
3897         PORTCR(225, 0xe60530e1), /* PORT225CR */
3898         PORTCR(226, 0xe60530e2), /* PORT226CR */
3899         PORTCR(227, 0xe60530e3), /* PORT227CR */
3900         PORTCR(228, 0xe60530e4), /* PORT228CR */
3901         PORTCR(229, 0xe60530e5), /* PORT229CR */
3902
3903         PORTCR(230, 0xe60530e6), /* PORT230CR */
3904         PORTCR(231, 0xe60530e7), /* PORT231CR */
3905         PORTCR(232, 0xe60530e8), /* PORT232CR */
3906         PORTCR(233, 0xe60530e9), /* PORT233CR */
3907         PORTCR(234, 0xe60530ea), /* PORT234CR */
3908         PORTCR(235, 0xe60530eb), /* PORT235CR */
3909         PORTCR(236, 0xe60530ec), /* PORT236CR */
3910         PORTCR(237, 0xe60530ed), /* PORT237CR */
3911         PORTCR(238, 0xe60530ee), /* PORT238CR */
3912         PORTCR(239, 0xe60530ef), /* PORT239CR */
3913
3914         PORTCR(240, 0xe60530f0), /* PORT240CR */
3915         PORTCR(241, 0xe60530f1), /* PORT241CR */
3916         PORTCR(242, 0xe60530f2), /* PORT242CR */
3917         PORTCR(243, 0xe60530f3), /* PORT243CR */
3918         PORTCR(244, 0xe60530f4), /* PORT244CR */
3919         PORTCR(245, 0xe60530f5), /* PORT245CR */
3920         PORTCR(246, 0xe60530f6), /* PORT246CR */
3921         PORTCR(247, 0xe60530f7), /* PORT247CR */
3922         PORTCR(248, 0xe60530f8), /* PORT248CR */
3923         PORTCR(249, 0xe60530f9), /* PORT249CR */
3924
3925         PORTCR(250, 0xe60530fa), /* PORT250CR */
3926         PORTCR(251, 0xe60530fb), /* PORT251CR */
3927         PORTCR(252, 0xe60530fc), /* PORT252CR */
3928         PORTCR(253, 0xe60530fd), /* PORT253CR */
3929         PORTCR(254, 0xe60530fe), /* PORT254CR */
3930         PORTCR(255, 0xe60530ff), /* PORT255CR */
3931         PORTCR(256, 0xe6053100), /* PORT256CR */
3932         PORTCR(257, 0xe6053101), /* PORT257CR */
3933         PORTCR(258, 0xe6053102), /* PORT258CR */
3934         PORTCR(259, 0xe6053103), /* PORT259CR */
3935
3936         PORTCR(260, 0xe6053104), /* PORT260CR */
3937         PORTCR(261, 0xe6053105), /* PORT261CR */
3938         PORTCR(262, 0xe6053106), /* PORT262CR */
3939         PORTCR(263, 0xe6053107), /* PORT263CR */
3940         PORTCR(264, 0xe6053108), /* PORT264CR */
3941         PORTCR(265, 0xe6053109), /* PORT265CR */
3942         PORTCR(266, 0xe605310a), /* PORT266CR */
3943         PORTCR(267, 0xe605310b), /* PORT267CR */
3944         PORTCR(268, 0xe605310c), /* PORT268CR */
3945         PORTCR(269, 0xe605310d), /* PORT269CR */
3946
3947         PORTCR(270, 0xe605310e), /* PORT270CR */
3948         PORTCR(271, 0xe605310f), /* PORT271CR */
3949         PORTCR(272, 0xe6053110), /* PORT272CR */
3950         PORTCR(273, 0xe6053111), /* PORT273CR */
3951         PORTCR(274, 0xe6053112), /* PORT274CR */
3952         PORTCR(275, 0xe6053113), /* PORT275CR */
3953         PORTCR(276, 0xe6053114), /* PORT276CR */
3954         PORTCR(277, 0xe6053115), /* PORT277CR */
3955         PORTCR(278, 0xe6053116), /* PORT278CR */
3956         PORTCR(279, 0xe6053117), /* PORT279CR */
3957
3958         PORTCR(280, 0xe6053118), /* PORT280CR */
3959         PORTCR(281, 0xe6053119), /* PORT281CR */
3960         PORTCR(282, 0xe605311a), /* PORT282CR */
3961
3962         PORTCR(288, 0xe6052120), /* PORT288CR */
3963         PORTCR(289, 0xe6052121), /* PORT289CR */
3964
3965         PORTCR(290, 0xe6052122), /* PORT290CR */
3966         PORTCR(291, 0xe6052123), /* PORT291CR */
3967         PORTCR(292, 0xe6052124), /* PORT292CR */
3968         PORTCR(293, 0xe6052125), /* PORT293CR */
3969         PORTCR(294, 0xe6052126), /* PORT294CR */
3970         PORTCR(295, 0xe6052127), /* PORT295CR */
3971         PORTCR(296, 0xe6052128), /* PORT296CR */
3972         PORTCR(297, 0xe6052129), /* PORT297CR */
3973         PORTCR(298, 0xe605212a), /* PORT298CR */
3974         PORTCR(299, 0xe605212b), /* PORT299CR */
3975
3976         PORTCR(300, 0xe605212c), /* PORT300CR */
3977         PORTCR(301, 0xe605212d), /* PORT301CR */
3978         PORTCR(302, 0xe605212e), /* PORT302CR */
3979         PORTCR(303, 0xe605212f), /* PORT303CR */
3980         PORTCR(304, 0xe6052130), /* PORT304CR */
3981         PORTCR(305, 0xe6052131), /* PORT305CR */
3982         PORTCR(306, 0xe6052132), /* PORT306CR */
3983         PORTCR(307, 0xe6052133), /* PORT307CR */
3984         PORTCR(308, 0xe6052134), /* PORT308CR */
3985         PORTCR(309, 0xe6052135), /* PORT309CR */
3986
3987         { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
3988                         0, 0,
3989                         0, 0,
3990                         0, 0,
3991                         0, 0,
3992                         0, 0,
3993                         0, 0,
3994                         0, 0,
3995                         0, 0,
3996                         0, 0,
3997                         0, 0,
3998                         0, 0,
3999                         0, 0,
4000                         MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
4001                         MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
4002                         MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
4003                         MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
4004                         0, 0,
4005                         MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
4006                         MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
4007                         MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
4008                         MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
4009                         MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
4010                         MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
4011                         MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
4012                         MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
4013                         MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
4014                         MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
4015                         MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
4016                         MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
4017                         MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
4018                         MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
4019                         MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
4020                 }
4021         },
4022         { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
4023                         0, 0,
4024                         0, 0,
4025                         0, 0,
4026                         MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
4027                         0, 0,
4028                         0, 0,
4029                         0, 0,
4030                         0, 0,
4031                         0, 0,
4032                         0, 0,
4033                         0, 0,
4034                         0, 0,
4035                         0, 0,
4036                         0, 0,
4037                         0, 0,
4038                         0, 0,
4039                         MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
4040                         0, 0,
4041                         0, 0,
4042                         0, 0,
4043                         MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
4044                         0, 0,
4045                         MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
4046                         0, 0,
4047                         0, 0,
4048                         MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
4049                         0, 0,
4050                         0, 0,
4051                         0, 0,
4052                         MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
4053                         0, 0,
4054                         0, 0,
4055                 }
4056         },
4057         { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
4058                         0, 0,
4059                         0, 0,
4060                         MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
4061                         0, 0,
4062                         MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
4063                         MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
4064                         0, 0,
4065                         0, 0,
4066                         0, 0,
4067                         MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
4068                         MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
4069                         MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
4070                         MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
4071                         0, 0,
4072                         0, 0,
4073                         0, 0,
4074                         MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
4075                         0, 0,
4076                         MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
4077                         MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
4078                         MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
4079                         MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
4080                         MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
4081                         MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
4082                         MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
4083                         0, 0,
4084                         0, 0,
4085                         MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
4086                         0, 0,
4087                         0, 0,
4088                         MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
4089                         0, 0,
4090                 }
4091         },
4092         { },
4093 };
4094
4095 static const struct pinmux_data_reg pinmux_data_regs[] = {
4096         { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
4097                         PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
4098                         PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
4099                         PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
4100                         PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
4101                         PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
4102                         PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
4103                         PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
4104                         PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
4105         },
4106         { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
4107                         PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
4108                         PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
4109                         PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
4110                         PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
4111                         PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
4112                         PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
4113                         PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
4114                         PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
4115         },
4116         { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
4117                         PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
4118                         PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
4119                         PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
4120                         PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
4121                         PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
4122                         PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
4123                         PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
4124                         PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
4125         },
4126         { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
4127                         0, 0, 0, 0,
4128                         0, 0, 0, 0,
4129                         0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
4130                         PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
4131                         PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
4132                         PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
4133                         PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
4134                         PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
4135         },
4136         { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
4137                         PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
4138                         PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
4139                         PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
4140                         PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
4141                         PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
4142                         PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
4143                         PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
4144                         PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
4145         },
4146         { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
4147                         0, 0, 0, 0,
4148                         0, 0, 0, 0,
4149                         0, 0, 0, 0,
4150                         0, 0, 0, 0,
4151                         0, 0, 0, 0,
4152                         0, 0, 0, 0,
4153                         0, 0, 0, PORT164_DATA,
4154                         PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
4155         },
4156         { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
4157                         PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
4158                         PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
4159                         PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
4160                         PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
4161                         PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
4162                         PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
4163                         PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
4164                         PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
4165         },
4166         { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
4167                         PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
4168                         PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
4169                         PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
4170                         PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
4171                         PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
4172                         PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
4173                         PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
4174                         PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
4175         },
4176         { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
4177                         0, 0, 0, 0,
4178                         0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
4179                         PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
4180                         PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
4181                         PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
4182                         PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
4183                         PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
4184                         PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
4185         },
4186         { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
4187                         0, 0, 0, 0,
4188                         0, 0, 0, 0,
4189                         0, 0, PORT309_DATA, PORT308_DATA,
4190                         PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
4191                         PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
4192                         PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
4193                         PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
4194                         PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
4195         },
4196         { },
4197 };
4198
4199 static const struct pinmux_irq pinmux_irqs[] = {
4200         PINMUX_IRQ(11),         /* IRQ0 */
4201         PINMUX_IRQ(10),         /* IRQ1 */
4202         PINMUX_IRQ(149),        /* IRQ2 */
4203         PINMUX_IRQ(224),        /* IRQ3 */
4204         PINMUX_IRQ(159),        /* IRQ4 */
4205         PINMUX_IRQ(227),        /* IRQ5 */
4206         PINMUX_IRQ(147),        /* IRQ6 */
4207         PINMUX_IRQ(150),        /* IRQ7 */
4208         PINMUX_IRQ(223),        /* IRQ8 */
4209         PINMUX_IRQ(56, 308),    /* IRQ9 */
4210         PINMUX_IRQ(54),         /* IRQ10 */
4211         PINMUX_IRQ(238),        /* IRQ11 */
4212         PINMUX_IRQ(156),        /* IRQ12 */
4213         PINMUX_IRQ(239),        /* IRQ13 */
4214         PINMUX_IRQ(251),        /* IRQ14 */
4215         PINMUX_IRQ(0),          /* IRQ15 */
4216         PINMUX_IRQ(249),        /* IRQ16 */
4217         PINMUX_IRQ(234),        /* IRQ17 */
4218         PINMUX_IRQ(13),         /* IRQ18 */
4219         PINMUX_IRQ(9),          /* IRQ19 */
4220         PINMUX_IRQ(14),         /* IRQ20 */
4221         PINMUX_IRQ(15),         /* IRQ21 */
4222         PINMUX_IRQ(40),         /* IRQ22 */
4223         PINMUX_IRQ(53),         /* IRQ23 */
4224         PINMUX_IRQ(118),        /* IRQ24 */
4225         PINMUX_IRQ(164),        /* IRQ25 */
4226         PINMUX_IRQ(115),        /* IRQ26 */
4227         PINMUX_IRQ(116),        /* IRQ27 */
4228         PINMUX_IRQ(117),        /* IRQ28 */
4229         PINMUX_IRQ(28),         /* IRQ29 */
4230         PINMUX_IRQ(27),         /* IRQ30 */
4231         PINMUX_IRQ(26),         /* IRQ31 */
4232 };
4233
4234 /* -----------------------------------------------------------------------------
4235  * VCCQ MC0 regulator
4236  */
4237
4238 static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
4239 {
4240         struct sh_pfc *pfc = reg->reg_data;
4241         void __iomem *addr = pfc->windows[1].virt + 4;
4242         unsigned long flags;
4243         u32 value;
4244
4245         spin_lock_irqsave(&pfc->lock, flags);
4246
4247         value = ioread32(addr);
4248
4249         if (enable)
4250                 value |= BIT(28);
4251         else
4252                 value &= ~BIT(28);
4253
4254         iowrite32(value, addr);
4255
4256         spin_unlock_irqrestore(&pfc->lock, flags);
4257 }
4258
4259 static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
4260 {
4261         sh73a0_vccq_mc0_endisable(reg, true);
4262         return 0;
4263 }
4264
4265 static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
4266 {
4267         sh73a0_vccq_mc0_endisable(reg, false);
4268         return 0;
4269 }
4270
4271 static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
4272 {
4273         struct sh_pfc *pfc = reg->reg_data;
4274         void __iomem *addr = pfc->windows[1].virt + 4;
4275         unsigned long flags;
4276         u32 value;
4277
4278         spin_lock_irqsave(&pfc->lock, flags);
4279         value = ioread32(addr);
4280         spin_unlock_irqrestore(&pfc->lock, flags);
4281
4282         return !!(value & BIT(28));
4283 }
4284
4285 static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
4286 {
4287         return 3300000;
4288 }
4289
4290 static struct regulator_ops sh73a0_vccq_mc0_ops = {
4291         .enable = sh73a0_vccq_mc0_enable,
4292         .disable = sh73a0_vccq_mc0_disable,
4293         .is_enabled = sh73a0_vccq_mc0_is_enabled,
4294         .get_voltage = sh73a0_vccq_mc0_get_voltage,
4295 };
4296
4297 static const struct regulator_desc sh73a0_vccq_mc0_desc = {
4298         .owner = THIS_MODULE,
4299         .name = "vccq_mc0",
4300         .type = REGULATOR_VOLTAGE,
4301         .ops = &sh73a0_vccq_mc0_ops,
4302 };
4303
4304 static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
4305         REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
4306         REGULATOR_SUPPLY("vqmmc", "ee100000.sdhi"),
4307 };
4308
4309 static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
4310         .constraints = {
4311                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
4312         },
4313         .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
4314         .consumer_supplies = sh73a0_vccq_mc0_consumers,
4315 };
4316
4317 /* -----------------------------------------------------------------------------
4318  * Pin bias
4319  */
4320
4321 #define PORTnCR_PULMD_OFF       (0 << 6)
4322 #define PORTnCR_PULMD_DOWN      (2 << 6)
4323 #define PORTnCR_PULMD_UP        (3 << 6)
4324 #define PORTnCR_PULMD_MASK      (3 << 6)
4325
4326 static const unsigned int sh73a0_portcr_offsets[] = {
4327         0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
4328         0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
4329 };
4330
4331 static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
4332 {
4333         void __iomem *addr = pfc->windows->virt
4334                            + sh73a0_portcr_offsets[pin >> 5] + pin;
4335         u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
4336
4337         switch (value) {
4338         case PORTnCR_PULMD_UP:
4339                 return PIN_CONFIG_BIAS_PULL_UP;
4340         case PORTnCR_PULMD_DOWN:
4341                 return PIN_CONFIG_BIAS_PULL_DOWN;
4342         case PORTnCR_PULMD_OFF:
4343         default:
4344                 return PIN_CONFIG_BIAS_DISABLE;
4345         }
4346 }
4347
4348 static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
4349                                    unsigned int bias)
4350 {
4351         void __iomem *addr = pfc->windows->virt
4352                            + sh73a0_portcr_offsets[pin >> 5] + pin;
4353         u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
4354
4355         switch (bias) {
4356         case PIN_CONFIG_BIAS_PULL_UP:
4357                 value |= PORTnCR_PULMD_UP;
4358                 break;
4359         case PIN_CONFIG_BIAS_PULL_DOWN:
4360                 value |= PORTnCR_PULMD_DOWN;
4361                 break;
4362         }
4363
4364         iowrite8(value, addr);
4365 }
4366
4367 /* -----------------------------------------------------------------------------
4368  * SoC information
4369  */
4370
4371 static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
4372 {
4373         struct regulator_config cfg = { };
4374         struct regulator_dev *vccq;
4375         int ret;
4376
4377         cfg.dev = pfc->dev;
4378         cfg.init_data = &sh73a0_vccq_mc0_init_data;
4379         cfg.driver_data = pfc;
4380
4381         vccq = devm_regulator_register(pfc->dev, &sh73a0_vccq_mc0_desc, &cfg);
4382         if (IS_ERR(vccq)) {
4383                 ret = PTR_ERR(vccq);
4384                 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
4385                         ret);
4386                 return ret;
4387         }
4388
4389         return 0;
4390 }
4391
4392 static const struct sh_pfc_soc_operations sh73a0_pfc_ops = {
4393         .init = sh73a0_pinmux_soc_init,
4394         .get_bias = sh73a0_pinmux_get_bias,
4395         .set_bias = sh73a0_pinmux_set_bias,
4396 };
4397
4398 const struct sh_pfc_soc_info sh73a0_pinmux_info = {
4399         .name = "sh73a0_pfc",
4400         .ops = &sh73a0_pfc_ops,
4401
4402         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
4403         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
4404         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4405
4406         .pins = pinmux_pins,
4407         .nr_pins = ARRAY_SIZE(pinmux_pins),
4408         .groups = pinmux_groups,
4409         .nr_groups = ARRAY_SIZE(pinmux_groups),
4410         .functions = pinmux_functions,
4411         .nr_functions = ARRAY_SIZE(pinmux_functions),
4412
4413         .cfg_regs = pinmux_config_regs,
4414         .data_regs = pinmux_data_regs,
4415
4416         .pinmux_data = pinmux_data,
4417         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4418
4419         .gpio_irq = pinmux_irqs,
4420         .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
4421 };