2 * Allwinner A31 SoCs pinctrl driver.
4 * Copyright (C) 2014 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
16 #include <linux/of_device.h>
17 #include <linux/pinctrl/pinctrl.h>
19 #include "pinctrl-sunxi.h"
21 static const struct sunxi_desc_pin sun6i_a31_pins[] = {
22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
26 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
27 PINCTRL_SUN6I_A31), /* D0 */
28 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
29 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
30 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
31 SUNXI_FUNCTION(0x0, "gpio_in"),
32 SUNXI_FUNCTION(0x1, "gpio_out"),
33 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
34 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
35 PINCTRL_SUN6I_A31), /* D1 */
36 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
37 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
38 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
39 SUNXI_FUNCTION(0x0, "gpio_in"),
40 SUNXI_FUNCTION(0x1, "gpio_out"),
41 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
42 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
43 PINCTRL_SUN6I_A31), /* D2 */
44 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
45 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
47 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
50 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
51 PINCTRL_SUN6I_A31), /* D3 */
52 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
53 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
54 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
55 SUNXI_FUNCTION(0x0, "gpio_in"),
56 SUNXI_FUNCTION(0x1, "gpio_out"),
57 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
58 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
59 PINCTRL_SUN6I_A31), /* D4 */
60 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
61 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
62 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
63 SUNXI_FUNCTION(0x0, "gpio_in"),
64 SUNXI_FUNCTION(0x1, "gpio_out"),
65 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
66 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
67 PINCTRL_SUN6I_A31), /* D5 */
68 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
69 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
74 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
75 PINCTRL_SUN6I_A31), /* D6 */
76 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
77 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
78 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
79 SUNXI_FUNCTION(0x0, "gpio_in"),
80 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
82 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
83 PINCTRL_SUN6I_A31), /* D7 */
84 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
85 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
86 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
87 SUNXI_FUNCTION(0x0, "gpio_in"),
88 SUNXI_FUNCTION(0x1, "gpio_out"),
89 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
90 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
91 PINCTRL_SUN6I_A31), /* D8 */
92 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
93 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
94 SUNXI_FUNCTION(0x0, "gpio_in"),
95 SUNXI_FUNCTION(0x1, "gpio_out"),
96 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
97 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
98 PINCTRL_SUN6I_A31), /* D9 */
99 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
100 SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
101 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
102 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
103 SUNXI_FUNCTION(0x0, "gpio_in"),
104 SUNXI_FUNCTION(0x1, "gpio_out"),
105 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
106 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
107 PINCTRL_SUN6I_A31), /* D10 */
108 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
109 SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
110 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
111 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
112 SUNXI_FUNCTION(0x0, "gpio_in"),
113 SUNXI_FUNCTION(0x1, "gpio_out"),
114 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
115 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
116 PINCTRL_SUN6I_A31), /* D11 */
117 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
118 SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
119 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
120 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
121 SUNXI_FUNCTION(0x0, "gpio_in"),
122 SUNXI_FUNCTION(0x1, "gpio_out"),
123 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
124 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
125 PINCTRL_SUN6I_A31), /* D12 */
126 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
127 SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
128 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
129 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
130 SUNXI_FUNCTION(0x0, "gpio_in"),
131 SUNXI_FUNCTION(0x1, "gpio_out"),
132 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
133 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
134 PINCTRL_SUN6I_A31), /* D13 */
135 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
136 SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
137 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
138 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
139 SUNXI_FUNCTION(0x0, "gpio_in"),
140 SUNXI_FUNCTION(0x1, "gpio_out"),
141 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
142 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
143 PINCTRL_SUN6I_A31), /* D14 */
144 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
145 SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
146 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
147 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
148 SUNXI_FUNCTION(0x0, "gpio_in"),
149 SUNXI_FUNCTION(0x1, "gpio_out"),
150 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
151 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
152 PINCTRL_SUN6I_A31), /* D15 */
153 SUNXI_FUNCTION(0x4, "clk_out_a"),
154 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
159 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
160 PINCTRL_SUN6I_A31), /* D16 */
161 SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
162 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
163 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
164 SUNXI_FUNCTION(0x0, "gpio_in"),
165 SUNXI_FUNCTION(0x1, "gpio_out"),
166 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
167 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
168 PINCTRL_SUN6I_A31), /* D17 */
169 SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
170 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
171 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
172 SUNXI_FUNCTION(0x0, "gpio_in"),
173 SUNXI_FUNCTION(0x1, "gpio_out"),
174 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
175 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
176 PINCTRL_SUN6I_A31), /* D18 */
177 SUNXI_FUNCTION(0x4, "clk_out_b"),
178 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
179 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
180 SUNXI_FUNCTION(0x0, "gpio_in"),
181 SUNXI_FUNCTION(0x1, "gpio_out"),
182 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
183 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
184 PINCTRL_SUN6I_A31), /* D19 */
185 SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
186 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
187 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
188 SUNXI_FUNCTION(0x0, "gpio_in"),
189 SUNXI_FUNCTION(0x1, "gpio_out"),
190 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
191 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
192 PINCTRL_SUN6I_A31), /* D20 */
193 SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
194 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
195 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
199 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
200 PINCTRL_SUN6I_A31), /* D21 */
201 SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
202 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
203 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
204 SUNXI_FUNCTION(0x0, "gpio_in"),
205 SUNXI_FUNCTION(0x1, "gpio_out"),
206 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
207 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
208 PINCTRL_SUN6I_A31), /* D22 */
209 SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
210 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
211 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
212 SUNXI_FUNCTION(0x0, "gpio_in"),
213 SUNXI_FUNCTION(0x1, "gpio_out"),
214 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
215 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
216 PINCTRL_SUN6I_A31), /* D23 */
217 SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
218 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
219 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
220 SUNXI_FUNCTION(0x0, "gpio_in"),
221 SUNXI_FUNCTION(0x1, "gpio_out"),
222 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
223 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
224 PINCTRL_SUN6I_A31), /* CLK */
225 SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
226 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
227 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
228 SUNXI_FUNCTION(0x0, "gpio_in"),
229 SUNXI_FUNCTION(0x1, "gpio_out"),
230 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
231 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
232 PINCTRL_SUN6I_A31), /* DE */
233 SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
234 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
235 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
236 SUNXI_FUNCTION(0x0, "gpio_in"),
237 SUNXI_FUNCTION(0x1, "gpio_out"),
238 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
239 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
240 PINCTRL_SUN6I_A31), /* HSYNC */
241 SUNXI_FUNCTION(0x4, "clk_out_c"),
242 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
243 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
244 SUNXI_FUNCTION(0x0, "gpio_in"),
245 SUNXI_FUNCTION(0x1, "gpio_out"),
246 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
247 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
248 PINCTRL_SUN6I_A31), /* VSYNC */
249 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
255 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
256 SUNXI_FUNCTION_VARIANT(0x4, "csi",
257 PINCTRL_SUN6I_A31), /* MCLK1 */
258 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
259 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
260 SUNXI_FUNCTION(0x0, "gpio_in"),
261 SUNXI_FUNCTION(0x1, "gpio_out"),
262 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
263 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
264 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
265 SUNXI_FUNCTION(0x0, "gpio_in"),
266 SUNXI_FUNCTION(0x1, "gpio_out"),
267 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
268 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
269 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
270 SUNXI_FUNCTION(0x0, "gpio_in"),
271 SUNXI_FUNCTION(0x1, "gpio_out"),
272 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
273 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
274 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
275 SUNXI_FUNCTION(0x0, "gpio_in"),
276 SUNXI_FUNCTION(0x1, "gpio_out"),
277 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
278 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
279 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
284 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
285 SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
286 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
287 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
288 SUNXI_FUNCTION(0x0, "gpio_in"),
289 SUNXI_FUNCTION(0x1, "gpio_out"),
290 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
291 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
292 SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
293 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
294 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
295 SUNXI_FUNCTION(0x0, "gpio_in"),
296 SUNXI_FUNCTION(0x1, "gpio_out"),
297 SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
298 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
300 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
301 SUNXI_FUNCTION(0x0, "gpio_in"),
302 SUNXI_FUNCTION(0x1, "gpio_out"),
303 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
304 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
305 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
306 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
309 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
310 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
311 SUNXI_FUNCTION(0x0, "gpio_in"),
312 SUNXI_FUNCTION(0x1, "gpio_out"),
313 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
314 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
315 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
316 SUNXI_FUNCTION(0x0, "gpio_in"),
317 SUNXI_FUNCTION(0x1, "gpio_out"),
318 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
319 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
320 SUNXI_FUNCTION(0x0, "gpio_in"),
321 SUNXI_FUNCTION(0x1, "gpio_out"),
322 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out"),
326 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
327 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
328 SUNXI_FUNCTION(0x0, "gpio_in"),
329 SUNXI_FUNCTION(0x1, "gpio_out"),
330 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
331 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
332 SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
333 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
334 SUNXI_FUNCTION(0x0, "gpio_in"),
335 SUNXI_FUNCTION(0x1, "gpio_out"),
336 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
337 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
338 SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
339 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
340 SUNXI_FUNCTION(0x0, "gpio_in"),
341 SUNXI_FUNCTION(0x1, "gpio_out"),
342 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
343 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
344 SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
345 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
346 SUNXI_FUNCTION(0x0, "gpio_in"),
347 SUNXI_FUNCTION(0x1, "gpio_out"),
348 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
349 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
350 SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
351 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
352 SUNXI_FUNCTION(0x0, "gpio_in"),
353 SUNXI_FUNCTION(0x1, "gpio_out"),
354 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
355 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
356 SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
358 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out"),
360 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
361 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
362 SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
363 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
364 SUNXI_FUNCTION(0x0, "gpio_in"),
365 SUNXI_FUNCTION(0x1, "gpio_out"),
366 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
367 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
368 SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
369 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
370 SUNXI_FUNCTION(0x0, "gpio_in"),
371 SUNXI_FUNCTION(0x1, "gpio_out"),
372 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
373 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
374 SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
375 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
376 SUNXI_FUNCTION(0x0, "gpio_in"),
377 SUNXI_FUNCTION(0x1, "gpio_out"),
378 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
379 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
380 SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
381 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
382 SUNXI_FUNCTION(0x0, "gpio_in"),
383 SUNXI_FUNCTION(0x1, "gpio_out"),
384 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
385 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
386 SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
387 /* Hole in pin numbering for A31s */
388 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 16), PINCTRL_SUN6I_A31,
389 SUNXI_FUNCTION(0x0, "gpio_in"),
390 SUNXI_FUNCTION(0x1, "gpio_out"),
391 SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */
392 SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */
393 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 17), PINCTRL_SUN6I_A31,
394 SUNXI_FUNCTION(0x0, "gpio_in"),
395 SUNXI_FUNCTION(0x1, "gpio_out"),
396 SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */
397 SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */
398 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 18), PINCTRL_SUN6I_A31,
399 SUNXI_FUNCTION(0x0, "gpio_in"),
400 SUNXI_FUNCTION(0x1, "gpio_out"),
401 SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */
402 SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */
403 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 19), PINCTRL_SUN6I_A31,
404 SUNXI_FUNCTION(0x0, "gpio_in"),
405 SUNXI_FUNCTION(0x1, "gpio_out"),
406 SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */
407 SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */
408 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 20), PINCTRL_SUN6I_A31,
409 SUNXI_FUNCTION(0x0, "gpio_in"),
410 SUNXI_FUNCTION(0x1, "gpio_out"),
411 SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */
412 SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */
413 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 21), PINCTRL_SUN6I_A31,
414 SUNXI_FUNCTION(0x0, "gpio_in"),
415 SUNXI_FUNCTION(0x1, "gpio_out"),
416 SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */
417 SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */
418 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 22), PINCTRL_SUN6I_A31,
419 SUNXI_FUNCTION(0x0, "gpio_in"),
420 SUNXI_FUNCTION(0x1, "gpio_out"),
421 SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */
422 SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */
423 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 23), PINCTRL_SUN6I_A31,
424 SUNXI_FUNCTION(0x0, "gpio_in"),
425 SUNXI_FUNCTION(0x1, "gpio_out"),
426 SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */
427 SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */
428 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
429 SUNXI_FUNCTION(0x0, "gpio_in"),
430 SUNXI_FUNCTION(0x1, "gpio_out"),
431 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
432 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
433 SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
434 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
435 SUNXI_FUNCTION(0x0, "gpio_in"),
436 SUNXI_FUNCTION(0x1, "gpio_out"),
437 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
438 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
439 SUNXI_FUNCTION(0x0, "gpio_in"),
440 SUNXI_FUNCTION(0x1, "gpio_out"),
441 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
442 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
443 SUNXI_FUNCTION(0x0, "gpio_in"),
444 SUNXI_FUNCTION(0x1, "gpio_out"),
445 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
447 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
448 SUNXI_FUNCTION(0x0, "gpio_in"),
449 SUNXI_FUNCTION(0x1, "gpio_out"),
450 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
451 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
452 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
453 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out"),
455 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
456 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
457 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
458 SUNXI_FUNCTION(0x0, "gpio_in"),
459 SUNXI_FUNCTION(0x1, "gpio_out"),
460 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
461 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
462 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
463 SUNXI_FUNCTION(0x0, "gpio_in"),
464 SUNXI_FUNCTION(0x1, "gpio_out"),
465 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
466 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out"),
470 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
471 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
476 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
477 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
481 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
482 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
483 SUNXI_FUNCTION(0x0, "gpio_in"),
484 SUNXI_FUNCTION(0x1, "gpio_out"),
485 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
486 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
487 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
488 SUNXI_FUNCTION(0x0, "gpio_in"),
489 SUNXI_FUNCTION(0x1, "gpio_out"),
490 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
491 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
492 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
493 SUNXI_FUNCTION(0x0, "gpio_in"),
494 SUNXI_FUNCTION(0x1, "gpio_out"),
495 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
496 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
497 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
498 SUNXI_FUNCTION(0x0, "gpio_in"),
499 SUNXI_FUNCTION(0x1, "gpio_out"),
500 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
501 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
502 PINCTRL_SUN6I_A31)), /* VP0 */
503 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
504 SUNXI_FUNCTION(0x0, "gpio_in"),
505 SUNXI_FUNCTION(0x1, "gpio_out"),
506 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
507 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
508 PINCTRL_SUN6I_A31)), /* VN0 */
509 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
510 SUNXI_FUNCTION(0x0, "gpio_in"),
511 SUNXI_FUNCTION(0x1, "gpio_out"),
512 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
513 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
514 PINCTRL_SUN6I_A31)), /* VP1 */
515 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
516 SUNXI_FUNCTION(0x0, "gpio_in"),
517 SUNXI_FUNCTION(0x1, "gpio_out"),
518 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
519 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
520 PINCTRL_SUN6I_A31)), /* VN1 */
521 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
522 SUNXI_FUNCTION(0x0, "gpio_in"),
523 SUNXI_FUNCTION(0x1, "gpio_out"),
524 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
525 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
526 PINCTRL_SUN6I_A31)), /* VP2 */
527 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
528 SUNXI_FUNCTION(0x0, "gpio_in"),
529 SUNXI_FUNCTION(0x1, "gpio_out"),
530 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
531 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
532 PINCTRL_SUN6I_A31)), /* VN2 */
533 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
534 SUNXI_FUNCTION(0x0, "gpio_in"),
535 SUNXI_FUNCTION(0x1, "gpio_out"),
536 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
537 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
538 PINCTRL_SUN6I_A31)), /* VPC */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
540 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
543 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
544 PINCTRL_SUN6I_A31)), /* VNC */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
549 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
550 PINCTRL_SUN6I_A31)), /* VP3 */
551 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
552 SUNXI_FUNCTION(0x0, "gpio_in"),
553 SUNXI_FUNCTION(0x1, "gpio_out"),
554 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
555 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
556 PINCTRL_SUN6I_A31)), /* VN3 */
557 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
558 SUNXI_FUNCTION(0x0, "gpio_in"),
559 SUNXI_FUNCTION(0x1, "gpio_out"),
560 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
561 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
562 SUNXI_FUNCTION(0x0, "gpio_in"),
563 SUNXI_FUNCTION(0x1, "gpio_out"),
564 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
565 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
566 SUNXI_FUNCTION(0x0, "gpio_in"),
567 SUNXI_FUNCTION(0x1, "gpio_out"),
568 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
569 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
570 SUNXI_FUNCTION(0x0, "gpio_in"),
571 SUNXI_FUNCTION(0x1, "gpio_out"),
572 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
573 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
574 SUNXI_FUNCTION(0x0, "gpio_in"),
575 SUNXI_FUNCTION(0x1, "gpio_out"),
576 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
577 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
578 SUNXI_FUNCTION(0x0, "gpio_in"),
579 SUNXI_FUNCTION(0x1, "gpio_out"),
580 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
581 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
582 SUNXI_FUNCTION(0x0, "gpio_in"),
583 SUNXI_FUNCTION(0x1, "gpio_out"),
584 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
585 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
586 SUNXI_FUNCTION(0x0, "gpio_in"),
587 SUNXI_FUNCTION(0x1, "gpio_out"),
588 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
590 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
591 SUNXI_FUNCTION(0x0, "gpio_in"),
592 SUNXI_FUNCTION(0x1, "gpio_out"),
593 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
594 SUNXI_FUNCTION(0x3, "ts"), /* CLK */
595 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
596 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
597 SUNXI_FUNCTION(0x0, "gpio_in"),
598 SUNXI_FUNCTION(0x1, "gpio_out"),
599 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
600 SUNXI_FUNCTION(0x3, "ts"), /* ERR */
601 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
602 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
603 SUNXI_FUNCTION(0x0, "gpio_in"),
604 SUNXI_FUNCTION(0x1, "gpio_out"),
605 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
606 SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
607 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
608 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
609 SUNXI_FUNCTION(0x0, "gpio_in"),
610 SUNXI_FUNCTION(0x1, "gpio_out"),
611 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
612 SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
613 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
614 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
615 SUNXI_FUNCTION(0x0, "gpio_in"),
616 SUNXI_FUNCTION(0x1, "gpio_out"),
617 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
618 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
619 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
620 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
621 SUNXI_FUNCTION(0x0, "gpio_in"),
622 SUNXI_FUNCTION(0x1, "gpio_out"),
623 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
624 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
625 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
626 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
627 SUNXI_FUNCTION(0x0, "gpio_in"),
628 SUNXI_FUNCTION(0x1, "gpio_out"),
629 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
630 SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
631 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
632 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
633 SUNXI_FUNCTION(0x0, "gpio_in"),
634 SUNXI_FUNCTION(0x1, "gpio_out"),
635 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
636 SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
637 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
638 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
639 SUNXI_FUNCTION(0x0, "gpio_in"),
640 SUNXI_FUNCTION(0x1, "gpio_out"),
641 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
642 SUNXI_FUNCTION(0x3, "ts"), /* D0 */
643 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
644 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
645 SUNXI_FUNCTION(0x0, "gpio_in"),
646 SUNXI_FUNCTION(0x1, "gpio_out"),
647 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
648 SUNXI_FUNCTION(0x3, "ts"), /* D1 */
649 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
650 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
651 SUNXI_FUNCTION(0x0, "gpio_in"),
652 SUNXI_FUNCTION(0x1, "gpio_out"),
653 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
654 SUNXI_FUNCTION(0x3, "ts"), /* D2 */
655 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
656 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
657 SUNXI_FUNCTION(0x0, "gpio_in"),
658 SUNXI_FUNCTION(0x1, "gpio_out"),
659 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
660 SUNXI_FUNCTION(0x3, "ts"), /* D3 */
661 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
662 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
663 SUNXI_FUNCTION(0x0, "gpio_in"),
664 SUNXI_FUNCTION(0x1, "gpio_out"),
665 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
666 SUNXI_FUNCTION(0x3, "ts"), /* D4 */
667 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
668 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
669 SUNXI_FUNCTION(0x0, "gpio_in"),
670 SUNXI_FUNCTION(0x1, "gpio_out"),
671 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
672 SUNXI_FUNCTION(0x3, "ts"), /* D5 */
673 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
674 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
675 SUNXI_FUNCTION(0x0, "gpio_in"),
676 SUNXI_FUNCTION(0x1, "gpio_out"),
677 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
678 SUNXI_FUNCTION(0x3, "ts"), /* D6 */
679 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
680 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
681 SUNXI_FUNCTION(0x0, "gpio_in"),
682 SUNXI_FUNCTION(0x1, "gpio_out"),
683 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
684 SUNXI_FUNCTION(0x3, "ts"), /* D7 */
685 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
686 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 16), PINCTRL_SUN6I_A31,
687 SUNXI_FUNCTION(0x0, "gpio_in"),
688 SUNXI_FUNCTION(0x1, "gpio_out"),
689 SUNXI_FUNCTION(0x2, "csi"), /* MIPI CSI MCLK */
690 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */
692 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
693 SUNXI_FUNCTION(0x0, "gpio_in"),
694 SUNXI_FUNCTION(0x1, "gpio_out"),
695 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
696 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
697 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
698 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
701 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
702 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
703 SUNXI_FUNCTION(0x0, "gpio_in"),
704 SUNXI_FUNCTION(0x1, "gpio_out"),
705 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
706 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
707 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
708 SUNXI_FUNCTION(0x0, "gpio_in"),
709 SUNXI_FUNCTION(0x1, "gpio_out"),
710 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
711 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
712 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
713 SUNXI_FUNCTION(0x0, "gpio_in"),
714 SUNXI_FUNCTION(0x1, "gpio_out"),
715 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
716 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
717 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
718 SUNXI_FUNCTION(0x0, "gpio_in"),
719 SUNXI_FUNCTION(0x1, "gpio_out"),
720 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
721 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
723 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
724 SUNXI_FUNCTION(0x0, "gpio_in"),
725 SUNXI_FUNCTION(0x1, "gpio_out"),
726 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
727 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
728 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
729 SUNXI_FUNCTION(0x0, "gpio_in"),
730 SUNXI_FUNCTION(0x1, "gpio_out"),
731 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
732 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
733 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
734 SUNXI_FUNCTION(0x0, "gpio_in"),
735 SUNXI_FUNCTION(0x1, "gpio_out"),
736 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
737 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
738 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
739 SUNXI_FUNCTION(0x0, "gpio_in"),
740 SUNXI_FUNCTION(0x1, "gpio_out"),
741 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
742 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
743 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
744 SUNXI_FUNCTION(0x0, "gpio_in"),
745 SUNXI_FUNCTION(0x1, "gpio_out"),
746 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
747 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
748 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
749 SUNXI_FUNCTION(0x0, "gpio_in"),
750 SUNXI_FUNCTION(0x1, "gpio_out"),
751 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
752 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
753 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
754 SUNXI_FUNCTION(0x0, "gpio_in"),
755 SUNXI_FUNCTION(0x1, "gpio_out"),
756 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
757 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
758 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
759 SUNXI_FUNCTION(0x0, "gpio_in"),
760 SUNXI_FUNCTION(0x1, "gpio_out"),
761 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
762 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
763 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
764 SUNXI_FUNCTION(0x0, "gpio_in"),
765 SUNXI_FUNCTION(0x1, "gpio_out"),
766 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
767 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
768 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
769 SUNXI_FUNCTION(0x0, "gpio_in"),
770 SUNXI_FUNCTION(0x1, "gpio_out"),
771 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
772 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
773 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
774 SUNXI_FUNCTION(0x0, "gpio_in"),
775 SUNXI_FUNCTION(0x1, "gpio_out"),
776 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
777 SUNXI_FUNCTION_VARIANT(0x3, "usb",
778 PINCTRL_SUN6I_A31), /* DP3 */
779 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
780 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
781 SUNXI_FUNCTION(0x0, "gpio_in"),
782 SUNXI_FUNCTION(0x1, "gpio_out"),
783 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
784 SUNXI_FUNCTION_VARIANT(0x3, "usb",
785 PINCTRL_SUN6I_A31), /* DM3 */
786 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
787 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
788 SUNXI_FUNCTION(0x0, "gpio_in"),
789 SUNXI_FUNCTION(0x1, "gpio_out"),
790 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
791 SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
792 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
793 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
794 SUNXI_FUNCTION(0x0, "gpio_in"),
795 SUNXI_FUNCTION(0x1, "gpio_out"),
796 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
797 SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
798 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
799 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
800 SUNXI_FUNCTION(0x0, "gpio_in"),
801 SUNXI_FUNCTION(0x1, "gpio_out"),
802 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
803 SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
804 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
805 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
806 SUNXI_FUNCTION(0x0, "gpio_in"),
807 SUNXI_FUNCTION(0x1, "gpio_out"),
808 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
809 SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
810 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
811 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
812 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out"),
814 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
815 SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
816 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
817 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
818 SUNXI_FUNCTION(0x0, "gpio_in"),
819 SUNXI_FUNCTION(0x1, "gpio_out"),
820 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
821 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
822 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
823 SUNXI_FUNCTION(0x0, "gpio_in"),
824 SUNXI_FUNCTION(0x1, "gpio_out"),
825 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
826 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
827 /* Hole; H starts at pin 9 for A31s */
828 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 0), PINCTRL_SUN6I_A31,
829 SUNXI_FUNCTION(0x0, "gpio_in"),
830 SUNXI_FUNCTION(0x1, "gpio_out"),
831 SUNXI_FUNCTION(0x2, "nand1")), /* WE */
832 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 1), PINCTRL_SUN6I_A31,
833 SUNXI_FUNCTION(0x0, "gpio_in"),
834 SUNXI_FUNCTION(0x1, "gpio_out"),
835 SUNXI_FUNCTION(0x2, "nand1")), /* ALE */
836 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 2), PINCTRL_SUN6I_A31,
837 SUNXI_FUNCTION(0x0, "gpio_in"),
838 SUNXI_FUNCTION(0x1, "gpio_out"),
839 SUNXI_FUNCTION(0x2, "nand1")), /* CLE */
840 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 3), PINCTRL_SUN6I_A31,
841 SUNXI_FUNCTION(0x0, "gpio_in"),
842 SUNXI_FUNCTION(0x1, "gpio_out"),
843 SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */
844 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 4), PINCTRL_SUN6I_A31,
845 SUNXI_FUNCTION(0x0, "gpio_in"),
846 SUNXI_FUNCTION(0x1, "gpio_out"),
847 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
848 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 5), PINCTRL_SUN6I_A31,
849 SUNXI_FUNCTION(0x0, "gpio_in"),
850 SUNXI_FUNCTION(0x1, "gpio_out"),
851 SUNXI_FUNCTION(0x2, "nand1")), /* RE */
852 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 6), PINCTRL_SUN6I_A31,
853 SUNXI_FUNCTION(0x0, "gpio_in"),
854 SUNXI_FUNCTION(0x1, "gpio_out"),
855 SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */
856 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 7), PINCTRL_SUN6I_A31,
857 SUNXI_FUNCTION(0x0, "gpio_in"),
858 SUNXI_FUNCTION(0x1, "gpio_out"),
859 SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */
860 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 8), PINCTRL_SUN6I_A31,
861 SUNXI_FUNCTION(0x0, "gpio_in"),
862 SUNXI_FUNCTION(0x1, "gpio_out"),
863 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
864 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
865 SUNXI_FUNCTION(0x0, "gpio_in"),
866 SUNXI_FUNCTION(0x1, "gpio_out"),
867 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
868 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
869 SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
870 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
871 SUNXI_FUNCTION(0x0, "gpio_in"),
872 SUNXI_FUNCTION(0x1, "gpio_out"),
873 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
874 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
875 SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
876 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
877 SUNXI_FUNCTION(0x0, "gpio_in"),
878 SUNXI_FUNCTION(0x1, "gpio_out"),
879 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
880 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
881 SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
882 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
883 SUNXI_FUNCTION(0x0, "gpio_in"),
884 SUNXI_FUNCTION(0x1, "gpio_out"),
885 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
886 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
887 SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
888 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
889 SUNXI_FUNCTION(0x0, "gpio_in"),
890 SUNXI_FUNCTION(0x1, "gpio_out"),
891 SUNXI_FUNCTION(0x2, "pwm0")),
892 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
893 SUNXI_FUNCTION(0x0, "gpio_in"),
894 SUNXI_FUNCTION(0x1, "gpio_out"),
895 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
896 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
897 SUNXI_FUNCTION(0x0, "gpio_in"),
898 SUNXI_FUNCTION(0x1, "gpio_out"),
899 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
900 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out"),
903 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
904 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
905 SUNXI_FUNCTION(0x0, "gpio_in"),
906 SUNXI_FUNCTION(0x1, "gpio_out"),
907 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
908 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
909 SUNXI_FUNCTION(0x0, "gpio_in"),
910 SUNXI_FUNCTION(0x1, "gpio_out"),
911 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
912 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
913 SUNXI_FUNCTION(0x0, "gpio_in"),
914 SUNXI_FUNCTION(0x1, "gpio_out"),
915 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
916 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
917 SUNXI_FUNCTION(0x0, "gpio_in"),
918 SUNXI_FUNCTION(0x1, "gpio_out"),
919 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
920 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
921 SUNXI_FUNCTION(0x0, "gpio_in"),
922 SUNXI_FUNCTION(0x1, "gpio_out"),
923 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
924 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
925 SUNXI_FUNCTION(0x0, "gpio_in"),
926 SUNXI_FUNCTION(0x1, "gpio_out")),
927 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
928 SUNXI_FUNCTION(0x0, "gpio_in"),
929 SUNXI_FUNCTION(0x1, "gpio_out")),
930 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
931 SUNXI_FUNCTION(0x0, "gpio_in"),
932 SUNXI_FUNCTION(0x1, "gpio_out")),
933 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
934 SUNXI_FUNCTION(0x0, "gpio_in"),
935 SUNXI_FUNCTION(0x1, "gpio_out")),
936 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
937 SUNXI_FUNCTION(0x0, "gpio_in"),
938 SUNXI_FUNCTION(0x1, "gpio_out")),
939 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
940 SUNXI_FUNCTION(0x0, "gpio_in"),
941 SUNXI_FUNCTION(0x1, "gpio_out"),
943 * The SPDIF block is not referenced at all in the A31 user
944 * manual. However it is described in the code leaked and the
945 * configuration files supplied by vendors.
947 SUNXI_FUNCTION(0x3, "spdif")), /* SPDIF IN */
948 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
949 SUNXI_FUNCTION(0x0, "gpio_in"),
950 SUNXI_FUNCTION(0x1, "gpio_out"),
951 /* Undocumented mux function - see above */
952 SUNXI_FUNCTION(0x3, "spdif")), /* SPDIF OUT */
953 /* 2 extra pins for A31 */
954 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 29), PINCTRL_SUN6I_A31,
955 SUNXI_FUNCTION(0x0, "gpio_in"),
956 SUNXI_FUNCTION(0x1, "gpio_out"),
957 SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */
958 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 30), PINCTRL_SUN6I_A31,
959 SUNXI_FUNCTION(0x0, "gpio_in"),
960 SUNXI_FUNCTION(0x1, "gpio_out"),
961 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
964 static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
965 .pins = sun6i_a31_pins,
966 .npins = ARRAY_SIZE(sun6i_a31_pins),
970 static int sun6i_a31_pinctrl_probe(struct platform_device *pdev)
972 unsigned long variant =
973 (unsigned long)of_device_get_match_data(&pdev->dev);
975 return sunxi_pinctrl_init_with_variant(pdev,
976 &sun6i_a31_pinctrl_data,
980 static const struct of_device_id sun6i_a31_pinctrl_match[] = {
982 .compatible = "allwinner,sun6i-a31-pinctrl",
983 .data = (void *)PINCTRL_SUN6I_A31
986 .compatible = "allwinner,sun6i-a31s-pinctrl",
987 .data = (void *)PINCTRL_SUN6I_A31S
992 static struct platform_driver sun6i_a31_pinctrl_driver = {
993 .probe = sun6i_a31_pinctrl_probe,
995 .name = "sun6i-a31-pinctrl",
996 .of_match_table = sun6i_a31_pinctrl_match,
999 builtin_platform_driver(sun6i_a31_pinctrl_driver);
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