drivers/pinctrl/tegra/pinctrl-tegra.c

   1 /*
   2  * Driver for the NVIDIA Tegra pinmux
   3  *
   4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * Derived from code:
   7  * Copyright (C) 2010 Google, Inc.
   8  * Copyright (C) 2010 NVIDIA Corporation
   9  * Copyright (C) 2009-2011 ST-Ericsson AB
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms and conditions of the GNU General Public License,
  13  * version 2, as published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  * more details.
  19  */
  20
  21 #include <linux/err.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/of.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pinctrl/machine.h>
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf.h>
  30 #include <linux/slab.h>
  31
  32 #include "../core.h"
  33 #include "../pinctrl-utils.h"
  34 #include "pinctrl-tegra.h"
  35
  36 struct tegra_pmx {
  37         struct device *dev;
  38         struct pinctrl_dev *pctl;
  39
  40         const struct tegra_pinctrl_soc_data *soc;
  41         const char **group_pins;
  42
  43         int nbanks;
  44         void __iomem **regs;
  45 };
  46
  47 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
  48 {
  49         return readl(pmx->regs[bank] + reg);
  50 }
  51
  52 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
  53 {
  54         writel_relaxed(val, pmx->regs[bank] + reg);
  55         /* make sure pinmux register write completed */
  56         pmx_readl(pmx, bank, reg);
  57 }
  58
  59 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  60 {
  61         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  62
  63         return pmx->soc->ngroups;
  64 }
  65
  66 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  67                                                 unsigned group)
  68 {
  69         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  70
  71         return pmx->soc->groups[group].name;
  72 }
  73
  74 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  75                                         unsigned group,
  76                                         const unsigned **pins,
  77                                         unsigned *num_pins)
  78 {
  79         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  80
  81         *pins = pmx->soc->groups[group].pins;
  82         *num_pins = pmx->soc->groups[group].npins;
  83
  84         return 0;
  85 }
  86
  87 #ifdef CONFIG_DEBUG_FS
  88 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
  89                                        struct seq_file *s,
  90                                        unsigned offset)
  91 {
  92         seq_printf(s, " %s", dev_name(pctldev->dev));
  93 }
  94 #endif
  95
  96 static const struct cfg_param {
  97         const char *property;
  98         enum tegra_pinconf_param param;
  99 } cfg_params[] = {
 100         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
 101         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
 102         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
 103         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
 104         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
 105         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
 106         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
 107         {"nvidia,io-hv",                TEGRA_PINCONF_PARAM_RCV_SEL},
 108         {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
 109         {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
 110         {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
 111         {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
 112         {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
 113         {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
 114         {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
 115         {"nvidia,drive-type",           TEGRA_PINCONF_PARAM_DRIVE_TYPE},
 116 };
 117
 118 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 119                                            struct device_node *np,
 120                                            struct pinctrl_map **map,
 121                                            unsigned *reserved_maps,
 122                                            unsigned *num_maps)
 123 {
 124         struct device *dev = pctldev->dev;
 125         int ret, i;
 126         const char *function;
 127         u32 val;
 128         unsigned long config;
 129         unsigned long *configs = NULL;
 130         unsigned num_configs = 0;
 131         unsigned reserve;
 132         struct property *prop;
 133         const char *group;
 134
 135         ret = of_property_read_string(np, "nvidia,function", &function);
 136         if (ret < 0) {
 137                 /* EINVAL=missing, which is fine since it's optional */
 138                 if (ret != -EINVAL)
 139                         dev_err(dev,
 140                                 "could not parse property nvidia,function\n");
 141                 function = NULL;
 142         }
 143
 144         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 145                 ret = of_property_read_u32(np, cfg_params[i].property, &val);
 146                 if (!ret) {
 147                         config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
 148                         ret = pinctrl_utils_add_config(pctldev, &configs,
 149                                         &num_configs, config);
 150                         if (ret < 0)
 151                                 goto exit;
 152                 /* EINVAL=missing, which is fine since it's optional */
 153                 } else if (ret != -EINVAL) {
 154                         dev_err(dev, "could not parse property %s\n",
 155                                 cfg_params[i].property);
 156                 }
 157         }
 158
 159         reserve = 0;
 160         if (function != NULL)
 161                 reserve++;
 162         if (num_configs)
 163                 reserve++;
 164         ret = of_property_count_strings(np, "nvidia,pins");
 165         if (ret < 0) {
 166                 dev_err(dev, "could not parse property nvidia,pins\n");
 167                 goto exit;
 168         }
 169         reserve *= ret;
 170
 171         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
 172                                         num_maps, reserve);
 173         if (ret < 0)
 174                 goto exit;
 175
 176         of_property_for_each_string(np, "nvidia,pins", prop, group) {
 177                 if (function) {
 178                         ret = pinctrl_utils_add_map_mux(pctldev, map,
 179                                         reserved_maps, num_maps, group,
 180                                         function);
 181                         if (ret < 0)
 182                                 goto exit;
 183                 }
 184
 185                 if (num_configs) {
 186                         ret = pinctrl_utils_add_map_configs(pctldev, map,
 187                                         reserved_maps, num_maps, group,
 188                                         configs, num_configs,
 189                                         PIN_MAP_TYPE_CONFIGS_GROUP);
 190                         if (ret < 0)
 191                                 goto exit;
 192                 }
 193         }
 194
 195         ret = 0;
 196
 197 exit:
 198         kfree(configs);
 199         return ret;
 200 }
 201
 202 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 203                                         struct device_node *np_config,
 204                                         struct pinctrl_map **map,
 205                                         unsigned *num_maps)
 206 {
 207         unsigned reserved_maps;
 208         struct device_node *np;
 209         int ret;
 210
 211         reserved_maps = 0;
 212         *map = NULL;
 213         *num_maps = 0;
 214
 215         for_each_child_of_node(np_config, np) {
 216                 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
 217                                                       &reserved_maps, num_maps);
 218                 if (ret < 0) {
 219                         pinctrl_utils_free_map(pctldev, *map,
 220                                 *num_maps);
 221                         of_node_put(np);
 222                         return ret;
 223                 }
 224         }
 225
 226         return 0;
 227 }
 228
 229 static const struct pinctrl_ops tegra_pinctrl_ops = {
 230         .get_groups_count = tegra_pinctrl_get_groups_count,
 231         .get_group_name = tegra_pinctrl_get_group_name,
 232         .get_group_pins = tegra_pinctrl_get_group_pins,
 233 #ifdef CONFIG_DEBUG_FS
 234         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
 235 #endif
 236         .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
 237         .dt_free_map = pinctrl_utils_free_map,
 238 };
 239
 240 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 241 {
 242         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 243
 244         return pmx->soc->nfunctions;
 245 }
 246
 247 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 248                                                unsigned function)
 249 {
 250         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 251
 252         return pmx->soc->functions[function].name;
 253 }
 254
 255 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 256                                          unsigned function,
 257                                          const char * const **groups,
 258                                          unsigned * const num_groups)
 259 {
 260         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 261
 262         *groups = pmx->soc->functions[function].groups;
 263         *num_groups = pmx->soc->functions[function].ngroups;
 264
 265         return 0;
 266 }
 267
 268 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 269                                  unsigned function,
 270                                  unsigned group)
 271 {
 272         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 273         const struct tegra_pingroup *g;
 274         int i;
 275         u32 val;
 276
 277         g = &pmx->soc->groups[group];
 278
 279         if (WARN_ON(g->mux_reg < 0))
 280                 return -EINVAL;
 281
 282         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 283                 if (g->funcs[i] == function)
 284                         break;
 285         }
 286         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 287                 return -EINVAL;
 288
 289         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 290         val &= ~(0x3 << g->mux_bit);
 291         val |= i << g->mux_bit;
 292         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 293
 294         return 0;
 295 }
 296
 297 static const struct pinmux_ops tegra_pinmux_ops = {
 298         .get_functions_count = tegra_pinctrl_get_funcs_count,
 299         .get_function_name = tegra_pinctrl_get_func_name,
 300         .get_function_groups = tegra_pinctrl_get_func_groups,
 301         .set_mux = tegra_pinctrl_set_mux,
 302 };
 303
 304 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 305                              const struct tegra_pingroup *g,
 306                              enum tegra_pinconf_param param,
 307                              bool report_err,
 308                              s8 *bank, s16 *reg, s8 *bit, s8 *width)
 309 {
 310         switch (param) {
 311         case TEGRA_PINCONF_PARAM_PULL:
 312                 *bank = g->pupd_bank;
 313                 *reg = g->pupd_reg;
 314                 *bit = g->pupd_bit;
 315                 *width = 2;
 316                 break;
 317         case TEGRA_PINCONF_PARAM_TRISTATE:
 318                 *bank = g->tri_bank;
 319                 *reg = g->tri_reg;
 320                 *bit = g->tri_bit;
 321                 *width = 1;
 322                 break;
 323         case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
 324                 *bank = g->mux_bank;
 325                 *reg = g->mux_reg;
 326                 *bit = g->einput_bit;
 327                 *width = 1;
 328                 break;
 329         case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
 330                 *bank = g->mux_bank;
 331                 *reg = g->mux_reg;
 332                 *bit = g->odrain_bit;
 333                 *width = 1;
 334                 break;
 335         case TEGRA_PINCONF_PARAM_LOCK:
 336                 *bank = g->mux_bank;
 337                 *reg = g->mux_reg;
 338                 *bit = g->lock_bit;
 339                 *width = 1;
 340                 break;
 341         case TEGRA_PINCONF_PARAM_IORESET:
 342                 *bank = g->mux_bank;
 343                 *reg = g->mux_reg;
 344                 *bit = g->ioreset_bit;
 345                 *width = 1;
 346                 break;
 347         case TEGRA_PINCONF_PARAM_RCV_SEL:
 348                 *bank = g->mux_bank;
 349                 *reg = g->mux_reg;
 350                 *bit = g->rcv_sel_bit;
 351                 *width = 1;
 352                 break;
 353         case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
 354                 if (pmx->soc->hsm_in_mux) {
 355                         *bank = g->mux_bank;
 356                         *reg = g->mux_reg;
 357                 } else {
 358                         *bank = g->drv_bank;
 359                         *reg = g->drv_reg;
 360                 }
 361                 *bit = g->hsm_bit;
 362                 *width = 1;
 363                 break;
 364         case TEGRA_PINCONF_PARAM_SCHMITT:
 365                 if (pmx->soc->schmitt_in_mux) {
 366                         *bank = g->mux_bank;
 367                         *reg = g->mux_reg;
 368                 } else {
 369                         *bank = g->drv_bank;
 370                         *reg = g->drv_reg;
 371                 }
 372                 *bit = g->schmitt_bit;
 373                 *width = 1;
 374                 break;
 375         case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
 376                 *bank = g->drv_bank;
 377                 *reg = g->drv_reg;
 378                 *bit = g->lpmd_bit;
 379                 *width = 2;
 380                 break;
 381         case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
 382                 *bank = g->drv_bank;
 383                 *reg = g->drv_reg;
 384                 *bit = g->drvdn_bit;
 385                 *width = g->drvdn_width;
 386                 break;
 387         case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
 388                 *bank = g->drv_bank;
 389                 *reg = g->drv_reg;
 390                 *bit = g->drvup_bit;
 391                 *width = g->drvup_width;
 392                 break;
 393         case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
 394                 *bank = g->drv_bank;
 395                 *reg = g->drv_reg;
 396                 *bit = g->slwf_bit;
 397                 *width = g->slwf_width;
 398                 break;
 399         case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
 400                 *bank = g->drv_bank;
 401                 *reg = g->drv_reg;
 402                 *bit = g->slwr_bit;
 403                 *width = g->slwr_width;
 404                 break;
 405         case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
 406                 if (pmx->soc->drvtype_in_mux) {
 407                         *bank = g->mux_bank;
 408                         *reg = g->mux_reg;
 409                 } else {
 410                         *bank = g->drv_bank;
 411                         *reg = g->drv_reg;
 412                 }
 413                 *bit = g->drvtype_bit;
 414                 *width = 2;
 415                 break;
 416         default:
 417                 dev_err(pmx->dev, "Invalid config param %04x\n", param);
 418                 return -ENOTSUPP;
 419         }
 420
 421         if (*reg < 0 || *bit < 0)  {
 422                 if (report_err) {
 423                         const char *prop = "unknown";
 424                         int i;
 425
 426                         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 427                                 if (cfg_params[i].param == param) {
 428                                         prop = cfg_params[i].property;
 429                                         break;
 430                                 }
 431                         }
 432
 433                         dev_err(pmx->dev,
 434                                 "Config param %04x (%s) not supported on group %s\n",
 435                                 param, prop, g->name);
 436                 }
 437                 return -ENOTSUPP;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
 444                              unsigned pin, unsigned long *config)
 445 {
 446         dev_err(pctldev->dev, "pin_config_get op not supported\n");
 447         return -ENOTSUPP;
 448 }
 449
 450 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
 451                              unsigned pin, unsigned long *configs,
 452                              unsigned num_configs)
 453 {
 454         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 455         return -ENOTSUPP;
 456 }
 457
 458 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
 459                                    unsigned group, unsigned long *config)
 460 {
 461         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 462         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
 463         u16 arg;
 464         const struct tegra_pingroup *g;
 465         int ret;
 466         s8 bank, bit, width;
 467         s16 reg;
 468         u32 val, mask;
 469
 470         g = &pmx->soc->groups[group];
 471
 472         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 473                                 &width);
 474         if (ret < 0)
 475                 return ret;
 476
 477         val = pmx_readl(pmx, bank, reg);
 478         mask = (1 << width) - 1;
 479         arg = (val >> bit) & mask;
 480
 481         *config = TEGRA_PINCONF_PACK(param, arg);
 482
 483         return 0;
 484 }
 485
 486 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
 487                                    unsigned group, unsigned long *configs,
 488                                    unsigned num_configs)
 489 {
 490         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 491         enum tegra_pinconf_param param;
 492         u16 arg;
 493         const struct tegra_pingroup *g;
 494         int ret, i;
 495         s8 bank, bit, width;
 496         s16 reg;
 497         u32 val, mask;
 498
 499         g = &pmx->soc->groups[group];
 500
 501         for (i = 0; i < num_configs; i++) {
 502                 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
 503                 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
 504
 505                 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 506                                         &width);
 507                 if (ret < 0)
 508                         return ret;
 509
 510                 val = pmx_readl(pmx, bank, reg);
 511
 512                 /* LOCK can't be cleared */
 513                 if (param == TEGRA_PINCONF_PARAM_LOCK) {
 514                         if ((val & BIT(bit)) && !arg) {
 515                                 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
 516                                 return -EINVAL;
 517                         }
 518                 }
 519
 520                 /* Special-case Boolean values; allow any non-zero as true */
 521                 if (width == 1)
 522                         arg = !!arg;
 523
 524                 /* Range-check user-supplied value */
 525                 mask = (1 << width) - 1;
 526                 if (arg & ~mask) {
 527                         dev_err(pctldev->dev,
 528                                 "config %lx: %x too big for %d bit register\n",
 529                                 configs[i], arg, width);
 530                         return -EINVAL;
 531                 }
 532
 533                 /* Update register */
 534                 val &= ~(mask << bit);
 535                 val |= arg << bit;
 536                 pmx_writel(pmx, val, bank, reg);
 537         } /* for each config */
 538
 539         return 0;
 540 }
 541
 542 #ifdef CONFIG_DEBUG_FS
 543 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 544                                    struct seq_file *s, unsigned offset)
 545 {
 546 }
 547
 548 static const char *strip_prefix(const char *s)
 549 {
 550         const char *comma = strchr(s, ',');
 551         if (!comma)
 552                 return s;
 553
 554         return comma + 1;
 555 }
 556
 557 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 558                                          struct seq_file *s, unsigned group)
 559 {
 560         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 561         const struct tegra_pingroup *g;
 562         int i, ret;
 563         s8 bank, bit, width;
 564         s16 reg;
 565         u32 val;
 566
 567         g = &pmx->soc->groups[group];
 568
 569         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 570                 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
 571                                         &bank, &reg, &bit, &width);
 572                 if (ret < 0)
 573                         continue;
 574
 575                 val = pmx_readl(pmx, bank, reg);
 576                 val >>= bit;
 577                 val &= (1 << width) - 1;
 578
 579                 seq_printf(s, "\n\t%s=%u",
 580                            strip_prefix(cfg_params[i].property), val);
 581         }
 582 }
 583
 584 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 585                                           struct seq_file *s,
 586                                           unsigned long config)
 587 {
 588         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 589         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 590         const char *pname = "unknown";
 591         int i;
 592
 593         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 594                 if (cfg_params[i].param == param) {
 595                         pname = cfg_params[i].property;
 596                         break;
 597                 }
 598         }
 599
 600         seq_printf(s, "%s=%d", strip_prefix(pname), arg);
 601 }
 602 #endif
 603
 604 static const struct pinconf_ops tegra_pinconf_ops = {
 605         .pin_config_get = tegra_pinconf_get,
 606         .pin_config_set = tegra_pinconf_set,
 607         .pin_config_group_get = tegra_pinconf_group_get,
 608         .pin_config_group_set = tegra_pinconf_group_set,
 609 #ifdef CONFIG_DEBUG_FS
 610         .pin_config_dbg_show = tegra_pinconf_dbg_show,
 611         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
 612         .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
 613 #endif
 614 };
 615
 616 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
 617         .name = "Tegra GPIOs",
 618         .id = 0,
 619         .base = 0,
 620 };
 621
 622 static struct pinctrl_desc tegra_pinctrl_desc = {
 623         .pctlops = &tegra_pinctrl_ops,
 624         .pmxops = &tegra_pinmux_ops,
 625         .confops = &tegra_pinconf_ops,
 626         .owner = THIS_MODULE,
 627 };
 628
 629 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
 630 {
 631         int i = 0;
 632         const struct tegra_pingroup *g;
 633         u32 val;
 634
 635         for (i = 0; i < pmx->soc->ngroups; ++i) {
 636                 g = &pmx->soc->groups[i];
 637                 if (g->parked_bit >= 0) {
 638                         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 639                         val &= ~(1 << g->parked_bit);
 640                         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 641                 }
 642         }
 643 }
 644
 645 static bool gpio_node_has_range(void)
 646 {
 647         struct device_node *np;
 648         bool has_prop = false;
 649
 650         np = of_find_compatible_node(NULL, NULL, "nvidia,tegra30-gpio");
 651         if (!np)
 652                 return has_prop;
 653
 654         has_prop = of_find_property(np, "gpio-ranges", NULL);
 655
 656         of_node_put(np);
 657
 658         return has_prop;
 659 }
 660
 661 int tegra_pinctrl_probe(struct platform_device *pdev,
 662                         const struct tegra_pinctrl_soc_data *soc_data)
 663 {
 664         struct tegra_pmx *pmx;
 665         struct resource *res;
 666         int i;
 667         const char **group_pins;
 668         int fn, gn, gfn;
 669
 670         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
 671         if (!pmx) {
 672                 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
 673                 return -ENOMEM;
 674         }
 675         pmx->dev = &pdev->dev;
 676         pmx->soc = soc_data;
 677
 678         /*
 679          * Each mux group will appear in 4 functions' list of groups.
 680          * This over-allocates slightly, since not all groups are mux groups.
 681          */
 682         pmx->group_pins = devm_kzalloc(&pdev->dev,
 683                 soc_data->ngroups * 4 * sizeof(*pmx->group_pins),
 684                 GFP_KERNEL);
 685         if (!pmx->group_pins)
 686                 return -ENOMEM;
 687
 688         group_pins = pmx->group_pins;
 689         for (fn = 0; fn < soc_data->nfunctions; fn++) {
 690                 struct tegra_function *func = &soc_data->functions[fn];
 691
 692                 func->groups = group_pins;
 693
 694                 for (gn = 0; gn < soc_data->ngroups; gn++) {
 695                         const struct tegra_pingroup *g = &soc_data->groups[gn];
 696
 697                         if (g->mux_reg == -1)
 698                                 continue;
 699
 700                         for (gfn = 0; gfn < 4; gfn++)
 701                                 if (g->funcs[gfn] == fn)
 702                                         break;
 703                         if (gfn == 4)
 704                                 continue;
 705
 706                         BUG_ON(group_pins - pmx->group_pins >=
 707                                 soc_data->ngroups * 4);
 708                         *group_pins++ = g->name;
 709                         func->ngroups++;
 710                 }
 711         }
 712
 713         tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
 714         tegra_pinctrl_desc.name = dev_name(&pdev->dev);
 715         tegra_pinctrl_desc.pins = pmx->soc->pins;
 716         tegra_pinctrl_desc.npins = pmx->soc->npins;
 717
 718         for (i = 0; ; i++) {
 719                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 720                 if (!res)
 721                         break;
 722         }
 723         pmx->nbanks = i;
 724
 725         pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
 726                                  GFP_KERNEL);
 727         if (!pmx->regs) {
 728                 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
 729                 return -ENOMEM;
 730         }
 731
 732         for (i = 0; i < pmx->nbanks; i++) {
 733                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 734                 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
 735                 if (IS_ERR(pmx->regs[i]))
 736                         return PTR_ERR(pmx->regs[i]);
 737         }
 738
 739         pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
 740         if (IS_ERR(pmx->pctl)) {
 741                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 742                 return PTR_ERR(pmx->pctl);
 743         }
 744
 745         tegra_pinctrl_clear_parked_bits(pmx);
 746
 747         if (!gpio_node_has_range())
 748                 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
 749
 750         platform_set_drvdata(pdev, pmx);
 751
 752         dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
 753
 754         return 0;
 755 }
 756 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);