drivers/pwm/pwm-meson.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright (c) 2016 BayLibre, SAS.
   8  * Author: Neil Armstrong <narmstrong@baylibre.com>
   9  * Copyright (C) 2014 Amlogic, Inc.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  22  * The full GNU General Public License is included in this distribution
  23  * in the file called COPYING.
  24  *
  25  * BSD LICENSE
  26  *
  27  * Copyright (c) 2016 BayLibre, SAS.
  28  * Author: Neil Armstrong <narmstrong@baylibre.com>
  29  * Copyright (C) 2014 Amlogic, Inc.
  30  *
  31  * Redistribution and use in source and binary forms, with or without
  32  * modification, are permitted provided that the following conditions
  33  * are met:
  34  *
  35  *   * Redistributions of source code must retain the above copyright
  36  *     notice, this list of conditions and the following disclaimer.
  37  *   * Redistributions in binary form must reproduce the above copyright
  38  *     notice, this list of conditions and the following disclaimer in
  39  *     the documentation and/or other materials provided with the
  40  *     distribution.
  41  *   * Neither the name of Intel Corporation nor the names of its
  42  *     contributors may be used to endorse or promote products derived
  43  *     from this software without specific prior written permission.
  44  *
  45  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  46  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  47  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  48  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  49  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  50  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  51  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  52  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  53  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  54  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  55  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  56  */
  57
  58 #include <linux/clk.h>
  59 #include <linux/clk-provider.h>
  60 #include <linux/err.h>
  61 #include <linux/io.h>
  62 #include <linux/kernel.h>
  63 #include <linux/module.h>
  64 #include <linux/of.h>
  65 #include <linux/of_device.h>
  66 #include <linux/platform_device.h>
  67 #include <linux/pwm.h>
  68 #include <linux/slab.h>
  69 #include <linux/spinlock.h>
  70
  71 #define REG_PWM_A               0x0
  72 #define REG_PWM_B               0x4
  73 #define PWM_HIGH_SHIFT          16
  74
  75 #define REG_MISC_AB             0x8
  76 #define MISC_B_CLK_EN           BIT(23)
  77 #define MISC_A_CLK_EN           BIT(15)
  78 #define MISC_CLK_DIV_MASK       0x7f
  79 #define MISC_B_CLK_DIV_SHIFT    16
  80 #define MISC_A_CLK_DIV_SHIFT    8
  81 #define MISC_B_CLK_SEL_SHIFT    6
  82 #define MISC_A_CLK_SEL_SHIFT    4
  83 #define MISC_CLK_SEL_WIDTH      2
  84 #define MISC_B_EN               BIT(1)
  85 #define MISC_A_EN               BIT(0)
  86
  87 static const unsigned int mux_reg_shifts[] = {
  88         MISC_A_CLK_SEL_SHIFT,
  89         MISC_B_CLK_SEL_SHIFT
  90 };
  91
  92 struct meson_pwm_channel {
  93         unsigned int hi;
  94         unsigned int lo;
  95         u8 pre_div;
  96
  97         struct pwm_state state;
  98
  99         struct clk *clk_parent;
 100         struct clk_mux mux;
 101         struct clk *clk;
 102 };
 103
 104 struct meson_pwm_data {
 105         const char * const *parent_names;
 106 };
 107
 108 struct meson_pwm {
 109         struct pwm_chip chip;
 110         const struct meson_pwm_data *data;
 111         void __iomem *base;
 112         u8 inverter_mask;
 113         /*
 114          * Protects register (write) access to the REG_MISC_AB register
 115          * that is shared between the two PWMs.
 116          */
 117         spinlock_t lock;
 118 };
 119
 120 static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
 121 {
 122         return container_of(chip, struct meson_pwm, chip);
 123 }
 124
 125 static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
 126 {
 127         struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
 128         struct device *dev = chip->dev;
 129         int err;
 130
 131         if (!channel)
 132                 return -ENODEV;
 133
 134         if (channel->clk_parent) {
 135                 err = clk_set_parent(channel->clk, channel->clk_parent);
 136                 if (err < 0) {
 137                         dev_err(dev, "failed to set parent %s for %s: %d\n",
 138                                 __clk_get_name(channel->clk_parent),
 139                                 __clk_get_name(channel->clk), err);
 140                                 return err;
 141                 }
 142         }
 143
 144         err = clk_prepare_enable(channel->clk);
 145         if (err < 0) {
 146                 dev_err(dev, "failed to enable clock %s: %d\n",
 147                         __clk_get_name(channel->clk), err);
 148                 return err;
 149         }
 150
 151         chip->ops->get_state(chip, pwm, &channel->state);
 152
 153         return 0;
 154 }
 155
 156 static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 157 {
 158         struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
 159
 160         if (channel)
 161                 clk_disable_unprepare(channel->clk);
 162 }
 163
 164 static int meson_pwm_calc(struct meson_pwm *meson,
 165                           struct meson_pwm_channel *channel, unsigned int id,
 166                           unsigned int duty, unsigned int period)
 167 {
 168         unsigned int pre_div, cnt, duty_cnt;
 169         unsigned long fin_freq = -1, fin_ns;
 170
 171         if (~(meson->inverter_mask >> id) & 0x1)
 172                 duty = period - duty;
 173
 174         if (period == channel->state.period &&
 175             duty == channel->state.duty_cycle)
 176                 return 0;
 177
 178         fin_freq = clk_get_rate(channel->clk);
 179         if (fin_freq == 0) {
 180                 dev_err(meson->chip.dev, "invalid source clock frequency\n");
 181                 return -EINVAL;
 182         }
 183
 184         dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
 185         fin_ns = NSEC_PER_SEC / fin_freq;
 186
 187         /* Calc pre_div with the period */
 188         for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) {
 189                 cnt = DIV_ROUND_CLOSEST(period, fin_ns * (pre_div + 1));
 190                 dev_dbg(meson->chip.dev, "fin_ns=%lu pre_div=%u cnt=%u\n",
 191                         fin_ns, pre_div, cnt);
 192                 if (cnt <= 0xffff)
 193                         break;
 194         }
 195
 196         if (pre_div == MISC_CLK_DIV_MASK) {
 197                 dev_err(meson->chip.dev, "unable to get period pre_div\n");
 198                 return -EINVAL;
 199         }
 200
 201         dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
 202                 pre_div, cnt);
 203
 204         if (duty == period) {
 205                 channel->pre_div = pre_div;
 206                 channel->hi = cnt;
 207                 channel->lo = 0;
 208         } else if (duty == 0) {
 209                 channel->pre_div = pre_div;
 210                 channel->hi = 0;
 211                 channel->lo = cnt;
 212         } else {
 213                 /* Then check is we can have the duty with the same pre_div */
 214                 duty_cnt = DIV_ROUND_CLOSEST(duty, fin_ns * (pre_div + 1));
 215                 if (duty_cnt > 0xffff) {
 216                         dev_err(meson->chip.dev, "unable to get duty cycle\n");
 217                         return -EINVAL;
 218                 }
 219
 220                 dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
 221                         duty, pre_div, duty_cnt);
 222
 223                 channel->pre_div = pre_div;
 224                 channel->hi = duty_cnt;
 225                 channel->lo = cnt - duty_cnt;
 226         }
 227
 228         return 0;
 229 }
 230
 231 static void meson_pwm_enable(struct meson_pwm *meson,
 232                              struct meson_pwm_channel *channel,
 233                              unsigned int id)
 234 {
 235         u32 value, clk_shift, clk_enable, enable;
 236         unsigned int offset;
 237         unsigned long flags;
 238
 239         switch (id) {
 240         case 0:
 241                 clk_shift = MISC_A_CLK_DIV_SHIFT;
 242                 clk_enable = MISC_A_CLK_EN;
 243                 enable = MISC_A_EN;
 244                 offset = REG_PWM_A;
 245                 break;
 246
 247         case 1:
 248                 clk_shift = MISC_B_CLK_DIV_SHIFT;
 249                 clk_enable = MISC_B_CLK_EN;
 250                 enable = MISC_B_EN;
 251                 offset = REG_PWM_B;
 252                 break;
 253
 254         default:
 255                 return;
 256         }
 257
 258         spin_lock_irqsave(&meson->lock, flags);
 259
 260         value = readl(meson->base + REG_MISC_AB);
 261         value &= ~(MISC_CLK_DIV_MASK << clk_shift);
 262         value |= channel->pre_div << clk_shift;
 263         value |= clk_enable;
 264         writel(value, meson->base + REG_MISC_AB);
 265
 266         value = (channel->hi << PWM_HIGH_SHIFT) | channel->lo;
 267         writel(value, meson->base + offset);
 268
 269         value = readl(meson->base + REG_MISC_AB);
 270         value |= enable;
 271         writel(value, meson->base + REG_MISC_AB);
 272
 273         spin_unlock_irqrestore(&meson->lock, flags);
 274 }
 275
 276 static void meson_pwm_disable(struct meson_pwm *meson, unsigned int id)
 277 {
 278         u32 value, enable;
 279         unsigned long flags;
 280
 281         switch (id) {
 282         case 0:
 283                 enable = MISC_A_EN;
 284                 break;
 285
 286         case 1:
 287                 enable = MISC_B_EN;
 288                 break;
 289
 290         default:
 291                 return;
 292         }
 293
 294         spin_lock_irqsave(&meson->lock, flags);
 295
 296         value = readl(meson->base + REG_MISC_AB);
 297         value &= ~enable;
 298         writel(value, meson->base + REG_MISC_AB);
 299
 300         spin_unlock_irqrestore(&meson->lock, flags);
 301 }
 302
 303 static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 304                            struct pwm_state *state)
 305 {
 306         struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
 307         struct meson_pwm *meson = to_meson_pwm(chip);
 308         int err = 0;
 309
 310         if (!state)
 311                 return -EINVAL;
 312
 313         if (!state->enabled) {
 314                 meson_pwm_disable(meson, pwm->hwpwm);
 315                 channel->state.enabled = false;
 316
 317                 return 0;
 318         }
 319
 320         if (state->period != channel->state.period ||
 321             state->duty_cycle != channel->state.duty_cycle ||
 322             state->polarity != channel->state.polarity) {
 323                 if (state->polarity != channel->state.polarity) {
 324                         if (state->polarity == PWM_POLARITY_NORMAL)
 325                                 meson->inverter_mask |= BIT(pwm->hwpwm);
 326                         else
 327                                 meson->inverter_mask &= ~BIT(pwm->hwpwm);
 328                 }
 329
 330                 err = meson_pwm_calc(meson, channel, pwm->hwpwm,
 331                                      state->duty_cycle, state->period);
 332                 if (err < 0)
 333                         return err;
 334
 335                 channel->state.polarity = state->polarity;
 336                 channel->state.period = state->period;
 337                 channel->state.duty_cycle = state->duty_cycle;
 338         }
 339
 340         if (state->enabled && !channel->state.enabled) {
 341                 meson_pwm_enable(meson, channel, pwm->hwpwm);
 342                 channel->state.enabled = true;
 343         }
 344
 345         return 0;
 346 }
 347
 348 static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 349                                 struct pwm_state *state)
 350 {
 351         struct meson_pwm *meson = to_meson_pwm(chip);
 352         u32 value, mask;
 353
 354         if (!state)
 355                 return;
 356
 357         switch (pwm->hwpwm) {
 358         case 0:
 359                 mask = MISC_A_EN;
 360                 break;
 361
 362         case 1:
 363                 mask = MISC_B_EN;
 364                 break;
 365
 366         default:
 367                 return;
 368         }
 369
 370         value = readl(meson->base + REG_MISC_AB);
 371         state->enabled = (value & mask) != 0;
 372 }
 373
 374 static const struct pwm_ops meson_pwm_ops = {
 375         .request = meson_pwm_request,
 376         .free = meson_pwm_free,
 377         .apply = meson_pwm_apply,
 378         .get_state = meson_pwm_get_state,
 379         .owner = THIS_MODULE,
 380 };
 381
 382 static const char * const pwm_meson8b_parent_names[] = {
 383         "xtal", "vid_pll", "fclk_div4", "fclk_div3"
 384 };
 385
 386 static const struct meson_pwm_data pwm_meson8b_data = {
 387         .parent_names = pwm_meson8b_parent_names,
 388 };
 389
 390 static const char * const pwm_gxbb_parent_names[] = {
 391         "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
 392 };
 393
 394 static const struct meson_pwm_data pwm_gxbb_data = {
 395         .parent_names = pwm_gxbb_parent_names,
 396 };
 397
 398 static const struct of_device_id meson_pwm_matches[] = {
 399         { .compatible = "amlogic,meson8b-pwm", .data = &pwm_meson8b_data },
 400         { .compatible = "amlogic,meson-gxbb-pwm", .data = &pwm_gxbb_data },
 401         {},
 402 };
 403 MODULE_DEVICE_TABLE(of, meson_pwm_matches);
 404
 405 static int meson_pwm_init_channels(struct meson_pwm *meson,
 406                                    struct meson_pwm_channel *channels)
 407 {
 408         struct device *dev = meson->chip.dev;
 409         struct device_node *np = dev->of_node;
 410         struct clk_init_data init;
 411         unsigned int i;
 412         char name[255];
 413         int err;
 414
 415         for (i = 0; i < meson->chip.npwm; i++) {
 416                 struct meson_pwm_channel *channel = &channels[i];
 417
 418                 snprintf(name, sizeof(name), "%s#mux%u", np->full_name, i);
 419
 420                 init.name = name;
 421                 init.ops = &clk_mux_ops;
 422                 init.flags = CLK_IS_BASIC;
 423                 init.parent_names = meson->data->parent_names;
 424                 init.num_parents = 1 << MISC_CLK_SEL_WIDTH;
 425
 426                 channel->mux.reg = meson->base + REG_MISC_AB;
 427                 channel->mux.shift = mux_reg_shifts[i];
 428                 channel->mux.mask = BIT(MISC_CLK_SEL_WIDTH) - 1;
 429                 channel->mux.flags = 0;
 430                 channel->mux.lock = &meson->lock;
 431                 channel->mux.table = NULL;
 432                 channel->mux.hw.init = &init;
 433
 434                 channel->clk = devm_clk_register(dev, &channel->mux.hw);
 435                 if (IS_ERR(channel->clk)) {
 436                         err = PTR_ERR(channel->clk);
 437                         dev_err(dev, "failed to register %s: %d\n", name, err);
 438                         return err;
 439                 }
 440
 441                 snprintf(name, sizeof(name), "clkin%u", i);
 442
 443                 channel->clk_parent = devm_clk_get(dev, name);
 444                 if (IS_ERR(channel->clk_parent)) {
 445                         err = PTR_ERR(channel->clk_parent);
 446                         if (err == -EPROBE_DEFER)
 447                                 return err;
 448
 449                         channel->clk_parent = NULL;
 450                 }
 451         }
 452
 453         return 0;
 454 }
 455
 456 static void meson_pwm_add_channels(struct meson_pwm *meson,
 457                                    struct meson_pwm_channel *channels)
 458 {
 459         unsigned int i;
 460
 461         for (i = 0; i < meson->chip.npwm; i++)
 462                 pwm_set_chip_data(&meson->chip.pwms[i], &channels[i]);
 463 }
 464
 465 static int meson_pwm_probe(struct platform_device *pdev)
 466 {
 467         struct meson_pwm_channel *channels;
 468         struct meson_pwm *meson;
 469         struct resource *regs;
 470         int err;
 471
 472         meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
 473         if (!meson)
 474                 return -ENOMEM;
 475
 476         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 477         meson->base = devm_ioremap_resource(&pdev->dev, regs);
 478         if (IS_ERR(meson->base))
 479                 return PTR_ERR(meson->base);
 480
 481         spin_lock_init(&meson->lock);
 482         meson->chip.dev = &pdev->dev;
 483         meson->chip.ops = &meson_pwm_ops;
 484         meson->chip.base = -1;
 485         meson->chip.npwm = 2;
 486         meson->chip.of_xlate = of_pwm_xlate_with_flags;
 487         meson->chip.of_pwm_n_cells = 3;
 488
 489         meson->data = of_device_get_match_data(&pdev->dev);
 490         meson->inverter_mask = BIT(meson->chip.npwm) - 1;
 491
 492         channels = devm_kcalloc(&pdev->dev, meson->chip.npwm, sizeof(*meson),
 493                                 GFP_KERNEL);
 494         if (!channels)
 495                 return -ENOMEM;
 496
 497         err = meson_pwm_init_channels(meson, channels);
 498         if (err < 0)
 499                 return err;
 500
 501         err = pwmchip_add(&meson->chip);
 502         if (err < 0) {
 503                 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
 504                 return err;
 505         }
 506
 507         meson_pwm_add_channels(meson, channels);
 508
 509         platform_set_drvdata(pdev, meson);
 510
 511         return 0;
 512 }
 513
 514 static int meson_pwm_remove(struct platform_device *pdev)
 515 {
 516         struct meson_pwm *meson = platform_get_drvdata(pdev);
 517
 518         return pwmchip_remove(&meson->chip);
 519 }
 520
 521 static struct platform_driver meson_pwm_driver = {
 522         .driver = {
 523                 .name = "meson-pwm",
 524                 .of_match_table = meson_pwm_matches,
 525         },
 526         .probe = meson_pwm_probe,
 527         .remove = meson_pwm_remove,
 528 };
 529 module_platform_driver(meson_pwm_driver);
 530
 531 MODULE_ALIAS("platform:meson-pwm");
 532 MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
 533 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
 534 MODULE_LICENSE("Dual BSD/GPL");