drivers/remoteproc/qcom_q6v5_pil.c

   1 /*
   2  * Qualcomm Peripheral Image Loader
   3  *
   4  * Copyright (C) 2016 Linaro Ltd.
   5  * Copyright (C) 2014 Sony Mobile Communications AB
   6  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/module.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/regmap.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/remoteproc.h>
  31 #include <linux/reset.h>
  32 #include <linux/soc/qcom/mdt_loader.h>
  33 #include <linux/iopoll.h>
  34
  35 #include "remoteproc_internal.h"
  36 #include "qcom_common.h"
  37 #include "qcom_q6v5.h"
  38
  39 #include <linux/qcom_scm.h>
  40
  41 #define MPSS_CRASH_REASON_SMEM          421
  42
  43 /* RMB Status Register Values */
  44 #define RMB_PBL_SUCCESS                 0x1
  45
  46 #define RMB_MBA_XPU_UNLOCKED            0x1
  47 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED  0x2
  48 #define RMB_MBA_META_DATA_AUTH_SUCCESS  0x3
  49 #define RMB_MBA_AUTH_COMPLETE           0x4
  50
  51 /* PBL/MBA interface registers */
  52 #define RMB_MBA_IMAGE_REG               0x00
  53 #define RMB_PBL_STATUS_REG              0x04
  54 #define RMB_MBA_COMMAND_REG             0x08
  55 #define RMB_MBA_STATUS_REG              0x0C
  56 #define RMB_PMI_META_DATA_REG           0x10
  57 #define RMB_PMI_CODE_START_REG          0x14
  58 #define RMB_PMI_CODE_LENGTH_REG         0x18
  59 #define RMB_MBA_MSS_STATUS              0x40
  60 #define RMB_MBA_ALT_RESET               0x44
  61
  62 #define RMB_CMD_META_DATA_READY         0x1
  63 #define RMB_CMD_LOAD_READY              0x2
  64
  65 /* QDSP6SS Register Offsets */
  66 #define QDSP6SS_RESET_REG               0x014
  67 #define QDSP6SS_GFMUX_CTL_REG           0x020
  68 #define QDSP6SS_PWR_CTL_REG             0x030
  69 #define QDSP6SS_MEM_PWR_CTL             0x0B0
  70 #define QDSP6SS_STRAP_ACC               0x110
  71
  72 /* AXI Halt Register Offsets */
  73 #define AXI_HALTREQ_REG                 0x0
  74 #define AXI_HALTACK_REG                 0x4
  75 #define AXI_IDLE_REG                    0x8
  76
  77 #define HALT_ACK_TIMEOUT_MS             100
  78
  79 /* QDSP6SS_RESET */
  80 #define Q6SS_STOP_CORE                  BIT(0)
  81 #define Q6SS_CORE_ARES                  BIT(1)
  82 #define Q6SS_BUS_ARES_ENABLE            BIT(2)
  83
  84 /* QDSP6SS_GFMUX_CTL */
  85 #define Q6SS_CLK_ENABLE                 BIT(1)
  86
  87 /* QDSP6SS_PWR_CTL */
  88 #define Q6SS_L2DATA_SLP_NRET_N_0        BIT(0)
  89 #define Q6SS_L2DATA_SLP_NRET_N_1        BIT(1)
  90 #define Q6SS_L2DATA_SLP_NRET_N_2        BIT(2)
  91 #define Q6SS_L2TAG_SLP_NRET_N           BIT(16)
  92 #define Q6SS_ETB_SLP_NRET_N             BIT(17)
  93 #define Q6SS_L2DATA_STBY_N              BIT(18)
  94 #define Q6SS_SLP_RET_N                  BIT(19)
  95 #define Q6SS_CLAMP_IO                   BIT(20)
  96 #define QDSS_BHS_ON                     BIT(21)
  97 #define QDSS_LDO_BYP                    BIT(22)
  98
  99 /* QDSP6v56 parameters */
 100 #define QDSP6v56_LDO_BYP                BIT(25)
 101 #define QDSP6v56_BHS_ON         BIT(24)
 102 #define QDSP6v56_CLAMP_WL               BIT(21)
 103 #define QDSP6v56_CLAMP_QMC_MEM          BIT(22)
 104 #define HALT_CHECK_MAX_LOOPS            200
 105 #define QDSP6SS_XO_CBCR         0x0038
 106 #define QDSP6SS_ACC_OVERRIDE_VAL                0x20
 107
 108 /* QDSP6v65 parameters */
 109 #define QDSP6SS_SLEEP                   0x3C
 110 #define QDSP6SS_BOOT_CORE_START         0x400
 111 #define QDSP6SS_BOOT_CMD                0x404
 112 #define SLEEP_CHECK_MAX_LOOPS           200
 113 #define BOOT_FSM_TIMEOUT                10000
 114
 115 struct reg_info {
 116         struct regulator *reg;
 117         int uV;
 118         int uA;
 119 };
 120
 121 struct qcom_mss_reg_res {
 122         const char *supply;
 123         int uV;
 124         int uA;
 125 };
 126
 127 struct rproc_hexagon_res {
 128         const char *hexagon_mba_image;
 129         struct qcom_mss_reg_res *proxy_supply;
 130         struct qcom_mss_reg_res *active_supply;
 131         char **proxy_clk_names;
 132         char **reset_clk_names;
 133         char **active_clk_names;
 134         int version;
 135         bool need_mem_protection;
 136         bool has_alt_reset;
 137 };
 138
 139 struct q6v5 {
 140         struct device *dev;
 141         struct rproc *rproc;
 142
 143         void __iomem *reg_base;
 144         void __iomem *rmb_base;
 145
 146         struct regmap *halt_map;
 147         u32 halt_q6;
 148         u32 halt_modem;
 149         u32 halt_nc;
 150
 151         struct reset_control *mss_restart;
 152
 153         struct qcom_q6v5 q6v5;
 154
 155         struct clk *active_clks[8];
 156         struct clk *reset_clks[4];
 157         struct clk *proxy_clks[4];
 158         int active_clk_count;
 159         int reset_clk_count;
 160         int proxy_clk_count;
 161
 162         struct reg_info active_regs[1];
 163         struct reg_info proxy_regs[3];
 164         int active_reg_count;
 165         int proxy_reg_count;
 166
 167         bool running;
 168
 169         phys_addr_t mba_phys;
 170         void *mba_region;
 171         size_t mba_size;
 172
 173         phys_addr_t mpss_phys;
 174         phys_addr_t mpss_reloc;
 175         void *mpss_region;
 176         size_t mpss_size;
 177
 178         struct qcom_rproc_glink glink_subdev;
 179         struct qcom_rproc_subdev smd_subdev;
 180         struct qcom_rproc_ssr ssr_subdev;
 181         struct qcom_sysmon *sysmon;
 182         bool need_mem_protection;
 183         bool has_alt_reset;
 184         int mpss_perm;
 185         int mba_perm;
 186         int version;
 187 };
 188
 189 enum {
 190         MSS_MSM8916,
 191         MSS_MSM8974,
 192         MSS_MSM8996,
 193         MSS_SDM845,
 194 };
 195
 196 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
 197                                const struct qcom_mss_reg_res *reg_res)
 198 {
 199         int rc;
 200         int i;
 201
 202         if (!reg_res)
 203                 return 0;
 204
 205         for (i = 0; reg_res[i].supply; i++) {
 206                 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
 207                 if (IS_ERR(regs[i].reg)) {
 208                         rc = PTR_ERR(regs[i].reg);
 209                         if (rc != -EPROBE_DEFER)
 210                                 dev_err(dev, "Failed to get %s\n regulator",
 211                                         reg_res[i].supply);
 212                         return rc;
 213                 }
 214
 215                 regs[i].uV = reg_res[i].uV;
 216                 regs[i].uA = reg_res[i].uA;
 217         }
 218
 219         return i;
 220 }
 221
 222 static int q6v5_regulator_enable(struct q6v5 *qproc,
 223                                  struct reg_info *regs, int count)
 224 {
 225         int ret;
 226         int i;
 227
 228         for (i = 0; i < count; i++) {
 229                 if (regs[i].uV > 0) {
 230                         ret = regulator_set_voltage(regs[i].reg,
 231                                         regs[i].uV, INT_MAX);
 232                         if (ret) {
 233                                 dev_err(qproc->dev,
 234                                         "Failed to request voltage for %d.\n",
 235                                                 i);
 236                                 goto err;
 237                         }
 238                 }
 239
 240                 if (regs[i].uA > 0) {
 241                         ret = regulator_set_load(regs[i].reg,
 242                                                  regs[i].uA);
 243                         if (ret < 0) {
 244                                 dev_err(qproc->dev,
 245                                         "Failed to set regulator mode\n");
 246                                 goto err;
 247                         }
 248                 }
 249
 250                 ret = regulator_enable(regs[i].reg);
 251                 if (ret) {
 252                         dev_err(qproc->dev, "Regulator enable failed\n");
 253                         goto err;
 254                 }
 255         }
 256
 257         return 0;
 258 err:
 259         for (; i >= 0; i--) {
 260                 if (regs[i].uV > 0)
 261                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 262
 263                 if (regs[i].uA > 0)
 264                         regulator_set_load(regs[i].reg, 0);
 265
 266                 regulator_disable(regs[i].reg);
 267         }
 268
 269         return ret;
 270 }
 271
 272 static void q6v5_regulator_disable(struct q6v5 *qproc,
 273                                    struct reg_info *regs, int count)
 274 {
 275         int i;
 276
 277         for (i = 0; i < count; i++) {
 278                 if (regs[i].uV > 0)
 279                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 280
 281                 if (regs[i].uA > 0)
 282                         regulator_set_load(regs[i].reg, 0);
 283
 284                 regulator_disable(regs[i].reg);
 285         }
 286 }
 287
 288 static int q6v5_clk_enable(struct device *dev,
 289                            struct clk **clks, int count)
 290 {
 291         int rc;
 292         int i;
 293
 294         for (i = 0; i < count; i++) {
 295                 rc = clk_prepare_enable(clks[i]);
 296                 if (rc) {
 297                         dev_err(dev, "Clock enable failed\n");
 298                         goto err;
 299                 }
 300         }
 301
 302         return 0;
 303 err:
 304         for (i--; i >= 0; i--)
 305                 clk_disable_unprepare(clks[i]);
 306
 307         return rc;
 308 }
 309
 310 static void q6v5_clk_disable(struct device *dev,
 311                              struct clk **clks, int count)
 312 {
 313         int i;
 314
 315         for (i = 0; i < count; i++)
 316                 clk_disable_unprepare(clks[i]);
 317 }
 318
 319 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
 320                                    bool remote_owner, phys_addr_t addr,
 321                                    size_t size)
 322 {
 323         struct qcom_scm_vmperm next;
 324
 325         if (!qproc->need_mem_protection)
 326                 return 0;
 327         if (remote_owner && *current_perm == BIT(QCOM_SCM_VMID_MSS_MSA))
 328                 return 0;
 329         if (!remote_owner && *current_perm == BIT(QCOM_SCM_VMID_HLOS))
 330                 return 0;
 331
 332         next.vmid = remote_owner ? QCOM_SCM_VMID_MSS_MSA : QCOM_SCM_VMID_HLOS;
 333         next.perm = remote_owner ? QCOM_SCM_PERM_RW : QCOM_SCM_PERM_RWX;
 334
 335         return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
 336                                    current_perm, &next, 1);
 337 }
 338
 339 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
 340 {
 341         struct q6v5 *qproc = rproc->priv;
 342
 343         /* MBA is restricted to a maximum size of 1M */
 344         if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
 345                 dev_err(qproc->dev, "MBA firmware load failed\n");
 346                 return -EINVAL;
 347         }
 348
 349         memcpy(qproc->mba_region, fw->data, fw->size);
 350
 351         return 0;
 352 }
 353
 354 static int q6v5_reset_assert(struct q6v5 *qproc)
 355 {
 356         if (qproc->has_alt_reset)
 357                 return reset_control_reset(qproc->mss_restart);
 358         else
 359                 return reset_control_assert(qproc->mss_restart);
 360 }
 361
 362 static int q6v5_reset_deassert(struct q6v5 *qproc)
 363 {
 364         int ret;
 365
 366         if (qproc->has_alt_reset) {
 367                 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
 368                 ret = reset_control_reset(qproc->mss_restart);
 369                 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
 370         } else {
 371                 ret = reset_control_deassert(qproc->mss_restart);
 372         }
 373
 374         return ret;
 375 }
 376
 377 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
 378 {
 379         unsigned long timeout;
 380         s32 val;
 381
 382         timeout = jiffies + msecs_to_jiffies(ms);
 383         for (;;) {
 384                 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
 385                 if (val)
 386                         break;
 387
 388                 if (time_after(jiffies, timeout))
 389                         return -ETIMEDOUT;
 390
 391                 msleep(1);
 392         }
 393
 394         return val;
 395 }
 396
 397 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
 398 {
 399
 400         unsigned long timeout;
 401         s32 val;
 402
 403         timeout = jiffies + msecs_to_jiffies(ms);
 404         for (;;) {
 405                 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
 406                 if (val < 0)
 407                         break;
 408
 409                 if (!status && val)
 410                         break;
 411                 else if (status && val == status)
 412                         break;
 413
 414                 if (time_after(jiffies, timeout))
 415                         return -ETIMEDOUT;
 416
 417                 msleep(1);
 418         }
 419
 420         return val;
 421 }
 422
 423 static int q6v5proc_reset(struct q6v5 *qproc)
 424 {
 425         u32 val;
 426         int ret;
 427         int i;
 428
 429         if (qproc->version == MSS_SDM845) {
 430                 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 431                 val |= 0x1;
 432                 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 433
 434                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 435                                          val, !(val & BIT(31)), 1,
 436                                          SLEEP_CHECK_MAX_LOOPS);
 437                 if (ret) {
 438                         dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 439                         return -ETIMEDOUT;
 440                 }
 441
 442                 /* De-assert QDSP6 stop core */
 443                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 444                 /* Trigger boot FSM */
 445                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 446
 447                 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 448                                 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 449                 if (ret) {
 450                         dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 451                         /* Reset the modem so that boot FSM is in reset state */
 452                         q6v5_reset_deassert(qproc);
 453                         return ret;
 454                 }
 455
 456                 goto pbl_wait;
 457         } else if (qproc->version == MSS_MSM8996) {
 458                 /* Override the ACC value if required */
 459                 writel(QDSP6SS_ACC_OVERRIDE_VAL,
 460                        qproc->reg_base + QDSP6SS_STRAP_ACC);
 461
 462                 /* Assert resets, stop core */
 463                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 464                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 465                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 466
 467                 /* BHS require xo cbcr to be enabled */
 468                 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 469                 val |= 0x1;
 470                 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 471
 472                 /* Read CLKOFF bit to go low indicating CLK is enabled */
 473                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 474                                          val, !(val & BIT(31)), 1,
 475                                          HALT_CHECK_MAX_LOOPS);
 476                 if (ret) {
 477                         dev_err(qproc->dev,
 478                                 "xo cbcr enabling timed out (rc:%d)\n", ret);
 479                         return ret;
 480                 }
 481                 /* Enable power block headswitch and wait for it to stabilize */
 482                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 483                 val |= QDSP6v56_BHS_ON;
 484                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 485                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 486                 udelay(1);
 487
 488                 /* Put LDO in bypass mode */
 489                 val |= QDSP6v56_LDO_BYP;
 490                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 491
 492                 /* Deassert QDSP6 compiler memory clamp */
 493                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 494                 val &= ~QDSP6v56_CLAMP_QMC_MEM;
 495                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 496
 497                 /* Deassert memory peripheral sleep and L2 memory standby */
 498                 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
 499                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 500
 501                 /* Turn on L1, L2, ETB and JU memories 1 at a time */
 502                 val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
 503                 for (i = 19; i >= 0; i--) {
 504                         val |= BIT(i);
 505                         writel(val, qproc->reg_base +
 506                                                 QDSP6SS_MEM_PWR_CTL);
 507                         /*
 508                          * Read back value to ensure the write is done then
 509                          * wait for 1us for both memory peripheral and data
 510                          * array to turn on.
 511                          */
 512                         val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
 513                         udelay(1);
 514                 }
 515                 /* Remove word line clamp */
 516                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 517                 val &= ~QDSP6v56_CLAMP_WL;
 518                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 519         } else {
 520                 /* Assert resets, stop core */
 521                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 522                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 523                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 524
 525                 /* Enable power block headswitch and wait for it to stabilize */
 526                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 527                 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
 528                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 529                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 530                 udelay(1);
 531                 /*
 532                  * Turn on memories. L2 banks should be done individually
 533                  * to minimize inrush current.
 534                  */
 535                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 536                 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
 537                         Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
 538                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 539                 val |= Q6SS_L2DATA_SLP_NRET_N_2;
 540                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 541                 val |= Q6SS_L2DATA_SLP_NRET_N_1;
 542                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 543                 val |= Q6SS_L2DATA_SLP_NRET_N_0;
 544                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 545         }
 546         /* Remove IO clamp */
 547         val &= ~Q6SS_CLAMP_IO;
 548         writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 549
 550         /* Bring core out of reset */
 551         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 552         val &= ~Q6SS_CORE_ARES;
 553         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 554
 555         /* Turn on core clock */
 556         val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 557         val |= Q6SS_CLK_ENABLE;
 558         writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 559
 560         /* Start core execution */
 561         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 562         val &= ~Q6SS_STOP_CORE;
 563         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 564
 565 pbl_wait:
 566         /* Wait for PBL status */
 567         ret = q6v5_rmb_pbl_wait(qproc, 1000);
 568         if (ret == -ETIMEDOUT) {
 569                 dev_err(qproc->dev, "PBL boot timed out\n");
 570         } else if (ret != RMB_PBL_SUCCESS) {
 571                 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
 572                 ret = -EINVAL;
 573         } else {
 574                 ret = 0;
 575         }
 576
 577         return ret;
 578 }
 579
 580 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
 581                                    struct regmap *halt_map,
 582                                    u32 offset)
 583 {
 584         unsigned long timeout;
 585         unsigned int val;
 586         int ret;
 587
 588         /* Check if we're already idle */
 589         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 590         if (!ret && val)
 591                 return;
 592
 593         /* Assert halt request */
 594         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
 595
 596         /* Wait for halt */
 597         timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
 598         for (;;) {
 599                 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
 600                 if (ret || val || time_after(jiffies, timeout))
 601                         break;
 602
 603                 msleep(1);
 604         }
 605
 606         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 607         if (ret || !val)
 608                 dev_err(qproc->dev, "port failed halt\n");
 609
 610         /* Clear halt request (port will remain halted until reset) */
 611         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
 612 }
 613
 614 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
 615 {
 616         unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
 617         dma_addr_t phys;
 618         int mdata_perm;
 619         int xferop_ret;
 620         void *ptr;
 621         int ret;
 622
 623         ptr = dma_alloc_attrs(qproc->dev, fw->size, &phys, GFP_KERNEL, dma_attrs);
 624         if (!ptr) {
 625                 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
 626                 return -ENOMEM;
 627         }
 628
 629         memcpy(ptr, fw->data, fw->size);
 630
 631         /* Hypervisor mapping to access metadata by modem */
 632         mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
 633         ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm,
 634                                       true, phys, fw->size);
 635         if (ret) {
 636                 dev_err(qproc->dev,
 637                         "assigning Q6 access to metadata failed: %d\n", ret);
 638                 ret = -EAGAIN;
 639                 goto free_dma_attrs;
 640         }
 641
 642         writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
 643         writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
 644
 645         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
 646         if (ret == -ETIMEDOUT)
 647                 dev_err(qproc->dev, "MPSS header authentication timed out\n");
 648         else if (ret < 0)
 649                 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
 650
 651         /* Metadata authentication done, remove modem access */
 652         xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm,
 653                                              false, phys, fw->size);
 654         if (xferop_ret)
 655                 dev_warn(qproc->dev,
 656                          "mdt buffer not reclaimed system may become unstable\n");
 657
 658 free_dma_attrs:
 659         dma_free_attrs(qproc->dev, fw->size, ptr, phys, dma_attrs);
 660
 661         return ret < 0 ? ret : 0;
 662 }
 663
 664 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
 665 {
 666         if (phdr->p_type != PT_LOAD)
 667                 return false;
 668
 669         if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
 670                 return false;
 671
 672         if (!phdr->p_memsz)
 673                 return false;
 674
 675         return true;
 676 }
 677
 678 static int q6v5_mpss_load(struct q6v5 *qproc)
 679 {
 680         const struct elf32_phdr *phdrs;
 681         const struct elf32_phdr *phdr;
 682         const struct firmware *seg_fw;
 683         const struct firmware *fw;
 684         struct elf32_hdr *ehdr;
 685         phys_addr_t mpss_reloc;
 686         phys_addr_t boot_addr;
 687         phys_addr_t min_addr = PHYS_ADDR_MAX;
 688         phys_addr_t max_addr = 0;
 689         bool relocate = false;
 690         char seg_name[10];
 691         ssize_t offset;
 692         size_t size = 0;
 693         void *ptr;
 694         int ret;
 695         int i;
 696
 697         ret = reject_firmware(&fw, "/*(DEBLOBBED)*/", qproc->dev);
 698         if (ret < 0) {
 699                 dev_err(qproc->dev, "unable to load /*(DEBLOBBED)*/\n");
 700                 return ret;
 701         }
 702
 703         /* Initialize the RMB validator */
 704         writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
 705
 706         ret = q6v5_mpss_init_image(qproc, fw);
 707         if (ret)
 708                 goto release_firmware;
 709
 710         ehdr = (struct elf32_hdr *)fw->data;
 711         phdrs = (struct elf32_phdr *)(ehdr + 1);
 712
 713         for (i = 0; i < ehdr->e_phnum; i++) {
 714                 phdr = &phdrs[i];
 715
 716                 if (!q6v5_phdr_valid(phdr))
 717                         continue;
 718
 719                 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
 720                         relocate = true;
 721
 722                 if (phdr->p_paddr < min_addr)
 723                         min_addr = phdr->p_paddr;
 724
 725                 if (phdr->p_paddr + phdr->p_memsz > max_addr)
 726                         max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
 727         }
 728
 729         mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
 730         /* Load firmware segments */
 731         for (i = 0; i < ehdr->e_phnum; i++) {
 732                 phdr = &phdrs[i];
 733
 734                 if (!q6v5_phdr_valid(phdr))
 735                         continue;
 736
 737                 offset = phdr->p_paddr - mpss_reloc;
 738                 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
 739                         dev_err(qproc->dev, "segment outside memory range\n");
 740                         ret = -EINVAL;
 741                         goto release_firmware;
 742                 }
 743
 744                 ptr = qproc->mpss_region + offset;
 745
 746                 if (phdr->p_filesz) {
 747                         snprintf(seg_name, sizeof(seg_name), "/*(DEBLOBBED)*/", i);
 748                         ret = reject_firmware_into_buf(&seg_fw, seg_name, qproc->dev,
 749                                                         ptr, phdr->p_filesz);
 750                         if (ret) {
 751                                 dev_err(qproc->dev, "failed to load %s\n", seg_name);
 752                                 goto release_firmware;
 753                         }
 754
 755                         release_firmware(seg_fw);
 756                 }
 757
 758                 if (phdr->p_memsz > phdr->p_filesz) {
 759                         memset(ptr + phdr->p_filesz, 0,
 760                                phdr->p_memsz - phdr->p_filesz);
 761                 }
 762                 size += phdr->p_memsz;
 763         }
 764
 765         /* Transfer ownership of modem ddr region to q6 */
 766         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true,
 767                                       qproc->mpss_phys, qproc->mpss_size);
 768         if (ret) {
 769                 dev_err(qproc->dev,
 770                         "assigning Q6 access to mpss memory failed: %d\n", ret);
 771                 ret = -EAGAIN;
 772                 goto release_firmware;
 773         }
 774
 775         boot_addr = relocate ? qproc->mpss_phys : min_addr;
 776         writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
 777         writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
 778         writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
 779
 780         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
 781         if (ret == -ETIMEDOUT)
 782                 dev_err(qproc->dev, "MPSS authentication timed out\n");
 783         else if (ret < 0)
 784                 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
 785
 786 release_firmware:
 787         release_firmware(fw);
 788
 789         return ret < 0 ? ret : 0;
 790 }
 791
 792 static int q6v5_start(struct rproc *rproc)
 793 {
 794         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
 795         int xfermemop_ret;
 796         int ret;
 797
 798         qcom_q6v5_prepare(&qproc->q6v5);
 799
 800         ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
 801                                     qproc->proxy_reg_count);
 802         if (ret) {
 803                 dev_err(qproc->dev, "failed to enable proxy supplies\n");
 804                 goto disable_irqs;
 805         }
 806
 807         ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
 808                               qproc->proxy_clk_count);
 809         if (ret) {
 810                 dev_err(qproc->dev, "failed to enable proxy clocks\n");
 811                 goto disable_proxy_reg;
 812         }
 813
 814         ret = q6v5_regulator_enable(qproc, qproc->active_regs,
 815                                     qproc->active_reg_count);
 816         if (ret) {
 817                 dev_err(qproc->dev, "failed to enable supplies\n");
 818                 goto disable_proxy_clk;
 819         }
 820
 821         ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
 822                               qproc->reset_clk_count);
 823         if (ret) {
 824                 dev_err(qproc->dev, "failed to enable reset clocks\n");
 825                 goto disable_vdd;
 826         }
 827
 828         ret = q6v5_reset_deassert(qproc);
 829         if (ret) {
 830                 dev_err(qproc->dev, "failed to deassert mss restart\n");
 831                 goto disable_reset_clks;
 832         }
 833
 834         ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
 835                               qproc->active_clk_count);
 836         if (ret) {
 837                 dev_err(qproc->dev, "failed to enable clocks\n");
 838                 goto assert_reset;
 839         }
 840
 841         /* Assign MBA image access in DDR to q6 */
 842         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
 843                                       qproc->mba_phys, qproc->mba_size);
 844         if (ret) {
 845                 dev_err(qproc->dev,
 846                         "assigning Q6 access to mba memory failed: %d\n", ret);
 847                 goto disable_active_clks;
 848         }
 849
 850         writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
 851
 852         ret = q6v5proc_reset(qproc);
 853         if (ret)
 854                 goto reclaim_mba;
 855
 856         ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
 857         if (ret == -ETIMEDOUT) {
 858                 dev_err(qproc->dev, "MBA boot timed out\n");
 859                 goto halt_axi_ports;
 860         } else if (ret != RMB_MBA_XPU_UNLOCKED &&
 861                    ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
 862                 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
 863                 ret = -EINVAL;
 864                 goto halt_axi_ports;
 865         }
 866
 867         dev_info(qproc->dev, "MBA booted, loading mpss\n");
 868
 869         ret = q6v5_mpss_load(qproc);
 870         if (ret)
 871                 goto reclaim_mpss;
 872
 873         ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
 874         if (ret == -ETIMEDOUT) {
 875                 dev_err(qproc->dev, "start timed out\n");
 876                 goto reclaim_mpss;
 877         }
 878
 879         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
 880                                                 qproc->mba_phys,
 881                                                 qproc->mba_size);
 882         if (xfermemop_ret)
 883                 dev_err(qproc->dev,
 884                         "Failed to reclaim mba buffer system may become unstable\n");
 885         qproc->running = true;
 886
 887         return 0;
 888
 889 reclaim_mpss:
 890         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
 891                                                 false, qproc->mpss_phys,
 892                                                 qproc->mpss_size);
 893         WARN_ON(xfermemop_ret);
 894
 895 halt_axi_ports:
 896         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
 897         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
 898         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 899
 900 reclaim_mba:
 901         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
 902                                                 qproc->mba_phys,
 903                                                 qproc->mba_size);
 904         if (xfermemop_ret) {
 905                 dev_err(qproc->dev,
 906                         "Failed to reclaim mba buffer, system may become unstable\n");
 907         }
 908
 909 disable_active_clks:
 910         q6v5_clk_disable(qproc->dev, qproc->active_clks,
 911                          qproc->active_clk_count);
 912
 913 assert_reset:
 914         q6v5_reset_assert(qproc);
 915 disable_reset_clks:
 916         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
 917                          qproc->reset_clk_count);
 918 disable_vdd:
 919         q6v5_regulator_disable(qproc, qproc->active_regs,
 920                                qproc->active_reg_count);
 921 disable_proxy_clk:
 922         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
 923                          qproc->proxy_clk_count);
 924 disable_proxy_reg:
 925         q6v5_regulator_disable(qproc, qproc->proxy_regs,
 926                                qproc->proxy_reg_count);
 927
 928 disable_irqs:
 929         qcom_q6v5_unprepare(&qproc->q6v5);
 930
 931         return ret;
 932 }
 933
 934 static int q6v5_stop(struct rproc *rproc)
 935 {
 936         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
 937         int ret;
 938         u32 val;
 939
 940         qproc->running = false;
 941
 942         ret = qcom_q6v5_request_stop(&qproc->q6v5);
 943         if (ret == -ETIMEDOUT)
 944                 dev_err(qproc->dev, "timed out on wait\n");
 945
 946         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
 947         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
 948         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 949         if (qproc->version == MSS_MSM8996) {
 950                 /*
 951                  * To avoid high MX current during LPASS/MSS restart.
 952                  */
 953                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 954                 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
 955                         QDSP6v56_CLAMP_QMC_MEM;
 956                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 957         }
 958
 959
 960         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false,
 961                                       qproc->mpss_phys, qproc->mpss_size);
 962         WARN_ON(ret);
 963
 964         q6v5_reset_assert(qproc);
 965
 966         ret = qcom_q6v5_unprepare(&qproc->q6v5);
 967         if (ret) {
 968                 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
 969                                  qproc->proxy_clk_count);
 970                 q6v5_regulator_disable(qproc, qproc->proxy_regs,
 971                                        qproc->proxy_reg_count);
 972         }
 973
 974         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
 975                          qproc->reset_clk_count);
 976         q6v5_clk_disable(qproc->dev, qproc->active_clks,
 977                          qproc->active_clk_count);
 978         q6v5_regulator_disable(qproc, qproc->active_regs,
 979                                qproc->active_reg_count);
 980
 981         return 0;
 982 }
 983
 984 static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
 985 {
 986         struct q6v5 *qproc = rproc->priv;
 987         int offset;
 988
 989         offset = da - qproc->mpss_reloc;
 990         if (offset < 0 || offset + len > qproc->mpss_size)
 991                 return NULL;
 992
 993         return qproc->mpss_region + offset;
 994 }
 995
 996 static const struct rproc_ops q6v5_ops = {
 997         .start = q6v5_start,
 998         .stop = q6v5_stop,
 999         .da_to_va = q6v5_da_to_va,
1000         .load = q6v5_load,
1001 };
1002
1003 static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1004 {
1005         struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1006
1007         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1008                          qproc->proxy_clk_count);
1009         q6v5_regulator_disable(qproc, qproc->proxy_regs,
1010                                qproc->proxy_reg_count);
1011 }
1012
1013 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1014 {
1015         struct of_phandle_args args;
1016         struct resource *res;
1017         int ret;
1018
1019         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
1020         qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
1021         if (IS_ERR(qproc->reg_base))
1022                 return PTR_ERR(qproc->reg_base);
1023
1024         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
1025         qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
1026         if (IS_ERR(qproc->rmb_base))
1027                 return PTR_ERR(qproc->rmb_base);
1028
1029         ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1030                                                "qcom,halt-regs", 3, 0, &args);
1031         if (ret < 0) {
1032                 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1033                 return -EINVAL;
1034         }
1035
1036         qproc->halt_map = syscon_node_to_regmap(args.np);
1037         of_node_put(args.np);
1038         if (IS_ERR(qproc->halt_map))
1039                 return PTR_ERR(qproc->halt_map);
1040
1041         qproc->halt_q6 = args.args[0];
1042         qproc->halt_modem = args.args[1];
1043         qproc->halt_nc = args.args[2];
1044
1045         return 0;
1046 }
1047
1048 static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1049                 char **clk_names)
1050 {
1051         int i;
1052
1053         if (!clk_names)
1054                 return 0;
1055
1056         for (i = 0; clk_names[i]; i++) {
1057                 clks[i] = devm_clk_get(dev, clk_names[i]);
1058                 if (IS_ERR(clks[i])) {
1059                         int rc = PTR_ERR(clks[i]);
1060
1061                         if (rc != -EPROBE_DEFER)
1062                                 dev_err(dev, "Failed to get %s clock\n",
1063                                         clk_names[i]);
1064                         return rc;
1065                 }
1066         }
1067
1068         return i;
1069 }
1070
1071 static int q6v5_init_reset(struct q6v5 *qproc)
1072 {
1073         qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1074                                                               NULL);
1075         if (IS_ERR(qproc->mss_restart)) {
1076                 dev_err(qproc->dev, "failed to acquire mss restart\n");
1077                 return PTR_ERR(qproc->mss_restart);
1078         }
1079
1080         return 0;
1081 }
1082
1083 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1084 {
1085         struct device_node *child;
1086         struct device_node *node;
1087         struct resource r;
1088         int ret;
1089
1090         child = of_get_child_by_name(qproc->dev->of_node, "mba");
1091         node = of_parse_phandle(child, "memory-region", 0);
1092         ret = of_address_to_resource(node, 0, &r);
1093         if (ret) {
1094                 dev_err(qproc->dev, "unable to resolve mba region\n");
1095                 return ret;
1096         }
1097         of_node_put(node);
1098
1099         qproc->mba_phys = r.start;
1100         qproc->mba_size = resource_size(&r);
1101         qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
1102         if (!qproc->mba_region) {
1103                 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1104                         &r.start, qproc->mba_size);
1105                 return -EBUSY;
1106         }
1107
1108         child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1109         node = of_parse_phandle(child, "memory-region", 0);
1110         ret = of_address_to_resource(node, 0, &r);
1111         if (ret) {
1112                 dev_err(qproc->dev, "unable to resolve mpss region\n");
1113                 return ret;
1114         }
1115         of_node_put(node);
1116
1117         qproc->mpss_phys = qproc->mpss_reloc = r.start;
1118         qproc->mpss_size = resource_size(&r);
1119         qproc->mpss_region = devm_ioremap_wc(qproc->dev, qproc->mpss_phys, qproc->mpss_size);
1120         if (!qproc->mpss_region) {
1121                 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1122                         &r.start, qproc->mpss_size);
1123                 return -EBUSY;
1124         }
1125
1126         return 0;
1127 }
1128
1129 static int q6v5_probe(struct platform_device *pdev)
1130 {
1131         const struct rproc_hexagon_res *desc;
1132         struct q6v5 *qproc;
1133         struct rproc *rproc;
1134         int ret;
1135
1136         desc = of_device_get_match_data(&pdev->dev);
1137         if (!desc)
1138                 return -EINVAL;
1139
1140         if (desc->need_mem_protection && !qcom_scm_is_available())
1141                 return -EPROBE_DEFER;
1142
1143         rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1144                             desc->hexagon_mba_image, sizeof(*qproc));
1145         if (!rproc) {
1146                 dev_err(&pdev->dev, "failed to allocate rproc\n");
1147                 return -ENOMEM;
1148         }
1149
1150         qproc = (struct q6v5 *)rproc->priv;
1151         qproc->dev = &pdev->dev;
1152         qproc->rproc = rproc;
1153         platform_set_drvdata(pdev, qproc);
1154
1155         ret = q6v5_init_mem(qproc, pdev);
1156         if (ret)
1157                 goto free_rproc;
1158
1159         ret = q6v5_alloc_memory_region(qproc);
1160         if (ret)
1161                 goto free_rproc;
1162
1163         ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1164                                desc->proxy_clk_names);
1165         if (ret < 0) {
1166                 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
1167                 goto free_rproc;
1168         }
1169         qproc->proxy_clk_count = ret;
1170
1171         ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
1172                                desc->reset_clk_names);
1173         if (ret < 0) {
1174                 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
1175                 goto free_rproc;
1176         }
1177         qproc->reset_clk_count = ret;
1178
1179         ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1180                                desc->active_clk_names);
1181         if (ret < 0) {
1182                 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1183                 goto free_rproc;
1184         }
1185         qproc->active_clk_count = ret;
1186
1187         ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1188                                   desc->proxy_supply);
1189         if (ret < 0) {
1190                 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1191                 goto free_rproc;
1192         }
1193         qproc->proxy_reg_count = ret;
1194
1195         ret = q6v5_regulator_init(&pdev->dev,  qproc->active_regs,
1196                                   desc->active_supply);
1197         if (ret < 0) {
1198                 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1199                 goto free_rproc;
1200         }
1201         qproc->active_reg_count = ret;
1202
1203         ret = q6v5_init_reset(qproc);
1204         if (ret)
1205                 goto free_rproc;
1206
1207         qproc->version = desc->version;
1208         qproc->has_alt_reset = desc->has_alt_reset;
1209         qproc->need_mem_protection = desc->need_mem_protection;
1210
1211         ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
1212                              qcom_msa_handover);
1213         if (ret)
1214                 goto free_rproc;
1215
1216         qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
1217         qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
1218         qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
1219         qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1220         qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1221         qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
1222
1223         ret = rproc_add(rproc);
1224         if (ret)
1225                 goto free_rproc;
1226
1227         return 0;
1228
1229 free_rproc:
1230         rproc_free(rproc);
1231
1232         return ret;
1233 }
1234
1235 static int q6v5_remove(struct platform_device *pdev)
1236 {
1237         struct q6v5 *qproc = platform_get_drvdata(pdev);
1238
1239         rproc_del(qproc->rproc);
1240
1241         qcom_remove_sysmon_subdev(qproc->sysmon);
1242         qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
1243         qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
1244         qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
1245         rproc_free(qproc->rproc);
1246
1247         return 0;
1248 }
1249
1250 static const struct rproc_hexagon_res sdm845_mss = {
1251         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1252         .proxy_clk_names = (char*[]){
1253                         "xo",
1254                         "prng",
1255                         NULL
1256         },
1257         .reset_clk_names = (char*[]){
1258                         "iface",
1259                         "snoc_axi",
1260                         NULL
1261         },
1262         .active_clk_names = (char*[]){
1263                         "bus",
1264                         "mem",
1265                         "gpll0_mss",
1266                         "mnoc_axi",
1267                         NULL
1268         },
1269         .need_mem_protection = true,
1270         .has_alt_reset = true,
1271         .version = MSS_SDM845,
1272 };
1273
1274 static const struct rproc_hexagon_res msm8996_mss = {
1275         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1276         .proxy_supply = (struct qcom_mss_reg_res[]) {
1277                 {
1278                         .supply = "pll",
1279                         .uA = 100000,
1280                 },
1281                 {}
1282         },
1283         .proxy_clk_names = (char*[]){
1284                         "xo",
1285                         "pnoc",
1286                         "qdss",
1287                         NULL
1288         },
1289         .active_clk_names = (char*[]){
1290                         "iface",
1291                         "bus",
1292                         "mem",
1293                         "gpll0_mss",
1294                         "snoc_axi",
1295                         "mnoc_axi",
1296                         NULL
1297         },
1298         .need_mem_protection = true,
1299         .has_alt_reset = false,
1300         .version = MSS_MSM8996,
1301 };
1302
1303 static const struct rproc_hexagon_res msm8916_mss = {
1304         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1305         .proxy_supply = (struct qcom_mss_reg_res[]) {
1306                 {
1307                         .supply = "mx",
1308                         .uV = 1050000,
1309                 },
1310                 {
1311                         .supply = "cx",
1312                         .uA = 100000,
1313                 },
1314                 {
1315                         .supply = "pll",
1316                         .uA = 100000,
1317                 },
1318                 {}
1319         },
1320         .proxy_clk_names = (char*[]){
1321                 "xo",
1322                 NULL
1323         },
1324         .active_clk_names = (char*[]){
1325                 "iface",
1326                 "bus",
1327                 "mem",
1328                 NULL
1329         },
1330         .need_mem_protection = false,
1331         .has_alt_reset = false,
1332         .version = MSS_MSM8916,
1333 };
1334
1335 static const struct rproc_hexagon_res msm8974_mss = {
1336         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1337         .proxy_supply = (struct qcom_mss_reg_res[]) {
1338                 {
1339                         .supply = "mx",
1340                         .uV = 1050000,
1341                 },
1342                 {
1343                         .supply = "cx",
1344                         .uA = 100000,
1345                 },
1346                 {
1347                         .supply = "pll",
1348                         .uA = 100000,
1349                 },
1350                 {}
1351         },
1352         .active_supply = (struct qcom_mss_reg_res[]) {
1353                 {
1354                         .supply = "mss",
1355                         .uV = 1050000,
1356                         .uA = 100000,
1357                 },
1358                 {}
1359         },
1360         .proxy_clk_names = (char*[]){
1361                 "xo",
1362                 NULL
1363         },
1364         .active_clk_names = (char*[]){
1365                 "iface",
1366                 "bus",
1367                 "mem",
1368                 NULL
1369         },
1370         .need_mem_protection = false,
1371         .has_alt_reset = false,
1372         .version = MSS_MSM8974,
1373 };
1374
1375 static const struct of_device_id q6v5_of_match[] = {
1376         { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
1377         { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
1378         { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
1379         { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
1380         { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
1381         { },
1382 };
1383 MODULE_DEVICE_TABLE(of, q6v5_of_match);
1384
1385 static struct platform_driver q6v5_driver = {
1386         .probe = q6v5_probe,
1387         .remove = q6v5_remove,
1388         .driver = {
1389                 .name = "qcom-q6v5-pil",
1390                 .of_match_table = q6v5_of_match,
1391         },
1392 };
1393 module_platform_driver(q6v5_driver);
1394
1395 MODULE_DESCRIPTION("Peripheral Image Loader for Hexagon");
1396 MODULE_LICENSE("GPL v2");