2 * An RTC driver for Allwinner A31/A23
4 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
8 * An RTC driver for Allwinner A10/A20
10 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
23 #include <linux/clk.h>
24 #include <linux/clk-provider.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
34 #include <linux/of_address.h>
35 #include <linux/of_device.h>
36 #include <linux/platform_device.h>
37 #include <linux/rtc.h>
38 #include <linux/slab.h>
39 #include <linux/types.h>
41 /* Control register */
42 #define SUN6I_LOSC_CTRL 0x0000
43 #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
44 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9)
45 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8)
46 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7)
47 #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0)
48 #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)
50 #define SUN6I_LOSC_CLK_PRESCAL 0x0008
53 #define SUN6I_RTC_YMD 0x0010
54 #define SUN6I_RTC_HMS 0x0014
56 /* Alarm 0 (counter) */
57 #define SUN6I_ALRM_COUNTER 0x0020
58 #define SUN6I_ALRM_CUR_VAL 0x0024
59 #define SUN6I_ALRM_EN 0x0028
60 #define SUN6I_ALRM_EN_CNT_EN BIT(0)
61 #define SUN6I_ALRM_IRQ_EN 0x002c
62 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
63 #define SUN6I_ALRM_IRQ_STA 0x0030
64 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
66 /* Alarm 1 (wall clock) */
67 #define SUN6I_ALRM1_EN 0x0044
68 #define SUN6I_ALRM1_IRQ_EN 0x0048
69 #define SUN6I_ALRM1_IRQ_STA 0x004c
70 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0)
73 #define SUN6I_ALARM_CONFIG 0x0050
74 #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
76 #define SUN6I_LOSC_OUT_GATING 0x0060
77 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0
82 #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f)
83 #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
84 #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16)
85 #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22)
90 #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f)
91 #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
92 #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
97 #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f)
98 #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00)
99 #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000)
100 #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000)
105 #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f)
106 #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00)
107 #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000)
110 * The year parameter passed to the driver is usually an offset relative to
111 * the year 1900. This macro is used to convert this offset to another one
112 * relative to the minimum year allowed by the hardware.
114 * The year range is 1970 - 2033. This range is selected to match Allwinner's
115 * driver, even though it is somewhat limited.
117 #define SUN6I_YEAR_MIN 1970
118 #define SUN6I_YEAR_MAX 2033
119 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900)
121 struct sun6i_rtc_dev {
122 struct rtc_device *rtc;
129 struct clk_hw *int_osc;
131 struct clk *ext_losc;
136 static struct sun6i_rtc_dev *sun6i_rtc;
138 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
139 unsigned long parent_rate)
141 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
144 val = readl(rtc->base + SUN6I_LOSC_CTRL);
145 if (val & SUN6I_LOSC_CTRL_EXT_OSC)
148 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
149 val &= GENMASK(4, 0);
151 return parent_rate / (val + 1);
154 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
156 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
158 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
161 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
163 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
170 spin_lock_irqsave(&rtc->lock, flags);
171 val = readl(rtc->base + SUN6I_LOSC_CTRL);
172 val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
173 val |= SUN6I_LOSC_CTRL_KEY;
174 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
175 writel(val, rtc->base + SUN6I_LOSC_CTRL);
176 spin_unlock_irqrestore(&rtc->lock, flags);
181 static const struct clk_ops sun6i_rtc_osc_ops = {
182 .recalc_rate = sun6i_rtc_osc_recalc_rate,
184 .get_parent = sun6i_rtc_osc_get_parent,
185 .set_parent = sun6i_rtc_osc_set_parent,
188 static void __init sun6i_rtc_clk_init(struct device_node *node)
190 struct clk_hw_onecell_data *clk_data;
191 struct sun6i_rtc_dev *rtc;
192 struct clk_init_data init = {
193 .ops = &sun6i_rtc_osc_ops,
195 const char *clkout_name = "osc32k-out";
196 const char *parents[2];
198 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
202 clk_data = kzalloc(sizeof(*clk_data) + (sizeof(*clk_data->hws) * 2),
209 spin_lock_init(&rtc->lock);
211 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
212 if (IS_ERR(rtc->base)) {
213 pr_crit("Can't map RTC registers");
217 /* Switch to the external, more precise, oscillator */
218 writel(SUN6I_LOSC_CTRL_KEY | SUN6I_LOSC_CTRL_EXT_OSC,
219 rtc->base + SUN6I_LOSC_CTRL);
221 /* Yes, I know, this is ugly. */
224 /* Deal with old DTs */
225 if (!of_get_property(node, "clocks", NULL))
228 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
233 if (IS_ERR(rtc->int_osc)) {
234 pr_crit("Couldn't register the internal oscillator\n");
238 parents[0] = clk_hw_get_name(rtc->int_osc);
239 parents[1] = of_clk_get_parent_name(node, 0);
241 rtc->hw.init = &init;
243 init.parent_names = parents;
244 init.num_parents = of_clk_get_parent_count(node) + 1;
245 of_property_read_string_index(node, "clock-output-names", 0,
248 rtc->losc = clk_register(NULL, &rtc->hw);
249 if (IS_ERR(rtc->losc)) {
250 pr_crit("Couldn't register the LOSC clock\n");
254 of_property_read_string_index(node, "clock-output-names", 1,
256 rtc->ext_losc = clk_register_gate(NULL, clkout_name, rtc->hw.init->name,
257 0, rtc->base + SUN6I_LOSC_OUT_GATING,
258 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
260 if (IS_ERR(rtc->ext_losc)) {
261 pr_crit("Couldn't register the LOSC external gate\n");
266 clk_data->hws[0] = &rtc->hw;
267 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
268 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
272 clk_hw_unregister_fixed_rate(rtc->int_osc);
276 CLK_OF_DECLARE_DRIVER(sun6i_rtc_clk, "allwinner,sun6i-a31-rtc",
279 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
281 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
282 irqreturn_t ret = IRQ_NONE;
285 spin_lock(&chip->lock);
286 val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
288 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
289 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
290 writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
292 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
296 spin_unlock(&chip->lock);
301 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
304 u32 alrm_irq_val = 0;
305 u32 alrm_wake_val = 0;
309 alrm_val = SUN6I_ALRM_EN_CNT_EN;
310 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
311 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
313 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
314 chip->base + SUN6I_ALRM_IRQ_STA);
317 spin_lock_irqsave(&chip->lock, flags);
318 writel(alrm_val, chip->base + SUN6I_ALRM_EN);
319 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
320 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
321 spin_unlock_irqrestore(&chip->lock, flags);
324 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
326 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
330 * read again in case it changes
333 date = readl(chip->base + SUN6I_RTC_YMD);
334 time = readl(chip->base + SUN6I_RTC_HMS);
335 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
336 (time != readl(chip->base + SUN6I_RTC_HMS)));
338 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time);
339 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
340 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
342 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
343 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date);
344 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
349 * switch from (data_year->min)-relative offset to
350 * a (1900)-relative one
352 rtc_tm->tm_year += SUN6I_YEAR_OFF;
357 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
359 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
364 spin_lock_irqsave(&chip->lock, flags);
365 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
366 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
367 spin_unlock_irqrestore(&chip->lock, flags);
369 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
370 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
371 rtc_time_to_tm(chip->alarm, &wkalrm->time);
376 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
378 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
379 struct rtc_time *alrm_tm = &wkalrm->time;
380 struct rtc_time tm_now;
381 unsigned long time_now = 0;
382 unsigned long time_set = 0;
383 unsigned long time_gap = 0;
386 ret = sun6i_rtc_gettime(dev, &tm_now);
388 dev_err(dev, "Error in getting time\n");
392 rtc_tm_to_time(alrm_tm, &time_set);
393 rtc_tm_to_time(&tm_now, &time_now);
394 if (time_set <= time_now) {
395 dev_err(dev, "Date to set in the past\n");
399 time_gap = time_set - time_now;
401 if (time_gap > U32_MAX) {
402 dev_err(dev, "Date too far in the future\n");
406 sun6i_rtc_setaie(0, chip);
407 writel(0, chip->base + SUN6I_ALRM_COUNTER);
408 usleep_range(100, 300);
410 writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
411 chip->alarm = time_set;
413 sun6i_rtc_setaie(wkalrm->enabled, chip);
418 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
419 unsigned int mask, unsigned int ms_timeout)
421 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
425 reg = readl(chip->base + offset);
431 } while (time_before(jiffies, timeout));
436 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
438 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
443 year = rtc_tm->tm_year + 1900;
444 if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) {
445 dev_err(dev, "rtc only supports year in range %d - %d\n",
446 SUN6I_YEAR_MIN, SUN6I_YEAR_MAX);
450 rtc_tm->tm_year -= SUN6I_YEAR_OFF;
453 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
454 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
455 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
457 if (is_leap_year(year))
458 date |= SUN6I_LEAP_SET_VALUE(1);
460 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
461 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
462 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
464 /* Check whether registers are writable */
465 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
466 SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
467 dev_err(dev, "rtc is still busy.\n");
471 writel(time, chip->base + SUN6I_RTC_HMS);
474 * After writing the RTC HH-MM-SS register, the
475 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
476 * be cleared until the real writing operation is finished
479 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
480 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
481 dev_err(dev, "Failed to set rtc time.\n");
485 writel(date, chip->base + SUN6I_RTC_YMD);
488 * After writing the RTC YY-MM-DD register, the
489 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
490 * be cleared until the real writing operation is finished
493 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
494 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
495 dev_err(dev, "Failed to set rtc time.\n");
502 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
504 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
507 sun6i_rtc_setaie(enabled, chip);
512 static const struct rtc_class_ops sun6i_rtc_ops = {
513 .read_time = sun6i_rtc_gettime,
514 .set_time = sun6i_rtc_settime,
515 .read_alarm = sun6i_rtc_getalarm,
516 .set_alarm = sun6i_rtc_setalarm,
517 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable
520 static int sun6i_rtc_probe(struct platform_device *pdev)
522 struct sun6i_rtc_dev *chip = sun6i_rtc;
528 platform_set_drvdata(pdev, chip);
529 chip->dev = &pdev->dev;
531 chip->irq = platform_get_irq(pdev, 0);
533 dev_err(&pdev->dev, "No IRQ resource\n");
537 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
538 0, dev_name(&pdev->dev), chip);
540 dev_err(&pdev->dev, "Could not request IRQ\n");
544 /* clear the alarm counter value */
545 writel(0, chip->base + SUN6I_ALRM_COUNTER);
547 /* disable counter alarm */
548 writel(0, chip->base + SUN6I_ALRM_EN);
550 /* disable counter alarm interrupt */
551 writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
553 /* disable week alarm */
554 writel(0, chip->base + SUN6I_ALRM1_EN);
556 /* disable week alarm interrupt */
557 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
559 /* clear counter alarm pending interrupts */
560 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
561 chip->base + SUN6I_ALRM_IRQ_STA);
563 /* clear week alarm pending interrupts */
564 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
565 chip->base + SUN6I_ALRM1_IRQ_STA);
567 /* disable alarm wakeup */
568 writel(0, chip->base + SUN6I_ALARM_CONFIG);
570 clk_prepare_enable(chip->losc);
572 chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-sun6i",
573 &sun6i_rtc_ops, THIS_MODULE);
574 if (IS_ERR(chip->rtc)) {
575 dev_err(&pdev->dev, "unable to register device\n");
576 return PTR_ERR(chip->rtc);
579 dev_info(&pdev->dev, "RTC enabled\n");
584 static const struct of_device_id sun6i_rtc_dt_ids[] = {
585 { .compatible = "allwinner,sun6i-a31-rtc" },
588 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
590 static struct platform_driver sun6i_rtc_driver = {
591 .probe = sun6i_rtc_probe,
594 .of_match_table = sun6i_rtc_dt_ids,
597 builtin_platform_driver(sun6i_rtc_driver);