drivers/scsi/be2iscsi/be_cmds.c

   1 /**
   2  * Copyright (C) 2005 - 2016 Broadcom
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@broadcom.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <scsi/iscsi_proto.h>
  19
  20 #include "be_main.h"
  21 #include "be.h"
  22 #include "be_mgmt.h"
  23
  24 /* UE Status Low CSR */
  25 static const char * const desc_ue_status_low[] = {
  26         "CEV",
  27         "CTX",
  28         "DBUF",
  29         "ERX",
  30         "Host",
  31         "MPU",
  32         "NDMA",
  33         "PTC ",
  34         "RDMA ",
  35         "RXF ",
  36         "RXIPS ",
  37         "RXULP0 ",
  38         "RXULP1 ",
  39         "RXULP2 ",
  40         "TIM ",
  41         "TPOST ",
  42         "TPRE ",
  43         "TXIPS ",
  44         "TXULP0 ",
  45         "TXULP1 ",
  46         "UC ",
  47         "WDMA ",
  48         "TXULP2 ",
  49         "HOST1 ",
  50         "P0_OB_LINK ",
  51         "P1_OB_LINK ",
  52         "HOST_GPIO ",
  53         "MBOX ",
  54         "AXGMAC0",
  55         "AXGMAC1",
  56         "JTAG",
  57         "MPU_INTPEND"
  58 };
  59
  60 /* UE Status High CSR */
  61 static const char * const desc_ue_status_hi[] = {
  62         "LPCMEMHOST",
  63         "MGMT_MAC",
  64         "PCS0ONLINE",
  65         "MPU_IRAM",
  66         "PCS1ONLINE",
  67         "PCTL0",
  68         "PCTL1",
  69         "PMEM",
  70         "RR",
  71         "TXPB",
  72         "RXPP",
  73         "XAUI",
  74         "TXP",
  75         "ARM",
  76         "IPC",
  77         "HOST2",
  78         "HOST3",
  79         "HOST4",
  80         "HOST5",
  81         "HOST6",
  82         "HOST7",
  83         "HOST8",
  84         "HOST9",
  85         "NETC",
  86         "Unknown",
  87         "Unknown",
  88         "Unknown",
  89         "Unknown",
  90         "Unknown",
  91         "Unknown",
  92         "Unknown",
  93         "Unknown"
  94 };
  95
  96 struct be_mcc_wrb *alloc_mcc_wrb(struct beiscsi_hba *phba,
  97                                  unsigned int *ref_tag)
  98 {
  99         struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
 100         struct be_mcc_wrb *wrb = NULL;
 101         unsigned int tag;
 102
 103         spin_lock(&phba->ctrl.mcc_lock);
 104         if (mccq->used == mccq->len) {
 105                 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT |
 106                             BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
 107                             "BC_%d : MCC queue full: WRB used %u tag avail %u\n",
 108                             mccq->used, phba->ctrl.mcc_tag_available);
 109                 goto alloc_failed;
 110         }
 111
 112         if (!phba->ctrl.mcc_tag_available)
 113                 goto alloc_failed;
 114
 115         tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index];
 116         if (!tag) {
 117                 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT |
 118                             BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
 119                             "BC_%d : MCC tag 0 allocated: tag avail %u alloc index %u\n",
 120                             phba->ctrl.mcc_tag_available,
 121                             phba->ctrl.mcc_alloc_index);
 122                 goto alloc_failed;
 123         }
 124
 125         /* return this tag for further reference */
 126         *ref_tag = tag;
 127         phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0;
 128         phba->ctrl.mcc_tag_status[tag] = 0;
 129         phba->ctrl.ptag_state[tag].tag_state = 0;
 130         phba->ctrl.ptag_state[tag].cbfn = NULL;
 131         phba->ctrl.mcc_tag_available--;
 132         if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1))
 133                 phba->ctrl.mcc_alloc_index = 0;
 134         else
 135                 phba->ctrl.mcc_alloc_index++;
 136
 137         wrb = queue_head_node(mccq);
 138         memset(wrb, 0, sizeof(*wrb));
 139         wrb->tag0 = tag;
 140         wrb->tag0 |= (mccq->head << MCC_Q_WRB_IDX_SHIFT) & MCC_Q_WRB_IDX_MASK;
 141         queue_head_inc(mccq);
 142         mccq->used++;
 143
 144 alloc_failed:
 145         spin_unlock(&phba->ctrl.mcc_lock);
 146         return wrb;
 147 }
 148
 149 void free_mcc_wrb(struct be_ctrl_info *ctrl, unsigned int tag)
 150 {
 151         struct be_queue_info *mccq = &ctrl->mcc_obj.q;
 152
 153         spin_lock(&ctrl->mcc_lock);
 154         tag = tag & MCC_Q_CMD_TAG_MASK;
 155         ctrl->mcc_tag[ctrl->mcc_free_index] = tag;
 156         if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1))
 157                 ctrl->mcc_free_index = 0;
 158         else
 159                 ctrl->mcc_free_index++;
 160         ctrl->mcc_tag_available++;
 161         mccq->used--;
 162         spin_unlock(&ctrl->mcc_lock);
 163 }
 164
 165 /*
 166  * beiscsi_mcc_compl_status - Return the status of MCC completion
 167  * @phba: Driver private structure
 168  * @tag: Tag for the MBX Command
 169  * @wrb: the WRB used for the MBX Command
 170  * @mbx_cmd_mem: ptr to memory allocated for MBX Cmd
 171  *
 172  * return
 173  * Success: 0
 174  * Failure: Non-Zero
 175  */
 176 int __beiscsi_mcc_compl_status(struct beiscsi_hba *phba,
 177                                unsigned int tag,
 178                                struct be_mcc_wrb **wrb,
 179                                struct be_dma_mem *mbx_cmd_mem)
 180 {
 181         struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
 182         uint16_t status = 0, addl_status = 0, wrb_num = 0;
 183         struct be_cmd_resp_hdr *mbx_resp_hdr;
 184         struct be_cmd_req_hdr *mbx_hdr;
 185         struct be_mcc_wrb *temp_wrb;
 186         uint32_t mcc_tag_status;
 187         int rc = 0;
 188
 189         mcc_tag_status = phba->ctrl.mcc_tag_status[tag];
 190         status = (mcc_tag_status & CQE_STATUS_MASK);
 191         addl_status = ((mcc_tag_status & CQE_STATUS_ADDL_MASK) >>
 192                         CQE_STATUS_ADDL_SHIFT);
 193
 194         if (mbx_cmd_mem) {
 195                 mbx_hdr = (struct be_cmd_req_hdr *)mbx_cmd_mem->va;
 196         } else {
 197                 wrb_num = (mcc_tag_status & CQE_STATUS_WRB_MASK) >>
 198                           CQE_STATUS_WRB_SHIFT;
 199                 temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num);
 200                 mbx_hdr = embedded_payload(temp_wrb);
 201
 202                 if (wrb)
 203                         *wrb = temp_wrb;
 204         }
 205
 206         if (status || addl_status) {
 207                 beiscsi_log(phba, KERN_WARNING,
 208                             BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
 209                             BEISCSI_LOG_CONFIG,
 210                             "BC_%d : MBX Cmd Failed for Subsys : %d Opcode : %d with Status : %d and Extd_Status : %d\n",
 211                             mbx_hdr->subsystem, mbx_hdr->opcode,
 212                             status, addl_status);
 213                 rc = -EIO;
 214                 if (status == MCC_STATUS_INSUFFICIENT_BUFFER) {
 215                         mbx_resp_hdr = (struct be_cmd_resp_hdr *)mbx_hdr;
 216                         beiscsi_log(phba, KERN_WARNING,
 217                                     BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
 218                                     BEISCSI_LOG_CONFIG,
 219                                     "BC_%d : Insufficient Buffer Error Resp_Len : %d Actual_Resp_Len : %d\n",
 220                                     mbx_resp_hdr->response_length,
 221                                     mbx_resp_hdr->actual_resp_len);
 222                         rc = -EAGAIN;
 223                 }
 224         }
 225
 226         return rc;
 227 }
 228
 229 /*
 230  * beiscsi_mccq_compl_wait()- Process completion in MCC CQ
 231  * @phba: Driver private structure
 232  * @tag: Tag for the MBX Command
 233  * @wrb: the WRB used for the MBX Command
 234  * @mbx_cmd_mem: ptr to memory allocated for MBX Cmd
 235  *
 236  * Waits for MBX completion with the passed TAG.
 237  *
 238  * return
 239  * Success: 0
 240  * Failure: Non-Zero
 241  **/
 242 int beiscsi_mccq_compl_wait(struct beiscsi_hba *phba,
 243                             unsigned int tag,
 244                             struct be_mcc_wrb **wrb,
 245                             struct be_dma_mem *mbx_cmd_mem)
 246 {
 247         int rc = 0;
 248
 249         if (!tag || tag > MAX_MCC_CMD) {
 250                 __beiscsi_log(phba, KERN_ERR,
 251                               "BC_%d : invalid tag %u\n", tag);
 252                 return -EINVAL;
 253         }
 254
 255         if (beiscsi_hba_in_error(phba)) {
 256                 clear_bit(MCC_TAG_STATE_RUNNING,
 257                           &phba->ctrl.ptag_state[tag].tag_state);
 258                 return -EIO;
 259         }
 260
 261         /* wait for the mccq completion */
 262         rc = wait_event_interruptible_timeout(phba->ctrl.mcc_wait[tag],
 263                                               phba->ctrl.mcc_tag_status[tag],
 264                                               msecs_to_jiffies(
 265                                                 BEISCSI_HOST_MBX_TIMEOUT));
 266         /**
 267          * Return EIO if port is being disabled. Associated DMA memory, if any,
 268          * is freed by the caller. When port goes offline, MCCQ is cleaned up
 269          * so does WRB.
 270          */
 271         if (!test_bit(BEISCSI_HBA_ONLINE, &phba->state)) {
 272                 clear_bit(MCC_TAG_STATE_RUNNING,
 273                           &phba->ctrl.ptag_state[tag].tag_state);
 274                 return -EIO;
 275         }
 276
 277         /**
 278          * If MBOX cmd timeout expired, tag and resource allocated
 279          * for cmd is not freed until FW returns completion.
 280          */
 281         if (rc <= 0) {
 282                 struct be_dma_mem *tag_mem;
 283
 284                 /**
 285                  * PCI/DMA memory allocated and posted in non-embedded mode
 286                  * will have mbx_cmd_mem != NULL.
 287                  * Save virtual and bus addresses for the command so that it
 288                  * can be freed later.
 289                  **/
 290                 tag_mem = &phba->ctrl.ptag_state[tag].tag_mem_state;
 291                 if (mbx_cmd_mem) {
 292                         tag_mem->size = mbx_cmd_mem->size;
 293                         tag_mem->va = mbx_cmd_mem->va;
 294                         tag_mem->dma = mbx_cmd_mem->dma;
 295                 } else
 296                         tag_mem->size = 0;
 297
 298                 /* first make tag_mem_state visible to all */
 299                 wmb();
 300                 set_bit(MCC_TAG_STATE_TIMEOUT,
 301                                 &phba->ctrl.ptag_state[tag].tag_state);
 302
 303                 beiscsi_log(phba, KERN_ERR,
 304                             BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
 305                             BEISCSI_LOG_CONFIG,
 306                             "BC_%d : MBX Cmd Completion timed out\n");
 307                 return -EBUSY;
 308         }
 309
 310         rc = __beiscsi_mcc_compl_status(phba, tag, wrb, mbx_cmd_mem);
 311
 312         free_mcc_wrb(&phba->ctrl, tag);
 313         return rc;
 314 }
 315
 316 /*
 317  * beiscsi_process_mbox_compl()- Check the MBX completion status
 318  * @ctrl: Function specific MBX data structure
 319  * @compl: Completion status of MBX Command
 320  *
 321  * Check for the MBX completion status when BMBX method used
 322  *
 323  * return
 324  * Success: Zero
 325  * Failure: Non-Zero
 326  **/
 327 static int beiscsi_process_mbox_compl(struct be_ctrl_info *ctrl,
 328                                       struct be_mcc_compl *compl)
 329 {
 330         struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
 331         struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
 332         struct be_cmd_req_hdr *hdr = embedded_payload(wrb);
 333         u16 compl_status, extd_status;
 334
 335         /**
 336          * To check if valid bit is set, check the entire word as we don't know
 337          * the endianness of the data (old entry is host endian while a new
 338          * entry is little endian)
 339          */
 340         if (!compl->flags) {
 341                 beiscsi_log(phba, KERN_ERR,
 342                                 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
 343                                 "BC_%d : BMBX busy, no completion\n");
 344                 return -EBUSY;
 345         }
 346         compl->flags = le32_to_cpu(compl->flags);
 347         WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
 348
 349         /**
 350          * Just swap the status to host endian;
 351          * mcc tag is opaquely copied from mcc_wrb.
 352          */
 353         be_dws_le_to_cpu(compl, 4);
 354         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
 355                 CQE_STATUS_COMPL_MASK;
 356         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 357                 CQE_STATUS_EXTD_MASK;
 358         /* Need to reset the entire word that houses the valid bit */
 359         compl->flags = 0;
 360
 361         if (compl_status == MCC_STATUS_SUCCESS)
 362                 return 0;
 363
 364         beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
 365                     "BC_%d : error in cmd completion: Subsystem : %d Opcode : %d status(compl/extd)=%d/%d\n",
 366                     hdr->subsystem, hdr->opcode, compl_status, extd_status);
 367         return compl_status;
 368 }
 369
 370 static void beiscsi_process_async_link(struct beiscsi_hba *phba,
 371                                        struct be_mcc_compl *compl)
 372 {
 373         struct be_async_event_link_state *evt;
 374
 375         evt = (struct be_async_event_link_state *)compl;
 376
 377         phba->port_speed = evt->port_speed;
 378         /**
 379          * Check logical link status in ASYNC event.
 380          * This has been newly introduced in SKH-R Firmware 10.0.338.45.
 381          **/
 382         if (evt->port_link_status & BE_ASYNC_LINK_UP_MASK) {
 383                 set_bit(BEISCSI_HBA_LINK_UP, &phba->state);
 384                 if (test_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state))
 385                         beiscsi_start_boot_work(phba, BE_BOOT_INVALID_SHANDLE);
 386                 __beiscsi_log(phba, KERN_ERR,
 387                               "BC_%d : Link Up on Port %d tag 0x%x\n",
 388                               evt->physical_port, evt->event_tag);
 389         } else {
 390                 clear_bit(BEISCSI_HBA_LINK_UP, &phba->state);
 391                 __beiscsi_log(phba, KERN_ERR,
 392                               "BC_%d : Link Down on Port %d tag 0x%x\n",
 393                               evt->physical_port, evt->event_tag);
 394                 iscsi_host_for_each_session(phba->shost,
 395                                             beiscsi_session_fail);
 396         }
 397 }
 398
 399 static char *beiscsi_port_misconf_event_msg[] = {
 400         "Physical Link is functional.",
 401         "Optics faulted/incorrectly installed/not installed - Reseat optics, if issue not resolved, replace.",
 402         "Optics of two types installed - Remove one optic or install matching pair of optics.",
 403         "Incompatible optics - Replace with compatible optics for card to function.",
 404         "Unqualified optics - Replace with Avago optics for Warranty and Technical Support.",
 405         "Uncertified optics - Replace with Avago Certified optics to enable link operation."
 406 };
 407
 408 static void beiscsi_process_async_sli(struct beiscsi_hba *phba,
 409                                       struct be_mcc_compl *compl)
 410 {
 411         struct be_async_event_sli *async_sli;
 412         u8 evt_type, state, old_state, le;
 413         char *sev = KERN_WARNING;
 414         char *msg = NULL;
 415
 416         evt_type = compl->flags >> ASYNC_TRAILER_EVENT_TYPE_SHIFT;
 417         evt_type &= ASYNC_TRAILER_EVENT_TYPE_MASK;
 418
 419         /* processing only MISCONFIGURED physical port event */
 420         if (evt_type != ASYNC_SLI_EVENT_TYPE_MISCONFIGURED)
 421                 return;
 422
 423         async_sli = (struct be_async_event_sli *)compl;
 424         state = async_sli->event_data1 >>
 425                  (phba->fw_config.phys_port * 8) & 0xff;
 426         le = async_sli->event_data2 >>
 427                  (phba->fw_config.phys_port * 8) & 0xff;
 428
 429         old_state = phba->optic_state;
 430         phba->optic_state = state;
 431
 432         if (state >= ARRAY_SIZE(beiscsi_port_misconf_event_msg)) {
 433                 /* fw is reporting a state we don't know, log and return */
 434                 __beiscsi_log(phba, KERN_ERR,
 435                             "BC_%d : Port %c: Unrecognized optic state 0x%x\n",
 436                             phba->port_name, async_sli->event_data1);
 437                 return;
 438         }
 439
 440         if (ASYNC_SLI_LINK_EFFECT_VALID(le)) {
 441                 /* log link effect for unqualified-4, uncertified-5 optics */
 442                 if (state > 3)
 443                         msg = (ASYNC_SLI_LINK_EFFECT_STATE(le)) ?
 444                                 " Link is non-operational." :
 445                                 " Link is operational.";
 446                 /* 1 - info */
 447                 if (ASYNC_SLI_LINK_EFFECT_SEV(le) == 1)
 448                         sev = KERN_INFO;
 449                 /* 2 - error */
 450                 if (ASYNC_SLI_LINK_EFFECT_SEV(le) == 2)
 451                         sev = KERN_ERR;
 452         }
 453
 454         if (old_state != phba->optic_state)
 455                 __beiscsi_log(phba, sev, "BC_%d : Port %c: %s%s\n",
 456                               phba->port_name,
 457                               beiscsi_port_misconf_event_msg[state],
 458                               !msg ? "" : msg);
 459 }
 460
 461 void beiscsi_process_async_event(struct beiscsi_hba *phba,
 462                                 struct be_mcc_compl *compl)
 463 {
 464         char *sev = KERN_INFO;
 465         u8 evt_code;
 466
 467         /* interpret flags as an async trailer */
 468         evt_code = compl->flags >> ASYNC_TRAILER_EVENT_CODE_SHIFT;
 469         evt_code &= ASYNC_TRAILER_EVENT_CODE_MASK;
 470         switch (evt_code) {
 471         case ASYNC_EVENT_CODE_LINK_STATE:
 472                 beiscsi_process_async_link(phba, compl);
 473                 break;
 474         case ASYNC_EVENT_CODE_ISCSI:
 475                 if (test_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state))
 476                         beiscsi_start_boot_work(phba, BE_BOOT_INVALID_SHANDLE);
 477                 sev = KERN_ERR;
 478                 break;
 479         case ASYNC_EVENT_CODE_SLI:
 480                 beiscsi_process_async_sli(phba, compl);
 481                 break;
 482         default:
 483                 /* event not registered */
 484                 sev = KERN_ERR;
 485         }
 486
 487         beiscsi_log(phba, sev, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
 488                     "BC_%d : ASYNC Event %x: status 0x%08x flags 0x%08x\n",
 489                     evt_code, compl->status, compl->flags);
 490 }
 491
 492 int beiscsi_process_mcc_compl(struct be_ctrl_info *ctrl,
 493                               struct be_mcc_compl *compl)
 494 {
 495         struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
 496         u16 compl_status, extd_status;
 497         struct be_dma_mem *tag_mem;
 498         unsigned int tag, wrb_idx;
 499
 500         be_dws_le_to_cpu(compl, 4);
 501         tag = (compl->tag0 & MCC_Q_CMD_TAG_MASK);
 502         wrb_idx = (compl->tag0 & CQE_STATUS_WRB_MASK) >> CQE_STATUS_WRB_SHIFT;
 503
 504         if (!test_bit(MCC_TAG_STATE_RUNNING,
 505                       &ctrl->ptag_state[tag].tag_state)) {
 506                 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX |
 507                             BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
 508                             "BC_%d : MBX cmd completed but not posted\n");
 509                 return 0;
 510         }
 511
 512         /* end MCC with this tag */
 513         clear_bit(MCC_TAG_STATE_RUNNING, &ctrl->ptag_state[tag].tag_state);
 514
 515         if (test_bit(MCC_TAG_STATE_TIMEOUT, &ctrl->ptag_state[tag].tag_state)) {
 516                 beiscsi_log(phba, KERN_WARNING,
 517                             BEISCSI_LOG_MBOX | BEISCSI_LOG_INIT |
 518                             BEISCSI_LOG_CONFIG,
 519                             "BC_%d : MBX Completion for timeout Command from FW\n");
 520                 /**
 521                  * Check for the size before freeing resource.
 522                  * Only for non-embedded cmd, PCI resource is allocated.
 523                  **/
 524                 tag_mem = &ctrl->ptag_state[tag].tag_mem_state;
 525                 if (tag_mem->size) {
 526                         pci_free_consistent(ctrl->pdev, tag_mem->size,
 527                                         tag_mem->va, tag_mem->dma);
 528                         tag_mem->size = 0;
 529                 }
 530                 free_mcc_wrb(ctrl, tag);
 531                 return 0;
 532         }
 533
 534         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
 535                        CQE_STATUS_COMPL_MASK;
 536         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 537                       CQE_STATUS_EXTD_MASK;
 538         /* The ctrl.mcc_tag_status[tag] is filled with
 539          * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
 540          * [7:0] = compl_status
 541          */
 542         ctrl->mcc_tag_status[tag] = CQE_VALID_MASK;
 543         ctrl->mcc_tag_status[tag] |= (wrb_idx << CQE_STATUS_WRB_SHIFT);
 544         ctrl->mcc_tag_status[tag] |= (extd_status << CQE_STATUS_ADDL_SHIFT) &
 545                                      CQE_STATUS_ADDL_MASK;
 546         ctrl->mcc_tag_status[tag] |= (compl_status & CQE_STATUS_MASK);
 547
 548         if (test_bit(MCC_TAG_STATE_ASYNC, &ctrl->ptag_state[tag].tag_state)) {
 549                 if (ctrl->ptag_state[tag].cbfn)
 550                         ctrl->ptag_state[tag].cbfn(phba, tag);
 551                 else
 552                         __beiscsi_log(phba, KERN_ERR,
 553                                       "BC_%d : MBX ASYNC command with no callback\n");
 554                 free_mcc_wrb(ctrl, tag);
 555                 return 0;
 556         }
 557
 558         if (test_bit(MCC_TAG_STATE_IGNORE, &ctrl->ptag_state[tag].tag_state)) {
 559                 /* just check completion status and free wrb */
 560                 __beiscsi_mcc_compl_status(phba, tag, NULL, NULL);
 561                 free_mcc_wrb(ctrl, tag);
 562                 return 0;
 563         }
 564
 565         wake_up_interruptible(&ctrl->mcc_wait[tag]);
 566         return 0;
 567 }
 568
 569 void be_mcc_notify(struct beiscsi_hba *phba, unsigned int tag)
 570 {
 571         struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
 572         u32 val = 0;
 573
 574         set_bit(MCC_TAG_STATE_RUNNING, &phba->ctrl.ptag_state[tag].tag_state);
 575         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
 576         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
 577         /* make request available for DMA */
 578         wmb();
 579         iowrite32(val, phba->db_va + DB_MCCQ_OFFSET);
 580 }
 581
 582 /*
 583  * be_mbox_db_ready_poll()- Check ready status
 584  * @ctrl: Function specific MBX data structure
 585  *
 586  * Check for the ready status of FW to send BMBX
 587  * commands to adapter.
 588  *
 589  * return
 590  * Success: 0
 591  * Failure: Non-Zero
 592  **/
 593 static int be_mbox_db_ready_poll(struct be_ctrl_info *ctrl)
 594 {
 595         /* wait 30s for generic non-flash MBOX operation */
 596 #define BEISCSI_MBX_RDY_BIT_TIMEOUT     30000
 597         void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
 598         struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
 599         unsigned long timeout;
 600         u32 ready;
 601
 602         /*
 603          * This BMBX busy wait path is used during init only.
 604          * For the commands executed during init, 5s should suffice.
 605          */
 606         timeout = jiffies + msecs_to_jiffies(BEISCSI_MBX_RDY_BIT_TIMEOUT);
 607         do {
 608                 if (beiscsi_hba_in_error(phba))
 609                         return -EIO;
 610
 611                 ready = ioread32(db);
 612                 if (ready == 0xffffffff)
 613                         return -EIO;
 614
 615                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 616                 if (ready)
 617                         return 0;
 618
 619                 if (time_after(jiffies, timeout))
 620                         break;
 621                 /* 1ms sleep is enough in most cases */
 622                 schedule_timeout_uninterruptible(msecs_to_jiffies(1));
 623         } while (!ready);
 624
 625         beiscsi_log(phba, KERN_ERR,
 626                         BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
 627                         "BC_%d : FW Timed Out\n");
 628         set_bit(BEISCSI_HBA_FW_TIMEOUT, &phba->state);
 629         return -EBUSY;
 630 }
 631
 632 /*
 633  * be_mbox_notify: Notify adapter of new BMBX command
 634  * @ctrl: Function specific MBX data structure
 635  *
 636  * Ring doorbell to inform adapter of a BMBX command
 637  * to process
 638  *
 639  * return
 640  * Success: 0
 641  * Failure: Non-Zero
 642  **/
 643 static int be_mbox_notify(struct be_ctrl_info *ctrl)
 644 {
 645         int status;
 646         u32 val = 0;
 647         void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
 648         struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
 649         struct be_mcc_mailbox *mbox = mbox_mem->va;
 650
 651         status = be_mbox_db_ready_poll(ctrl);
 652         if (status)
 653                 return status;
 654
 655         val &= ~MPU_MAILBOX_DB_RDY_MASK;
 656         val |= MPU_MAILBOX_DB_HI_MASK;
 657         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 658         iowrite32(val, db);
 659
 660         status = be_mbox_db_ready_poll(ctrl);
 661         if (status)
 662                 return status;
 663
 664         val = 0;
 665         val &= ~MPU_MAILBOX_DB_RDY_MASK;
 666         val &= ~MPU_MAILBOX_DB_HI_MASK;
 667         val |= (u32) (mbox_mem->dma >> 4) << 2;
 668         iowrite32(val, db);
 669
 670         status = be_mbox_db_ready_poll(ctrl);
 671         if (status)
 672                 return status;
 673
 674         /* RDY is set; small delay before CQE read. */
 675         udelay(1);
 676
 677         status = beiscsi_process_mbox_compl(ctrl, &mbox->compl);
 678         return status;
 679 }
 680
 681 void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
 682                                 bool embedded, u8 sge_cnt)
 683 {
 684         if (embedded)
 685                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 686         else
 687                 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
 688                                                 MCC_WRB_SGE_CNT_SHIFT;
 689         wrb->payload_length = payload_len;
 690         be_dws_cpu_to_le(wrb, 8);
 691 }
 692
 693 void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 694                         u8 subsystem, u8 opcode, int cmd_len)
 695 {
 696         req_hdr->opcode = opcode;
 697         req_hdr->subsystem = subsystem;
 698         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 699         req_hdr->timeout = BEISCSI_FW_MBX_TIMEOUT;
 700 }
 701
 702 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 703                                                         struct be_dma_mem *mem)
 704 {
 705         int i, buf_pages;
 706         u64 dma = (u64) mem->dma;
 707
 708         buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 709         for (i = 0; i < buf_pages; i++) {
 710                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 711                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 712                 dma += PAGE_SIZE_4K;
 713         }
 714 }
 715
 716 static u32 eq_delay_to_mult(u32 usec_delay)
 717 {
 718 #define MAX_INTR_RATE 651042
 719         const u32 round = 10;
 720         u32 multiplier;
 721
 722         if (usec_delay == 0)
 723                 multiplier = 0;
 724         else {
 725                 u32 interrupt_rate = 1000000 / usec_delay;
 726                 if (interrupt_rate == 0)
 727                         multiplier = 1023;
 728                 else {
 729                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 730                         multiplier /= interrupt_rate;
 731                         multiplier = (multiplier + round / 2) / round;
 732                         multiplier = min(multiplier, (u32) 1023);
 733                 }
 734         }
 735         return multiplier;
 736 }
 737
 738 struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
 739 {
 740         return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 741 }
 742
 743 int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
 744                           struct be_queue_info *eq, int eq_delay)
 745 {
 746         struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
 747         struct be_cmd_req_eq_create *req = embedded_payload(wrb);
 748         struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 749         struct be_dma_mem *q_mem = &eq->dma_mem;
 750         int status;
 751
 752         mutex_lock(&ctrl->mbox_lock);
 753         memset(wrb, 0, sizeof(*wrb));
 754
 755         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 756
 757         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 758                         OPCODE_COMMON_EQ_CREATE, sizeof(*req));
 759
 760         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 761
 762         AMAP_SET_BITS(struct amap_eq_context, func, req->context,
 763                                                 PCI_FUNC(ctrl->pdev->devfn));
 764         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 765         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 766         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 767                                         __ilog2_u32(eq->len / 256));
 768         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 769                                         eq_delay_to_mult(eq_delay));
 770         be_dws_cpu_to_le(req->context, sizeof(req->context));
 771
 772         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 773
 774         status = be_mbox_notify(ctrl);
 775         if (!status) {
 776                 eq->id = le16_to_cpu(resp->eq_id);
 777                 eq->created = true;
 778         }
 779         mutex_unlock(&ctrl->mbox_lock);
 780         return status;
 781 }
 782
 783 int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
 784                           struct be_queue_info *cq, struct be_queue_info *eq,
 785                           bool sol_evts, bool no_delay, int coalesce_wm)
 786 {
 787         struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
 788         struct be_cmd_req_cq_create *req = embedded_payload(wrb);
 789         struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 790         struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
 791         struct be_dma_mem *q_mem = &cq->dma_mem;
 792         void *ctxt = &req->context;
 793         int status;
 794
 795         mutex_lock(&ctrl->mbox_lock);
 796         memset(wrb, 0, sizeof(*wrb));
 797
 798         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 799
 800         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 801                         OPCODE_COMMON_CQ_CREATE, sizeof(*req));
 802
 803         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 804         if (is_chip_be2_be3r(phba)) {
 805                 AMAP_SET_BITS(struct amap_cq_context, coalescwm,
 806                               ctxt, coalesce_wm);
 807                 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
 808                 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
 809                               __ilog2_u32(cq->len / 256));
 810                 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
 811                 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
 812                 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
 813                 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
 814                 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
 815                 AMAP_SET_BITS(struct amap_cq_context, func, ctxt,
 816                               PCI_FUNC(ctrl->pdev->devfn));
 817         } else {
 818                 req->hdr.version = MBX_CMD_VER2;
 819                 req->page_size = 1;
 820                 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
 821                               ctxt, coalesce_wm);
 822                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay,
 823                               ctxt, no_delay);
 824                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
 825                               __ilog2_u32(cq->len / 256));
 826                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
 827                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
 828                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
 829                 AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1);
 830         }
 831
 832         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 833
 834         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 835
 836         status = be_mbox_notify(ctrl);
 837         if (!status) {
 838                 cq->id = le16_to_cpu(resp->cq_id);
 839                 cq->created = true;
 840         } else
 841                 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
 842                             "BC_%d : In be_cmd_cq_create, status=ox%08x\n",
 843                             status);
 844
 845         mutex_unlock(&ctrl->mbox_lock);
 846
 847         return status;
 848 }
 849
 850 static u32 be_encoded_q_len(int q_len)
 851 {
 852         u32 len_encoded = fls(q_len);   /* log2(len) + 1 */
 853         if (len_encoded == 16)
 854                 len_encoded = 0;
 855         return len_encoded;
 856 }
 857
 858 int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba,
 859                         struct be_queue_info *mccq,
 860                         struct be_queue_info *cq)
 861 {
 862         struct be_mcc_wrb *wrb;
 863         struct be_cmd_req_mcc_create_ext *req;
 864         struct be_dma_mem *q_mem = &mccq->dma_mem;
 865         struct be_ctrl_info *ctrl;
 866         void *ctxt;
 867         int status;
 868
 869         mutex_lock(&phba->ctrl.mbox_lock);
 870         ctrl = &phba->ctrl;
 871         wrb = wrb_from_mbox(&ctrl->mbox_mem);
 872         memset(wrb, 0, sizeof(*wrb));
 873         req = embedded_payload(wrb);
 874         ctxt = &req->context;
 875
 876         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 877
 878         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 879                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
 880
 881         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 882         req->async_evt_bitmap = 1 << ASYNC_EVENT_CODE_LINK_STATE;
 883         req->async_evt_bitmap |= 1 << ASYNC_EVENT_CODE_ISCSI;
 884         req->async_evt_bitmap |= 1 << ASYNC_EVENT_CODE_SLI;
 885
 886         AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt,
 887                       PCI_FUNC(phba->pcidev->devfn));
 888         AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
 889         AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
 890                 be_encoded_q_len(mccq->len));
 891         AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
 892
 893         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 894
 895         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 896
 897         status = be_mbox_notify(ctrl);
 898         if (!status) {
 899                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 900                 mccq->id = le16_to_cpu(resp->id);
 901                 mccq->created = true;
 902         }
 903         mutex_unlock(&phba->ctrl.mbox_lock);
 904
 905         return status;
 906 }
 907
 908 int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
 909                           int queue_type)
 910 {
 911         struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
 912         struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
 913         struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
 914         u8 subsys = 0, opcode = 0;
 915         int status;
 916
 917         beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
 918                     "BC_%d : In beiscsi_cmd_q_destroy "
 919                     "queue_type : %d\n", queue_type);
 920
 921         mutex_lock(&ctrl->mbox_lock);
 922         memset(wrb, 0, sizeof(*wrb));
 923         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 924
 925         switch (queue_type) {
 926         case QTYPE_EQ:
 927                 subsys = CMD_SUBSYSTEM_COMMON;
 928                 opcode = OPCODE_COMMON_EQ_DESTROY;
 929                 break;
 930         case QTYPE_CQ:
 931                 subsys = CMD_SUBSYSTEM_COMMON;
 932                 opcode = OPCODE_COMMON_CQ_DESTROY;
 933                 break;
 934         case QTYPE_MCCQ:
 935                 subsys = CMD_SUBSYSTEM_COMMON;
 936                 opcode = OPCODE_COMMON_MCC_DESTROY;
 937                 break;
 938         case QTYPE_WRBQ:
 939                 subsys = CMD_SUBSYSTEM_ISCSI;
 940                 opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY;
 941                 break;
 942         case QTYPE_DPDUQ:
 943                 subsys = CMD_SUBSYSTEM_ISCSI;
 944                 opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY;
 945                 break;
 946         case QTYPE_SGL:
 947                 subsys = CMD_SUBSYSTEM_ISCSI;
 948                 opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES;
 949                 break;
 950         default:
 951                 mutex_unlock(&ctrl->mbox_lock);
 952                 BUG();
 953                 return -ENXIO;
 954         }
 955         be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
 956         if (queue_type != QTYPE_SGL)
 957                 req->id = cpu_to_le16(q->id);
 958
 959         status = be_mbox_notify(ctrl);
 960
 961         mutex_unlock(&ctrl->mbox_lock);
 962         return status;
 963 }
 964
 965 /**
 966  * be_cmd_create_default_pdu_queue()- Create DEFQ for the adapter
 967  * @ctrl: ptr to ctrl_info
 968  * @cq: Completion Queue
 969  * @dq: Default Queue
 970  * @lenght: ring size
 971  * @entry_size: size of each entry in DEFQ
 972  * @is_header: Header or Data DEFQ
 973  * @ulp_num: Bind to which ULP
 974  *
 975  * Create HDR/Data DEFQ for the passed ULP. Unsol PDU are posted
 976  * on this queue by the FW
 977  *
 978  * return
 979  *      Success: 0
 980  *      Failure: Non-Zero Value
 981  *
 982  **/
 983 int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
 984                                     struct be_queue_info *cq,
 985                                     struct be_queue_info *dq, int length,
 986                                     int entry_size, uint8_t is_header,
 987                                     uint8_t ulp_num)
 988 {
 989         struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
 990         struct be_defq_create_req *req = embedded_payload(wrb);
 991         struct be_dma_mem *q_mem = &dq->dma_mem;
 992         struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
 993         void *ctxt = &req->context;
 994         int status;
 995
 996         mutex_lock(&ctrl->mbox_lock);
 997         memset(wrb, 0, sizeof(*wrb));
 998
 999         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1000
1001         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1002                            OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req));
1003
1004         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1005         if (phba->fw_config.dual_ulp_aware) {
1006                 req->ulp_num = ulp_num;
1007                 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
1008                 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
1009         }
1010
1011         if (is_chip_be2_be3r(phba)) {
1012                 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1013                               rx_pdid, ctxt, 0);
1014                 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1015                               rx_pdid_valid, ctxt, 1);
1016                 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1017                               pci_func_id, ctxt, PCI_FUNC(ctrl->pdev->devfn));
1018                 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1019                               ring_size, ctxt,
1020                               be_encoded_q_len(length /
1021                               sizeof(struct phys_addr)));
1022                 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1023                               default_buffer_size, ctxt, entry_size);
1024                 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1025                               cq_id_recv, ctxt, cq->id);
1026         } else {
1027                 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1028                               rx_pdid, ctxt, 0);
1029                 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1030                               rx_pdid_valid, ctxt, 1);
1031                 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1032                               ring_size, ctxt,
1033                               be_encoded_q_len(length /
1034                               sizeof(struct phys_addr)));
1035                 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1036                               default_buffer_size, ctxt, entry_size);
1037                 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1038                               cq_id_recv, ctxt, cq->id);
1039         }
1040
1041         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1042
1043         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1044
1045         status = be_mbox_notify(ctrl);
1046         if (!status) {
1047                 struct be_ring *defq_ring;
1048                 struct be_defq_create_resp *resp = embedded_payload(wrb);
1049
1050                 dq->id = le16_to_cpu(resp->id);
1051                 dq->created = true;
1052                 if (is_header)
1053                         defq_ring = &phba->phwi_ctrlr->default_pdu_hdr[ulp_num];
1054                 else
1055                         defq_ring = &phba->phwi_ctrlr->
1056                                     default_pdu_data[ulp_num];
1057
1058                 defq_ring->id = dq->id;
1059
1060                 if (!phba->fw_config.dual_ulp_aware) {
1061                         defq_ring->ulp_num = BEISCSI_ULP0;
1062                         defq_ring->doorbell_offset = DB_RXULP0_OFFSET;
1063                 } else {
1064                         defq_ring->ulp_num = resp->ulp_num;
1065                         defq_ring->doorbell_offset = resp->doorbell_offset;
1066                 }
1067         }
1068         mutex_unlock(&ctrl->mbox_lock);
1069
1070         return status;
1071 }
1072
1073 /**
1074  * be_cmd_wrbq_create()- Create WRBQ
1075  * @ctrl: ptr to ctrl_info
1076  * @q_mem: memory details for the queue
1077  * @wrbq: queue info
1078  * @pwrb_context: ptr to wrb_context
1079  * @ulp_num: ULP on which the WRBQ is to be created
1080  *
1081  * Create WRBQ on the passed ULP_NUM.
1082  *
1083  **/
1084 int be_cmd_wrbq_create(struct be_ctrl_info *ctrl,
1085                         struct be_dma_mem *q_mem,
1086                         struct be_queue_info *wrbq,
1087                         struct hwi_wrb_context *pwrb_context,
1088                         uint8_t ulp_num)
1089 {
1090         struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1091         struct be_wrbq_create_req *req = embedded_payload(wrb);
1092         struct be_wrbq_create_resp *resp = embedded_payload(wrb);
1093         struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1094         int status;
1095
1096         mutex_lock(&ctrl->mbox_lock);
1097         memset(wrb, 0, sizeof(*wrb));
1098
1099         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1100
1101         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1102                 OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req));
1103         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1104
1105         if (phba->fw_config.dual_ulp_aware) {
1106                 req->ulp_num = ulp_num;
1107                 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
1108                 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
1109         }
1110
1111         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1112
1113         status = be_mbox_notify(ctrl);
1114         if (!status) {
1115                 wrbq->id = le16_to_cpu(resp->cid);
1116                 wrbq->created = true;
1117
1118                 pwrb_context->cid = wrbq->id;
1119                 if (!phba->fw_config.dual_ulp_aware) {
1120                         pwrb_context->doorbell_offset = DB_TXULP0_OFFSET;
1121                         pwrb_context->ulp_num = BEISCSI_ULP0;
1122                 } else {
1123                         pwrb_context->ulp_num = resp->ulp_num;
1124                         pwrb_context->doorbell_offset = resp->doorbell_offset;
1125                 }
1126         }
1127         mutex_unlock(&ctrl->mbox_lock);
1128         return status;
1129 }
1130
1131 int be_cmd_iscsi_post_template_hdr(struct be_ctrl_info *ctrl,
1132                                     struct be_dma_mem *q_mem)
1133 {
1134         struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1135         struct be_post_template_pages_req *req = embedded_payload(wrb);
1136         int status;
1137
1138         mutex_lock(&ctrl->mbox_lock);
1139
1140         memset(wrb, 0, sizeof(*wrb));
1141         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1142         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1143                            OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS,
1144                            sizeof(*req));
1145
1146         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1147         req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
1148         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1149
1150         status = be_mbox_notify(ctrl);
1151         mutex_unlock(&ctrl->mbox_lock);
1152         return status;
1153 }
1154
1155 int be_cmd_iscsi_remove_template_hdr(struct be_ctrl_info *ctrl)
1156 {
1157         struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1158         struct be_remove_template_pages_req *req = embedded_payload(wrb);
1159         int status;
1160
1161         mutex_lock(&ctrl->mbox_lock);
1162
1163         memset(wrb, 0, sizeof(*wrb));
1164         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1165         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1166                            OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS,
1167                            sizeof(*req));
1168
1169         req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
1170
1171         status = be_mbox_notify(ctrl);
1172         mutex_unlock(&ctrl->mbox_lock);
1173         return status;
1174 }
1175
1176 int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
1177                                 struct be_dma_mem *q_mem,
1178                                 u32 page_offset, u32 num_pages)
1179 {
1180         struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1181         struct be_post_sgl_pages_req *req = embedded_payload(wrb);
1182         struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1183         int status;
1184         unsigned int curr_pages;
1185         u32 internal_page_offset = 0;
1186         u32 temp_num_pages = num_pages;
1187
1188         if (num_pages == 0xff)
1189                 num_pages = 1;
1190
1191         mutex_lock(&ctrl->mbox_lock);
1192         do {
1193                 memset(wrb, 0, sizeof(*wrb));
1194                 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1195                 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1196                                    OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES,
1197                                    sizeof(*req));
1198                 curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req,
1199                                                 pages);
1200                 req->num_pages = min(num_pages, curr_pages);
1201                 req->page_offset = page_offset;
1202                 be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem);
1203                 q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE);
1204                 internal_page_offset += req->num_pages;
1205                 page_offset += req->num_pages;
1206                 num_pages -= req->num_pages;
1207
1208                 if (temp_num_pages == 0xff)
1209                         req->num_pages = temp_num_pages;
1210
1211                 status = be_mbox_notify(ctrl);
1212                 if (status) {
1213                         beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1214                                     "BC_%d : FW CMD to map iscsi frags failed.\n");
1215
1216                         goto error;
1217                 }
1218         } while (num_pages > 0);
1219 error:
1220         mutex_unlock(&ctrl->mbox_lock);
1221         if (status != 0)
1222                 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
1223         return status;
1224 }
1225
1226 /**
1227  * be_cmd_set_vlan()- Configure VLAN paramters on the adapter
1228  * @phba: device priv structure instance
1229  * @vlan_tag: TAG to be set
1230  *
1231  * Set the VLAN_TAG for the adapter or Disable VLAN on adapter
1232  *
1233  * returns
1234  *      TAG for the MBX Cmd
1235  * **/
1236 int be_cmd_set_vlan(struct beiscsi_hba *phba,
1237                      uint16_t vlan_tag)
1238 {
1239         unsigned int tag;
1240         struct be_mcc_wrb *wrb;
1241         struct be_cmd_set_vlan_req *req;
1242         struct be_ctrl_info *ctrl = &phba->ctrl;
1243
1244         if (mutex_lock_interruptible(&ctrl->mbox_lock))
1245                 return 0;
1246         wrb = alloc_mcc_wrb(phba, &tag);
1247         if (!wrb) {
1248                 mutex_unlock(&ctrl->mbox_lock);
1249                 return 0;
1250         }
1251
1252         req = embedded_payload(wrb);
1253         be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0);
1254         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1255                            OPCODE_COMMON_ISCSI_NTWK_SET_VLAN,
1256                            sizeof(*req));
1257
1258         req->interface_hndl = phba->interface_handle;
1259         req->vlan_priority = vlan_tag;
1260
1261         be_mcc_notify(phba, tag);
1262         mutex_unlock(&ctrl->mbox_lock);
1263
1264         return tag;
1265 }
1266
1267 int beiscsi_check_supported_fw(struct be_ctrl_info *ctrl,
1268                                struct beiscsi_hba *phba)
1269 {
1270         struct be_dma_mem nonemb_cmd;
1271         struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1272         struct be_mgmt_controller_attributes *req;
1273         struct be_sge *sge = nonembedded_sgl(wrb);
1274         int status = 0;
1275
1276         nonemb_cmd.va = pci_alloc_consistent(ctrl->pdev,
1277                                 sizeof(struct be_mgmt_controller_attributes),
1278                                 &nonemb_cmd.dma);
1279         if (nonemb_cmd.va == NULL) {
1280                 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1281                             "BG_%d : pci_alloc_consistent failed in %s\n",
1282                             __func__);
1283                 return -ENOMEM;
1284         }
1285         nonemb_cmd.size = sizeof(struct be_mgmt_controller_attributes);
1286         req = nonemb_cmd.va;
1287         memset(req, 0, sizeof(*req));
1288         mutex_lock(&ctrl->mbox_lock);
1289         memset(wrb, 0, sizeof(*wrb));
1290         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1);
1291         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1292                            OPCODE_COMMON_GET_CNTL_ATTRIBUTES, sizeof(*req));
1293         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd.dma));
1294         sge->pa_lo = cpu_to_le32(nonemb_cmd.dma & 0xFFFFFFFF);
1295         sge->len = cpu_to_le32(nonemb_cmd.size);
1296         status = be_mbox_notify(ctrl);
1297         if (!status) {
1298                 struct be_mgmt_controller_attributes_resp *resp = nonemb_cmd.va;
1299
1300                 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1301                             "BG_%d : Firmware Version of CMD : %s\n"
1302                             "Firmware Version is : %s\n"
1303                             "Developer Build, not performing version check...\n",
1304                             resp->params.hba_attribs
1305                             .flashrom_version_string,
1306                             resp->params.hba_attribs.
1307                             firmware_version_string);
1308
1309                 phba->fw_config.iscsi_features =
1310                                 resp->params.hba_attribs.iscsi_features;
1311                 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1312                             "BM_%d : phba->fw_config.iscsi_features = %d\n",
1313                             phba->fw_config.iscsi_features);
1314                 memcpy(phba->fw_ver_str, resp->params.hba_attribs.
1315                        firmware_version_string, BEISCSI_VER_STRLEN);
1316         } else
1317                 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1318                             "BG_%d :  Failed in beiscsi_check_supported_fw\n");
1319         mutex_unlock(&ctrl->mbox_lock);
1320         if (nonemb_cmd.va)
1321                 pci_free_consistent(ctrl->pdev, nonemb_cmd.size,
1322                                     nonemb_cmd.va, nonemb_cmd.dma);
1323
1324         return status;
1325 }
1326
1327 /**
1328  * beiscsi_get_fw_config()- Get the FW config for the function
1329  * @ctrl: ptr to Ctrl Info
1330  * @phba: ptr to the dev priv structure
1331  *
1332  * Get the FW config and resources available for the function.
1333  * The resources are created based on the count received here.
1334  *
1335  * return
1336  *      Success: 0
1337  *      Failure: Non-Zero Value
1338  **/
1339 int beiscsi_get_fw_config(struct be_ctrl_info *ctrl,
1340                           struct beiscsi_hba *phba)
1341 {
1342         struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1343         struct be_fw_cfg *pfw_cfg = embedded_payload(wrb);
1344         uint32_t cid_count, icd_count;
1345         int status = -EINVAL;
1346         uint8_t ulp_num = 0;
1347
1348         mutex_lock(&ctrl->mbox_lock);
1349         memset(wrb, 0, sizeof(*wrb));
1350         be_wrb_hdr_prepare(wrb, sizeof(*pfw_cfg), true, 0);
1351
1352         be_cmd_hdr_prepare(&pfw_cfg->hdr, CMD_SUBSYSTEM_COMMON,
1353                            OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
1354                            EMBED_MBX_MAX_PAYLOAD_SIZE);
1355
1356         if (be_mbox_notify(ctrl)) {
1357                 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1358                             "BG_%d : Failed in beiscsi_get_fw_config\n");
1359                 goto fail_init;
1360         }
1361
1362         /* FW response formats depend on port id */
1363         phba->fw_config.phys_port = pfw_cfg->phys_port;
1364         if (phba->fw_config.phys_port >= BEISCSI_PHYS_PORT_MAX) {
1365                 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1366                             "BG_%d : invalid physical port id %d\n",
1367                             phba->fw_config.phys_port);
1368                 goto fail_init;
1369         }
1370
1371         /* populate and check FW config against min and max values */
1372         if (!is_chip_be2_be3r(phba)) {
1373                 phba->fw_config.eqid_count = pfw_cfg->eqid_count;
1374                 phba->fw_config.cqid_count = pfw_cfg->cqid_count;
1375                 if (phba->fw_config.eqid_count == 0 ||
1376                     phba->fw_config.eqid_count > 2048) {
1377                         beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1378                                     "BG_%d : invalid EQ count %d\n",
1379                                     phba->fw_config.eqid_count);
1380                         goto fail_init;
1381                 }
1382                 if (phba->fw_config.cqid_count == 0 ||
1383                     phba->fw_config.cqid_count > 4096) {
1384                         beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1385                                     "BG_%d : invalid CQ count %d\n",
1386                                     phba->fw_config.cqid_count);
1387                         goto fail_init;
1388                 }
1389                 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1390                             "BG_%d : EQ_Count : %d CQ_Count : %d\n",
1391                             phba->fw_config.eqid_count,
1392                             phba->fw_config.cqid_count);
1393         }
1394
1395         /**
1396          * Check on which all ULP iSCSI Protocol is loaded.
1397          * Set the Bit for those ULP. This set flag is used
1398          * at all places in the code to check on which ULP
1399          * iSCSi Protocol is loaded
1400          **/
1401         for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
1402                 if (pfw_cfg->ulp[ulp_num].ulp_mode &
1403                     BEISCSI_ULP_ISCSI_INI_MODE) {
1404                         set_bit(ulp_num, &phba->fw_config.ulp_supported);
1405
1406                         /* Get the CID, ICD and Chain count for each ULP */
1407                         phba->fw_config.iscsi_cid_start[ulp_num] =
1408                                 pfw_cfg->ulp[ulp_num].sq_base;
1409                         phba->fw_config.iscsi_cid_count[ulp_num] =
1410                                 pfw_cfg->ulp[ulp_num].sq_count;
1411
1412                         phba->fw_config.iscsi_icd_start[ulp_num] =
1413                                 pfw_cfg->ulp[ulp_num].icd_base;
1414                         phba->fw_config.iscsi_icd_count[ulp_num] =
1415                                 pfw_cfg->ulp[ulp_num].icd_count;
1416
1417                         phba->fw_config.iscsi_chain_start[ulp_num] =
1418                                 pfw_cfg->chain_icd[ulp_num].chain_base;
1419                         phba->fw_config.iscsi_chain_count[ulp_num] =
1420                                 pfw_cfg->chain_icd[ulp_num].chain_count;
1421
1422                         beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1423                                     "BG_%d : Function loaded on ULP : %d\n"
1424                                     "\tiscsi_cid_count : %d\n"
1425                                     "\tiscsi_cid_start : %d\n"
1426                                     "\t iscsi_icd_count : %d\n"
1427                                     "\t iscsi_icd_start : %d\n",
1428                                     ulp_num,
1429                                     phba->fw_config.
1430                                     iscsi_cid_count[ulp_num],
1431                                     phba->fw_config.
1432                                     iscsi_cid_start[ulp_num],
1433                                     phba->fw_config.
1434                                     iscsi_icd_count[ulp_num],
1435                                     phba->fw_config.
1436                                     iscsi_icd_start[ulp_num]);
1437                 }
1438         }
1439
1440         if (phba->fw_config.ulp_supported == 0) {
1441                 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1442                             "BG_%d : iSCSI initiator mode not set: ULP0 %x ULP1 %x\n",
1443                             pfw_cfg->ulp[BEISCSI_ULP0].ulp_mode,
1444                             pfw_cfg->ulp[BEISCSI_ULP1].ulp_mode);
1445                 goto fail_init;
1446         }
1447
1448         /**
1449          * ICD is shared among ULPs. Use icd_count of any one loaded ULP
1450          **/
1451         for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
1452                 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
1453                         break;
1454         icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
1455         if (icd_count == 0 || icd_count > 65536) {
1456                 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1457                             "BG_%d: invalid ICD count %d\n", icd_count);
1458                 goto fail_init;
1459         }
1460
1461         cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) +
1462                     BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1);
1463         if (cid_count == 0 || cid_count > 4096) {
1464                 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1465                             "BG_%d: invalid CID count %d\n", cid_count);
1466                 goto fail_init;
1467         }
1468
1469         /**
1470          * Check FW is dual ULP aware i.e. can handle either
1471          * of the protocols.
1472          */
1473         phba->fw_config.dual_ulp_aware = (pfw_cfg->function_mode &
1474                                           BEISCSI_FUNC_DUA_MODE);
1475
1476         beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1477                     "BG_%d : DUA Mode : 0x%x\n",
1478                     phba->fw_config.dual_ulp_aware);
1479
1480         /* all set, continue using this FW config */
1481         status = 0;
1482 fail_init:
1483         mutex_unlock(&ctrl->mbox_lock);
1484         return status;
1485 }
1486
1487 /**
1488  * beiscsi_get_port_name()- Get port name for the function
1489  * @ctrl: ptr to Ctrl Info
1490  * @phba: ptr to the dev priv structure
1491  *
1492  * Get the alphanumeric character for port
1493  *
1494  **/
1495 int beiscsi_get_port_name(struct be_ctrl_info *ctrl, struct beiscsi_hba *phba)
1496 {
1497         int ret = 0;
1498         struct be_mcc_wrb *wrb;
1499         struct be_cmd_get_port_name *ioctl;
1500
1501         mutex_lock(&ctrl->mbox_lock);
1502         wrb = wrb_from_mbox(&ctrl->mbox_mem);
1503         memset(wrb, 0, sizeof(*wrb));
1504         ioctl = embedded_payload(wrb);
1505
1506         be_wrb_hdr_prepare(wrb, sizeof(*ioctl), true, 0);
1507         be_cmd_hdr_prepare(&ioctl->h.req_hdr, CMD_SUBSYSTEM_COMMON,
1508                            OPCODE_COMMON_GET_PORT_NAME,
1509                            EMBED_MBX_MAX_PAYLOAD_SIZE);
1510         ret = be_mbox_notify(ctrl);
1511         phba->port_name = 0;
1512         if (!ret) {
1513                 phba->port_name = ioctl->p.resp.port_names >>
1514                                   (phba->fw_config.phys_port * 8) & 0xff;
1515         } else {
1516                 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1517                             "BG_%d : GET_PORT_NAME ret 0x%x status 0x%x\n",
1518                             ret, ioctl->h.resp_hdr.status);
1519         }
1520
1521         if (phba->port_name == 0)
1522                 phba->port_name = '?';
1523
1524         mutex_unlock(&ctrl->mbox_lock);
1525         return ret;
1526 }
1527
1528 int beiscsi_set_uer_feature(struct beiscsi_hba *phba)
1529 {
1530         struct be_ctrl_info *ctrl = &phba->ctrl;
1531         struct be_cmd_set_features *ioctl;
1532         struct be_mcc_wrb *wrb;
1533         int ret = 0;
1534
1535         mutex_lock(&ctrl->mbox_lock);
1536         wrb = wrb_from_mbox(&ctrl->mbox_mem);
1537         memset(wrb, 0, sizeof(*wrb));
1538         ioctl = embedded_payload(wrb);
1539
1540         be_wrb_hdr_prepare(wrb, sizeof(*ioctl), true, 0);
1541         be_cmd_hdr_prepare(&ioctl->h.req_hdr, CMD_SUBSYSTEM_COMMON,
1542                            OPCODE_COMMON_SET_FEATURES,
1543                            EMBED_MBX_MAX_PAYLOAD_SIZE);
1544         ioctl->feature = BE_CMD_SET_FEATURE_UER;
1545         ioctl->param_len = sizeof(ioctl->param.req);
1546         ioctl->param.req.uer = BE_CMD_UER_SUPP_BIT;
1547         ret = be_mbox_notify(ctrl);
1548         if (!ret) {
1549                 phba->ue2rp = ioctl->param.resp.ue2rp;
1550                 set_bit(BEISCSI_HBA_UER_SUPP, &phba->state);
1551                 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1552                             "BG_%d : HBA error recovery supported\n");
1553         } else {
1554                 /**
1555                  * Check "MCC_STATUS_INVALID_LENGTH" for SKH.
1556                  * Older FW versions return this error.
1557                  */
1558                 if (ret == MCC_STATUS_ILLEGAL_REQUEST ||
1559                     ret == MCC_STATUS_INVALID_LENGTH)
1560                         __beiscsi_log(phba, KERN_INFO,
1561                                       "BG_%d : HBA error recovery not supported\n");
1562         }
1563
1564         mutex_unlock(&ctrl->mbox_lock);
1565         return ret;
1566 }
1567
1568 static u32 beiscsi_get_post_stage(struct beiscsi_hba *phba)
1569 {
1570         u32 sem;
1571
1572         if (is_chip_be2_be3r(phba))
1573                 sem = ioread32(phba->csr_va + SLIPORT_SEMAPHORE_OFFSET_BEx);
1574         else
1575                 pci_read_config_dword(phba->pcidev,
1576                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
1577         return sem;
1578 }
1579
1580 int beiscsi_check_fw_rdy(struct beiscsi_hba *phba)
1581 {
1582         u32 loop, post, rdy = 0;
1583
1584         loop = 1000;
1585         while (loop--) {
1586                 post = beiscsi_get_post_stage(phba);
1587                 if (post & POST_ERROR_BIT)
1588                         break;
1589                 if ((post & POST_STAGE_MASK) == POST_STAGE_ARMFW_RDY) {
1590                         rdy = 1;
1591                         break;
1592                 }
1593                 msleep(60);
1594         }
1595
1596         if (!rdy) {
1597                 __beiscsi_log(phba, KERN_ERR,
1598                               "BC_%d : FW not ready 0x%x\n", post);
1599         }
1600
1601         return rdy;
1602 }
1603
1604 int beiscsi_cmd_function_reset(struct beiscsi_hba *phba)
1605 {
1606         struct be_ctrl_info *ctrl = &phba->ctrl;
1607         struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1608         struct be_post_sgl_pages_req *req = embedded_payload(wrb);
1609         int status;
1610
1611         mutex_lock(&ctrl->mbox_lock);
1612
1613         req = embedded_payload(wrb);
1614         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1615         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1616                            OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1617         status = be_mbox_notify(ctrl);
1618
1619         mutex_unlock(&ctrl->mbox_lock);
1620         return status;
1621 }
1622
1623 int beiscsi_cmd_special_wrb(struct be_ctrl_info *ctrl, u32 load)
1624 {
1625         struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1626         struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1627         u8 *endian_check;
1628         int status;
1629
1630         mutex_lock(&ctrl->mbox_lock);
1631         memset(wrb, 0, sizeof(*wrb));
1632
1633         endian_check = (u8 *) wrb;
1634         if (load) {
1635                 /* to start communicating */
1636                 *endian_check++ = 0xFF;
1637                 *endian_check++ = 0x12;
1638                 *endian_check++ = 0x34;
1639                 *endian_check++ = 0xFF;
1640                 *endian_check++ = 0xFF;
1641                 *endian_check++ = 0x56;
1642                 *endian_check++ = 0x78;
1643                 *endian_check++ = 0xFF;
1644         } else {
1645                 /* to stop communicating */
1646                 *endian_check++ = 0xFF;
1647                 *endian_check++ = 0xAA;
1648                 *endian_check++ = 0xBB;
1649                 *endian_check++ = 0xFF;
1650                 *endian_check++ = 0xFF;
1651                 *endian_check++ = 0xCC;
1652                 *endian_check++ = 0xDD;
1653                 *endian_check = 0xFF;
1654         }
1655         be_dws_cpu_to_le(wrb, sizeof(*wrb));
1656
1657         status = be_mbox_notify(ctrl);
1658         if (status)
1659                 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1660                             "BC_%d : special WRB message failed\n");
1661         mutex_unlock(&ctrl->mbox_lock);
1662         return status;
1663 }
1664
1665 int beiscsi_init_sliport(struct beiscsi_hba *phba)
1666 {
1667         int status;
1668
1669         /* check POST stage before talking to FW */
1670         status = beiscsi_check_fw_rdy(phba);
1671         if (!status)
1672                 return -EIO;
1673
1674         /* clear all error states after checking FW rdy */
1675         phba->state &= ~BEISCSI_HBA_IN_ERR;
1676
1677         /* check again UER support */
1678         phba->state &= ~BEISCSI_HBA_UER_SUPP;
1679
1680         /*
1681          * SLI COMMON_FUNCTION_RESET completion is indicated by BMBX RDY bit.
1682          * It should clean up any stale info in FW for this fn.
1683          */
1684         status = beiscsi_cmd_function_reset(phba);
1685         if (status) {
1686                 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1687                             "BC_%d : SLI Function Reset failed\n");
1688                 return status;
1689         }
1690
1691         /* indicate driver is loading */
1692         return beiscsi_cmd_special_wrb(&phba->ctrl, 1);
1693 }
1694
1695 /**
1696  * beiscsi_cmd_iscsi_cleanup()- Inform FW to cleanup EP data structures.
1697  * @phba: pointer to dev priv structure
1698  * @ulp: ULP number.
1699  *
1700  * return
1701  *      Success: 0
1702  *      Failure: Non-Zero Value
1703  **/
1704 int beiscsi_cmd_iscsi_cleanup(struct beiscsi_hba *phba, unsigned short ulp)
1705 {
1706         struct be_ctrl_info *ctrl = &phba->ctrl;
1707         struct iscsi_cleanup_req_v1 *req_v1;
1708         struct iscsi_cleanup_req *req;
1709         struct be_mcc_wrb *wrb;
1710         int status;
1711
1712         mutex_lock(&ctrl->mbox_lock);
1713         wrb = wrb_from_mbox(&ctrl->mbox_mem);
1714         req = embedded_payload(wrb);
1715         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1716         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1717                            OPCODE_COMMON_ISCSI_CLEANUP, sizeof(*req));
1718
1719        /**
1720         * TODO: Check with FW folks the chute value to be set.
1721         * For now, use the ULP_MASK as the chute value.
1722         */
1723         if (is_chip_be2_be3r(phba)) {
1724                 req->chute = (1 << ulp);
1725                 req->hdr_ring_id = HWI_GET_DEF_HDRQ_ID(phba, ulp);
1726                 req->data_ring_id = HWI_GET_DEF_BUFQ_ID(phba, ulp);
1727         } else {
1728                 req_v1 = (struct iscsi_cleanup_req_v1 *)req;
1729                 req_v1->hdr.version = 1;
1730                 req_v1->hdr_ring_id = cpu_to_le16(HWI_GET_DEF_HDRQ_ID(phba,
1731                                                                       ulp));
1732                 req_v1->data_ring_id = cpu_to_le16(HWI_GET_DEF_BUFQ_ID(phba,
1733                                                                        ulp));
1734         }
1735
1736         status = be_mbox_notify(ctrl);
1737         if (status)
1738                 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
1739                             "BG_%d : %s failed %d\n", __func__, ulp);
1740         mutex_unlock(&ctrl->mbox_lock);
1741         return status;
1742 }
1743
1744 /*
1745  * beiscsi_detect_ue()- Detect Unrecoverable Error on adapter
1746  * @phba: Driver priv structure
1747  *
1748  * Read registers linked to UE and check for the UE status
1749  **/
1750 int beiscsi_detect_ue(struct beiscsi_hba *phba)
1751 {
1752         uint32_t ue_mask_hi = 0, ue_mask_lo = 0;
1753         uint32_t ue_hi = 0, ue_lo = 0;
1754         uint8_t i = 0;
1755         int ret = 0;
1756
1757         pci_read_config_dword(phba->pcidev,
1758                               PCICFG_UE_STATUS_LOW, &ue_lo);
1759         pci_read_config_dword(phba->pcidev,
1760                               PCICFG_UE_STATUS_MASK_LOW,
1761                               &ue_mask_lo);
1762         pci_read_config_dword(phba->pcidev,
1763                               PCICFG_UE_STATUS_HIGH,
1764                               &ue_hi);
1765         pci_read_config_dword(phba->pcidev,
1766                               PCICFG_UE_STATUS_MASK_HI,
1767                               &ue_mask_hi);
1768
1769         ue_lo = (ue_lo & ~ue_mask_lo);
1770         ue_hi = (ue_hi & ~ue_mask_hi);
1771
1772
1773         if (ue_lo || ue_hi) {
1774                 set_bit(BEISCSI_HBA_IN_UE, &phba->state);
1775                 __beiscsi_log(phba, KERN_ERR,
1776                               "BC_%d : HBA error detected\n");
1777                 ret = 1;
1778         }
1779
1780         if (ue_lo) {
1781                 for (i = 0; ue_lo; ue_lo >>= 1, i++) {
1782                         if (ue_lo & 1)
1783                                 __beiscsi_log(phba, KERN_ERR,
1784                                               "BC_%d : UE_LOW %s bit set\n",
1785                                               desc_ue_status_low[i]);
1786                 }
1787         }
1788
1789         if (ue_hi) {
1790                 for (i = 0; ue_hi; ue_hi >>= 1, i++) {
1791                         if (ue_hi & 1)
1792                                 __beiscsi_log(phba, KERN_ERR,
1793                                               "BC_%d : UE_HIGH %s bit set\n",
1794                                               desc_ue_status_hi[i]);
1795                 }
1796         }
1797         return ret;
1798 }
1799
1800 /*
1801  * beiscsi_detect_tpe()- Detect Transient Parity Error on adapter
1802  * @phba: Driver priv structure
1803  *
1804  * Read SLIPORT SEMAPHORE register to check for UER
1805  *
1806  **/
1807 int beiscsi_detect_tpe(struct beiscsi_hba *phba)
1808 {
1809         u32 post, status;
1810         int ret = 0;
1811
1812         post = beiscsi_get_post_stage(phba);
1813         status = post & POST_STAGE_MASK;
1814         if ((status & POST_ERR_RECOVERY_CODE_MASK) ==
1815             POST_STAGE_RECOVERABLE_ERR) {
1816                 set_bit(BEISCSI_HBA_IN_TPE, &phba->state);
1817                 __beiscsi_log(phba, KERN_INFO,
1818                               "BC_%d : HBA error recoverable: 0x%x\n", post);
1819                 ret = 1;
1820         } else {
1821                 __beiscsi_log(phba, KERN_INFO,
1822                               "BC_%d : HBA in UE: 0x%x\n", post);
1823         }
1824
1825         return ret;
1826 }