drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

   1 /*
   2  * Copyright (c) 2016 Linaro Ltd.
   3  * Copyright (c) 2016 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  */
  11
  12 #include "hisi_sas.h"
  13 #define DRV_NAME "hisi_sas_v2_hw"
  14
  15 /* global registers need init*/
  16 #define DLVRY_QUEUE_ENABLE              0x0
  17 #define IOST_BASE_ADDR_LO               0x8
  18 #define IOST_BASE_ADDR_HI               0xc
  19 #define ITCT_BASE_ADDR_LO               0x10
  20 #define ITCT_BASE_ADDR_HI               0x14
  21 #define IO_BROKEN_MSG_ADDR_LO           0x18
  22 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  23 #define PHY_CONTEXT                     0x20
  24 #define PHY_STATE                       0x24
  25 #define PHY_PORT_NUM_MA                 0x28
  26 #define PORT_STATE                      0x2c
  27 #define PORT_STATE_PHY8_PORT_NUM_OFF    16
  28 #define PORT_STATE_PHY8_PORT_NUM_MSK    (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
  29 #define PORT_STATE_PHY8_CONN_RATE_OFF   20
  30 #define PORT_STATE_PHY8_CONN_RATE_MSK   (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
  31 #define PHY_CONN_RATE                   0x30
  32 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
  33 #define AXI_AHB_CLK_CFG                 0x3c
  34 #define ITCT_CLR                        0x44
  35 #define ITCT_CLR_EN_OFF                 16
  36 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  37 #define ITCT_DEV_OFF                    0
  38 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  39 #define AXI_USER1                       0x48
  40 #define AXI_USER2                       0x4c
  41 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  42 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  43 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  44 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  46 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  47 #define HGC_GET_ITV_TIME                0x90
  48 #define DEVICE_MSG_WORK_MODE            0x94
  49 #define OPENA_WT_CONTI_TIME             0x9c
  50 #define I_T_NEXUS_LOSS_TIME             0xa0
  51 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  52 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  53 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  54 #define CFG_AGING_TIME                  0xbc
  55 #define HGC_DFX_CFG2                    0xc0
  56 #define HGC_IOMB_PROC1_STATUS   0x104
  57 #define CFG_1US_TIMER_TRSH              0xcc
  58 #define HGC_LM_DFX_STATUS2              0x128
  59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF         0
  60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
  61                                          HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
  62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF         12
  63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
  64                                          HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
  65 #define HGC_CQE_ECC_ADDR                0x13c
  66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
  67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
  68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
  69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
  70 #define HGC_IOST_ECC_ADDR               0x140
  71 #define HGC_IOST_ECC_1B_ADDR_OFF        0
  72 #define HGC_IOST_ECC_1B_ADDR_MSK        (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
  73 #define HGC_IOST_ECC_MB_ADDR_OFF        16
  74 #define HGC_IOST_ECC_MB_ADDR_MSK        (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
  75 #define HGC_DQE_ECC_ADDR                0x144
  76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
  77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
  78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
  79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
  80 #define HGC_INVLD_DQE_INFO              0x148
  81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF   9
  82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK   (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
  83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF   18
  84 #define HGC_ITCT_ECC_ADDR               0x150
  85 #define HGC_ITCT_ECC_1B_ADDR_OFF                0
  86 #define HGC_ITCT_ECC_1B_ADDR_MSK                (0x3ff << \
  87                                                  HGC_ITCT_ECC_1B_ADDR_OFF)
  88 #define HGC_ITCT_ECC_MB_ADDR_OFF                16
  89 #define HGC_ITCT_ECC_MB_ADDR_MSK                (0x3ff << \
  90                                                  HGC_ITCT_ECC_MB_ADDR_OFF)
  91 #define HGC_AXI_FIFO_ERR_INFO   0x154
  92 #define AXI_ERR_INFO_OFF                0
  93 #define AXI_ERR_INFO_MSK                (0xff << AXI_ERR_INFO_OFF)
  94 #define FIFO_ERR_INFO_OFF               8
  95 #define FIFO_ERR_INFO_MSK               (0xff << FIFO_ERR_INFO_OFF)
  96 #define INT_COAL_EN                     0x19c
  97 #define OQ_INT_COAL_TIME                0x1a0
  98 #define OQ_INT_COAL_CNT                 0x1a4
  99 #define ENT_INT_COAL_TIME               0x1a8
 100 #define ENT_INT_COAL_CNT                0x1ac
 101 #define OQ_INT_SRC                      0x1b0
 102 #define OQ_INT_SRC_MSK                  0x1b4
 103 #define ENT_INT_SRC1                    0x1b8
 104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
 105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
 106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
 107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
 108 #define ENT_INT_SRC2                    0x1bc
 109 #define ENT_INT_SRC3                    0x1c0
 110 #define ENT_INT_SRC3_WP_DEPTH_OFF               8
 111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF      9
 112 #define ENT_INT_SRC3_RP_DEPTH_OFF               10
 113 #define ENT_INT_SRC3_AXI_OFF                    11
 114 #define ENT_INT_SRC3_FIFO_OFF                   12
 115 #define ENT_INT_SRC3_LM_OFF                             14
 116 #define ENT_INT_SRC3_ITC_INT_OFF        15
 117 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
 118 #define ENT_INT_SRC3_ABT_OFF            16
 119 #define ENT_INT_SRC_MSK1                0x1c4
 120 #define ENT_INT_SRC_MSK2                0x1c8
 121 #define ENT_INT_SRC_MSK3                0x1cc
 122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
 123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
 124 #define SAS_ECC_INTR                    0x1e8
 125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF             0
 126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF             1
 127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF    2
 128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF    3
 129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF    4
 130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF    5
 131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF        6
 132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF        7
 133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF        8
 134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF        9
 135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF             10
 136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF             11
 137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF        12
 138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF        13
 139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF        14
 140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF        15
 141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF        16
 142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF        17
 143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF        18
 144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF        19
 145 #define SAS_ECC_INTR_MSK                0x1ec
 146 #define HGC_ERR_STAT_EN                 0x238
 147 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
 148 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
 149 #define DLVRY_Q_0_DEPTH                 0x268
 150 #define DLVRY_Q_0_WR_PTR                0x26c
 151 #define DLVRY_Q_0_RD_PTR                0x270
 152 #define HYPER_STREAM_ID_EN_CFG          0xc80
 153 #define OQ0_INT_SRC_MSK                 0xc90
 154 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
 155 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
 156 #define COMPL_Q_0_DEPTH                 0x4e8
 157 #define COMPL_Q_0_WR_PTR                0x4ec
 158 #define COMPL_Q_0_RD_PTR                0x4f0
 159 #define HGC_RXM_DFX_STATUS14    0xae8
 160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF           0
 161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK           (0x1ff << \
 162                                                  HGC_RXM_DFX_STATUS14_MEM0_OFF)
 163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF           9
 164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK           (0x1ff << \
 165                                                  HGC_RXM_DFX_STATUS14_MEM1_OFF)
 166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF           18
 167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK           (0x1ff << \
 168                                                  HGC_RXM_DFX_STATUS14_MEM2_OFF)
 169 #define HGC_RXM_DFX_STATUS15    0xaec
 170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF           0
 171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK           (0x1ff << \
 172                                                  HGC_RXM_DFX_STATUS15_MEM3_OFF)
 173 /* phy registers need init */
 174 #define PORT_BASE                       (0x2000)
 175
 176 #define PHY_CFG                         (PORT_BASE + 0x0)
 177 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 178 #define PHY_CFG_ENA_OFF                 0
 179 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 180 #define PHY_CFG_DC_OPT_OFF              2
 181 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 182 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 183 #define PROG_PHY_LINK_RATE_MAX_OFF      0
 184 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
 185 #define PHY_CTRL                        (PORT_BASE + 0x14)
 186 #define PHY_CTRL_RESET_OFF              0
 187 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 188 #define SAS_PHY_CTRL                    (PORT_BASE + 0x20)
 189 #define SL_CFG                          (PORT_BASE + 0x84)
 190 #define PHY_PCN                         (PORT_BASE + 0x44)
 191 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
 192 #define SL_CONTROL                      (PORT_BASE + 0x94)
 193 #define SL_CONTROL_NOTIFY_EN_OFF        0
 194 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 195 #define SL_CONTROL_CTA_OFF              17
 196 #define SL_CONTROL_CTA_MSK              (0x1 << SL_CONTROL_CTA_OFF)
 197 #define RX_PRIMS_STATUS                 (PORT_BASE + 0x98)
 198 #define RX_BCAST_CHG_OFF                1
 199 #define RX_BCAST_CHG_MSK                (0x1 << RX_BCAST_CHG_OFF)
 200 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 201 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 202 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 203 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 204 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 205 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 206 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 207 #define TXID_AUTO                       (PORT_BASE + 0xb8)
 208 #define TXID_AUTO_CT3_OFF               1
 209 #define TXID_AUTO_CT3_MSK               (0x1 << TXID_AUTO_CT3_OFF)
 210 #define TXID_AUTO_CTB_OFF               11
 211 #define TXID_AUTO_CTB_MSK               (0x1 << TXID_AUTO_CTB_OFF)
 212 #define TX_HARDRST_OFF                  2
 213 #define TX_HARDRST_MSK                  (0x1 << TX_HARDRST_OFF)
 214 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 215 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
 216 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
 217 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
 218 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
 219 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
 220 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
 221 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 222 #define CON_CONTROL                     (PORT_BASE + 0x118)
 223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF        0
 224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK        \
 225                 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
 226 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x11c)
 227 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 228 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 229 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 230 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 231 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 232 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 233 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 234 #define CHL_INT0_NOT_RDY_OFF            4
 235 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 236 #define CHL_INT0_PHY_RDY_OFF            5
 237 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 238 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 243 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 244 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 245 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 246 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 247 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 248 #define DMA_TX_DFX0                             (PORT_BASE + 0x200)
 249 #define DMA_TX_DFX1                             (PORT_BASE + 0x204)
 250 #define DMA_TX_DFX1_IPTT_OFF            0
 251 #define DMA_TX_DFX1_IPTT_MSK            (0xffff << DMA_TX_DFX1_IPTT_OFF)
 252 #define DMA_TX_FIFO_DFX0                (PORT_BASE + 0x240)
 253 #define PORT_DFX0                               (PORT_BASE + 0x258)
 254 #define LINK_DFX2                                       (PORT_BASE + 0X264)
 255 #define LINK_DFX2_RCVR_HOLD_STS_OFF     9
 256 #define LINK_DFX2_RCVR_HOLD_STS_MSK     (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
 257 #define LINK_DFX2_SEND_HOLD_STS_OFF     10
 258 #define LINK_DFX2_SEND_HOLD_STS_MSK     (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
 259 #define SAS_ERR_CNT4_REG                (PORT_BASE + 0x290)
 260 #define SAS_ERR_CNT6_REG                (PORT_BASE + 0x298)
 261 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 262 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 263 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 264 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 265 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 266 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 267 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 268 #define DMA_TX_STATUS_BUSY_OFF          0
 269 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 270 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 271 #define DMA_RX_STATUS_BUSY_OFF          0
 272 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 273
 274 #define AXI_CFG                         (0x5100)
 275 #define AM_CFG_MAX_TRANS                (0x5010)
 276 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 277
 278 #define AXI_MASTER_CFG_BASE             (0x5000)
 279 #define AM_CTRL_GLOBAL                  (0x0)
 280 #define AM_CURR_TRANS_RETURN    (0x150)
 281
 282 /* HW dma structures */
 283 /* Delivery queue header */
 284 /* dw0 */
 285 #define CMD_HDR_ABORT_FLAG_OFF          0
 286 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
 287 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
 288 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
 289 #define CMD_HDR_RESP_REPORT_OFF         5
 290 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 291 #define CMD_HDR_TLR_CTRL_OFF            6
 292 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 293 #define CMD_HDR_PORT_OFF                18
 294 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 295 #define CMD_HDR_PRIORITY_OFF            27
 296 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 297 #define CMD_HDR_CMD_OFF                 29
 298 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 299 /* dw1 */
 300 #define CMD_HDR_DIR_OFF                 5
 301 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 302 #define CMD_HDR_RESET_OFF               7
 303 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 304 #define CMD_HDR_VDTL_OFF                10
 305 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 306 #define CMD_HDR_FRAME_TYPE_OFF          11
 307 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 308 #define CMD_HDR_DEV_ID_OFF              16
 309 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 310 /* dw2 */
 311 #define CMD_HDR_CFL_OFF                 0
 312 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 313 #define CMD_HDR_NCQ_TAG_OFF             10
 314 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 315 #define CMD_HDR_MRFL_OFF                15
 316 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 317 #define CMD_HDR_SG_MOD_OFF              24
 318 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 319 #define CMD_HDR_FIRST_BURST_OFF         26
 320 #define CMD_HDR_FIRST_BURST_MSK         (0x1 << CMD_HDR_SG_MOD_OFF)
 321 /* dw3 */
 322 #define CMD_HDR_IPTT_OFF                0
 323 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 324 /* dw6 */
 325 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 326 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 327 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 328 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 329 #define CMD_HDR_ABORT_IPTT_OFF          16
 330 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
 331
 332 /* Completion header */
 333 /* dw0 */
 334 #define CMPLT_HDR_ERR_PHASE_OFF 2
 335 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
 336 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 337 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 338 #define CMPLT_HDR_ERX_OFF               12
 339 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 340 #define CMPLT_HDR_ABORT_STAT_OFF        13
 341 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
 342 /* abort_stat */
 343 #define STAT_IO_NOT_VALID               0x1
 344 #define STAT_IO_NO_DEVICE               0x2
 345 #define STAT_IO_COMPLETE                0x3
 346 #define STAT_IO_ABORTED                 0x4
 347 /* dw1 */
 348 #define CMPLT_HDR_IPTT_OFF              0
 349 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 350 #define CMPLT_HDR_DEV_ID_OFF            16
 351 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 352
 353 /* ITCT header */
 354 /* qw0 */
 355 #define ITCT_HDR_DEV_TYPE_OFF           0
 356 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 357 #define ITCT_HDR_VALID_OFF              2
 358 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 359 #define ITCT_HDR_MCR_OFF                5
 360 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 361 #define ITCT_HDR_VLN_OFF                9
 362 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 363 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
 364 #define ITCT_HDR_SMP_TIMEOUT_8US        1
 365 #define ITCT_HDR_SMP_TIMEOUT            (ITCT_HDR_SMP_TIMEOUT_8US * \
 366                                          250) /* 2ms */
 367 #define ITCT_HDR_AWT_CONTINUE_OFF       25
 368 #define ITCT_HDR_PORT_ID_OFF            28
 369 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 370 /* qw2 */
 371 #define ITCT_HDR_INLT_OFF               0
 372 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 373 #define ITCT_HDR_BITLT_OFF              16
 374 #define ITCT_HDR_BITLT_MSK              (0xffffULL << ITCT_HDR_BITLT_OFF)
 375 #define ITCT_HDR_MCTLT_OFF              32
 376 #define ITCT_HDR_MCTLT_MSK              (0xffffULL << ITCT_HDR_MCTLT_OFF)
 377 #define ITCT_HDR_RTOLT_OFF              48
 378 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 379
 380 #define HISI_SAS_FATAL_INT_NR   2
 381
 382 struct hisi_sas_complete_v2_hdr {
 383         __le32 dw0;
 384         __le32 dw1;
 385         __le32 act;
 386         __le32 dw3;
 387 };
 388
 389 struct hisi_sas_err_record_v2 {
 390         /* dw0 */
 391         __le32 trans_tx_fail_type;
 392
 393         /* dw1 */
 394         __le32 trans_rx_fail_type;
 395
 396         /* dw2 */
 397         __le16 dma_tx_err_type;
 398         __le16 sipc_rx_err_type;
 399
 400         /* dw3 */
 401         __le32 dma_rx_err_type;
 402 };
 403
 404 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
 405         {
 406                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
 407                 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
 408                 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
 409                 .msg = "hgc_dqe_acc1b_intr found: \
 410                                 Ram address is 0x%08X\n",
 411                 .reg = HGC_DQE_ECC_ADDR,
 412         },
 413         {
 414                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
 415                 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
 416                 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
 417                 .msg = "hgc_iost_acc1b_intr found: \
 418                                 Ram address is 0x%08X\n",
 419                 .reg = HGC_IOST_ECC_ADDR,
 420         },
 421         {
 422                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
 423                 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
 424                 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
 425                 .msg = "hgc_itct_acc1b_intr found: \
 426                                 Ram address is 0x%08X\n",
 427                 .reg = HGC_ITCT_ECC_ADDR,
 428         },
 429         {
 430                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
 431                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
 432                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
 433                 .msg = "hgc_iostl_acc1b_intr found:  \
 434                                 memory address is 0x%08X\n",
 435                 .reg = HGC_LM_DFX_STATUS2,
 436         },
 437         {
 438                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
 439                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
 440                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
 441                 .msg = "hgc_itctl_acc1b_intr found: \
 442                                 memory address is 0x%08X\n",
 443                 .reg = HGC_LM_DFX_STATUS2,
 444         },
 445         {
 446                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
 447                 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
 448                 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
 449                 .msg = "hgc_cqe_acc1b_intr found: \
 450                                 Ram address is 0x%08X\n",
 451                 .reg = HGC_CQE_ECC_ADDR,
 452         },
 453         {
 454                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
 455                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
 456                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
 457                 .msg = "rxm_mem0_acc1b_intr found: \
 458                                 memory address is 0x%08X\n",
 459                 .reg = HGC_RXM_DFX_STATUS14,
 460         },
 461         {
 462                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
 463                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
 464                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
 465                 .msg = "rxm_mem1_acc1b_intr found: \
 466                                 memory address is 0x%08X\n",
 467                 .reg = HGC_RXM_DFX_STATUS14,
 468         },
 469         {
 470                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
 471                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
 472                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
 473                 .msg = "rxm_mem2_acc1b_intr found: \
 474                                 memory address is 0x%08X\n",
 475                 .reg = HGC_RXM_DFX_STATUS14,
 476         },
 477         {
 478                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
 479                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
 480                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
 481                 .msg = "rxm_mem3_acc1b_intr found: \
 482                                 memory address is 0x%08X\n",
 483                 .reg = HGC_RXM_DFX_STATUS15,
 484         },
 485 };
 486
 487 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
 488         {
 489                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
 490                 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
 491                 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
 492                 .msg = "hgc_dqe_accbad_intr (0x%x) found: \
 493                                 Ram address is 0x%08X\n",
 494                 .reg = HGC_DQE_ECC_ADDR,
 495         },
 496         {
 497                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
 498                 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
 499                 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
 500                 .msg = "hgc_iost_accbad_intr (0x%x) found: \
 501                                 Ram address is 0x%08X\n",
 502                 .reg = HGC_IOST_ECC_ADDR,
 503         },
 504         {
 505                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
 506                 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
 507                 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
 508                 .msg = "hgc_itct_accbad_intr (0x%x) found: \
 509                                 Ram address is 0x%08X\n",
 510                 .reg = HGC_ITCT_ECC_ADDR,
 511         },
 512         {
 513                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
 514                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
 515                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
 516                 .msg = "hgc_iostl_accbad_intr (0x%x) found: \
 517                                 memory address is 0x%08X\n",
 518                 .reg = HGC_LM_DFX_STATUS2,
 519         },
 520         {
 521                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
 522                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
 523                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
 524                 .msg = "hgc_itctl_accbad_intr (0x%x) found: \
 525                                 memory address is 0x%08X\n",
 526                 .reg = HGC_LM_DFX_STATUS2,
 527         },
 528         {
 529                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
 530                 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
 531                 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
 532                 .msg = "hgc_cqe_accbad_intr (0x%x) found: \
 533                                 Ram address is 0x%08X\n",
 534                 .reg = HGC_CQE_ECC_ADDR,
 535         },
 536         {
 537                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
 538                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
 539                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
 540                 .msg = "rxm_mem0_accbad_intr (0x%x) found: \
 541                         memory address is 0x%08X\n",
 542                 .reg = HGC_RXM_DFX_STATUS14,
 543         },
 544         {
 545                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
 546                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
 547                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
 548                 .msg = "rxm_mem1_accbad_intr (0x%x) found: \
 549                         memory address is 0x%08X\n",
 550                 .reg = HGC_RXM_DFX_STATUS14,
 551         },
 552         {
 553                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
 554                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
 555                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
 556                 .msg = "rxm_mem2_accbad_intr (0x%x) found: \
 557                                 memory address is 0x%08X\n",
 558                 .reg = HGC_RXM_DFX_STATUS14,
 559         },
 560         {
 561                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
 562                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
 563                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
 564                 .msg = "rxm_mem3_accbad_intr (0x%x) found: \
 565                                 memory address is 0x%08X\n",
 566                 .reg = HGC_RXM_DFX_STATUS15,
 567         },
 568 };
 569
 570 enum {
 571         HISI_SAS_PHY_PHY_UPDOWN,
 572         HISI_SAS_PHY_CHNL_INT,
 573         HISI_SAS_PHY_INT_NR
 574 };
 575
 576 enum {
 577         TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
 578         TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
 579         DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
 580         SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
 581         DMA_RX_ERR_BASE = 0x60, /* dw3 */
 582
 583         /* trans tx*/
 584         TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
 585         TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
 586         TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
 587         TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
 588         TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
 589         RESERVED0, /* 0x5 */
 590         TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
 591         TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
 592         TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
 593         TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
 594         TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
 595         TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
 596         TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
 597         TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
 598         TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
 599         TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
 600         TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
 601         TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
 602         TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
 603         TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
 604         TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
 605         TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
 606         TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
 607         TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
 608         TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
 609         TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
 610         TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
 611         TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
 612         /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
 613         TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
 614         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
 615         TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
 616         TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
 617         /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
 618         TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
 619
 620         /* trans rx */
 621         TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
 622         TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
 623         TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
 624         /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
 625         TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
 626         TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
 627         TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
 628         /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
 629         TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
 630         TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
 631         TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
 632         TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
 633         TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
 634         RESERVED1, /* 0x2b */
 635         TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
 636         TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
 637         TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
 638         TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
 639         TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
 640         TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
 641         /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
 642         TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
 643         /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
 644         TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
 645         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
 646         RESERVED2, /* 0x34 */
 647         RESERVED3, /* 0x35 */
 648         RESERVED4, /* 0x36 */
 649         RESERVED5, /* 0x37 */
 650         TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
 651         TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
 652         TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
 653         RESERVED6, /* 0x3b */
 654         RESERVED7, /* 0x3c */
 655         RESERVED8, /* 0x3d */
 656         RESERVED9, /* 0x3e */
 657         TRANS_RX_R_ERR, /* 0x3f */
 658
 659         /* dma tx */
 660         DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
 661         DMA_TX_DIF_APP_ERR, /* 0x41 */
 662         DMA_TX_DIF_RPP_ERR, /* 0x42 */
 663         DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
 664         DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
 665         DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
 666         DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
 667         DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
 668         DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
 669         DMA_TX_RAM_ECC_ERR, /* 0x49 */
 670         DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
 671         DMA_TX_MAX_ERR_CODE,
 672
 673         /* sipc rx */
 674         SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
 675         SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
 676         SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
 677         SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
 678         SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
 679         SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
 680         SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
 681         SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
 682         SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
 683         SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
 684         SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
 685         SIPC_RX_MAX_ERR_CODE,
 686
 687         /* dma rx */
 688         DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
 689         DMA_RX_DIF_APP_ERR, /* 0x61 */
 690         DMA_RX_DIF_RPP_ERR, /* 0x62 */
 691         DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
 692         DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
 693         DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
 694         DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
 695         DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
 696         RESERVED10, /* 0x68 */
 697         DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
 698         DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
 699         DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
 700         DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
 701         DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
 702         DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
 703         DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
 704         DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
 705         DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
 706         DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
 707         DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
 708         DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
 709         DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
 710         DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
 711         DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
 712         DMA_RX_RAM_ECC_ERR, /* 0x78 */
 713         DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
 714         DMA_RX_MAX_ERR_CODE,
 715 };
 716
 717 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
 718 #define HISI_MAX_SATA_SUPPORT_V2_HW     (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
 719
 720 #define DIR_NO_DATA 0
 721 #define DIR_TO_INI 1
 722 #define DIR_TO_DEVICE 2
 723 #define DIR_RESERVED 3
 724
 725 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
 726                 err_phase == 0x4 || err_phase == 0x8 ||\
 727                 err_phase == 0x6 || err_phase == 0xa)
 728 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
 729                 err_phase == 0x20 || err_phase == 0x40)
 730
 731 static void link_timeout_disable_link(unsigned long data);
 732
 733 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 734 {
 735         void __iomem *regs = hisi_hba->regs + off;
 736
 737         return readl(regs);
 738 }
 739
 740 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 741 {
 742         void __iomem *regs = hisi_hba->regs + off;
 743
 744         return readl_relaxed(regs);
 745 }
 746
 747 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 748 {
 749         void __iomem *regs = hisi_hba->regs + off;
 750
 751         writel(val, regs);
 752 }
 753
 754 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 755                                  u32 off, u32 val)
 756 {
 757         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 758
 759         writel(val, regs);
 760 }
 761
 762 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 763                                       int phy_no, u32 off)
 764 {
 765         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 766
 767         return readl(regs);
 768 }
 769
 770 /* This function needs to be protected from pre-emption. */
 771 static int
 772 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
 773                              struct domain_device *device)
 774 {
 775         int sata_dev = dev_is_sata(device);
 776         void *bitmap = hisi_hba->slot_index_tags;
 777         struct hisi_sas_device *sas_dev = device->lldd_dev;
 778         int sata_idx = sas_dev->sata_idx;
 779         int start, end;
 780
 781         if (!sata_dev) {
 782                 /*
 783                  * STP link SoC bug workaround: index starts from 1.
 784                  * additionally, we can only allocate odd IPTT(1~4095)
 785                  * for SAS/SMP device.
 786                  */
 787                 start = 1;
 788                 end = hisi_hba->slot_index_count;
 789         } else {
 790                 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
 791                         return -EINVAL;
 792
 793                 /*
 794                  * For SATA device: allocate even IPTT in this interval
 795                  * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
 796                  * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
 797                  * SoC bug workaround. So we ignore the first 32 even IPTTs.
 798                  */
 799                 start = 64 * (sata_idx + 1);
 800                 end = 64 * (sata_idx + 2);
 801         }
 802
 803         while (1) {
 804                 start = find_next_zero_bit(bitmap,
 805                                         hisi_hba->slot_index_count, start);
 806                 if (start >= end)
 807                         return -SAS_QUEUE_FULL;
 808                 /*
 809                   * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
 810                   */
 811                 if (sata_dev ^ (start & 1))
 812                         break;
 813                 start++;
 814         }
 815
 816         set_bit(start, bitmap);
 817         *slot_idx = start;
 818         return 0;
 819 }
 820
 821 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
 822 {
 823         unsigned int index;
 824         struct device *dev = hisi_hba->dev;
 825         void *bitmap = hisi_hba->sata_dev_bitmap;
 826
 827         index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
 828         if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
 829                 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
 830                 return false;
 831         }
 832
 833         set_bit(index, bitmap);
 834         *idx = index;
 835         return true;
 836 }
 837
 838
 839 static struct
 840 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
 841 {
 842         struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
 843         struct hisi_sas_device *sas_dev = NULL;
 844         int i, sata_dev = dev_is_sata(device);
 845         int sata_idx = -1;
 846
 847         spin_lock(&hisi_hba->lock);
 848
 849         if (sata_dev)
 850                 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
 851                         goto out;
 852
 853         for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
 854                 /*
 855                  * SATA device id bit0 should be 0
 856                  */
 857                 if (sata_dev && (i & 1))
 858                         continue;
 859                 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
 860                         int queue = i % hisi_hba->queue_count;
 861                         struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
 862
 863                         hisi_hba->devices[i].device_id = i;
 864                         sas_dev = &hisi_hba->devices[i];
 865                         sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
 866                         sas_dev->dev_type = device->dev_type;
 867                         sas_dev->hisi_hba = hisi_hba;
 868                         sas_dev->sas_device = device;
 869                         sas_dev->sata_idx = sata_idx;
 870                         sas_dev->dq = dq;
 871                         INIT_LIST_HEAD(&hisi_hba->devices[i].list);
 872                         break;
 873                 }
 874         }
 875
 876 out:
 877         spin_unlock(&hisi_hba->lock);
 878
 879         return sas_dev;
 880 }
 881
 882 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 883 {
 884         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 885
 886         cfg &= ~PHY_CFG_DC_OPT_MSK;
 887         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 888         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 889 }
 890
 891 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 892 {
 893         struct sas_identify_frame identify_frame;
 894         u32 *identify_buffer;
 895
 896         memset(&identify_frame, 0, sizeof(identify_frame));
 897         identify_frame.dev_type = SAS_END_DEVICE;
 898         identify_frame.frame_type = 0;
 899         identify_frame._un1 = 1;
 900         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 901         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 902         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 903         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 904         identify_frame.phy_id = phy_no;
 905         identify_buffer = (u32 *)(&identify_frame);
 906
 907         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 908                         __swab32(identify_buffer[0]));
 909         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 910                         __swab32(identify_buffer[1]));
 911         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 912                         __swab32(identify_buffer[2]));
 913         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 914                         __swab32(identify_buffer[3]));
 915         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 916                         __swab32(identify_buffer[4]));
 917         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 918                         __swab32(identify_buffer[5]));
 919 }
 920
 921 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
 922                              struct hisi_sas_device *sas_dev)
 923 {
 924         struct domain_device *device = sas_dev->sas_device;
 925         struct device *dev = hisi_hba->dev;
 926         u64 qw0, device_id = sas_dev->device_id;
 927         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 928         struct domain_device *parent_dev = device->parent;
 929         struct asd_sas_port *sas_port = device->port;
 930         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
 931
 932         memset(itct, 0, sizeof(*itct));
 933
 934         /* qw0 */
 935         qw0 = 0;
 936         switch (sas_dev->dev_type) {
 937         case SAS_END_DEVICE:
 938         case SAS_EDGE_EXPANDER_DEVICE:
 939         case SAS_FANOUT_EXPANDER_DEVICE:
 940                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 941                 break;
 942         case SAS_SATA_DEV:
 943         case SAS_SATA_PENDING:
 944                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
 945                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 946                 else
 947                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 948                 break;
 949         default:
 950                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 951                          sas_dev->dev_type);
 952         }
 953
 954         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 955                 (device->linkrate << ITCT_HDR_MCR_OFF) |
 956                 (1 << ITCT_HDR_VLN_OFF) |
 957                 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
 958                 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
 959                 (port->id << ITCT_HDR_PORT_ID_OFF));
 960         itct->qw0 = cpu_to_le64(qw0);
 961
 962         /* qw1 */
 963         memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 964         itct->sas_addr = __swab64(itct->sas_addr);
 965
 966         /* qw2 */
 967         if (!dev_is_sata(device))
 968                 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
 969                                         (0x1ULL << ITCT_HDR_BITLT_OFF) |
 970                                         (0x32ULL << ITCT_HDR_MCTLT_OFF) |
 971                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
 972 }
 973
 974 static void free_device_v2_hw(struct hisi_hba *hisi_hba,
 975                               struct hisi_sas_device *sas_dev)
 976 {
 977         DECLARE_COMPLETION_ONSTACK(completion);
 978         u64 dev_id = sas_dev->device_id;
 979         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 980         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 981         int i;
 982
 983         sas_dev->completion = &completion;
 984
 985         /* SoC bug workaround */
 986         if (dev_is_sata(sas_dev->sas_device))
 987                 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
 988
 989         /* clear the itct interrupt state */
 990         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 991                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 992                                  ENT_INT_SRC3_ITC_INT_MSK);
 993
 994         for (i = 0; i < 2; i++) {
 995                 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 996                 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 997                 wait_for_completion(sas_dev->completion);
 998
 999                 memset(itct, 0, sizeof(struct hisi_sas_itct));
1000         }
1001 }
1002
1003 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
1004 {
1005         int i, reset_val;
1006         u32 val;
1007         unsigned long end_time;
1008         struct device *dev = hisi_hba->dev;
1009
1010         /* The mask needs to be set depending on the number of phys */
1011         if (hisi_hba->n_phy == 9)
1012                 reset_val = 0x1fffff;
1013         else
1014                 reset_val = 0x7ffff;
1015
1016         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1017
1018         /* Disable all of the PHYs */
1019         for (i = 0; i < hisi_hba->n_phy; i++) {
1020                 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1021
1022                 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1023                 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1024         }
1025         udelay(50);
1026
1027         /* Ensure DMA tx & rx idle */
1028         for (i = 0; i < hisi_hba->n_phy; i++) {
1029                 u32 dma_tx_status, dma_rx_status;
1030
1031                 end_time = jiffies + msecs_to_jiffies(1000);
1032
1033                 while (1) {
1034                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1035                                                             DMA_TX_STATUS);
1036                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1037                                                             DMA_RX_STATUS);
1038
1039                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1040                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1041                                 break;
1042
1043                         msleep(20);
1044                         if (time_after(jiffies, end_time))
1045                                 return -EIO;
1046                 }
1047         }
1048
1049         /* Ensure axi bus idle */
1050         end_time = jiffies + msecs_to_jiffies(1000);
1051         while (1) {
1052                 u32 axi_status =
1053                         hisi_sas_read32(hisi_hba, AXI_CFG);
1054
1055                 if (axi_status == 0)
1056                         break;
1057
1058                 msleep(20);
1059                 if (time_after(jiffies, end_time))
1060                         return -EIO;
1061         }
1062
1063         if (ACPI_HANDLE(dev)) {
1064                 acpi_status s;
1065
1066                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1067                 if (ACPI_FAILURE(s)) {
1068                         dev_err(dev, "Reset failed\n");
1069                         return -EIO;
1070                 }
1071         } else if (hisi_hba->ctrl) {
1072                 /* reset and disable clock*/
1073                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1074                                 reset_val);
1075                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1076                                 reset_val);
1077                 msleep(1);
1078                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1079                 if (reset_val != (val & reset_val)) {
1080                         dev_err(dev, "SAS reset fail.\n");
1081                         return -EIO;
1082                 }
1083
1084                 /* De-reset and enable clock*/
1085                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1086                                 reset_val);
1087                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1088                                 reset_val);
1089                 msleep(1);
1090                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1091                                 &val);
1092                 if (val & reset_val) {
1093                         dev_err(dev, "SAS de-reset fail.\n");
1094                         return -EIO;
1095                 }
1096         } else
1097                 dev_warn(dev, "no reset method\n");
1098
1099         return 0;
1100 }
1101
1102 /* This function needs to be called after resetting SAS controller. */
1103 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1104 {
1105         u32 cfg;
1106         int phy_no;
1107
1108         hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1109         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1110                 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1111                 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1112                         continue;
1113
1114                 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1115                 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1116         }
1117 }
1118
1119 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1120 {
1121         int phy_no;
1122         u32 dma_tx_dfx1;
1123
1124         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1125                 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1126                         continue;
1127
1128                 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1129                                                 DMA_TX_DFX1);
1130                 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1131                         u32 cfg = hisi_sas_phy_read32(hisi_hba,
1132                                 phy_no, CON_CONTROL);
1133
1134                         cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1135                         hisi_sas_phy_write32(hisi_hba, phy_no,
1136                                 CON_CONTROL, cfg);
1137                         clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1138                 }
1139         }
1140 }
1141
1142 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1143 {
1144         struct device *dev = hisi_hba->dev;
1145         int i;
1146
1147         /* Global registers init */
1148
1149         /* Deal with am-max-transmissions quirk */
1150         if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1151                 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1152                 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1153                                  0x2020);
1154         } /* Else, use defaults -> do nothing */
1155
1156         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1157                          (u32)((1ULL << hisi_hba->queue_count) - 1));
1158         hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1159         hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1160         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1161         hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1162         hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1163         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1164         hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1165         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1166         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1167         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1168         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1169         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1170         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1171         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1172         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1173         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1174         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1175         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1176         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1177         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1178         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1179         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1180         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1181         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1182         for (i = 0; i < hisi_hba->queue_count; i++)
1183                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1184
1185         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1186         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1187
1188         for (i = 0; i < hisi_hba->n_phy; i++) {
1189                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
1190                 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
1191                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1192                 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1193                 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1194                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1195                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1196                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1197                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1198                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1199                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1200                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
1201                 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1202                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1203                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1204                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1205                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1206                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1207                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1208                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1209                 if (hisi_hba->refclk_frequency_mhz == 66)
1210                         hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1211                 /* else, do nothing -> leave it how you found it */
1212         }
1213
1214         for (i = 0; i < hisi_hba->queue_count; i++) {
1215                 /* Delivery queue */
1216                 hisi_sas_write32(hisi_hba,
1217                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1218                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1219
1220                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1221                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1222
1223                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1224                                  HISI_SAS_QUEUE_SLOTS);
1225
1226                 /* Completion queue */
1227                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1228                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1229
1230                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1231                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1232
1233                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1234                                  HISI_SAS_QUEUE_SLOTS);
1235         }
1236
1237         /* itct */
1238         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1239                          lower_32_bits(hisi_hba->itct_dma));
1240
1241         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1242                          upper_32_bits(hisi_hba->itct_dma));
1243
1244         /* iost */
1245         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1246                          lower_32_bits(hisi_hba->iost_dma));
1247
1248         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1249                          upper_32_bits(hisi_hba->iost_dma));
1250
1251         /* breakpoint */
1252         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1253                          lower_32_bits(hisi_hba->breakpoint_dma));
1254
1255         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1256                          upper_32_bits(hisi_hba->breakpoint_dma));
1257
1258         /* SATA broken msg */
1259         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1260                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
1261
1262         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1263                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
1264
1265         /* SATA initial fis */
1266         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1267                          lower_32_bits(hisi_hba->initial_fis_dma));
1268
1269         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1270                          upper_32_bits(hisi_hba->initial_fis_dma));
1271 }
1272
1273 static void link_timeout_enable_link(unsigned long data)
1274 {
1275         struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
1276         int i, reg_val;
1277
1278         for (i = 0; i < hisi_hba->n_phy; i++) {
1279                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1280                         continue;
1281
1282                 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1283                 if (!(reg_val & BIT(0))) {
1284                         hisi_sas_phy_write32(hisi_hba, i,
1285                                         CON_CONTROL, 0x7);
1286                         break;
1287                 }
1288         }
1289
1290         hisi_hba->timer.function = link_timeout_disable_link;
1291         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1292 }
1293
1294 static void link_timeout_disable_link(unsigned long data)
1295 {
1296         struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
1297         int i, reg_val;
1298
1299         reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1300         for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1301                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1302                         continue;
1303
1304                 if (reg_val & BIT(i)) {
1305                         hisi_sas_phy_write32(hisi_hba, i,
1306                                         CON_CONTROL, 0x6);
1307                         break;
1308                 }
1309         }
1310
1311         hisi_hba->timer.function = link_timeout_enable_link;
1312         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1313 }
1314
1315 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1316 {
1317         hisi_hba->timer.data = (unsigned long)hisi_hba;
1318         hisi_hba->timer.function = link_timeout_disable_link;
1319         hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1320         add_timer(&hisi_hba->timer);
1321 }
1322
1323 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1324 {
1325         struct device *dev = hisi_hba->dev;
1326         int rc;
1327
1328         rc = reset_hw_v2_hw(hisi_hba);
1329         if (rc) {
1330                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1331                 return rc;
1332         }
1333
1334         msleep(100);
1335         init_reg_v2_hw(hisi_hba);
1336
1337         return 0;
1338 }
1339
1340 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1341 {
1342         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1343
1344         cfg |= PHY_CFG_ENA_MSK;
1345         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1346 }
1347
1348 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1349 {
1350         u32 context;
1351
1352         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1353         if (context & (1 << phy_no))
1354                 return true;
1355
1356         return false;
1357 }
1358
1359 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1360 {
1361         u32 dfx_val;
1362
1363         dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1364
1365         if (dfx_val & BIT(16))
1366                 return false;
1367
1368         return true;
1369 }
1370
1371 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1372 {
1373         int i, max_loop = 1000;
1374         struct device *dev = hisi_hba->dev;
1375         u32 status, axi_status, dfx_val, dfx_tx_val;
1376
1377         for (i = 0; i < max_loop; i++) {
1378                 status = hisi_sas_read32_relaxed(hisi_hba,
1379                         AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1380
1381                 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1382                 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1383                 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1384                         phy_no, DMA_TX_FIFO_DFX0);
1385
1386                 if ((status == 0x3) && (axi_status == 0x0) &&
1387                     (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1388                         return true;
1389                 udelay(10);
1390         }
1391         dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1392                         phy_no, status, axi_status,
1393                         dfx_val, dfx_tx_val);
1394         return false;
1395 }
1396
1397 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1398 {
1399         int i, max_loop = 1000;
1400         struct device *dev = hisi_hba->dev;
1401         u32 status, tx_dfx0;
1402
1403         for (i = 0; i < max_loop; i++) {
1404                 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1405                 status = (status & 0x3fc0) >> 6;
1406
1407                 if (status != 0x1)
1408                         return true;
1409
1410                 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1411                 if ((tx_dfx0 & 0x1ff) == 0x2)
1412                         return true;
1413                 udelay(10);
1414         }
1415         dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1416                         phy_no, status, tx_dfx0);
1417         return false;
1418 }
1419
1420 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1421 {
1422         if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1423                 return true;
1424
1425         if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1426                 return false;
1427
1428         if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1429                 return false;
1430
1431         return true;
1432 }
1433
1434
1435 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1436 {
1437         u32 cfg, axi_val, dfx0_val, txid_auto;
1438         struct device *dev = hisi_hba->dev;
1439
1440         /* Close axi bus. */
1441         axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1442                                 AM_CTRL_GLOBAL);
1443         axi_val |= 0x1;
1444         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1445                 AM_CTRL_GLOBAL, axi_val);
1446
1447         if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1448                 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1449                         goto do_disable;
1450
1451                 /* Reset host controller. */
1452                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1453                 return;
1454         }
1455
1456         dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1457         dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1458         if (dfx0_val != 0x4)
1459                 goto do_disable;
1460
1461         if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1462                 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1463                         phy_no);
1464                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1465                                         TXID_AUTO);
1466                 txid_auto |= TXID_AUTO_CTB_MSK;
1467                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1468                                         txid_auto);
1469         }
1470
1471 do_disable:
1472         cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1473         cfg &= ~PHY_CFG_ENA_MSK;
1474         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1475
1476         /* Open axi bus. */
1477         axi_val &= ~0x1;
1478         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1479                 AM_CTRL_GLOBAL, axi_val);
1480 }
1481
1482 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1483 {
1484         config_id_frame_v2_hw(hisi_hba, phy_no);
1485         config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1486         enable_phy_v2_hw(hisi_hba, phy_no);
1487 }
1488
1489 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1490 {
1491         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1492         u32 txid_auto;
1493
1494         disable_phy_v2_hw(hisi_hba, phy_no);
1495         if (phy->identify.device_type == SAS_END_DEVICE) {
1496                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1497                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1498                                         txid_auto | TX_HARDRST_MSK);
1499         }
1500         msleep(100);
1501         start_phy_v2_hw(hisi_hba, phy_no);
1502 }
1503
1504 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1505 {
1506         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1507         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1508         struct sas_phy *sphy = sas_phy->phy;
1509         u32 err4_reg_val, err6_reg_val;
1510
1511         /* loss dword syn, phy reset problem */
1512         err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1513
1514         /* disparity err, invalid dword */
1515         err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1516
1517         sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1518         sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1519         sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1520         sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1521 }
1522
1523 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1524 {
1525         int i;
1526
1527         for (i = 0; i < hisi_hba->n_phy; i++) {
1528                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1529                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1530
1531                 if (!sas_phy->phy->enabled)
1532                         continue;
1533
1534                 start_phy_v2_hw(hisi_hba, i);
1535         }
1536 }
1537
1538 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1539 {
1540         u32 sl_control;
1541
1542         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1543         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1544         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1545         msleep(1);
1546         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1547         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1548         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1549 }
1550
1551 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1552 {
1553         return SAS_LINK_RATE_12_0_GBPS;
1554 }
1555
1556 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1557                 struct sas_phy_linkrates *r)
1558 {
1559         u32 prog_phy_link_rate =
1560                 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1561         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1562         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1563         int i;
1564         enum sas_linkrate min, max;
1565         u32 rate_mask = 0;
1566
1567         if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1568                 max = sas_phy->phy->maximum_linkrate;
1569                 min = r->minimum_linkrate;
1570         } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1571                 max = r->maximum_linkrate;
1572                 min = sas_phy->phy->minimum_linkrate;
1573         } else
1574                 return;
1575
1576         sas_phy->phy->maximum_linkrate = max;
1577         sas_phy->phy->minimum_linkrate = min;
1578
1579         min -= SAS_LINK_RATE_1_5_GBPS;
1580         max -= SAS_LINK_RATE_1_5_GBPS;
1581
1582         for (i = 0; i <= max; i++)
1583                 rate_mask |= 1 << (i * 2);
1584
1585         prog_phy_link_rate &= ~0xff;
1586         prog_phy_link_rate |= rate_mask;
1587
1588         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1589                         prog_phy_link_rate);
1590
1591         phy_hard_reset_v2_hw(hisi_hba, phy_no);
1592 }
1593
1594 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1595 {
1596         int i, bitmap = 0;
1597         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1598         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1599
1600         for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1601                 if (phy_state & 1 << i)
1602                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1603                                 bitmap |= 1 << i;
1604
1605         if (hisi_hba->n_phy == 9) {
1606                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1607
1608                 if (phy_state & 1 << 8)
1609                         if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1610                              PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1611                                 bitmap |= 1 << 9;
1612         }
1613
1614         return bitmap;
1615 }
1616
1617 /*
1618  * The callpath to this function and upto writing the write
1619  * queue pointer should be safe from interruption.
1620  */
1621 static int
1622 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1623 {
1624         struct device *dev = hisi_hba->dev;
1625         int queue = dq->id;
1626         u32 r, w;
1627
1628         w = dq->wr_point;
1629         r = hisi_sas_read32_relaxed(hisi_hba,
1630                                 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1631         if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1632                 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
1633                                 queue, r, w);
1634                 return -EAGAIN;
1635         }
1636
1637         return 0;
1638 }
1639
1640 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1641 {
1642         struct hisi_hba *hisi_hba = dq->hisi_hba;
1643         int dlvry_queue = dq->slot_prep->dlvry_queue;
1644         int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
1645
1646         dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1647         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1648                          dq->wr_point);
1649 }
1650
1651 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1652                               struct hisi_sas_slot *slot,
1653                               struct hisi_sas_cmd_hdr *hdr,
1654                               struct scatterlist *scatter,
1655                               int n_elem)
1656 {
1657         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1658         struct device *dev = hisi_hba->dev;
1659         struct scatterlist *sg;
1660         int i;
1661
1662         if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1663                 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1664                         n_elem);
1665                 return -EINVAL;
1666         }
1667
1668         for_each_sg(scatter, sg, n_elem, i) {
1669                 struct hisi_sas_sge *entry = &sge_page->sge[i];
1670
1671                 entry->addr = cpu_to_le64(sg_dma_address(sg));
1672                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1673                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1674                 entry->data_off = 0;
1675         }
1676
1677         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1678
1679         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1680
1681         return 0;
1682 }
1683
1684 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1685                           struct hisi_sas_slot *slot)
1686 {
1687         struct sas_task *task = slot->task;
1688         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1689         struct domain_device *device = task->dev;
1690         struct device *dev = hisi_hba->dev;
1691         struct hisi_sas_port *port = slot->port;
1692         struct scatterlist *sg_req, *sg_resp;
1693         struct hisi_sas_device *sas_dev = device->lldd_dev;
1694         dma_addr_t req_dma_addr;
1695         unsigned int req_len, resp_len;
1696         int elem, rc;
1697
1698         /*
1699         * DMA-map SMP request, response buffers
1700         */
1701         /* req */
1702         sg_req = &task->smp_task.smp_req;
1703         elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1704         if (!elem)
1705                 return -ENOMEM;
1706         req_len = sg_dma_len(sg_req);
1707         req_dma_addr = sg_dma_address(sg_req);
1708
1709         /* resp */
1710         sg_resp = &task->smp_task.smp_resp;
1711         elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1712         if (!elem) {
1713                 rc = -ENOMEM;
1714                 goto err_out_req;
1715         }
1716         resp_len = sg_dma_len(sg_resp);
1717         if ((req_len & 0x3) || (resp_len & 0x3)) {
1718                 rc = -EINVAL;
1719                 goto err_out_resp;
1720         }
1721
1722         /* create header */
1723         /* dw0 */
1724         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1725                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1726                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1727
1728         /* map itct entry */
1729         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1730                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1731                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1732
1733         /* dw2 */
1734         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1735                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1736                                CMD_HDR_MRFL_OFF));
1737
1738         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1739
1740         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1741         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1742
1743         return 0;
1744
1745 err_out_resp:
1746         dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1747                      DMA_FROM_DEVICE);
1748 err_out_req:
1749         dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1750                      DMA_TO_DEVICE);
1751         return rc;
1752 }
1753
1754 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1755                           struct hisi_sas_slot *slot, int is_tmf,
1756                           struct hisi_sas_tmf_task *tmf)
1757 {
1758         struct sas_task *task = slot->task;
1759         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1760         struct domain_device *device = task->dev;
1761         struct hisi_sas_device *sas_dev = device->lldd_dev;
1762         struct hisi_sas_port *port = slot->port;
1763         struct sas_ssp_task *ssp_task = &task->ssp_task;
1764         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1765         int has_data = 0, rc, priority = is_tmf;
1766         u8 *buf_cmd;
1767         u32 dw1 = 0, dw2 = 0;
1768
1769         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1770                                (2 << CMD_HDR_TLR_CTRL_OFF) |
1771                                (port->id << CMD_HDR_PORT_OFF) |
1772                                (priority << CMD_HDR_PRIORITY_OFF) |
1773                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1774
1775         dw1 = 1 << CMD_HDR_VDTL_OFF;
1776         if (is_tmf) {
1777                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1778                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1779         } else {
1780                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1781                 switch (scsi_cmnd->sc_data_direction) {
1782                 case DMA_TO_DEVICE:
1783                         has_data = 1;
1784                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1785                         break;
1786                 case DMA_FROM_DEVICE:
1787                         has_data = 1;
1788                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1789                         break;
1790                 default:
1791                         dw1 &= ~CMD_HDR_DIR_MSK;
1792                 }
1793         }
1794
1795         /* map itct entry */
1796         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1797         hdr->dw1 = cpu_to_le32(dw1);
1798
1799         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1800               + 3) / 4) << CMD_HDR_CFL_OFF) |
1801               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1802               (2 << CMD_HDR_SG_MOD_OFF);
1803         hdr->dw2 = cpu_to_le32(dw2);
1804
1805         hdr->transfer_tags = cpu_to_le32(slot->idx);
1806
1807         if (has_data) {
1808                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1809                                         slot->n_elem);
1810                 if (rc)
1811                         return rc;
1812         }
1813
1814         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1815         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1816         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1817
1818         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1819                 sizeof(struct ssp_frame_hdr);
1820
1821         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1822         if (!is_tmf) {
1823                 buf_cmd[9] = task->ssp_task.task_attr |
1824                                 (task->ssp_task.task_prio << 3);
1825                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1826                                 task->ssp_task.cmd->cmd_len);
1827         } else {
1828                 buf_cmd[10] = tmf->tmf;
1829                 switch (tmf->tmf) {
1830                 case TMF_ABORT_TASK:
1831                 case TMF_QUERY_TASK:
1832                         buf_cmd[12] =
1833                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1834                         buf_cmd[13] =
1835                                 tmf->tag_of_task_to_be_managed & 0xff;
1836                         break;
1837                 default:
1838                         break;
1839                 }
1840         }
1841
1842         return 0;
1843 }
1844
1845 #define TRANS_TX_ERR    0
1846 #define TRANS_RX_ERR    1
1847 #define DMA_TX_ERR              2
1848 #define SIPC_RX_ERR             3
1849 #define DMA_RX_ERR              4
1850
1851 #define DMA_TX_ERR_OFF  0
1852 #define DMA_TX_ERR_MSK  (0xffff << DMA_TX_ERR_OFF)
1853 #define SIPC_RX_ERR_OFF 16
1854 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1855
1856 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1857 {
1858         static const u8 trans_tx_err_code_prio[] = {
1859                 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1860                 TRANS_TX_ERR_PHY_NOT_ENABLE,
1861                 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1862                 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1863                 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1864                 RESERVED0,
1865                 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1866                 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1867                 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1868                 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1869                 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1870                 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1871                 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1872                 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1873                 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1874                 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1875                 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1876                 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1877                 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1878                 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1879                 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1880                 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1881                 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1882                 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1883                 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1884                 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1885                 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1886                 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1887                 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1888                 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1889                 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1890         };
1891         int index, i;
1892
1893         for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1894                 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1895                 if (err_msk & (1 << index))
1896                         return trans_tx_err_code_prio[i];
1897         }
1898         return -1;
1899 }
1900
1901 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1902 {
1903         static const u8 trans_rx_err_code_prio[] = {
1904                 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1905                 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1906                 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1907                 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1908                 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1909                 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1910                 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1911                 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1912                 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1913                 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1914                 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1915                 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1916                 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1917                 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1918                 RESERVED1,
1919                 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1920                 TRANS_RX_ERR_WITH_DATA_LEN0,
1921                 TRANS_RX_ERR_WITH_BAD_HASH,
1922                 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1923                 TRANS_RX_SSP_FRM_LEN_ERR,
1924                 RESERVED2,
1925                 RESERVED3,
1926                 RESERVED4,
1927                 RESERVED5,
1928                 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1929                 TRANS_RX_SMP_FRM_LEN_ERR,
1930                 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1931                 RESERVED6,
1932                 RESERVED7,
1933                 RESERVED8,
1934                 RESERVED9,
1935                 TRANS_RX_R_ERR,
1936         };
1937         int index, i;
1938
1939         for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1940                 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1941                 if (err_msk & (1 << index))
1942                         return trans_rx_err_code_prio[i];
1943         }
1944         return -1;
1945 }
1946
1947 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1948 {
1949         static const u8 dma_tx_err_code_prio[] = {
1950                 DMA_TX_UNEXP_XFER_ERR,
1951                 DMA_TX_UNEXP_RETRANS_ERR,
1952                 DMA_TX_XFER_LEN_OVERFLOW,
1953                 DMA_TX_XFER_OFFSET_ERR,
1954                 DMA_TX_RAM_ECC_ERR,
1955                 DMA_TX_DIF_LEN_ALIGN_ERR,
1956                 DMA_TX_DIF_CRC_ERR,
1957                 DMA_TX_DIF_APP_ERR,
1958                 DMA_TX_DIF_RPP_ERR,
1959                 DMA_TX_DATA_SGL_OVERFLOW,
1960                 DMA_TX_DIF_SGL_OVERFLOW,
1961         };
1962         int index, i;
1963
1964         for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1965                 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1966                 err_msk = err_msk & DMA_TX_ERR_MSK;
1967                 if (err_msk & (1 << index))
1968                         return dma_tx_err_code_prio[i];
1969         }
1970         return -1;
1971 }
1972
1973 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1974 {
1975         static const u8 sipc_rx_err_code_prio[] = {
1976                 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1977                 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1978                 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1979                 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1980                 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1981                 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1982                 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1983                 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1984                 SIPC_RX_SATA_UNEXP_FIS_ERR,
1985                 SIPC_RX_WRSETUP_ESTATUS_ERR,
1986                 SIPC_RX_DATA_UNDERFLOW_ERR,
1987         };
1988         int index, i;
1989
1990         for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1991                 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1992                 err_msk = err_msk & SIPC_RX_ERR_MSK;
1993                 if (err_msk & (1 << (index + 0x10)))
1994                         return sipc_rx_err_code_prio[i];
1995         }
1996         return -1;
1997 }
1998
1999 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
2000 {
2001         static const u8 dma_rx_err_code_prio[] = {
2002                 DMA_RX_UNKNOWN_FRM_ERR,
2003                 DMA_RX_DATA_LEN_OVERFLOW,
2004                 DMA_RX_DATA_LEN_UNDERFLOW,
2005                 DMA_RX_DATA_OFFSET_ERR,
2006                 RESERVED10,
2007                 DMA_RX_SATA_FRAME_TYPE_ERR,
2008                 DMA_RX_RESP_BUF_OVERFLOW,
2009                 DMA_RX_UNEXP_RETRANS_RESP_ERR,
2010                 DMA_RX_UNEXP_NORM_RESP_ERR,
2011                 DMA_RX_UNEXP_RDFRAME_ERR,
2012                 DMA_RX_PIO_DATA_LEN_ERR,
2013                 DMA_RX_RDSETUP_STATUS_ERR,
2014                 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2015                 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2016                 DMA_RX_RDSETUP_LEN_ODD_ERR,
2017                 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2018                 DMA_RX_RDSETUP_LEN_OVER_ERR,
2019                 DMA_RX_RDSETUP_OFFSET_ERR,
2020                 DMA_RX_RDSETUP_ACTIVE_ERR,
2021                 DMA_RX_RDSETUP_ESTATUS_ERR,
2022                 DMA_RX_RAM_ECC_ERR,
2023                 DMA_RX_DIF_CRC_ERR,
2024                 DMA_RX_DIF_APP_ERR,
2025                 DMA_RX_DIF_RPP_ERR,
2026                 DMA_RX_DATA_SGL_OVERFLOW,
2027                 DMA_RX_DIF_SGL_OVERFLOW,
2028         };
2029         int index, i;
2030
2031         for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2032                 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2033                 if (err_msk & (1 << index))
2034                         return dma_rx_err_code_prio[i];
2035         }
2036         return -1;
2037 }
2038
2039 /* by default, task resp is complete */
2040 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2041                            struct sas_task *task,
2042                            struct hisi_sas_slot *slot,
2043                            int err_phase)
2044 {
2045         struct task_status_struct *ts = &task->task_status;
2046         struct hisi_sas_err_record_v2 *err_record =
2047                         hisi_sas_status_buf_addr_mem(slot);
2048         u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2049         u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2050         u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2051         u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2052         u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2053         int error = -1;
2054
2055         if (err_phase == 1) {
2056                 /* error in TX phase, the priority of error is: DW2 > DW0 */
2057                 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2058                 if (error == -1)
2059                         error = parse_trans_tx_err_code_v2_hw(
2060                                         trans_tx_fail_type);
2061         } else if (err_phase == 2) {
2062                 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2063                 error = parse_trans_rx_err_code_v2_hw(
2064                                         trans_rx_fail_type);
2065                 if (error == -1) {
2066                         error = parse_dma_rx_err_code_v2_hw(
2067                                         dma_rx_err_type);
2068                         if (error == -1)
2069                                 error = parse_sipc_rx_err_code_v2_hw(
2070                                                 sipc_rx_err_type);
2071                 }
2072         }
2073
2074         switch (task->task_proto) {
2075         case SAS_PROTOCOL_SSP:
2076         {
2077                 switch (error) {
2078                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2079                 {
2080                         ts->stat = SAS_OPEN_REJECT;
2081                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2082                         break;
2083                 }
2084                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2085                 {
2086                         ts->stat = SAS_OPEN_REJECT;
2087                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2088                         break;
2089                 }
2090                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2091                 {
2092                         ts->stat = SAS_OPEN_REJECT;
2093                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2094                         break;
2095                 }
2096                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2097                 {
2098                         ts->stat = SAS_OPEN_REJECT;
2099                         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2100                         break;
2101                 }
2102                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2103                 {
2104                         ts->stat = SAS_OPEN_REJECT;
2105                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2106                         break;
2107                 }
2108                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2109                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2110                 case DMA_RX_RESP_BUF_OVERFLOW:
2111                 {
2112                         ts->stat = SAS_OPEN_REJECT;
2113                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2114                         break;
2115                 }
2116                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2117                 {
2118                         /* not sure */
2119                         ts->stat = SAS_DEV_NO_RESPONSE;
2120                         break;
2121                 }
2122                 case DMA_RX_DATA_LEN_OVERFLOW:
2123                 {
2124                         ts->stat = SAS_DATA_OVERRUN;
2125                         ts->residual = 0;
2126                         break;
2127                 }
2128                 case DMA_RX_DATA_LEN_UNDERFLOW:
2129                 {
2130                         ts->residual = trans_tx_fail_type;
2131                         ts->stat = SAS_DATA_UNDERRUN;
2132                         break;
2133                 }
2134                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2135                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2136                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2137                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2138                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2139                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2140                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2141                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2142                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2143                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2144                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2145                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2146                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2147                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2148                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2149                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2150                 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2151                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2152                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2153                 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2154                 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2155                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2156                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2157                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2158                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2159                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2160                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2161                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2162                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2163                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2164                 case TRANS_TX_ERR_FRAME_TXED:
2165                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2166                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2167                 case TRANS_RX_ERR_WITH_BAD_HASH:
2168                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2169                 case TRANS_RX_SSP_FRM_LEN_ERR:
2170                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2171                 case DMA_TX_DATA_SGL_OVERFLOW:
2172                 case DMA_TX_UNEXP_XFER_ERR:
2173                 case DMA_TX_UNEXP_RETRANS_ERR:
2174                 case DMA_TX_XFER_LEN_OVERFLOW:
2175                 case DMA_TX_XFER_OFFSET_ERR:
2176                 case SIPC_RX_DATA_UNDERFLOW_ERR:
2177                 case DMA_RX_DATA_SGL_OVERFLOW:
2178                 case DMA_RX_DATA_OFFSET_ERR:
2179                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2180                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2181                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2182                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2183                 case DMA_RX_UNKNOWN_FRM_ERR:
2184                 {
2185                         /* This will request a retry */
2186                         ts->stat = SAS_QUEUE_FULL;
2187                         slot->abort = 1;
2188                         break;
2189                 }
2190                 default:
2191                         break;
2192                 }
2193         }
2194                 break;
2195         case SAS_PROTOCOL_SMP:
2196                 ts->stat = SAM_STAT_CHECK_CONDITION;
2197                 break;
2198
2199         case SAS_PROTOCOL_SATA:
2200         case SAS_PROTOCOL_STP:
2201         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2202         {
2203                 switch (error) {
2204                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2205                 {
2206                         ts->stat = SAS_OPEN_REJECT;
2207                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2208                         break;
2209                 }
2210                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2211                 {
2212                         ts->resp = SAS_TASK_UNDELIVERED;
2213                         ts->stat = SAS_DEV_NO_RESPONSE;
2214                         break;
2215                 }
2216                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2217                 {
2218                         ts->stat = SAS_OPEN_REJECT;
2219                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2220                         break;
2221                 }
2222                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2223                 {
2224                         ts->stat = SAS_OPEN_REJECT;
2225                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2226                         break;
2227                 }
2228                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2229                 {
2230                         ts->stat = SAS_OPEN_REJECT;
2231                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2232                         break;
2233                 }
2234                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2235                 {
2236                         ts->stat = SAS_OPEN_REJECT;
2237                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2238                         break;
2239                 }
2240                 case DMA_RX_RESP_BUF_OVERFLOW:
2241                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2242                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2243                 {
2244                         ts->stat = SAS_OPEN_REJECT;
2245                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2246                         break;
2247                 }
2248                 case DMA_RX_DATA_LEN_OVERFLOW:
2249                 {
2250                         ts->stat = SAS_DATA_OVERRUN;
2251                         ts->residual = 0;
2252                         break;
2253                 }
2254                 case DMA_RX_DATA_LEN_UNDERFLOW:
2255                 {
2256                         ts->residual = trans_tx_fail_type;
2257                         ts->stat = SAS_DATA_UNDERRUN;
2258                         break;
2259                 }
2260                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2261                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2262                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2263                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2264                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2265                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2266                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2267                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2268                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2269                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2270                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2271                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2272                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2273                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2274                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2275                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2276                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2277                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2278                 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2279                 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2280                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2281                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2282                 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2283                 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2284                 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2285                 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2286                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2287                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2288                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2289                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2290                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2291                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2292                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2293                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2294                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2295                 case TRANS_RX_ERR_WITH_BAD_HASH:
2296                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2297                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2298                 case DMA_TX_DATA_SGL_OVERFLOW:
2299                 case DMA_TX_UNEXP_XFER_ERR:
2300                 case DMA_TX_UNEXP_RETRANS_ERR:
2301                 case DMA_TX_XFER_LEN_OVERFLOW:
2302                 case DMA_TX_XFER_OFFSET_ERR:
2303                 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2304                 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2305                 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2306                 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2307                 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2308                 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2309                 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2310                 case DMA_RX_DATA_SGL_OVERFLOW:
2311                 case DMA_RX_DATA_OFFSET_ERR:
2312                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2313                 case DMA_RX_UNEXP_RDFRAME_ERR:
2314                 case DMA_RX_PIO_DATA_LEN_ERR:
2315                 case DMA_RX_RDSETUP_STATUS_ERR:
2316                 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2317                 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2318                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2319                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2320                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2321                 case DMA_RX_RDSETUP_OFFSET_ERR:
2322                 case DMA_RX_RDSETUP_ACTIVE_ERR:
2323                 case DMA_RX_RDSETUP_ESTATUS_ERR:
2324                 case DMA_RX_UNKNOWN_FRM_ERR:
2325                 case TRANS_RX_SSP_FRM_LEN_ERR:
2326                 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2327                 {
2328                         slot->abort = 1;
2329                         ts->stat = SAS_PHY_DOWN;
2330                         break;
2331                 }
2332                 default:
2333                 {
2334                         ts->stat = SAS_PROTO_RESPONSE;
2335                         break;
2336                 }
2337                 }
2338                 hisi_sas_sata_done(task, slot);
2339         }
2340                 break;
2341         default:
2342                 break;
2343         }
2344 }
2345
2346 static int
2347 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2348 {
2349         struct sas_task *task = slot->task;
2350         struct hisi_sas_device *sas_dev;
2351         struct device *dev = hisi_hba->dev;
2352         struct task_status_struct *ts;
2353         struct domain_device *device;
2354         enum exec_status sts;
2355         struct hisi_sas_complete_v2_hdr *complete_queue =
2356                         hisi_hba->complete_hdr[slot->cmplt_queue];
2357         struct hisi_sas_complete_v2_hdr *complete_hdr =
2358                         &complete_queue[slot->cmplt_queue_slot];
2359         unsigned long flags;
2360         int aborted;
2361
2362         if (unlikely(!task || !task->lldd_task || !task->dev))
2363                 return -EINVAL;
2364
2365         ts = &task->task_status;
2366         device = task->dev;
2367         sas_dev = device->lldd_dev;
2368
2369         spin_lock_irqsave(&task->task_state_lock, flags);
2370         aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
2371         task->task_state_flags &=
2372                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2373         spin_unlock_irqrestore(&task->task_state_lock, flags);
2374
2375         memset(ts, 0, sizeof(*ts));
2376         ts->resp = SAS_TASK_COMPLETE;
2377
2378         if (unlikely(aborted)) {
2379                 ts->stat = SAS_ABORTED_TASK;
2380                 hisi_sas_slot_task_free(hisi_hba, task, slot);
2381                 return -1;
2382         }
2383
2384         if (unlikely(!sas_dev)) {
2385                 dev_dbg(dev, "slot complete: port has no device\n");
2386                 ts->stat = SAS_PHY_DOWN;
2387                 goto out;
2388         }
2389
2390         /* Use SAS+TMF status codes */
2391         switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2392                         >> CMPLT_HDR_ABORT_STAT_OFF) {
2393         case STAT_IO_ABORTED:
2394                 /* this io has been aborted by abort command */
2395                 ts->stat = SAS_ABORTED_TASK;
2396                 goto out;
2397         case STAT_IO_COMPLETE:
2398                 /* internal abort command complete */
2399                 ts->stat = TMF_RESP_FUNC_SUCC;
2400                 del_timer(&slot->internal_abort_timer);
2401                 goto out;
2402         case STAT_IO_NO_DEVICE:
2403                 ts->stat = TMF_RESP_FUNC_COMPLETE;
2404                 del_timer(&slot->internal_abort_timer);
2405                 goto out;
2406         case STAT_IO_NOT_VALID:
2407                 /* abort single io, controller don't find
2408                  * the io need to abort
2409                  */
2410                 ts->stat = TMF_RESP_FUNC_FAILED;
2411                 del_timer(&slot->internal_abort_timer);
2412                 goto out;
2413         default:
2414                 break;
2415         }
2416
2417         if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2418                 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2419                 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2420                                 >> CMPLT_HDR_ERR_PHASE_OFF;
2421
2422                 /* Analyse error happens on which phase TX or RX */
2423                 if (ERR_ON_TX_PHASE(err_phase))
2424                         slot_err_v2_hw(hisi_hba, task, slot, 1);
2425                 else if (ERR_ON_RX_PHASE(err_phase))
2426                         slot_err_v2_hw(hisi_hba, task, slot, 2);
2427
2428                 if (unlikely(slot->abort))
2429                         return ts->stat;
2430                 goto out;
2431         }
2432
2433         switch (task->task_proto) {
2434         case SAS_PROTOCOL_SSP:
2435         {
2436                 struct hisi_sas_status_buffer *status_buffer =
2437                                 hisi_sas_status_buf_addr_mem(slot);
2438                 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2439                                 &status_buffer->iu[0];
2440
2441                 sas_ssp_task_response(dev, task, iu);
2442                 break;
2443         }
2444         case SAS_PROTOCOL_SMP:
2445         {
2446                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2447                 void *to;
2448
2449                 ts->stat = SAM_STAT_GOOD;
2450                 to = kmap_atomic(sg_page(sg_resp));
2451
2452                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2453                              DMA_FROM_DEVICE);
2454                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2455                              DMA_TO_DEVICE);
2456                 memcpy(to + sg_resp->offset,
2457                        hisi_sas_status_buf_addr_mem(slot) +
2458                        sizeof(struct hisi_sas_err_record),
2459                        sg_dma_len(sg_resp));
2460                 kunmap_atomic(to);
2461                 break;
2462         }
2463         case SAS_PROTOCOL_SATA:
2464         case SAS_PROTOCOL_STP:
2465         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2466         {
2467                 ts->stat = SAM_STAT_GOOD;
2468                 hisi_sas_sata_done(task, slot);
2469                 break;
2470         }
2471         default:
2472                 ts->stat = SAM_STAT_CHECK_CONDITION;
2473                 break;
2474         }
2475
2476         if (!slot->port->port_attached) {
2477                 dev_err(dev, "slot complete: port %d has removed\n",
2478                         slot->port->sas_port.id);
2479                 ts->stat = SAS_PHY_DOWN;
2480         }
2481
2482 out:
2483         spin_lock_irqsave(&task->task_state_lock, flags);
2484         task->task_state_flags |= SAS_TASK_STATE_DONE;
2485         spin_unlock_irqrestore(&task->task_state_lock, flags);
2486         spin_lock_irqsave(&hisi_hba->lock, flags);
2487         hisi_sas_slot_task_free(hisi_hba, task, slot);
2488         spin_unlock_irqrestore(&hisi_hba->lock, flags);
2489         sts = ts->stat;
2490
2491         if (task->task_done)
2492                 task->task_done(task);
2493
2494         return sts;
2495 }
2496
2497 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2498                           struct hisi_sas_slot *slot)
2499 {
2500         struct sas_task *task = slot->task;
2501         struct domain_device *device = task->dev;
2502         struct domain_device *parent_dev = device->parent;
2503         struct hisi_sas_device *sas_dev = device->lldd_dev;
2504         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2505         struct asd_sas_port *sas_port = device->port;
2506         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2507         u8 *buf_cmd;
2508         int has_data = 0, rc = 0, hdr_tag = 0;
2509         u32 dw1 = 0, dw2 = 0;
2510
2511         /* create header */
2512         /* dw0 */
2513         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2514         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2515                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2516         else
2517                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2518
2519         /* dw1 */
2520         switch (task->data_dir) {
2521         case DMA_TO_DEVICE:
2522                 has_data = 1;
2523                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2524                 break;
2525         case DMA_FROM_DEVICE:
2526                 has_data = 1;
2527                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2528                 break;
2529         default:
2530                 dw1 &= ~CMD_HDR_DIR_MSK;
2531         }
2532
2533         if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2534                         (task->ata_task.fis.control & ATA_SRST))
2535                 dw1 |= 1 << CMD_HDR_RESET_OFF;
2536
2537         dw1 |= (hisi_sas_get_ata_protocol(
2538                 task->ata_task.fis.command, task->data_dir))
2539                 << CMD_HDR_FRAME_TYPE_OFF;
2540         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2541         hdr->dw1 = cpu_to_le32(dw1);
2542
2543         /* dw2 */
2544         if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2545                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2546                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2547         }
2548
2549         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2550                         2 << CMD_HDR_SG_MOD_OFF;
2551         hdr->dw2 = cpu_to_le32(dw2);
2552
2553         /* dw3 */
2554         hdr->transfer_tags = cpu_to_le32(slot->idx);
2555
2556         if (has_data) {
2557                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2558                                         slot->n_elem);
2559                 if (rc)
2560                         return rc;
2561         }
2562
2563         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2564         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2565         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2566
2567         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2568
2569         if (likely(!task->ata_task.device_control_reg_update))
2570                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2571         /* fill in command FIS */
2572         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2573
2574         return 0;
2575 }
2576
2577 static void hisi_sas_internal_abort_quirk_timeout(unsigned long data)
2578 {
2579         struct hisi_sas_slot *slot = (struct hisi_sas_slot *)data;
2580         struct hisi_sas_port *port = slot->port;
2581         struct asd_sas_port *asd_sas_port;
2582         struct asd_sas_phy *sas_phy;
2583
2584         if (!port)
2585                 return;
2586
2587         asd_sas_port = &port->sas_port;
2588
2589         /* Kick the hardware - send break command */
2590         list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2591                 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2592                 struct hisi_hba *hisi_hba = phy->hisi_hba;
2593                 int phy_no = sas_phy->id;
2594                 u32 link_dfx2;
2595
2596                 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2597                 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2598                     (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2599                         u32 txid_auto;
2600
2601                         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2602                                                         TXID_AUTO);
2603                         txid_auto |= TXID_AUTO_CTB_MSK;
2604                         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2605                                              txid_auto);
2606                         return;
2607                 }
2608         }
2609 }
2610
2611 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2612                 struct hisi_sas_slot *slot,
2613                 int device_id, int abort_flag, int tag_to_abort)
2614 {
2615         struct sas_task *task = slot->task;
2616         struct domain_device *dev = task->dev;
2617         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2618         struct hisi_sas_port *port = slot->port;
2619         struct timer_list *timer = &slot->internal_abort_timer;
2620
2621         /* setup the quirk timer */
2622         setup_timer(timer, hisi_sas_internal_abort_quirk_timeout,
2623                     (unsigned long)slot);
2624         /* Set the timeout to 10ms less than internal abort timeout */
2625         mod_timer(timer, jiffies + msecs_to_jiffies(100));
2626
2627         /* dw0 */
2628         hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2629                                (port->id << CMD_HDR_PORT_OFF) |
2630                                ((dev_is_sata(dev) ? 1:0) <<
2631                                 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2632                                (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2633
2634         /* dw1 */
2635         hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2636
2637         /* dw7 */
2638         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2639         hdr->transfer_tags = cpu_to_le32(slot->idx);
2640
2641         return 0;
2642 }
2643
2644 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2645 {
2646         int i, res = IRQ_HANDLED;
2647         u32 port_id, link_rate, hard_phy_linkrate;
2648         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2649         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2650         struct device *dev = hisi_hba->dev;
2651         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2652         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2653
2654         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2655
2656         if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2657                 goto end;
2658
2659         if (phy_no == 8) {
2660                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2661
2662                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2663                           PORT_STATE_PHY8_PORT_NUM_OFF;
2664                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2665                             PORT_STATE_PHY8_CONN_RATE_OFF;
2666         } else {
2667                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2668                 port_id = (port_id >> (4 * phy_no)) & 0xf;
2669                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2670                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2671         }
2672
2673         if (port_id == 0xf) {
2674                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2675                 res = IRQ_NONE;
2676                 goto end;
2677         }
2678
2679         for (i = 0; i < 6; i++) {
2680                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2681                                                RX_IDAF_DWORD0 + (i * 4));
2682                 frame_rcvd[i] = __swab32(idaf);
2683         }
2684
2685         sas_phy->linkrate = link_rate;
2686         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2687                                                 HARD_PHY_LINKRATE);
2688         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2689         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2690
2691         sas_phy->oob_mode = SAS_OOB_MODE;
2692         memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2693         dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2694         phy->port_id = port_id;
2695         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2696         phy->phy_type |= PORT_TYPE_SAS;
2697         phy->phy_attached = 1;
2698         phy->identify.device_type = id->dev_type;
2699         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
2700         if (phy->identify.device_type == SAS_END_DEVICE)
2701                 phy->identify.target_port_protocols =
2702                         SAS_PROTOCOL_SSP;
2703         else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2704                 phy->identify.target_port_protocols =
2705                         SAS_PROTOCOL_SMP;
2706                 if (!timer_pending(&hisi_hba->timer))
2707                         set_link_timer_quirk(hisi_hba);
2708         }
2709         queue_work(hisi_hba->wq, &phy->phyup_ws);
2710
2711 end:
2712         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2713                              CHL_INT0_SL_PHY_ENABLE_MSK);
2714         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2715
2716         return res;
2717 }
2718
2719 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2720 {
2721         u32 port_state;
2722
2723         port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2724         if (port_state & 0x1ff)
2725                 return true;
2726
2727         return false;
2728 }
2729
2730 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2731 {
2732         u32 phy_state, sl_ctrl, txid_auto;
2733         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2734         struct hisi_sas_port *port = phy->port;
2735
2736         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2737
2738         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2739         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2740
2741         sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2742         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2743                              sl_ctrl & ~SL_CONTROL_CTA_MSK);
2744         if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2745                 if (!check_any_wideports_v2_hw(hisi_hba) &&
2746                                 timer_pending(&hisi_hba->timer))
2747                         del_timer(&hisi_hba->timer);
2748
2749         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2750         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2751                              txid_auto | TXID_AUTO_CT3_MSK);
2752
2753         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2754         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2755
2756         return IRQ_HANDLED;
2757 }
2758
2759 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2760 {
2761         struct hisi_hba *hisi_hba = p;
2762         u32 irq_msk;
2763         int phy_no = 0;
2764         irqreturn_t res = IRQ_NONE;
2765
2766         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2767                    >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2768         while (irq_msk) {
2769                 if (irq_msk  & 1) {
2770                         u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2771                                             CHL_INT0);
2772
2773                         switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2774                                         CHL_INT0_SL_PHY_ENABLE_MSK)) {
2775
2776                         case CHL_INT0_SL_PHY_ENABLE_MSK:
2777                                 /* phy up */
2778                                 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2779                                     IRQ_HANDLED)
2780                                         res = IRQ_HANDLED;
2781                                 break;
2782
2783                         case CHL_INT0_NOT_RDY_MSK:
2784                                 /* phy down */
2785                                 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2786                                     IRQ_HANDLED)
2787                                         res = IRQ_HANDLED;
2788                                 break;
2789
2790                         case (CHL_INT0_NOT_RDY_MSK |
2791                                         CHL_INT0_SL_PHY_ENABLE_MSK):
2792                                 reg_value = hisi_sas_read32(hisi_hba,
2793                                                 PHY_STATE);
2794                                 if (reg_value & BIT(phy_no)) {
2795                                         /* phy up */
2796                                         if (phy_up_v2_hw(phy_no, hisi_hba) ==
2797                                             IRQ_HANDLED)
2798                                                 res = IRQ_HANDLED;
2799                                 } else {
2800                                         /* phy down */
2801                                         if (phy_down_v2_hw(phy_no, hisi_hba) ==
2802                                             IRQ_HANDLED)
2803                                                 res = IRQ_HANDLED;
2804                                 }
2805                                 break;
2806
2807                         default:
2808                                 break;
2809                         }
2810
2811                 }
2812                 irq_msk >>= 1;
2813                 phy_no++;
2814         }
2815
2816         return res;
2817 }
2818
2819 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2820 {
2821         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2822         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2823         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2824         u32 bcast_status;
2825
2826         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2827         bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2828         if (bcast_status & RX_BCAST_CHG_MSK)
2829                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2830         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2831                              CHL_INT0_SL_RX_BCST_ACK_MSK);
2832         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2833 }
2834
2835 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2836 {
2837         struct hisi_hba *hisi_hba = p;
2838         struct device *dev = hisi_hba->dev;
2839         u32 ent_msk, ent_tmp, irq_msk;
2840         int phy_no = 0;
2841
2842         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2843         ent_tmp = ent_msk;
2844         ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2845         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2846
2847         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2848                         HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2849
2850         while (irq_msk) {
2851                 if (irq_msk & (1 << phy_no)) {
2852                         u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2853                                                              CHL_INT0);
2854                         u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2855                                                              CHL_INT1);
2856                         u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2857                                                              CHL_INT2);
2858
2859                         if (irq_value1) {
2860                                 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
2861                                                   CHL_INT1_DMAC_TX_ECC_ERR_MSK))
2862                                         panic("%s: DMAC RX/TX ecc bad error!\
2863                                                (0x%x)",
2864                                               dev_name(dev), irq_value1);
2865
2866                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2867                                                      CHL_INT1, irq_value1);
2868                         }
2869
2870                         if (irq_value2)
2871                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2872                                                      CHL_INT2, irq_value2);
2873
2874
2875                         if (irq_value0) {
2876                                 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2877                                         phy_bcast_v2_hw(phy_no, hisi_hba);
2878
2879                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2880                                                 CHL_INT0, irq_value0
2881                                                 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2882                                                 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2883                                                 & (~CHL_INT0_NOT_RDY_MSK));
2884                         }
2885                 }
2886                 irq_msk &= ~(1 << phy_no);
2887                 phy_no++;
2888         }
2889
2890         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2891
2892         return IRQ_HANDLED;
2893 }
2894
2895 static void
2896 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2897 {
2898         struct device *dev = hisi_hba->dev;
2899         const struct hisi_sas_hw_error *ecc_error;
2900         u32 val;
2901         int i;
2902
2903         for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2904                 ecc_error = &one_bit_ecc_errors[i];
2905                 if (irq_value & ecc_error->irq_msk) {
2906                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2907                         val &= ecc_error->msk;
2908                         val >>= ecc_error->shift;
2909                         dev_warn(dev, ecc_error->msg, val);
2910                 }
2911         }
2912 }
2913
2914 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2915                 u32 irq_value)
2916 {
2917         struct device *dev = hisi_hba->dev;
2918         const struct hisi_sas_hw_error *ecc_error;
2919         u32 val;
2920         int i;
2921
2922         for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2923                 ecc_error = &multi_bit_ecc_errors[i];
2924                 if (irq_value & ecc_error->irq_msk) {
2925                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2926                         val &= ecc_error->msk;
2927                         val >>= ecc_error->shift;
2928                         dev_warn(dev, ecc_error->msg, irq_value, val);
2929                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2930                 }
2931         }
2932
2933         return;
2934 }
2935
2936 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
2937 {
2938         struct hisi_hba *hisi_hba = p;
2939         u32 irq_value, irq_msk;
2940
2941         irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2942         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
2943
2944         irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2945         if (irq_value) {
2946                 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2947                 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2948         }
2949
2950         hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2951         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2952
2953         return IRQ_HANDLED;
2954 }
2955
2956 #define AXI_ERR_NR      8
2957 static const char axi_err_info[AXI_ERR_NR][32] = {
2958         "IOST_AXI_W_ERR",
2959         "IOST_AXI_R_ERR",
2960         "ITCT_AXI_W_ERR",
2961         "ITCT_AXI_R_ERR",
2962         "SATA_AXI_W_ERR",
2963         "SATA_AXI_R_ERR",
2964         "DQE_AXI_R_ERR",
2965         "CQE_AXI_W_ERR"
2966 };
2967
2968 #define FIFO_ERR_NR     5
2969 static const char fifo_err_info[FIFO_ERR_NR][32] = {
2970         "CQE_WINFO_FIFO",
2971         "CQE_MSG_FIFIO",
2972         "GETDQE_FIFO",
2973         "CMDP_FIFO",
2974         "AWTCTRL_FIFO"
2975 };
2976
2977 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
2978 {
2979         struct hisi_hba *hisi_hba = p;
2980         u32 irq_value, irq_msk, err_value;
2981         struct device *dev = hisi_hba->dev;
2982
2983         irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2984         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
2985
2986         irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2987         if (irq_value) {
2988                 if (irq_value & BIT(ENT_INT_SRC3_WP_DEPTH_OFF)) {
2989                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
2990                                         1 << ENT_INT_SRC3_WP_DEPTH_OFF);
2991                         dev_warn(dev, "write pointer and depth error (0x%x) \
2992                                found!\n",
2993                                irq_value);
2994                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2995                 }
2996
2997                 if (irq_value & BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF)) {
2998                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
2999                                          1 <<
3000                                          ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF);
3001                         dev_warn(dev, "iptt no match slot error (0x%x) found!\n",
3002                               irq_value);
3003                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3004                 }
3005
3006                 if (irq_value & BIT(ENT_INT_SRC3_RP_DEPTH_OFF)) {
3007                         dev_warn(dev, "read pointer and depth error (0x%x) \
3008                                found!\n",
3009                                irq_value);
3010                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3011                 }
3012
3013                 if (irq_value & BIT(ENT_INT_SRC3_AXI_OFF)) {
3014                         int i;
3015
3016                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3017                                         1 << ENT_INT_SRC3_AXI_OFF);
3018                         err_value = hisi_sas_read32(hisi_hba,
3019                                                     HGC_AXI_FIFO_ERR_INFO);
3020
3021                         for (i = 0; i < AXI_ERR_NR; i++) {
3022                                 if (err_value & BIT(i)) {
3023                                         dev_warn(dev, "%s (0x%x) found!\n",
3024                                               axi_err_info[i], irq_value);
3025                                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3026                                 }
3027                         }
3028                 }
3029
3030                 if (irq_value & BIT(ENT_INT_SRC3_FIFO_OFF)) {
3031                         int i;
3032
3033                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3034                                         1 << ENT_INT_SRC3_FIFO_OFF);
3035                         err_value = hisi_sas_read32(hisi_hba,
3036                                                     HGC_AXI_FIFO_ERR_INFO);
3037
3038                         for (i = 0; i < FIFO_ERR_NR; i++) {
3039                                 if (err_value & BIT(AXI_ERR_NR + i)) {
3040                                         dev_warn(dev, "%s (0x%x) found!\n",
3041                                               fifo_err_info[i], irq_value);
3042                                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3043                                 }
3044                         }
3045
3046                 }
3047
3048                 if (irq_value & BIT(ENT_INT_SRC3_LM_OFF)) {
3049                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3050                                         1 << ENT_INT_SRC3_LM_OFF);
3051                         dev_warn(dev, "LM add/fetch list error (0x%x) found!\n",
3052                               irq_value);
3053                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3054                 }
3055
3056                 if (irq_value & BIT(ENT_INT_SRC3_ABT_OFF)) {
3057                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3058                                         1 << ENT_INT_SRC3_ABT_OFF);
3059                         dev_warn(dev, "SAS_HGC_ABT fetch LM list error (0x%x) found!\n",
3060                               irq_value);
3061                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3062                 }
3063
3064                 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3065                         u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3066                         u32 dev_id = reg_val & ITCT_DEV_MSK;
3067                         struct hisi_sas_device *sas_dev =
3068                                         &hisi_hba->devices[dev_id];
3069
3070                         hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3071                         dev_dbg(dev, "clear ITCT ok\n");
3072                         complete(sas_dev->completion);
3073                 }
3074         }
3075
3076         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3077         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3078
3079         return IRQ_HANDLED;
3080 }
3081
3082 static void cq_tasklet_v2_hw(unsigned long val)
3083 {
3084         struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3085         struct hisi_hba *hisi_hba = cq->hisi_hba;
3086         struct hisi_sas_slot *slot;
3087         struct hisi_sas_itct *itct;
3088         struct hisi_sas_complete_v2_hdr *complete_queue;
3089         u32 rd_point = cq->rd_point, wr_point, dev_id;
3090         int queue = cq->id;
3091         struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
3092
3093         if (unlikely(hisi_hba->reject_stp_links_msk))
3094                 phys_try_accept_stp_links_v2_hw(hisi_hba);
3095
3096         complete_queue = hisi_hba->complete_hdr[queue];
3097
3098         spin_lock(&dq->lock);
3099         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3100                                    (0x14 * queue));
3101
3102         while (rd_point != wr_point) {
3103                 struct hisi_sas_complete_v2_hdr *complete_hdr;
3104                 int iptt;
3105
3106                 complete_hdr = &complete_queue[rd_point];
3107
3108                 /* Check for NCQ completion */
3109                 if (complete_hdr->act) {
3110                         u32 act_tmp = complete_hdr->act;
3111                         int ncq_tag_count = ffs(act_tmp);
3112
3113                         dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3114                                  CMPLT_HDR_DEV_ID_OFF;
3115                         itct = &hisi_hba->itct[dev_id];
3116
3117                         /* The NCQ tags are held in the itct header */
3118                         while (ncq_tag_count) {
3119                                 __le64 *ncq_tag = &itct->qw4_15[0];
3120
3121                                 ncq_tag_count -= 1;
3122                                 iptt = (ncq_tag[ncq_tag_count / 5]
3123                                         >> (ncq_tag_count % 5) * 12) & 0xfff;
3124
3125                                 slot = &hisi_hba->slot_info[iptt];
3126                                 slot->cmplt_queue_slot = rd_point;
3127                                 slot->cmplt_queue = queue;
3128                                 slot_complete_v2_hw(hisi_hba, slot);
3129
3130                                 act_tmp &= ~(1 << ncq_tag_count);
3131                                 ncq_tag_count = ffs(act_tmp);
3132                         }
3133                 } else {
3134                         iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3135                         slot = &hisi_hba->slot_info[iptt];
3136                         slot->cmplt_queue_slot = rd_point;
3137                         slot->cmplt_queue = queue;
3138                         slot_complete_v2_hw(hisi_hba, slot);
3139                 }
3140
3141                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3142                         rd_point = 0;
3143         }
3144
3145         /* update rd_point */
3146         cq->rd_point = rd_point;
3147         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3148         spin_unlock(&dq->lock);
3149 }
3150
3151 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3152 {
3153         struct hisi_sas_cq *cq = p;
3154         struct hisi_hba *hisi_hba = cq->hisi_hba;
3155         int queue = cq->id;
3156
3157         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3158
3159         tasklet_schedule(&cq->tasklet);
3160
3161         return IRQ_HANDLED;
3162 }
3163
3164 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3165 {
3166         struct hisi_sas_phy *phy = p;
3167         struct hisi_hba *hisi_hba = phy->hisi_hba;
3168         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3169         struct device *dev = hisi_hba->dev;
3170         struct  hisi_sas_initial_fis *initial_fis;
3171         struct dev_to_host_fis *fis;
3172         u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3173         irqreturn_t res = IRQ_HANDLED;
3174         u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3175         int phy_no, offset;
3176
3177         phy_no = sas_phy->id;
3178         initial_fis = &hisi_hba->initial_fis[phy_no];
3179         fis = &initial_fis->fis;
3180
3181         offset = 4 * (phy_no / 4);
3182         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3183         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3184                          ent_msk | 1 << ((phy_no % 4) * 8));
3185
3186         ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3187         ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3188                              (phy_no % 4)));
3189         ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3190         if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3191                 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3192                 res = IRQ_NONE;
3193                 goto end;
3194         }
3195
3196         /* check ERR bit of Status Register */
3197         if (fis->status & ATA_ERR) {
3198                 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3199                                 fis->status);
3200                 disable_phy_v2_hw(hisi_hba, phy_no);
3201                 enable_phy_v2_hw(hisi_hba, phy_no);
3202                 res = IRQ_NONE;
3203                 goto end;
3204         }
3205
3206         if (unlikely(phy_no == 8)) {
3207                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3208
3209                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3210                           PORT_STATE_PHY8_PORT_NUM_OFF;
3211                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3212                             PORT_STATE_PHY8_CONN_RATE_OFF;
3213         } else {
3214                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3215                 port_id = (port_id >> (4 * phy_no)) & 0xf;
3216                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3217                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3218         }
3219
3220         if (port_id == 0xf) {
3221                 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3222                 res = IRQ_NONE;
3223                 goto end;
3224         }
3225
3226         sas_phy->linkrate = link_rate;
3227         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3228                                                 HARD_PHY_LINKRATE);
3229         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3230         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3231
3232         sas_phy->oob_mode = SATA_OOB_MODE;
3233         /* Make up some unique SAS address */
3234         attached_sas_addr[0] = 0x50;
3235         attached_sas_addr[7] = phy_no;
3236         memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3237         memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3238         dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3239         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3240         phy->port_id = port_id;
3241         phy->phy_type |= PORT_TYPE_SATA;
3242         phy->phy_attached = 1;
3243         phy->identify.device_type = SAS_SATA_DEV;
3244         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3245         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3246         queue_work(hisi_hba->wq, &phy->phyup_ws);
3247
3248 end:
3249         hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3250         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3251
3252         return res;
3253 }
3254
3255 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3256         int_phy_updown_v2_hw,
3257         int_chnl_int_v2_hw,
3258 };
3259
3260 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3261         fatal_ecc_int_v2_hw,
3262         fatal_axi_int_v2_hw
3263 };
3264
3265 /**
3266  * There is a limitation in the hip06 chipset that we need
3267  * to map in all mbigen interrupts, even if they are not used.
3268  */
3269 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3270 {
3271         struct platform_device *pdev = hisi_hba->platform_dev;
3272         struct device *dev = &pdev->dev;
3273         int irq, rc, irq_map[128];
3274         int i, phy_no, fatal_no, queue_no, k;
3275
3276         for (i = 0; i < 128; i++)
3277                 irq_map[i] = platform_get_irq(pdev, i);
3278
3279         for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3280                 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3281                 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3282                                       DRV_NAME " phy", hisi_hba);
3283                 if (rc) {
3284                         dev_err(dev, "irq init: could not request "
3285                                 "phy interrupt %d, rc=%d\n",
3286                                 irq, rc);
3287                         rc = -ENOENT;
3288                         goto free_phy_int_irqs;
3289                 }
3290         }
3291
3292         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3293                 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3294
3295                 irq = irq_map[phy_no + 72];
3296                 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3297                                       DRV_NAME " sata", phy);
3298                 if (rc) {
3299                         dev_err(dev, "irq init: could not request "
3300                                 "sata interrupt %d, rc=%d\n",
3301                                 irq, rc);
3302                         rc = -ENOENT;
3303                         goto free_sata_int_irqs;
3304                 }
3305         }
3306
3307         for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3308                 irq = irq_map[fatal_no + 81];
3309                 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3310                                       DRV_NAME " fatal", hisi_hba);
3311                 if (rc) {
3312                         dev_err(dev,
3313                                 "irq init: could not request fatal interrupt %d, rc=%d\n",
3314                                 irq, rc);
3315                         rc = -ENOENT;
3316                         goto free_fatal_int_irqs;
3317                 }
3318         }
3319
3320         for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3321                 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3322                 struct tasklet_struct *t = &cq->tasklet;
3323
3324                 irq = irq_map[queue_no + 96];
3325                 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3326                                       DRV_NAME " cq", cq);
3327                 if (rc) {
3328                         dev_err(dev,
3329                                 "irq init: could not request cq interrupt %d, rc=%d\n",
3330                                 irq, rc);
3331                         rc = -ENOENT;
3332                         goto free_cq_int_irqs;
3333                 }
3334                 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3335         }
3336
3337         return 0;
3338
3339 free_cq_int_irqs:
3340         for (k = 0; k < queue_no; k++) {
3341                 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3342
3343                 free_irq(irq_map[k + 96], cq);
3344                 tasklet_kill(&cq->tasklet);
3345         }
3346 free_fatal_int_irqs:
3347         for (k = 0; k < fatal_no; k++)
3348                 free_irq(irq_map[k + 81], hisi_hba);
3349 free_sata_int_irqs:
3350         for (k = 0; k < phy_no; k++) {
3351                 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3352
3353                 free_irq(irq_map[k + 72], phy);
3354         }
3355 free_phy_int_irqs:
3356         for (k = 0; k < i; k++)
3357                 free_irq(irq_map[k + 1], hisi_hba);
3358         return rc;
3359 }
3360
3361 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3362 {
3363         int rc;
3364
3365         memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3366
3367         rc = hw_init_v2_hw(hisi_hba);
3368         if (rc)
3369                 return rc;
3370
3371         rc = interrupt_init_v2_hw(hisi_hba);
3372         if (rc)
3373                 return rc;
3374
3375         return 0;
3376 }
3377
3378 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3379 {
3380         struct platform_device *pdev = hisi_hba->platform_dev;
3381         int i;
3382
3383         for (i = 0; i < hisi_hba->queue_count; i++)
3384                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3385
3386         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3387         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3388         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3389         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3390
3391         for (i = 0; i < hisi_hba->n_phy; i++) {
3392                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3393                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3394         }
3395
3396         for (i = 0; i < 128; i++)
3397                 synchronize_irq(platform_get_irq(pdev, i));
3398 }
3399
3400
3401 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3402 {
3403         return hisi_sas_read32(hisi_hba, PHY_STATE);
3404 }
3405
3406 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3407 {
3408         struct device *dev = hisi_hba->dev;
3409         int rc, cnt;
3410
3411         interrupt_disable_v2_hw(hisi_hba);
3412         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3413
3414         hisi_sas_stop_phys(hisi_hba);
3415
3416         mdelay(10);
3417
3418         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3419
3420         /* wait until bus idle */
3421         cnt = 0;
3422         while (1) {
3423                 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3424                                 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3425
3426                 if (status == 0x3)
3427                         break;
3428
3429                 udelay(10);
3430                 if (cnt++ > 10) {
3431                         dev_info(dev, "wait axi bus state to idle timeout!\n");
3432                         return -1;
3433                 }
3434         }
3435
3436         hisi_sas_init_mem(hisi_hba);
3437
3438         rc = hw_init_v2_hw(hisi_hba);
3439         if (rc)
3440                 return rc;
3441
3442         phys_reject_stp_links_v2_hw(hisi_hba);
3443
3444         return 0;
3445 }
3446
3447 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3448         .hw_init = hisi_sas_v2_init,
3449         .setup_itct = setup_itct_v2_hw,
3450         .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3451         .alloc_dev = alloc_dev_quirk_v2_hw,
3452         .sl_notify = sl_notify_v2_hw,
3453         .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3454         .free_device = free_device_v2_hw,
3455         .prep_smp = prep_smp_v2_hw,
3456         .prep_ssp = prep_ssp_v2_hw,
3457         .prep_stp = prep_ata_v2_hw,
3458         .prep_abort = prep_abort_v2_hw,
3459         .get_free_slot = get_free_slot_v2_hw,
3460         .start_delivery = start_delivery_v2_hw,
3461         .slot_complete = slot_complete_v2_hw,
3462         .phys_init = phys_init_v2_hw,
3463         .phy_enable = enable_phy_v2_hw,
3464         .phy_disable = disable_phy_v2_hw,
3465         .phy_hard_reset = phy_hard_reset_v2_hw,
3466         .get_events = phy_get_events_v2_hw,
3467         .phy_set_linkrate = phy_set_linkrate_v2_hw,
3468         .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3469         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3470         .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3471         .soft_reset = soft_reset_v2_hw,
3472         .get_phys_state = get_phys_state_v2_hw,
3473 };
3474
3475 static int hisi_sas_v2_probe(struct platform_device *pdev)
3476 {
3477         /*
3478          * Check if we should defer the probe before we probe the
3479          * upper layer, as it's hard to defer later on.
3480          */
3481         int ret = platform_get_irq(pdev, 0);
3482
3483         if (ret < 0) {
3484                 if (ret != -EPROBE_DEFER)
3485                         dev_err(&pdev->dev, "cannot obtain irq\n");
3486                 return ret;
3487         }
3488
3489         return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3490 }
3491
3492 static int hisi_sas_v2_remove(struct platform_device *pdev)
3493 {
3494         struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3495         struct hisi_hba *hisi_hba = sha->lldd_ha;
3496         int i;
3497
3498         if (timer_pending(&hisi_hba->timer))
3499                 del_timer(&hisi_hba->timer);
3500
3501         for (i = 0; i < hisi_hba->queue_count; i++) {
3502                 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
3503
3504                 tasklet_kill(&cq->tasklet);
3505         }
3506
3507         return hisi_sas_remove(pdev);
3508 }
3509
3510 static const struct of_device_id sas_v2_of_match[] = {
3511         { .compatible = "hisilicon,hip06-sas-v2",},
3512         { .compatible = "hisilicon,hip07-sas-v2",},
3513         {},
3514 };
3515 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3516
3517 static const struct acpi_device_id sas_v2_acpi_match[] = {
3518         { "HISI0162", 0 },
3519         { }
3520 };
3521
3522 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3523
3524 static struct platform_driver hisi_sas_v2_driver = {
3525         .probe = hisi_sas_v2_probe,
3526         .remove = hisi_sas_v2_remove,
3527         .driver = {
3528                 .name = DRV_NAME,
3529                 .of_match_table = sas_v2_of_match,
3530                 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3531         },
3532 };
3533
3534 module_platform_driver(hisi_sas_v2_driver);
3535
3536 MODULE_LICENSE("GPL");
3537 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3538 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3539 MODULE_ALIAS("platform:" DRV_NAME);