drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

   1 /*
   2  * Copyright (c) 2017 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  */
  10
  11 #include "hisi_sas.h"
  12 #define DRV_NAME "hisi_sas_v3_hw"
  13
  14 /* global registers need init*/
  15 #define DLVRY_QUEUE_ENABLE              0x0
  16 #define IOST_BASE_ADDR_LO               0x8
  17 #define IOST_BASE_ADDR_HI               0xc
  18 #define ITCT_BASE_ADDR_LO               0x10
  19 #define ITCT_BASE_ADDR_HI               0x14
  20 #define IO_BROKEN_MSG_ADDR_LO           0x18
  21 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  22 #define PHY_CONTEXT                     0x20
  23 #define PHY_STATE                       0x24
  24 #define PHY_PORT_NUM_MA                 0x28
  25 #define PHY_CONN_RATE                   0x30
  26 #define ITCT_CLR                        0x44
  27 #define ITCT_CLR_EN_OFF                 16
  28 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  29 #define ITCT_DEV_OFF                    0
  30 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  31 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  32 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  33 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  34 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  35 #define CFG_MAX_TAG                     0x68
  36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  37 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  38 #define HGC_GET_ITV_TIME                0x90
  39 #define DEVICE_MSG_WORK_MODE            0x94
  40 #define OPENA_WT_CONTI_TIME             0x9c
  41 #define I_T_NEXUS_LOSS_TIME             0xa0
  42 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  43 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  44 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  45 #define CFG_AGING_TIME                  0xbc
  46 #define HGC_DFX_CFG2                    0xc0
  47 #define CFG_ABT_SET_QUERY_IPTT  0xd4
  48 #define CFG_SET_ABORTED_IPTT_OFF        0
  49 #define CFG_SET_ABORTED_IPTT_MSK        (0xfff << CFG_SET_ABORTED_IPTT_OFF)
  50 #define CFG_SET_ABORTED_EN_OFF  12
  51 #define CFG_ABT_SET_IPTT_DONE   0xd8
  52 #define CFG_ABT_SET_IPTT_DONE_OFF       0
  53 #define HGC_IOMB_PROC1_STATUS   0x104
  54 #define CFG_1US_TIMER_TRSH              0xcc
  55 #define CHNL_INT_STATUS                 0x148
  56 #define INT_COAL_EN                     0x19c
  57 #define OQ_INT_COAL_TIME                0x1a0
  58 #define OQ_INT_COAL_CNT                 0x1a4
  59 #define ENT_INT_COAL_TIME               0x1a8
  60 #define ENT_INT_COAL_CNT                0x1ac
  61 #define OQ_INT_SRC                      0x1b0
  62 #define OQ_INT_SRC_MSK                  0x1b4
  63 #define ENT_INT_SRC1                    0x1b8
  64 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
  65 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
  66 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
  67 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
  68 #define ENT_INT_SRC2                    0x1bc
  69 #define ENT_INT_SRC3                    0x1c0
  70 #define ENT_INT_SRC3_WP_DEPTH_OFF               8
  71 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF      9
  72 #define ENT_INT_SRC3_RP_DEPTH_OFF               10
  73 #define ENT_INT_SRC3_AXI_OFF                    11
  74 #define ENT_INT_SRC3_FIFO_OFF                   12
  75 #define ENT_INT_SRC3_LM_OFF                             14
  76 #define ENT_INT_SRC3_ITC_INT_OFF        15
  77 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
  78 #define ENT_INT_SRC3_ABT_OFF            16
  79 #define ENT_INT_SRC_MSK1                0x1c4
  80 #define ENT_INT_SRC_MSK2                0x1c8
  81 #define ENT_INT_SRC_MSK3                0x1cc
  82 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
  83 #define CHNL_PHYUPDOWN_INT_MSK          0x1d0
  84 #define CHNL_ENT_INT_MSK                        0x1d4
  85 #define HGC_COM_INT_MSK                         0x1d8
  86 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
  87 #define SAS_ECC_INTR                    0x1e8
  88 #define SAS_ECC_INTR_MSK                0x1ec
  89 #define HGC_ERR_STAT_EN                 0x238
  90 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
  91 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
  92 #define DLVRY_Q_0_DEPTH                 0x268
  93 #define DLVRY_Q_0_WR_PTR                0x26c
  94 #define DLVRY_Q_0_RD_PTR                0x270
  95 #define HYPER_STREAM_ID_EN_CFG          0xc80
  96 #define OQ0_INT_SRC_MSK                 0xc90
  97 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
  98 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
  99 #define COMPL_Q_0_DEPTH                 0x4e8
 100 #define COMPL_Q_0_WR_PTR                0x4ec
 101 #define COMPL_Q_0_RD_PTR                0x4f0
 102 #define AWQOS_AWCACHE_CFG       0xc84
 103 #define ARQOS_ARCACHE_CFG       0xc88
 104
 105 /* phy registers requiring init */
 106 #define PORT_BASE                       (0x2000)
 107 #define PHY_CFG                         (PORT_BASE + 0x0)
 108 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 109 #define PHY_CFG_ENA_OFF                 0
 110 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 111 #define PHY_CFG_DC_OPT_OFF              2
 112 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 113 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 114 #define PHY_CTRL                        (PORT_BASE + 0x14)
 115 #define PHY_CTRL_RESET_OFF              0
 116 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 117 #define SL_CFG                          (PORT_BASE + 0x84)
 118 #define SL_CONTROL                      (PORT_BASE + 0x94)
 119 #define SL_CONTROL_NOTIFY_EN_OFF        0
 120 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 121 #define SL_CTA_OFF              17
 122 #define SL_CTA_MSK              (0x1 << SL_CTA_OFF)
 123 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 124 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 125 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 126 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 127 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 128 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 129 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 130 #define TXID_AUTO                               (PORT_BASE + 0xb8)
 131 #define CT3_OFF         1
 132 #define CT3_MSK         (0x1 << CT3_OFF)
 133 #define TX_HARDRST_OFF          2
 134 #define TX_HARDRST_MSK          (0x1 << TX_HARDRST_OFF)
 135 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 136 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 137 #define STP_LINK_TIMER                  (PORT_BASE + 0x120)
 138 #define SAS_SSP_CON_TIMER_CFG           (PORT_BASE + 0x134)
 139 #define SAS_SMP_CON_TIMER_CFG           (PORT_BASE + 0x138)
 140 #define SAS_STP_CON_TIMER_CFG           (PORT_BASE + 0x13c)
 141 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 142 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 143 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 144 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 145 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 146 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 147 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 148 #define CHL_INT0_NOT_RDY_OFF            4
 149 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 150 #define CHL_INT0_PHY_RDY_OFF            5
 151 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 152 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 153 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 154 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 155 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 156 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 157 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 158 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 159 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 160 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 161 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 162 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 163 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 164 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 165 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 166 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 167 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 168 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 169 #define DMA_TX_STATUS_BUSY_OFF          0
 170 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 171 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 172 #define DMA_RX_STATUS_BUSY_OFF          0
 173 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 174
 175 #define MAX_ITCT_HW                     4096 /* max the hw can support */
 176 #define DEFAULT_ITCT_HW         2048 /* reset value, not reprogrammed */
 177 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
 178 #error Max ITCT exceeded
 179 #endif
 180
 181 #define AXI_MASTER_CFG_BASE             (0x5000)
 182 #define AM_CTRL_GLOBAL                  (0x0)
 183 #define AM_CURR_TRANS_RETURN    (0x150)
 184
 185 #define AM_CFG_MAX_TRANS                (0x5010)
 186 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 187 #define AXI_CFG                                 (0x5100)
 188 #define AM_ROB_ECC_ERR_ADDR             (0x510c)
 189 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF  0
 190 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK  (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
 191 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF  8
 192 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK  (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
 193
 194 /* HW dma structures */
 195 /* Delivery queue header */
 196 /* dw0 */
 197 #define CMD_HDR_ABORT_FLAG_OFF          0
 198 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
 199 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
 200 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
 201 #define CMD_HDR_RESP_REPORT_OFF         5
 202 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 203 #define CMD_HDR_TLR_CTRL_OFF            6
 204 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 205 #define CMD_HDR_PORT_OFF                18
 206 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 207 #define CMD_HDR_PRIORITY_OFF            27
 208 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 209 #define CMD_HDR_CMD_OFF                 29
 210 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 211 /* dw1 */
 212 #define CMD_HDR_UNCON_CMD_OFF   3
 213 #define CMD_HDR_DIR_OFF                 5
 214 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 215 #define CMD_HDR_RESET_OFF               7
 216 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 217 #define CMD_HDR_VDTL_OFF                10
 218 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 219 #define CMD_HDR_FRAME_TYPE_OFF          11
 220 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 221 #define CMD_HDR_DEV_ID_OFF              16
 222 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 223 /* dw2 */
 224 #define CMD_HDR_CFL_OFF                 0
 225 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 226 #define CMD_HDR_NCQ_TAG_OFF             10
 227 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 228 #define CMD_HDR_MRFL_OFF                15
 229 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 230 #define CMD_HDR_SG_MOD_OFF              24
 231 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 232 /* dw3 */
 233 #define CMD_HDR_IPTT_OFF                0
 234 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 235 /* dw6 */
 236 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 237 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 238 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 239 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 240 /* dw7 */
 241 #define CMD_HDR_ADDR_MODE_SEL_OFF               15
 242 #define CMD_HDR_ADDR_MODE_SEL_MSK               (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
 243 #define CMD_HDR_ABORT_IPTT_OFF          16
 244 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
 245
 246 /* Completion header */
 247 /* dw0 */
 248 #define CMPLT_HDR_CMPLT_OFF             0
 249 #define CMPLT_HDR_CMPLT_MSK             (0x3 << CMPLT_HDR_CMPLT_OFF)
 250 #define CMPLT_HDR_ERROR_PHASE_OFF   2
 251 #define CMPLT_HDR_ERROR_PHASE_MSK   (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
 252 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 253 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 254 #define CMPLT_HDR_ERX_OFF               12
 255 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 256 #define CMPLT_HDR_ABORT_STAT_OFF        13
 257 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
 258 /* abort_stat */
 259 #define STAT_IO_NOT_VALID               0x1
 260 #define STAT_IO_NO_DEVICE               0x2
 261 #define STAT_IO_COMPLETE                0x3
 262 #define STAT_IO_ABORTED                 0x4
 263 /* dw1 */
 264 #define CMPLT_HDR_IPTT_OFF              0
 265 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 266 #define CMPLT_HDR_DEV_ID_OFF            16
 267 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 268 /* dw3 */
 269 #define CMPLT_HDR_IO_IN_TARGET_OFF      17
 270 #define CMPLT_HDR_IO_IN_TARGET_MSK      (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
 271
 272 /* ITCT header */
 273 /* qw0 */
 274 #define ITCT_HDR_DEV_TYPE_OFF           0
 275 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 276 #define ITCT_HDR_VALID_OFF              2
 277 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 278 #define ITCT_HDR_MCR_OFF                5
 279 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 280 #define ITCT_HDR_VLN_OFF                9
 281 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 282 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
 283 #define ITCT_HDR_AWT_CONTINUE_OFF       25
 284 #define ITCT_HDR_PORT_ID_OFF            28
 285 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 286 /* qw2 */
 287 #define ITCT_HDR_INLT_OFF               0
 288 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 289 #define ITCT_HDR_RTOLT_OFF              48
 290 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 291
 292 struct hisi_sas_complete_v3_hdr {
 293         __le32 dw0;
 294         __le32 dw1;
 295         __le32 act;
 296         __le32 dw3;
 297 };
 298
 299 struct hisi_sas_err_record_v3 {
 300         /* dw0 */
 301         __le32 trans_tx_fail_type;
 302
 303         /* dw1 */
 304         __le32 trans_rx_fail_type;
 305
 306         /* dw2 */
 307         __le16 dma_tx_err_type;
 308         __le16 sipc_rx_err_type;
 309
 310         /* dw3 */
 311         __le32 dma_rx_err_type;
 312 };
 313
 314 #define RX_DATA_LEN_UNDERFLOW_OFF       6
 315 #define RX_DATA_LEN_UNDERFLOW_MSK       (1 << RX_DATA_LEN_UNDERFLOW_OFF)
 316
 317 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
 318 #define HISI_SAS_MSI_COUNT_V3_HW 32
 319
 320 enum {
 321         HISI_SAS_PHY_PHY_UPDOWN,
 322         HISI_SAS_PHY_CHNL_INT,
 323         HISI_SAS_PHY_INT_NR
 324 };
 325
 326 #define DIR_NO_DATA 0
 327 #define DIR_TO_INI 1
 328 #define DIR_TO_DEVICE 2
 329 #define DIR_RESERVED 3
 330
 331 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
 332         ((fis.command == ATA_CMD_READ_LOG_EXT) || \
 333         (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
 334         ((fis.command == ATA_CMD_DEV_RESET) && \
 335         ((fis.control & ATA_SRST) != 0)))
 336
 337 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 338 {
 339         void __iomem *regs = hisi_hba->regs + off;
 340
 341         return readl(regs);
 342 }
 343
 344 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 345 {
 346         void __iomem *regs = hisi_hba->regs + off;
 347
 348         return readl_relaxed(regs);
 349 }
 350
 351 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 352 {
 353         void __iomem *regs = hisi_hba->regs + off;
 354
 355         writel(val, regs);
 356 }
 357
 358 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 359                                  u32 off, u32 val)
 360 {
 361         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 362
 363         writel(val, regs);
 364 }
 365
 366 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 367                                       int phy_no, u32 off)
 368 {
 369         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 370
 371         return readl(regs);
 372 }
 373
 374 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
 375 {
 376         int i;
 377
 378         /* Global registers init */
 379         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
 380                          (u32)((1ULL << hisi_hba->queue_count) - 1));
 381         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
 382         hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
 383         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
 384         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
 385         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
 386         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
 387         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
 388         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
 389         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
 390         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
 391         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
 392         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
 393         hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
 394         hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
 395         hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
 396         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
 397         hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
 398         hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
 399         for (i = 0; i < hisi_hba->queue_count; i++)
 400                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
 401
 402         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
 403         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE, 0x30000);
 404
 405         for (i = 0; i < hisi_hba->n_phy; i++) {
 406                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801);
 407                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
 408                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
 409                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
 410                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
 411                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
 412                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
 413                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
 414                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
 415                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
 416                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
 417                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
 418                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
 419                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa);
 420                 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG,
 421                                      0xa03e8);
 422                 hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG,
 423                                      0xa03e8);
 424                 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER,
 425                                      0x7f7a120);
 426         }
 427         for (i = 0; i < hisi_hba->queue_count; i++) {
 428                 /* Delivery queue */
 429                 hisi_sas_write32(hisi_hba,
 430                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
 431                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
 432
 433                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
 434                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
 435
 436                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
 437                                  HISI_SAS_QUEUE_SLOTS);
 438
 439                 /* Completion queue */
 440                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
 441                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
 442
 443                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
 444                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
 445
 446                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
 447                                  HISI_SAS_QUEUE_SLOTS);
 448         }
 449
 450         /* itct */
 451         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
 452                          lower_32_bits(hisi_hba->itct_dma));
 453
 454         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
 455                          upper_32_bits(hisi_hba->itct_dma));
 456
 457         /* iost */
 458         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
 459                          lower_32_bits(hisi_hba->iost_dma));
 460
 461         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
 462                          upper_32_bits(hisi_hba->iost_dma));
 463
 464         /* breakpoint */
 465         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
 466                          lower_32_bits(hisi_hba->breakpoint_dma));
 467
 468         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
 469                          upper_32_bits(hisi_hba->breakpoint_dma));
 470
 471         /* SATA broken msg */
 472         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
 473                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
 474
 475         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
 476                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
 477
 478         /* SATA initial fis */
 479         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
 480                          lower_32_bits(hisi_hba->initial_fis_dma));
 481
 482         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
 483                          upper_32_bits(hisi_hba->initial_fis_dma));
 484 }
 485
 486 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 487 {
 488         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 489
 490         cfg &= ~PHY_CFG_DC_OPT_MSK;
 491         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 492         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 493 }
 494
 495 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 496 {
 497         struct sas_identify_frame identify_frame;
 498         u32 *identify_buffer;
 499
 500         memset(&identify_frame, 0, sizeof(identify_frame));
 501         identify_frame.dev_type = SAS_END_DEVICE;
 502         identify_frame.frame_type = 0;
 503         identify_frame._un1 = 1;
 504         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 505         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 506         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 507         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 508         identify_frame.phy_id = phy_no;
 509         identify_buffer = (u32 *)(&identify_frame);
 510
 511         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 512                         __swab32(identify_buffer[0]));
 513         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 514                         __swab32(identify_buffer[1]));
 515         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 516                         __swab32(identify_buffer[2]));
 517         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 518                         __swab32(identify_buffer[3]));
 519         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 520                         __swab32(identify_buffer[4]));
 521         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 522                         __swab32(identify_buffer[5]));
 523 }
 524
 525 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
 526                              struct hisi_sas_device *sas_dev)
 527 {
 528         struct domain_device *device = sas_dev->sas_device;
 529         struct device *dev = hisi_hba->dev;
 530         u64 qw0, device_id = sas_dev->device_id;
 531         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 532         struct domain_device *parent_dev = device->parent;
 533         struct asd_sas_port *sas_port = device->port;
 534         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
 535
 536         memset(itct, 0, sizeof(*itct));
 537
 538         /* qw0 */
 539         qw0 = 0;
 540         switch (sas_dev->dev_type) {
 541         case SAS_END_DEVICE:
 542         case SAS_EDGE_EXPANDER_DEVICE:
 543         case SAS_FANOUT_EXPANDER_DEVICE:
 544                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 545                 break;
 546         case SAS_SATA_DEV:
 547         case SAS_SATA_PENDING:
 548                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
 549                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 550                 else
 551                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 552                 break;
 553         default:
 554                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 555                          sas_dev->dev_type);
 556         }
 557
 558         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 559                 (device->linkrate << ITCT_HDR_MCR_OFF) |
 560                 (1 << ITCT_HDR_VLN_OFF) |
 561                 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
 562                 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
 563                 (port->id << ITCT_HDR_PORT_ID_OFF));
 564         itct->qw0 = cpu_to_le64(qw0);
 565
 566         /* qw1 */
 567         memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 568         itct->sas_addr = __swab64(itct->sas_addr);
 569
 570         /* qw2 */
 571         if (!dev_is_sata(device))
 572                 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
 573                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
 574 }
 575
 576 static void free_device_v3_hw(struct hisi_hba *hisi_hba,
 577                               struct hisi_sas_device *sas_dev)
 578 {
 579         u64 dev_id = sas_dev->device_id;
 580         struct device *dev = hisi_hba->dev;
 581         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 582         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 583
 584         /* clear the itct interrupt state */
 585         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 586                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 587                                  ENT_INT_SRC3_ITC_INT_MSK);
 588
 589         /* clear the itct table*/
 590         reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
 591         reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 592         hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 593
 594         udelay(10);
 595         reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 596         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
 597                 dev_dbg(dev, "got clear ITCT done interrupt\n");
 598
 599                 /* invalid the itct state*/
 600                 memset(itct, 0, sizeof(struct hisi_sas_itct));
 601                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 602                                  ENT_INT_SRC3_ITC_INT_MSK);
 603
 604                 /* clear the itct */
 605                 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
 606                 dev_dbg(dev, "clear ITCT ok\n");
 607         }
 608 }
 609
 610 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
 611                                 struct domain_device *device)
 612 {
 613         struct hisi_sas_slot *slot, *slot2;
 614         struct hisi_sas_device *sas_dev = device->lldd_dev;
 615         u32 cfg_abt_set_query_iptt;
 616
 617         cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
 618                 CFG_ABT_SET_QUERY_IPTT);
 619         list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
 620                 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
 621                 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
 622                         (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
 623                 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
 624                         cfg_abt_set_query_iptt);
 625         }
 626         cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
 627         hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
 628                 cfg_abt_set_query_iptt);
 629         hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
 630                                         1 << CFG_ABT_SET_IPTT_DONE_OFF);
 631 }
 632
 633 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
 634 {
 635         struct device *dev = hisi_hba->dev;
 636         int ret;
 637         u32 val;
 638
 639         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
 640
 641         /* Disable all of the PHYs */
 642         hisi_sas_stop_phys(hisi_hba);
 643         udelay(50);
 644
 645         /* Ensure axi bus idle */
 646         ret = readl_poll_timeout(hisi_hba->regs + AXI_CFG, val, !val,
 647                         20000, 1000000);
 648         if (ret) {
 649                 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
 650                 return -EIO;
 651         }
 652
 653         if (ACPI_HANDLE(dev)) {
 654                 acpi_status s;
 655
 656                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
 657                 if (ACPI_FAILURE(s)) {
 658                         dev_err(dev, "Reset failed\n");
 659                         return -EIO;
 660                 }
 661         } else
 662                 dev_err(dev, "no reset method!\n");
 663
 664         return 0;
 665 }
 666
 667 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
 668 {
 669         struct device *dev = hisi_hba->dev;
 670         int rc;
 671
 672         rc = reset_hw_v3_hw(hisi_hba);
 673         if (rc) {
 674                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
 675                 return rc;
 676         }
 677
 678         msleep(100);
 679         init_reg_v3_hw(hisi_hba);
 680
 681         return 0;
 682 }
 683
 684 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 685 {
 686         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 687
 688         cfg |= PHY_CFG_ENA_MSK;
 689         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 690 }
 691
 692 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 693 {
 694         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 695
 696         cfg &= ~PHY_CFG_ENA_MSK;
 697         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 698 }
 699
 700 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 701 {
 702         config_id_frame_v3_hw(hisi_hba, phy_no);
 703         config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
 704         enable_phy_v3_hw(hisi_hba, phy_no);
 705 }
 706
 707 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 708 {
 709         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
 710         u32 txid_auto;
 711
 712         disable_phy_v3_hw(hisi_hba, phy_no);
 713         if (phy->identify.device_type == SAS_END_DEVICE) {
 714                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
 715                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
 716                                         txid_auto | TX_HARDRST_MSK);
 717         }
 718         msleep(100);
 719         start_phy_v3_hw(hisi_hba, phy_no);
 720 }
 721
 722 enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
 723 {
 724         return SAS_LINK_RATE_12_0_GBPS;
 725 }
 726
 727 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
 728 {
 729         int i;
 730
 731         for (i = 0; i < hisi_hba->n_phy; i++) {
 732                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
 733                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
 734
 735                 if (!sas_phy->phy->enabled)
 736                         continue;
 737
 738                 start_phy_v3_hw(hisi_hba, i);
 739         }
 740 }
 741
 742 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 743 {
 744         u32 sl_control;
 745
 746         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 747         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
 748         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 749         msleep(1);
 750         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 751         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
 752         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 753 }
 754
 755 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
 756 {
 757         int i, bitmap = 0;
 758         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
 759
 760         for (i = 0; i < hisi_hba->n_phy; i++)
 761                 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
 762                         bitmap |= 1 << i;
 763
 764         return bitmap;
 765 }
 766
 767 /**
 768  * The callpath to this function and upto writing the write
 769  * queue pointer should be safe from interruption.
 770  */
 771 static int
 772 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
 773 {
 774         struct device *dev = hisi_hba->dev;
 775         int queue = dq->id;
 776         u32 r, w;
 777
 778         w = dq->wr_point;
 779         r = hisi_sas_read32_relaxed(hisi_hba,
 780                                 DLVRY_Q_0_RD_PTR + (queue * 0x14));
 781         if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
 782                 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
 783                                 queue, r, w);
 784                 return -EAGAIN;
 785         }
 786
 787         return 0;
 788 }
 789
 790 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
 791 {
 792         struct hisi_hba *hisi_hba = dq->hisi_hba;
 793         int dlvry_queue = dq->slot_prep->dlvry_queue;
 794         int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
 795
 796         dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
 797         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
 798                          dq->wr_point);
 799 }
 800
 801 static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
 802                               struct hisi_sas_slot *slot,
 803                               struct hisi_sas_cmd_hdr *hdr,
 804                               struct scatterlist *scatter,
 805                               int n_elem)
 806 {
 807         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
 808         struct device *dev = hisi_hba->dev;
 809         struct scatterlist *sg;
 810         int i;
 811
 812         if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
 813                 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
 814                         n_elem);
 815                 return -EINVAL;
 816         }
 817
 818         for_each_sg(scatter, sg, n_elem, i) {
 819                 struct hisi_sas_sge *entry = &sge_page->sge[i];
 820
 821                 entry->addr = cpu_to_le64(sg_dma_address(sg));
 822                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
 823                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
 824                 entry->data_off = 0;
 825         }
 826
 827         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
 828
 829         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
 830
 831         return 0;
 832 }
 833
 834 static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
 835                           struct hisi_sas_slot *slot, int is_tmf,
 836                           struct hisi_sas_tmf_task *tmf)
 837 {
 838         struct sas_task *task = slot->task;
 839         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
 840         struct domain_device *device = task->dev;
 841         struct hisi_sas_device *sas_dev = device->lldd_dev;
 842         struct hisi_sas_port *port = slot->port;
 843         struct sas_ssp_task *ssp_task = &task->ssp_task;
 844         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
 845         int has_data = 0, rc, priority = is_tmf;
 846         u8 *buf_cmd;
 847         u32 dw1 = 0, dw2 = 0;
 848
 849         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
 850                                (2 << CMD_HDR_TLR_CTRL_OFF) |
 851                                (port->id << CMD_HDR_PORT_OFF) |
 852                                (priority << CMD_HDR_PRIORITY_OFF) |
 853                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
 854
 855         dw1 = 1 << CMD_HDR_VDTL_OFF;
 856         if (is_tmf) {
 857                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
 858                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
 859         } else {
 860                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
 861                 switch (scsi_cmnd->sc_data_direction) {
 862                 case DMA_TO_DEVICE:
 863                         has_data = 1;
 864                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
 865                         break;
 866                 case DMA_FROM_DEVICE:
 867                         has_data = 1;
 868                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
 869                         break;
 870                 default:
 871                         dw1 &= ~CMD_HDR_DIR_MSK;
 872                 }
 873         }
 874
 875         /* map itct entry */
 876         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
 877         hdr->dw1 = cpu_to_le32(dw1);
 878
 879         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
 880               + 3) / 4) << CMD_HDR_CFL_OFF) |
 881               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
 882               (2 << CMD_HDR_SG_MOD_OFF);
 883         hdr->dw2 = cpu_to_le32(dw2);
 884         hdr->transfer_tags = cpu_to_le32(slot->idx);
 885
 886         if (has_data) {
 887                 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
 888                                         slot->n_elem);
 889                 if (rc)
 890                         return rc;
 891         }
 892
 893         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
 894         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
 895         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
 896
 897         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
 898                 sizeof(struct ssp_frame_hdr);
 899
 900         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
 901         if (!is_tmf) {
 902                 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
 903                 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
 904         } else {
 905                 buf_cmd[10] = tmf->tmf;
 906                 switch (tmf->tmf) {
 907                 case TMF_ABORT_TASK:
 908                 case TMF_QUERY_TASK:
 909                         buf_cmd[12] =
 910                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
 911                         buf_cmd[13] =
 912                                 tmf->tag_of_task_to_be_managed & 0xff;
 913                         break;
 914                 default:
 915                         break;
 916                 }
 917         }
 918
 919         return 0;
 920 }
 921
 922 static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
 923                           struct hisi_sas_slot *slot)
 924 {
 925         struct sas_task *task = slot->task;
 926         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
 927         struct domain_device *device = task->dev;
 928         struct device *dev = hisi_hba->dev;
 929         struct hisi_sas_port *port = slot->port;
 930         struct scatterlist *sg_req, *sg_resp;
 931         struct hisi_sas_device *sas_dev = device->lldd_dev;
 932         dma_addr_t req_dma_addr;
 933         unsigned int req_len, resp_len;
 934         int elem, rc;
 935
 936         /*
 937          * DMA-map SMP request, response buffers
 938          */
 939         /* req */
 940         sg_req = &task->smp_task.smp_req;
 941         elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
 942         if (!elem)
 943                 return -ENOMEM;
 944         req_len = sg_dma_len(sg_req);
 945         req_dma_addr = sg_dma_address(sg_req);
 946
 947         /* resp */
 948         sg_resp = &task->smp_task.smp_resp;
 949         elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
 950         if (!elem) {
 951                 rc = -ENOMEM;
 952                 goto err_out_req;
 953         }
 954         resp_len = sg_dma_len(sg_resp);
 955         if ((req_len & 0x3) || (resp_len & 0x3)) {
 956                 rc = -EINVAL;
 957                 goto err_out_resp;
 958         }
 959
 960         /* create header */
 961         /* dw0 */
 962         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
 963                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
 964                                (2 << CMD_HDR_CMD_OFF)); /* smp */
 965
 966         /* map itct entry */
 967         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
 968                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
 969                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
 970
 971         /* dw2 */
 972         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
 973                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
 974                                CMD_HDR_MRFL_OFF));
 975
 976         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
 977
 978         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
 979         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
 980
 981         return 0;
 982
 983 err_out_resp:
 984         dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
 985                      DMA_FROM_DEVICE);
 986 err_out_req:
 987         dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
 988                      DMA_TO_DEVICE);
 989         return rc;
 990 }
 991
 992 static int get_ncq_tag_v3_hw(struct sas_task *task, u32 *tag)
 993 {
 994         struct ata_queued_cmd *qc = task->uldd_task;
 995
 996         if (qc) {
 997                 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
 998                         qc->tf.command == ATA_CMD_FPDMA_READ) {
 999                         *tag = qc->tag;
1000                         return 1;
1001                 }
1002         }
1003         return 0;
1004 }
1005
1006 static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1007                           struct hisi_sas_slot *slot)
1008 {
1009         struct sas_task *task = slot->task;
1010         struct domain_device *device = task->dev;
1011         struct domain_device *parent_dev = device->parent;
1012         struct hisi_sas_device *sas_dev = device->lldd_dev;
1013         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1014         struct asd_sas_port *sas_port = device->port;
1015         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1016         u8 *buf_cmd;
1017         int has_data = 0, rc = 0, hdr_tag = 0;
1018         u32 dw1 = 0, dw2 = 0;
1019
1020         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1021         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1022                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1023         else
1024                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1025
1026         switch (task->data_dir) {
1027         case DMA_TO_DEVICE:
1028                 has_data = 1;
1029                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1030                 break;
1031         case DMA_FROM_DEVICE:
1032                 has_data = 1;
1033                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1034                 break;
1035         default:
1036                 dw1 &= ~CMD_HDR_DIR_MSK;
1037         }
1038
1039         if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1040                         (task->ata_task.fis.control & ATA_SRST))
1041                 dw1 |= 1 << CMD_HDR_RESET_OFF;
1042
1043         dw1 |= (hisi_sas_get_ata_protocol(
1044                 task->ata_task.fis.command, task->data_dir))
1045                 << CMD_HDR_FRAME_TYPE_OFF;
1046         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1047
1048         if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1049                 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1050
1051         hdr->dw1 = cpu_to_le32(dw1);
1052
1053         /* dw2 */
1054         if (task->ata_task.use_ncq && get_ncq_tag_v3_hw(task, &hdr_tag)) {
1055                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1056                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1057         }
1058
1059         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1060                         2 << CMD_HDR_SG_MOD_OFF;
1061         hdr->dw2 = cpu_to_le32(dw2);
1062
1063         /* dw3 */
1064         hdr->transfer_tags = cpu_to_le32(slot->idx);
1065
1066         if (has_data) {
1067                 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1068                                         slot->n_elem);
1069                 if (rc)
1070                         return rc;
1071         }
1072
1073         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1074         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1075         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1076
1077         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1078
1079         if (likely(!task->ata_task.device_control_reg_update))
1080                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1081         /* fill in command FIS */
1082         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1083
1084         return 0;
1085 }
1086
1087 static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1088                 struct hisi_sas_slot *slot,
1089                 int device_id, int abort_flag, int tag_to_abort)
1090 {
1091         struct sas_task *task = slot->task;
1092         struct domain_device *dev = task->dev;
1093         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1094         struct hisi_sas_port *port = slot->port;
1095
1096         /* dw0 */
1097         hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1098                                (port->id << CMD_HDR_PORT_OFF) |
1099                                    ((dev_is_sata(dev) ? 1:0)
1100                                         << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1101                                         (abort_flag
1102                                          << CMD_HDR_ABORT_FLAG_OFF));
1103
1104         /* dw1 */
1105         hdr->dw1 = cpu_to_le32(device_id
1106                         << CMD_HDR_DEV_ID_OFF);
1107
1108         /* dw7 */
1109         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1110         hdr->transfer_tags = cpu_to_le32(slot->idx);
1111
1112         return 0;
1113 }
1114
1115 static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1116 {
1117         int i, res = 0;
1118         u32 context, port_id, link_rate, hard_phy_linkrate;
1119         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1120         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1121         struct device *dev = hisi_hba->dev;
1122
1123         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1124
1125         port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1126         port_id = (port_id >> (4 * phy_no)) & 0xf;
1127         link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1128         link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1129
1130         if (port_id == 0xf) {
1131                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1132                 res = IRQ_NONE;
1133                 goto end;
1134         }
1135         sas_phy->linkrate = link_rate;
1136         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1137                                                 HARD_PHY_LINKRATE);
1138         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1139         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1140         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1141
1142         /* Check for SATA dev */
1143         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1144         if (context & (1 << phy_no)) {
1145                 struct hisi_sas_initial_fis *initial_fis;
1146                 struct dev_to_host_fis *fis;
1147                 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1148
1149                 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1150                 initial_fis = &hisi_hba->initial_fis[phy_no];
1151                 fis = &initial_fis->fis;
1152                 sas_phy->oob_mode = SATA_OOB_MODE;
1153                 attached_sas_addr[0] = 0x50;
1154                 attached_sas_addr[7] = phy_no;
1155                 memcpy(sas_phy->attached_sas_addr,
1156                        attached_sas_addr,
1157                        SAS_ADDR_SIZE);
1158                 memcpy(sas_phy->frame_rcvd, fis,
1159                        sizeof(struct dev_to_host_fis));
1160                 phy->phy_type |= PORT_TYPE_SATA;
1161                 phy->identify.device_type = SAS_SATA_DEV;
1162                 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1163                 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1164         } else {
1165                 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1166                 struct sas_identify_frame *id =
1167                         (struct sas_identify_frame *)frame_rcvd;
1168
1169                 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1170                 for (i = 0; i < 6; i++) {
1171                         u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1172                                                RX_IDAF_DWORD0 + (i * 4));
1173                         frame_rcvd[i] = __swab32(idaf);
1174                 }
1175                 sas_phy->oob_mode = SAS_OOB_MODE;
1176                 memcpy(sas_phy->attached_sas_addr,
1177                        &id->sas_addr,
1178                        SAS_ADDR_SIZE);
1179                 phy->phy_type |= PORT_TYPE_SAS;
1180                 phy->identify.device_type = id->dev_type;
1181                 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1182                 if (phy->identify.device_type == SAS_END_DEVICE)
1183                         phy->identify.target_port_protocols =
1184                                 SAS_PROTOCOL_SSP;
1185                 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1186                         phy->identify.target_port_protocols =
1187                                 SAS_PROTOCOL_SMP;
1188         }
1189
1190         phy->port_id = port_id;
1191         phy->phy_attached = 1;
1192         queue_work(hisi_hba->wq, &phy->phyup_ws);
1193
1194 end:
1195         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1196                              CHL_INT0_SL_PHY_ENABLE_MSK);
1197         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1198
1199         return res;
1200 }
1201
1202 static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1203 {
1204         u32 phy_state, sl_ctrl, txid_auto;
1205         struct device *dev = hisi_hba->dev;
1206
1207         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1208
1209         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1210         dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1211         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1212
1213         sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1214         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1215                                                 sl_ctrl&(~SL_CTA_MSK));
1216
1217         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1218         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1219                                                 txid_auto | CT3_MSK);
1220
1221         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1222         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1223
1224         return 0;
1225 }
1226
1227 static void phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1228 {
1229         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1230         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1231         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1232
1233         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1234         sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1235         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1236                              CHL_INT0_SL_RX_BCST_ACK_MSK);
1237         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1238 }
1239
1240 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1241 {
1242         struct hisi_hba *hisi_hba = p;
1243         u32 irq_msk;
1244         int phy_no = 0;
1245         irqreturn_t res = IRQ_NONE;
1246
1247         irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1248                                 & 0x11111111;
1249         while (irq_msk) {
1250                 if (irq_msk  & 1) {
1251                         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1252                                                             CHL_INT0);
1253                         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1254                         int rdy = phy_state & (1 << phy_no);
1255
1256                         if (rdy) {
1257                                 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1258                                         /* phy up */
1259                                         if (phy_up_v3_hw(phy_no, hisi_hba)
1260                                                         == IRQ_HANDLED)
1261                                                 res = IRQ_HANDLED;
1262                                 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1263                                         /* phy bcast */
1264                                         phy_bcast_v3_hw(phy_no, hisi_hba);
1265                         } else {
1266                                 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1267                                         /* phy down */
1268                                         if (phy_down_v3_hw(phy_no, hisi_hba)
1269                                                         == IRQ_HANDLED)
1270                                                 res = IRQ_HANDLED;
1271                         }
1272                 }
1273                 irq_msk >>= 4;
1274                 phy_no++;
1275         }
1276
1277         return res;
1278 }
1279
1280 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1281 {
1282         struct hisi_hba *hisi_hba = p;
1283         struct device *dev = hisi_hba->dev;
1284         u32 ent_msk, ent_tmp, irq_msk;
1285         int phy_no = 0;
1286
1287         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1288         ent_tmp = ent_msk;
1289         ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1290         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1291
1292         irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1293                                 & 0xeeeeeeee;
1294
1295         while (irq_msk) {
1296                 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1297                                                      CHL_INT0);
1298                 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1299                                                      CHL_INT1);
1300                 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1301                                                      CHL_INT2);
1302
1303                 if ((irq_msk & (4 << (phy_no * 4))) &&
1304                                                 irq_value1) {
1305                         if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
1306                                           CHL_INT1_DMAC_TX_ECC_ERR_MSK))
1307                                 panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
1308                                         dev_name(dev), irq_value1);
1309
1310                         hisi_sas_phy_write32(hisi_hba, phy_no,
1311                                              CHL_INT1, irq_value1);
1312                 }
1313
1314                 if (irq_msk & (8 << (phy_no * 4)) && irq_value2)
1315                         hisi_sas_phy_write32(hisi_hba, phy_no,
1316                                              CHL_INT2, irq_value2);
1317
1318
1319                 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1320                         hisi_sas_phy_write32(hisi_hba, phy_no,
1321                                         CHL_INT0, irq_value0
1322                                         & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1323                                         & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1324                                         & (~CHL_INT0_NOT_RDY_MSK));
1325                 }
1326                 irq_msk &= ~(0xe << (phy_no * 4));
1327                 phy_no++;
1328         }
1329
1330         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1331
1332         return IRQ_HANDLED;
1333 }
1334
1335 static void
1336 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1337                struct hisi_sas_slot *slot)
1338 {
1339         struct task_status_struct *ts = &task->task_status;
1340         struct hisi_sas_complete_v3_hdr *complete_queue =
1341                         hisi_hba->complete_hdr[slot->cmplt_queue];
1342         struct hisi_sas_complete_v3_hdr *complete_hdr =
1343                         &complete_queue[slot->cmplt_queue_slot];
1344         struct hisi_sas_err_record_v3 *record =
1345                         hisi_sas_status_buf_addr_mem(slot);
1346         u32 dma_rx_err_type = record->dma_rx_err_type;
1347         u32 trans_tx_fail_type = record->trans_tx_fail_type;
1348
1349         switch (task->task_proto) {
1350         case SAS_PROTOCOL_SSP:
1351                 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1352                         ts->residual = trans_tx_fail_type;
1353                         ts->stat = SAS_DATA_UNDERRUN;
1354                 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1355                         ts->stat = SAS_QUEUE_FULL;
1356                         slot->abort = 1;
1357                 } else {
1358                         ts->stat = SAS_OPEN_REJECT;
1359                         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1360                 }
1361                 break;
1362         case SAS_PROTOCOL_SATA:
1363         case SAS_PROTOCOL_STP:
1364         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1365                 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1366                         ts->residual = trans_tx_fail_type;
1367                         ts->stat = SAS_DATA_UNDERRUN;
1368                 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1369                         ts->stat = SAS_PHY_DOWN;
1370                         slot->abort = 1;
1371                 } else {
1372                         ts->stat = SAS_OPEN_REJECT;
1373                         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1374                 }
1375                 hisi_sas_sata_done(task, slot);
1376                 break;
1377         case SAS_PROTOCOL_SMP:
1378                 ts->stat = SAM_STAT_CHECK_CONDITION;
1379                 break;
1380         default:
1381                 break;
1382         }
1383 }
1384
1385 static int
1386 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1387 {
1388         struct sas_task *task = slot->task;
1389         struct hisi_sas_device *sas_dev;
1390         struct device *dev = hisi_hba->dev;
1391         struct task_status_struct *ts;
1392         struct domain_device *device;
1393         enum exec_status sts;
1394         struct hisi_sas_complete_v3_hdr *complete_queue =
1395                         hisi_hba->complete_hdr[slot->cmplt_queue];
1396         struct hisi_sas_complete_v3_hdr *complete_hdr =
1397                         &complete_queue[slot->cmplt_queue_slot];
1398         int aborted;
1399         unsigned long flags;
1400
1401         if (unlikely(!task || !task->lldd_task || !task->dev))
1402                 return -EINVAL;
1403
1404         ts = &task->task_status;
1405         device = task->dev;
1406         sas_dev = device->lldd_dev;
1407
1408         spin_lock_irqsave(&task->task_state_lock, flags);
1409         aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1410         task->task_state_flags &=
1411                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1412         spin_unlock_irqrestore(&task->task_state_lock, flags);
1413
1414         memset(ts, 0, sizeof(*ts));
1415         ts->resp = SAS_TASK_COMPLETE;
1416         if (unlikely(aborted)) {
1417                 ts->stat = SAS_ABORTED_TASK;
1418                 hisi_sas_slot_task_free(hisi_hba, task, slot);
1419                 return -1;
1420         }
1421
1422         if (unlikely(!sas_dev)) {
1423                 dev_dbg(dev, "slot complete: port has not device\n");
1424                 ts->stat = SAS_PHY_DOWN;
1425                 goto out;
1426         }
1427
1428         /*
1429          * Use SAS+TMF status codes
1430          */
1431         switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1432                         >> CMPLT_HDR_ABORT_STAT_OFF) {
1433         case STAT_IO_ABORTED:
1434                 /* this IO has been aborted by abort command */
1435                 ts->stat = SAS_ABORTED_TASK;
1436                 goto out;
1437         case STAT_IO_COMPLETE:
1438                 /* internal abort command complete */
1439                 ts->stat = TMF_RESP_FUNC_SUCC;
1440                 goto out;
1441         case STAT_IO_NO_DEVICE:
1442                 ts->stat = TMF_RESP_FUNC_COMPLETE;
1443                 goto out;
1444         case STAT_IO_NOT_VALID:
1445                 /*
1446                  * abort single IO, the controller can't find the IO
1447                  */
1448                 ts->stat = TMF_RESP_FUNC_FAILED;
1449                 goto out;
1450         default:
1451                 break;
1452         }
1453
1454         /* check for erroneous completion */
1455         if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1456                 slot_err_v3_hw(hisi_hba, task, slot);
1457                 if (unlikely(slot->abort))
1458                         return ts->stat;
1459                 goto out;
1460         }
1461
1462         switch (task->task_proto) {
1463         case SAS_PROTOCOL_SSP: {
1464                 struct ssp_response_iu *iu =
1465                         hisi_sas_status_buf_addr_mem(slot) +
1466                         sizeof(struct hisi_sas_err_record);
1467
1468                 sas_ssp_task_response(dev, task, iu);
1469                 break;
1470         }
1471         case SAS_PROTOCOL_SMP: {
1472                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1473                 void *to;
1474
1475                 ts->stat = SAM_STAT_GOOD;
1476                 to = kmap_atomic(sg_page(sg_resp));
1477
1478                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1479                              DMA_FROM_DEVICE);
1480                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1481                              DMA_TO_DEVICE);
1482                 memcpy(to + sg_resp->offset,
1483                         hisi_sas_status_buf_addr_mem(slot) +
1484                        sizeof(struct hisi_sas_err_record),
1485                        sg_dma_len(sg_resp));
1486                 kunmap_atomic(to);
1487                 break;
1488         }
1489         case SAS_PROTOCOL_SATA:
1490         case SAS_PROTOCOL_STP:
1491         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1492                 ts->stat = SAM_STAT_GOOD;
1493                 hisi_sas_sata_done(task, slot);
1494                 break;
1495         default:
1496                 ts->stat = SAM_STAT_CHECK_CONDITION;
1497                 break;
1498         }
1499
1500         if (!slot->port->port_attached) {
1501                 dev_err(dev, "slot complete: port %d has removed\n",
1502                         slot->port->sas_port.id);
1503                 ts->stat = SAS_PHY_DOWN;
1504         }
1505
1506 out:
1507         spin_lock_irqsave(&task->task_state_lock, flags);
1508         task->task_state_flags |= SAS_TASK_STATE_DONE;
1509         spin_unlock_irqrestore(&task->task_state_lock, flags);
1510         spin_lock_irqsave(&hisi_hba->lock, flags);
1511         hisi_sas_slot_task_free(hisi_hba, task, slot);
1512         spin_unlock_irqrestore(&hisi_hba->lock, flags);
1513         sts = ts->stat;
1514
1515         if (task->task_done)
1516                 task->task_done(task);
1517
1518         return sts;
1519 }
1520
1521 static void cq_tasklet_v3_hw(unsigned long val)
1522 {
1523         struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1524         struct hisi_hba *hisi_hba = cq->hisi_hba;
1525         struct hisi_sas_slot *slot;
1526         struct hisi_sas_itct *itct;
1527         struct hisi_sas_complete_v3_hdr *complete_queue;
1528         u32 rd_point = cq->rd_point, wr_point, dev_id;
1529         int queue = cq->id;
1530         struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
1531
1532         complete_queue = hisi_hba->complete_hdr[queue];
1533
1534         spin_lock(&dq->lock);
1535         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1536                                    (0x14 * queue));
1537
1538         while (rd_point != wr_point) {
1539                 struct hisi_sas_complete_v3_hdr *complete_hdr;
1540                 int iptt;
1541
1542                 complete_hdr = &complete_queue[rd_point];
1543
1544                 /* Check for NCQ completion */
1545                 if (complete_hdr->act) {
1546                         u32 act_tmp = complete_hdr->act;
1547                         int ncq_tag_count = ffs(act_tmp);
1548
1549                         dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
1550                                  CMPLT_HDR_DEV_ID_OFF;
1551                         itct = &hisi_hba->itct[dev_id];
1552
1553                         /* The NCQ tags are held in the itct header */
1554                         while (ncq_tag_count) {
1555                                 __le64 *ncq_tag = &itct->qw4_15[0];
1556
1557                                 ncq_tag_count -= 1;
1558                                 iptt = (ncq_tag[ncq_tag_count / 5]
1559                                         >> (ncq_tag_count % 5) * 12) & 0xfff;
1560
1561                                 slot = &hisi_hba->slot_info[iptt];
1562                                 slot->cmplt_queue_slot = rd_point;
1563                                 slot->cmplt_queue = queue;
1564                                 slot_complete_v3_hw(hisi_hba, slot);
1565
1566                                 act_tmp &= ~(1 << ncq_tag_count);
1567                                 ncq_tag_count = ffs(act_tmp);
1568                         }
1569                 } else {
1570                         iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1571                         slot = &hisi_hba->slot_info[iptt];
1572                         slot->cmplt_queue_slot = rd_point;
1573                         slot->cmplt_queue = queue;
1574                         slot_complete_v3_hw(hisi_hba, slot);
1575                 }
1576
1577                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1578                         rd_point = 0;
1579         }
1580
1581         /* update rd_point */
1582         cq->rd_point = rd_point;
1583         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1584         spin_unlock(&dq->lock);
1585 }
1586
1587 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1588 {
1589         struct hisi_sas_cq *cq = p;
1590         struct hisi_hba *hisi_hba = cq->hisi_hba;
1591         int queue = cq->id;
1592
1593         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1594
1595         tasklet_schedule(&cq->tasklet);
1596
1597         return IRQ_HANDLED;
1598 }
1599
1600 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1601 {
1602         struct device *dev = hisi_hba->dev;
1603         struct pci_dev *pdev = hisi_hba->pci_dev;
1604         int vectors, rc;
1605         int i, k;
1606         int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1607
1608         vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1609                                         max_msi, PCI_IRQ_MSI);
1610         if (vectors < max_msi) {
1611                 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1612                 return -ENOENT;
1613         }
1614
1615         rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1616                               int_phy_up_down_bcast_v3_hw, 0,
1617                               DRV_NAME " phy", hisi_hba);
1618         if (rc) {
1619                 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1620                 rc = -ENOENT;
1621                 goto free_irq_vectors;
1622         }
1623
1624         rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1625                               int_chnl_int_v3_hw, 0,
1626                               DRV_NAME " channel", hisi_hba);
1627         if (rc) {
1628                 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1629                 rc = -ENOENT;
1630                 goto free_phy_irq;
1631         }
1632
1633         /* Init tasklets for cq only */
1634         for (i = 0; i < hisi_hba->queue_count; i++) {
1635                 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1636                 struct tasklet_struct *t = &cq->tasklet;
1637
1638                 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1639                                           cq_interrupt_v3_hw, 0,
1640                                           DRV_NAME " cq", cq);
1641                 if (rc) {
1642                         dev_err(dev,
1643                                 "could not request cq%d interrupt, rc=%d\n",
1644                                 i, rc);
1645                         rc = -ENOENT;
1646                         goto free_cq_irqs;
1647                 }
1648
1649                 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1650         }
1651
1652         return 0;
1653
1654 free_cq_irqs:
1655         for (k = 0; k < i; k++) {
1656                 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1657
1658                 free_irq(pci_irq_vector(pdev, k+16), cq);
1659         }
1660         free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1661 free_phy_irq:
1662         free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1663 free_irq_vectors:
1664         pci_free_irq_vectors(pdev);
1665         return rc;
1666 }
1667
1668 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1669 {
1670         int rc;
1671
1672         rc = hw_init_v3_hw(hisi_hba);
1673         if (rc)
1674                 return rc;
1675
1676         rc = interrupt_init_v3_hw(hisi_hba);
1677         if (rc)
1678                 return rc;
1679
1680         return 0;
1681 }
1682
1683 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1684                 struct sas_phy_linkrates *r)
1685 {
1686         u32 prog_phy_link_rate =
1687                 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1688         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1689         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1690         int i;
1691         enum sas_linkrate min, max;
1692         u32 rate_mask = 0;
1693
1694         if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1695                 max = sas_phy->phy->maximum_linkrate;
1696                 min = r->minimum_linkrate;
1697         } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1698                 max = r->maximum_linkrate;
1699                 min = sas_phy->phy->minimum_linkrate;
1700         } else
1701                 return;
1702
1703         sas_phy->phy->maximum_linkrate = max;
1704         sas_phy->phy->minimum_linkrate = min;
1705
1706         min -= SAS_LINK_RATE_1_5_GBPS;
1707         max -= SAS_LINK_RATE_1_5_GBPS;
1708
1709         for (i = 0; i <= max; i++)
1710                 rate_mask |= 1 << (i * 2);
1711
1712         prog_phy_link_rate &= ~0xff;
1713         prog_phy_link_rate |= rate_mask;
1714
1715         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1716                         prog_phy_link_rate);
1717
1718         phy_hard_reset_v3_hw(hisi_hba, phy_no);
1719 }
1720
1721 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1722 {
1723         struct pci_dev *pdev = hisi_hba->pci_dev;
1724         int i;
1725
1726         synchronize_irq(pci_irq_vector(pdev, 1));
1727         synchronize_irq(pci_irq_vector(pdev, 2));
1728         synchronize_irq(pci_irq_vector(pdev, 11));
1729         for (i = 0; i < hisi_hba->queue_count; i++) {
1730                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1731                 synchronize_irq(pci_irq_vector(pdev, i + 16));
1732         }
1733
1734         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1735         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1736         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1737         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1738
1739         for (i = 0; i < hisi_hba->n_phy; i++) {
1740                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1741                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1742                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1743                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1744                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1745         }
1746 }
1747
1748 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1749 {
1750         return hisi_sas_read32(hisi_hba, PHY_STATE);
1751 }
1752
1753 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
1754 {
1755         struct device *dev = hisi_hba->dev;
1756         int rc;
1757         u32 status;
1758
1759         interrupt_disable_v3_hw(hisi_hba);
1760         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
1761
1762         hisi_sas_stop_phys(hisi_hba);
1763
1764         mdelay(10);
1765
1766         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
1767
1768         /* wait until bus idle */
1769         rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
1770                 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
1771         if (rc) {
1772                 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
1773                 return rc;
1774         }
1775
1776         hisi_sas_init_mem(hisi_hba);
1777
1778         return hw_init_v3_hw(hisi_hba);
1779 }
1780
1781 static const struct hisi_sas_hw hisi_sas_v3_hw = {
1782         .hw_init = hisi_sas_v3_init,
1783         .setup_itct = setup_itct_v3_hw,
1784         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
1785         .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
1786         .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
1787         .free_device = free_device_v3_hw,
1788         .sl_notify = sl_notify_v3_hw,
1789         .prep_ssp = prep_ssp_v3_hw,
1790         .prep_smp = prep_smp_v3_hw,
1791         .prep_stp = prep_ata_v3_hw,
1792         .prep_abort = prep_abort_v3_hw,
1793         .get_free_slot = get_free_slot_v3_hw,
1794         .start_delivery = start_delivery_v3_hw,
1795         .slot_complete = slot_complete_v3_hw,
1796         .phys_init = phys_init_v3_hw,
1797         .phy_enable = enable_phy_v3_hw,
1798         .phy_disable = disable_phy_v3_hw,
1799         .phy_hard_reset = phy_hard_reset_v3_hw,
1800         .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
1801         .phy_set_linkrate = phy_set_linkrate_v3_hw,
1802         .dereg_device = dereg_device_v3_hw,
1803         .soft_reset = soft_reset_v3_hw,
1804         .get_phys_state = get_phys_state_v3_hw,
1805 };
1806
1807 static struct Scsi_Host *
1808 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
1809 {
1810         struct Scsi_Host *shost;
1811         struct hisi_hba *hisi_hba;
1812         struct device *dev = &pdev->dev;
1813
1814         shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
1815         if (!shost) {
1816                 dev_err(dev, "shost alloc failed\n");
1817                 return NULL;
1818         }
1819         hisi_hba = shost_priv(shost);
1820
1821         hisi_hba->hw = &hisi_sas_v3_hw;
1822         hisi_hba->pci_dev = pdev;
1823         hisi_hba->dev = dev;
1824         hisi_hba->shost = shost;
1825         SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
1826
1827         init_timer(&hisi_hba->timer);
1828
1829         if (hisi_sas_get_fw_info(hisi_hba) < 0)
1830                 goto err_out;
1831
1832         if (hisi_sas_alloc(hisi_hba, shost)) {
1833                 hisi_sas_free(hisi_hba);
1834                 goto err_out;
1835         }
1836
1837         return shost;
1838 err_out:
1839         scsi_host_put(shost);
1840         dev_err(dev, "shost alloc failed\n");
1841         return NULL;
1842 }
1843
1844 static int
1845 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1846 {
1847         struct Scsi_Host *shost;
1848         struct hisi_hba *hisi_hba;
1849         struct device *dev = &pdev->dev;
1850         struct asd_sas_phy **arr_phy;
1851         struct asd_sas_port **arr_port;
1852         struct sas_ha_struct *sha;
1853         int rc, phy_nr, port_nr, i;
1854
1855         rc = pci_enable_device(pdev);
1856         if (rc)
1857                 goto err_out;
1858
1859         pci_set_master(pdev);
1860
1861         rc = pci_request_regions(pdev, DRV_NAME);
1862         if (rc)
1863                 goto err_out_disable_device;
1864
1865         if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
1866             (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
1867                 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
1868                    (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
1869                         dev_err(dev, "No usable DMA addressing method\n");
1870                         rc = -EIO;
1871                         goto err_out_regions;
1872                 }
1873         }
1874
1875         shost = hisi_sas_shost_alloc_pci(pdev);
1876         if (!shost) {
1877                 rc = -ENOMEM;
1878                 goto err_out_regions;
1879         }
1880
1881         sha = SHOST_TO_SAS_HA(shost);
1882         hisi_hba = shost_priv(shost);
1883         dev_set_drvdata(dev, sha);
1884
1885         hisi_hba->regs = pcim_iomap(pdev, 5, 0);
1886         if (!hisi_hba->regs) {
1887                 dev_err(dev, "cannot map register.\n");
1888                 rc = -ENOMEM;
1889                 goto err_out_ha;
1890         }
1891
1892         phy_nr = port_nr = hisi_hba->n_phy;
1893
1894         arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
1895         arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
1896         if (!arr_phy || !arr_port) {
1897                 rc = -ENOMEM;
1898                 goto err_out_ha;
1899         }
1900
1901         sha->sas_phy = arr_phy;
1902         sha->sas_port = arr_port;
1903         sha->core.shost = shost;
1904         sha->lldd_ha = hisi_hba;
1905
1906         shost->transportt = hisi_sas_stt;
1907         shost->max_id = HISI_SAS_MAX_DEVICES;
1908         shost->max_lun = ~0;
1909         shost->max_channel = 1;
1910         shost->max_cmd_len = 16;
1911         shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
1912         shost->can_queue = hisi_hba->hw->max_command_entries;
1913         shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
1914
1915         sha->sas_ha_name = DRV_NAME;
1916         sha->dev = dev;
1917         sha->lldd_module = THIS_MODULE;
1918         sha->sas_addr = &hisi_hba->sas_addr[0];
1919         sha->num_phys = hisi_hba->n_phy;
1920         sha->core.shost = hisi_hba->shost;
1921
1922         for (i = 0; i < hisi_hba->n_phy; i++) {
1923                 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
1924                 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
1925         }
1926
1927         hisi_sas_init_add(hisi_hba);
1928
1929         rc = scsi_add_host(shost, dev);
1930         if (rc)
1931                 goto err_out_ha;
1932
1933         rc = sas_register_ha(sha);
1934         if (rc)
1935                 goto err_out_register_ha;
1936
1937         rc = hisi_hba->hw->hw_init(hisi_hba);
1938         if (rc)
1939                 goto err_out_register_ha;
1940
1941         scsi_scan_host(shost);
1942
1943         return 0;
1944
1945 err_out_register_ha:
1946         scsi_remove_host(shost);
1947 err_out_ha:
1948         scsi_host_put(shost);
1949 err_out_regions:
1950         pci_release_regions(pdev);
1951 err_out_disable_device:
1952         pci_disable_device(pdev);
1953 err_out:
1954         return rc;
1955 }
1956
1957 static void
1958 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
1959 {
1960         int i;
1961
1962         free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1963         free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1964         for (i = 0; i < hisi_hba->queue_count; i++) {
1965                 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1966
1967                 free_irq(pci_irq_vector(pdev, i+16), cq);
1968                 tasklet_kill(&cq->tasklet);
1969         }
1970         pci_free_irq_vectors(pdev);
1971 }
1972
1973 static void hisi_sas_v3_remove(struct pci_dev *pdev)
1974 {
1975         struct device *dev = &pdev->dev;
1976         struct sas_ha_struct *sha = dev_get_drvdata(dev);
1977         struct hisi_hba *hisi_hba = sha->lldd_ha;
1978         struct Scsi_Host *shost = sha->core.shost;
1979
1980         sas_unregister_ha(sha);
1981         sas_remove_host(sha->core.shost);
1982
1983         hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
1984         pci_release_regions(pdev);
1985         pci_disable_device(pdev);
1986         hisi_sas_free(hisi_hba);
1987         scsi_host_put(shost);
1988 }
1989
1990 enum {
1991         /* instances of the controller */
1992         hip08,
1993 };
1994
1995 static const struct pci_device_id sas_v3_pci_table[] = {
1996         { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
1997         {}
1998 };
1999
2000 static struct pci_driver sas_v3_pci_driver = {
2001         .name           = DRV_NAME,
2002         .id_table       = sas_v3_pci_table,
2003         .probe          = hisi_sas_v3_probe,
2004         .remove         = hisi_sas_v3_remove,
2005 };
2006
2007 module_pci_driver(sas_v3_pci_driver);
2008
2009 MODULE_LICENSE("GPL");
2010 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2011 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2012 MODULE_ALIAS("platform:" DRV_NAME);