drivers/scsi/megaraid/megaraid_sas_fusion.h

   1 /*
   2  *  Linux MegaRAID driver for SAS based RAID controllers
   3  *
   4  *  Copyright (c) 2009-2013  LSI Corporation
   5  *  Copyright (c) 2013-2014  Avago Technologies
   6  *
   7  *  This program is free software; you can redistribute it and/or
   8  *  modify it under the terms of the GNU General Public License
   9  *  as published by the Free Software Foundation; either version 2
  10  *  of the License, or (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  FILE: megaraid_sas_fusion.h
  21  *
  22  *  Authors: Avago Technologies
  23  *           Manoj Jose
  24  *           Sumant Patro
  25  *           Kashyap Desai <kashyap.desai@avagotech.com>
  26  *           Sumit Saxena <sumit.saxena@avagotech.com>
  27  *
  28  *  Send feedback to: megaraidlinux.pdl@avagotech.com
  29  *
  30  *  Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
  31  *  San Jose, California 95131
  32  */
  33
  34 #ifndef _MEGARAID_SAS_FUSION_H_
  35 #define _MEGARAID_SAS_FUSION_H_
  36
  37 /* Fusion defines */
  38 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
  39 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
  40 #define MEGASAS_MAX_CHAIN_SHIFT                 5
  41 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK       0x400000
  42 #define MEGASAS_MAX_CHAIN_SIZE_MASK             0x3E0
  43 #define MEGASAS_256K_IO                         128
  44 #define MEGASAS_1MB_IO                          (MEGASAS_256K_IO * 4)
  45 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
  46 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST   0xF0
  47 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST         0xF1
  48 #define MEGASAS_LOAD_BALANCE_FLAG                   0x1
  49 #define MEGASAS_DCMD_MBOX_PEND_FLAG                 0x1
  50 #define HOST_DIAG_WRITE_ENABLE                      0x80
  51 #define HOST_DIAG_RESET_ADAPTER                     0x4
  52 #define MEGASAS_FUSION_MAX_RESET_TRIES              3
  53 #define MAX_MSIX_QUEUES_FUSION                      128
  54
  55 /* Invader defines */
  56 #define MPI2_TYPE_CUDA                              0x2
  57 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH   0x4000
  58 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0          0x00
  59 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1          0x10
  60 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA          0x80
  61 #define MR_RL_FLAGS_SEQ_NUM_ENABLE                  0x8
  62
  63 /* T10 PI defines */
  64 #define MR_PROT_INFO_TYPE_CONTROLLER                0x8
  65 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD            0x7f
  66 #define MEGASAS_SCSI_SERVICE_ACTION_READ32          0x9
  67 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32         0xB
  68 #define MEGASAS_SCSI_ADDL_CDB_LEN                   0x18
  69 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL             0x20
  70 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE            0x60
  71
  72 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET   (0x0000030C)
  73 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET       (0x0000006C)
  74
  75 /*
  76  * Raid context flags
  77  */
  78
  79 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT   0x4
  80 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK    0x30
  81 enum MR_RAID_FLAGS_IO_SUB_TYPE {
  82         MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
  83         MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
  84 };
  85
  86 /*
  87  * Request descriptor types
  88  */
  89 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO           0x7
  90 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA             0x1
  91 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK         0x2
  92 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT      1
  93
  94 #define MEGASAS_FP_CMD_LEN      16
  95 #define MEGASAS_FUSION_IN_RESET 0
  96 #define MEGASAS_FUSION_OCR_NOT_POSSIBLE 1
  97 #define THRESHOLD_REPLY_COUNT 50
  98 #define JBOD_MAPS_COUNT 2
  99
 100 enum MR_FUSION_ADAPTER_TYPE {
 101         THUNDERBOLT_SERIES = 0,
 102         INVADER_SERIES = 1,
 103 };
 104
 105 /*
 106  * Raid Context structure which describes MegaRAID specific IO Parameters
 107  * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
 108  */
 109
 110 struct RAID_CONTEXT {
 111 #if   defined(__BIG_ENDIAN_BITFIELD)
 112         u8      nseg:4;
 113         u8      Type:4;
 114 #else
 115         u8      Type:4;
 116         u8      nseg:4;
 117 #endif
 118         u8      resvd0;
 119         __le16  timeoutValue;
 120         u8      regLockFlags;
 121         u8      resvd1;
 122         __le16  VirtualDiskTgtId;
 123         __le64  regLockRowLBA;
 124         __le32  regLockLength;
 125         __le16  nextLMId;
 126         u8      exStatus;
 127         u8      status;
 128         u8      RAIDFlags;
 129         u8      numSGE;
 130         __le16  configSeqNum;
 131         u8      spanArm;
 132         u8      priority;
 133         u8      numSGEExt;
 134         u8      resvd2;
 135 };
 136
 137 #define RAID_CTX_SPANARM_ARM_SHIFT      (0)
 138 #define RAID_CTX_SPANARM_ARM_MASK       (0x1f)
 139
 140 #define RAID_CTX_SPANARM_SPAN_SHIFT     (5)
 141 #define RAID_CTX_SPANARM_SPAN_MASK      (0xE0)
 142
 143 /*
 144  * define region lock types
 145  */
 146 enum REGION_TYPE {
 147         REGION_TYPE_UNUSED       = 0,
 148         REGION_TYPE_SHARED_READ  = 1,
 149         REGION_TYPE_SHARED_WRITE = 2,
 150         REGION_TYPE_EXCLUSIVE    = 3,
 151 };
 152
 153 /* MPI2 defines */
 154 #define MPI2_FUNCTION_IOC_INIT              (0x02) /* IOC Init */
 155 #define MPI2_WHOINIT_HOST_DRIVER            (0x04)
 156 #define MPI2_VERSION_MAJOR                  (0x02)
 157 #define MPI2_VERSION_MINOR                  (0x00)
 158 #define MPI2_VERSION_MAJOR_MASK             (0xFF00)
 159 #define MPI2_VERSION_MAJOR_SHIFT            (8)
 160 #define MPI2_VERSION_MINOR_MASK             (0x00FF)
 161 #define MPI2_VERSION_MINOR_SHIFT            (0)
 162 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
 163                       MPI2_VERSION_MINOR)
 164 #define MPI2_HEADER_VERSION_UNIT            (0x10)
 165 #define MPI2_HEADER_VERSION_DEV             (0x00)
 166 #define MPI2_HEADER_VERSION_UNIT_MASK       (0xFF00)
 167 #define MPI2_HEADER_VERSION_UNIT_SHIFT      (8)
 168 #define MPI2_HEADER_VERSION_DEV_MASK        (0x00FF)
 169 #define MPI2_HEADER_VERSION_DEV_SHIFT       (0)
 170 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
 171                              MPI2_HEADER_VERSION_DEV)
 172 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR      (0x03)
 173 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG        (0x8000)
 174 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG          (0x0400)
 175 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP       (0x0003)
 176 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG          (0x0200)
 177 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD           (0x0100)
 178 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP             (0x0004)
 179 #define MPI2_FUNCTION_SCSI_IO_REQUEST               (0x00) /* SCSI IO */
 180 #define MPI2_FUNCTION_SCSI_TASK_MGMT                (0x01)
 181 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY       (0x03)
 182 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO               (0x06)
 183 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 184 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING        (0x02)
 185 #define MPI2_SCSIIO_CONTROL_WRITE               (0x01000000)
 186 #define MPI2_SCSIIO_CONTROL_READ                (0x02000000)
 187 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK       (0x0E)
 188 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED          (0x0F)
 189 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
 190 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK       (0x0F)
 191 #define MPI2_WRSEQ_FLUSH_KEY_VALUE              (0x0)
 192 #define MPI2_WRITE_SEQUENCE_OFFSET              (0x00000004)
 193 #define MPI2_WRSEQ_1ST_KEY_VALUE                (0xF)
 194 #define MPI2_WRSEQ_2ND_KEY_VALUE                (0x4)
 195 #define MPI2_WRSEQ_3RD_KEY_VALUE                (0xB)
 196 #define MPI2_WRSEQ_4TH_KEY_VALUE                (0x2)
 197 #define MPI2_WRSEQ_5TH_KEY_VALUE                (0x7)
 198 #define MPI2_WRSEQ_6TH_KEY_VALUE                (0xD)
 199
 200 struct MPI25_IEEE_SGE_CHAIN64 {
 201         __le64                  Address;
 202         __le32                  Length;
 203         __le16                  Reserved1;
 204         u8                      NextChainOffset;
 205         u8                      Flags;
 206 };
 207
 208 struct MPI2_SGE_SIMPLE_UNION {
 209         __le32                     FlagsLength;
 210         union {
 211                 __le32                 Address32;
 212                 __le64                 Address64;
 213         } u;
 214 };
 215
 216 struct MPI2_SCSI_IO_CDB_EEDP32 {
 217         u8                      CDB[20];                    /* 0x00 */
 218         __be32                  PrimaryReferenceTag;        /* 0x14 */
 219         __be16                  PrimaryApplicationTag;      /* 0x18 */
 220         __be16                  PrimaryApplicationTagMask;  /* 0x1A */
 221         __le32                  TransferLength;             /* 0x1C */
 222 };
 223
 224 struct MPI2_SGE_CHAIN_UNION {
 225         __le16                  Length;
 226         u8                      NextChainOffset;
 227         u8                      Flags;
 228         union {
 229                 __le32          Address32;
 230                 __le64          Address64;
 231         } u;
 232 };
 233
 234 struct MPI2_IEEE_SGE_SIMPLE32 {
 235         __le32                  Address;
 236         __le32                  FlagsLength;
 237 };
 238
 239 struct MPI2_IEEE_SGE_CHAIN32 {
 240         __le32                  Address;
 241         __le32                  FlagsLength;
 242 };
 243
 244 struct MPI2_IEEE_SGE_SIMPLE64 {
 245         __le64                  Address;
 246         __le32                  Length;
 247         __le16                  Reserved1;
 248         u8                      Reserved2;
 249         u8                      Flags;
 250 };
 251
 252 struct MPI2_IEEE_SGE_CHAIN64 {
 253         __le64                  Address;
 254         __le32                  Length;
 255         __le16                  Reserved1;
 256         u8                      Reserved2;
 257         u8                      Flags;
 258 };
 259
 260 union MPI2_IEEE_SGE_SIMPLE_UNION {
 261         struct MPI2_IEEE_SGE_SIMPLE32  Simple32;
 262         struct MPI2_IEEE_SGE_SIMPLE64  Simple64;
 263 };
 264
 265 union MPI2_IEEE_SGE_CHAIN_UNION {
 266         struct MPI2_IEEE_SGE_CHAIN32   Chain32;
 267         struct MPI2_IEEE_SGE_CHAIN64   Chain64;
 268 };
 269
 270 union MPI2_SGE_IO_UNION {
 271         struct MPI2_SGE_SIMPLE_UNION       MpiSimple;
 272         struct MPI2_SGE_CHAIN_UNION        MpiChain;
 273         union MPI2_IEEE_SGE_SIMPLE_UNION  IeeeSimple;
 274         union MPI2_IEEE_SGE_CHAIN_UNION   IeeeChain;
 275 };
 276
 277 union MPI2_SCSI_IO_CDB_UNION {
 278         u8                      CDB32[32];
 279         struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
 280         struct MPI2_SGE_SIMPLE_UNION SGE;
 281 };
 282
 283 /****************************************************************************
 284 *  SCSI Task Management messages
 285 ****************************************************************************/
 286
 287 /*SCSI Task Management Request Message */
 288 struct MPI2_SCSI_TASK_MANAGE_REQUEST {
 289         u16 DevHandle;          /*0x00 */
 290         u8 ChainOffset;         /*0x02 */
 291         u8 Function;            /*0x03 */
 292         u8 Reserved1;           /*0x04 */
 293         u8 TaskType;            /*0x05 */
 294         u8 Reserved2;           /*0x06 */
 295         u8 MsgFlags;            /*0x07 */
 296         u8 VP_ID;               /*0x08 */
 297         u8 VF_ID;               /*0x09 */
 298         u16 Reserved3;          /*0x0A */
 299         u8 LUN[8];              /*0x0C */
 300         u32 Reserved4[7];       /*0x14 */
 301         u16 TaskMID;            /*0x30 */
 302         u16 Reserved5;          /*0x32 */
 303 };
 304
 305
 306 /*SCSI Task Management Reply Message */
 307 struct MPI2_SCSI_TASK_MANAGE_REPLY {
 308         u16 DevHandle;          /*0x00 */
 309         u8 MsgLength;           /*0x02 */
 310         u8 Function;            /*0x03 */
 311         u8 ResponseCode;        /*0x04 */
 312         u8 TaskType;            /*0x05 */
 313         u8 Reserved1;           /*0x06 */
 314         u8 MsgFlags;            /*0x07 */
 315         u8 VP_ID;               /*0x08 */
 316         u8 VF_ID;               /*0x09 */
 317         u16 Reserved2;          /*0x0A */
 318         u16 Reserved3;          /*0x0C */
 319         u16 IOCStatus;          /*0x0E */
 320         u32 IOCLogInfo;         /*0x10 */
 321         u32 TerminationCount;   /*0x14 */
 322         u32 ResponseInfo;       /*0x18 */
 323 };
 324
 325 struct MR_TM_REQUEST {
 326         char request[128];
 327 };
 328
 329 struct MR_TM_REPLY {
 330         char reply[128];
 331 };
 332
 333 /* SCSI Task Management Request Message */
 334 struct MR_TASK_MANAGE_REQUEST {
 335         /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */
 336         struct MR_TM_REQUEST         TmRequest;
 337         union {
 338                 struct {
 339 #if   defined(__BIG_ENDIAN_BITFIELD)
 340                         u32 reserved1:30;
 341                         u32 isTMForPD:1;
 342                         u32 isTMForLD:1;
 343 #else
 344                         u32 isTMForLD:1;
 345                         u32 isTMForPD:1;
 346                         u32 reserved1:30;
 347 #endif
 348                         u32 reserved2;
 349                 } tmReqFlags;
 350                 struct MR_TM_REPLY   TMReply;
 351         };
 352 };
 353
 354 /* TaskType values */
 355
 356 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK           (0x01)
 357 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET        (0x02)
 358 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET         (0x03)
 359 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET   (0x05)
 360 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET       (0x06)
 361 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK           (0x07)
 362 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA              (0x08)
 363 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET         (0x09)
 364 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT      (0x0A)
 365
 366 /* ResponseCode values */
 367
 368 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE               (0x00)
 369 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME             (0x02)
 370 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED          (0x04)
 371 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED                 (0x05)
 372 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED              (0x08)
 373 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN            (0x09)
 374 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG         (0x0A)
 375 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC          (0x80)
 376
 377 /*
 378  * RAID SCSI IO Request Message
 379  * Total SGE count will be one less than  _MPI2_SCSI_IO_REQUEST
 380  */
 381 struct MPI2_RAID_SCSI_IO_REQUEST {
 382         __le16                  DevHandle;                      /* 0x00 */
 383         u8                      ChainOffset;                    /* 0x02 */
 384         u8                      Function;                       /* 0x03 */
 385         __le16                  Reserved1;                      /* 0x04 */
 386         u8                      Reserved2;                      /* 0x06 */
 387         u8                      MsgFlags;                       /* 0x07 */
 388         u8                      VP_ID;                          /* 0x08 */
 389         u8                      VF_ID;                          /* 0x09 */
 390         __le16                  Reserved3;                      /* 0x0A */
 391         __le32                  SenseBufferLowAddress;          /* 0x0C */
 392         __le16                  SGLFlags;                       /* 0x10 */
 393         u8                      SenseBufferLength;              /* 0x12 */
 394         u8                      Reserved4;                      /* 0x13 */
 395         u8                      SGLOffset0;                     /* 0x14 */
 396         u8                      SGLOffset1;                     /* 0x15 */
 397         u8                      SGLOffset2;                     /* 0x16 */
 398         u8                      SGLOffset3;                     /* 0x17 */
 399         __le32                  SkipCount;                      /* 0x18 */
 400         __le32                  DataLength;                     /* 0x1C */
 401         __le32                  BidirectionalDataLength;        /* 0x20 */
 402         __le16                  IoFlags;                        /* 0x24 */
 403         __le16                  EEDPFlags;                      /* 0x26 */
 404         __le32                  EEDPBlockSize;                  /* 0x28 */
 405         __le32                  SecondaryReferenceTag;          /* 0x2C */
 406         __le16                  SecondaryApplicationTag;        /* 0x30 */
 407         __le16                  ApplicationTagTranslationMask;  /* 0x32 */
 408         u8                      LUN[8];                         /* 0x34 */
 409         __le32                  Control;                        /* 0x3C */
 410         union MPI2_SCSI_IO_CDB_UNION  CDB;                      /* 0x40 */
 411         struct RAID_CONTEXT     RaidContext;                    /* 0x60 */
 412         union MPI2_SGE_IO_UNION       SGL;                      /* 0x80 */
 413 };
 414
 415 /*
 416  * MPT RAID MFA IO Descriptor.
 417  */
 418 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
 419         u32     RequestFlags:8;
 420         u32     MessageAddress1:24;
 421         u32     MessageAddress2;
 422 };
 423
 424 /* Default Request Descriptor */
 425 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
 426         u8              RequestFlags;               /* 0x00 */
 427         u8              MSIxIndex;                  /* 0x01 */
 428         __le16          SMID;                       /* 0x02 */
 429         __le16          LMID;                       /* 0x04 */
 430         __le16          DescriptorTypeDependent;    /* 0x06 */
 431 };
 432
 433 /* High Priority Request Descriptor */
 434 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
 435         u8              RequestFlags;               /* 0x00 */
 436         u8              MSIxIndex;                  /* 0x01 */
 437         __le16          SMID;                       /* 0x02 */
 438         __le16          LMID;                       /* 0x04 */
 439         __le16          Reserved1;                  /* 0x06 */
 440 };
 441
 442 /* SCSI IO Request Descriptor */
 443 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
 444         u8              RequestFlags;               /* 0x00 */
 445         u8              MSIxIndex;                  /* 0x01 */
 446         __le16          SMID;                       /* 0x02 */
 447         __le16          LMID;                       /* 0x04 */
 448         __le16          DevHandle;                  /* 0x06 */
 449 };
 450
 451 /* SCSI Target Request Descriptor */
 452 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
 453         u8              RequestFlags;               /* 0x00 */
 454         u8              MSIxIndex;                  /* 0x01 */
 455         __le16          SMID;                       /* 0x02 */
 456         __le16          LMID;                       /* 0x04 */
 457         __le16          IoIndex;                    /* 0x06 */
 458 };
 459
 460 /* RAID Accelerator Request Descriptor */
 461 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
 462         u8              RequestFlags;               /* 0x00 */
 463         u8              MSIxIndex;                  /* 0x01 */
 464         __le16          SMID;                       /* 0x02 */
 465         __le16          LMID;                       /* 0x04 */
 466         __le16          Reserved;                   /* 0x06 */
 467 };
 468
 469 /* union of Request Descriptors */
 470 union MEGASAS_REQUEST_DESCRIPTOR_UNION {
 471         struct MPI2_DEFAULT_REQUEST_DESCRIPTOR             Default;
 472         struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR       HighPriority;
 473         struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR             SCSIIO;
 474         struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR         SCSITarget;
 475         struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR          RAIDAccelerator;
 476         struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR      MFAIo;
 477         union {
 478                 struct {
 479                         __le32 low;
 480                         __le32 high;
 481                 } u;
 482                 __le64 Words;
 483         };
 484 };
 485
 486 /* Default Reply Descriptor */
 487 struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
 488         u8              ReplyFlags;                 /* 0x00 */
 489         u8              MSIxIndex;                  /* 0x01 */
 490         __le16          DescriptorTypeDependent1;   /* 0x02 */
 491         __le32          DescriptorTypeDependent2;   /* 0x04 */
 492 };
 493
 494 /* Address Reply Descriptor */
 495 struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
 496         u8              ReplyFlags;                 /* 0x00 */
 497         u8              MSIxIndex;                  /* 0x01 */
 498         __le16          SMID;                       /* 0x02 */
 499         __le32          ReplyFrameAddress;          /* 0x04 */
 500 };
 501
 502 /* SCSI IO Success Reply Descriptor */
 503 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
 504         u8              ReplyFlags;                 /* 0x00 */
 505         u8              MSIxIndex;                  /* 0x01 */
 506         __le16          SMID;                       /* 0x02 */
 507         __le16          TaskTag;                    /* 0x04 */
 508         __le16          Reserved1;                  /* 0x06 */
 509 };
 510
 511 /* TargetAssist Success Reply Descriptor */
 512 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
 513         u8              ReplyFlags;                 /* 0x00 */
 514         u8              MSIxIndex;                  /* 0x01 */
 515         __le16          SMID;                       /* 0x02 */
 516         u8              SequenceNumber;             /* 0x04 */
 517         u8              Reserved1;                  /* 0x05 */
 518         __le16          IoIndex;                    /* 0x06 */
 519 };
 520
 521 /* Target Command Buffer Reply Descriptor */
 522 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
 523         u8              ReplyFlags;                 /* 0x00 */
 524         u8              MSIxIndex;                  /* 0x01 */
 525         u8              VP_ID;                      /* 0x02 */
 526         u8              Flags;                      /* 0x03 */
 527         __le16          InitiatorDevHandle;         /* 0x04 */
 528         __le16          IoIndex;                    /* 0x06 */
 529 };
 530
 531 /* RAID Accelerator Success Reply Descriptor */
 532 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
 533         u8              ReplyFlags;                 /* 0x00 */
 534         u8              MSIxIndex;                  /* 0x01 */
 535         __le16          SMID;                       /* 0x02 */
 536         __le32          Reserved;                   /* 0x04 */
 537 };
 538
 539 /* union of Reply Descriptors */
 540 union MPI2_REPLY_DESCRIPTORS_UNION {
 541         struct MPI2_DEFAULT_REPLY_DESCRIPTOR                   Default;
 542         struct MPI2_ADDRESS_REPLY_DESCRIPTOR                   AddressReply;
 543         struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR           SCSIIOSuccess;
 544         struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
 545         struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
 546         struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
 547         RAIDAcceleratorSuccess;
 548         __le64                                             Words;
 549 };
 550
 551 /* IOCInit Request message */
 552 struct MPI2_IOC_INIT_REQUEST {
 553         u8                      WhoInit;                        /* 0x00 */
 554         u8                      Reserved1;                      /* 0x01 */
 555         u8                      ChainOffset;                    /* 0x02 */
 556         u8                      Function;                       /* 0x03 */
 557         __le16                  Reserved2;                      /* 0x04 */
 558         u8                      Reserved3;                      /* 0x06 */
 559         u8                      MsgFlags;                       /* 0x07 */
 560         u8                      VP_ID;                          /* 0x08 */
 561         u8                      VF_ID;                          /* 0x09 */
 562         __le16                  Reserved4;                      /* 0x0A */
 563         __le16                  MsgVersion;                     /* 0x0C */
 564         __le16                  HeaderVersion;                  /* 0x0E */
 565         u32                     Reserved5;                      /* 0x10 */
 566         __le16                  Reserved6;                      /* 0x14 */
 567         u8                      Reserved7;                      /* 0x16 */
 568         u8                      HostMSIxVectors;                /* 0x17 */
 569         __le16                  Reserved8;                      /* 0x18 */
 570         __le16                  SystemRequestFrameSize;         /* 0x1A */
 571         __le16                  ReplyDescriptorPostQueueDepth;  /* 0x1C */
 572         __le16                  ReplyFreeQueueDepth;            /* 0x1E */
 573         __le32                  SenseBufferAddressHigh;         /* 0x20 */
 574         __le32                  SystemReplyAddressHigh;         /* 0x24 */
 575         __le64                  SystemRequestFrameBaseAddress;  /* 0x28 */
 576         __le64                  ReplyDescriptorPostQueueAddress;/* 0x30 */
 577         __le64                  ReplyFreeQueueAddress;          /* 0x38 */
 578         __le64                  TimeStamp;                      /* 0x40 */
 579 };
 580
 581 /* mrpriv defines */
 582 #define MR_PD_INVALID 0xFFFF
 583 #define MAX_SPAN_DEPTH 8
 584 #define MAX_QUAD_DEPTH  MAX_SPAN_DEPTH
 585 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
 586 #define MAX_ROW_SIZE 32
 587 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
 588 #define MAX_LOGICAL_DRIVES 64
 589 #define MAX_LOGICAL_DRIVES_EXT 256
 590 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
 591 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
 592 #define MAX_ARRAYS 128
 593 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
 594 #define MAX_ARRAYS_EXT  256
 595 #define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT)
 596 #define MAX_PHYSICAL_DEVICES 256
 597 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
 598 #define MR_DCMD_LD_MAP_GET_INFO             0x0300e101
 599 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO      0x0200e102
 600 #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC  0x010e8485   /* SR-IOV HB alloc*/
 601 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111   0x03200200
 602 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS       0x03150200
 603
 604 struct MR_DEV_HANDLE_INFO {
 605         __le16  curDevHdl;
 606         u8      validHandles;
 607         u8      reserved;
 608         __le16  devHandle[2];
 609 };
 610
 611 struct MR_ARRAY_INFO {
 612         __le16  pd[MAX_RAIDMAP_ROW_SIZE];
 613 };
 614
 615 struct MR_QUAD_ELEMENT {
 616         __le64     logStart;
 617         __le64     logEnd;
 618         __le64     offsetInSpan;
 619         __le32     diff;
 620         __le32     reserved1;
 621 };
 622
 623 struct MR_SPAN_INFO {
 624         __le32             noElements;
 625         __le32             reserved1;
 626         struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
 627 };
 628
 629 struct MR_LD_SPAN {
 630         __le64   startBlk;
 631         __le64   numBlks;
 632         __le16   arrayRef;
 633         u8       spanRowSize;
 634         u8       spanRowDataSize;
 635         u8       reserved[4];
 636 };
 637
 638 struct MR_SPAN_BLOCK_INFO {
 639         __le64          num_rows;
 640         struct MR_LD_SPAN   span;
 641         struct MR_SPAN_INFO block_span_info;
 642 };
 643
 644 struct MR_LD_RAID {
 645         struct {
 646 #if   defined(__BIG_ENDIAN_BITFIELD)
 647                 u32     reserved4:5;
 648                 u32     fpBypassRegionLock:1;
 649                 u32     tmCapable:1;
 650                 u32     fpNonRWCapable:1;
 651                 u32     fpReadAcrossStripe:1;
 652                 u32     fpWriteAcrossStripe:1;
 653                 u32     fpReadCapable:1;
 654                 u32     fpWriteCapable:1;
 655                 u32     encryptionType:8;
 656                 u32     pdPiMode:4;
 657                 u32     ldPiMode:4;
 658                 u32     reserved5:3;
 659                 u32     fpCapable:1;
 660 #else
 661                 u32     fpCapable:1;
 662                 u32     reserved5:3;
 663                 u32     ldPiMode:4;
 664                 u32     pdPiMode:4;
 665                 u32     encryptionType:8;
 666                 u32     fpWriteCapable:1;
 667                 u32     fpReadCapable:1;
 668                 u32     fpWriteAcrossStripe:1;
 669                 u32     fpReadAcrossStripe:1;
 670                 u32     fpNonRWCapable:1;
 671                 u32     tmCapable:1;
 672                 u32     fpBypassRegionLock:1;
 673                 u32     reserved4:5;
 674 #endif
 675         } capability;
 676         __le32     reserved6;
 677         __le64     size;
 678         u8      spanDepth;
 679         u8      level;
 680         u8      stripeShift;
 681         u8      rowSize;
 682         u8      rowDataSize;
 683         u8      writeMode;
 684         u8      PRL;
 685         u8      SRL;
 686         __le16     targetId;
 687         u8      ldState;
 688         u8      regTypeReqOnWrite;
 689         u8      modFactor;
 690         u8      regTypeReqOnRead;
 691         __le16     seqNum;
 692
 693         struct {
 694                 u32 ldSyncRequired:1;
 695                 u32 reserved:31;
 696         } flags;
 697
 698         u8      LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */
 699         u8      fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/
 700         u8      reserved3[0x80-0x2D]; /* 0x2D */
 701 };
 702
 703 struct MR_LD_SPAN_MAP {
 704         struct MR_LD_RAID          ldRaid;
 705         u8                  dataArmMap[MAX_RAIDMAP_ROW_SIZE];
 706         struct MR_SPAN_BLOCK_INFO  spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
 707 };
 708
 709 struct MR_FW_RAID_MAP {
 710         __le32                 totalSize;
 711         union {
 712                 struct {
 713                         __le32         maxLd;
 714                         __le32         maxSpanDepth;
 715                         __le32         maxRowSize;
 716                         __le32         maxPdCount;
 717                         __le32         maxArrays;
 718                 } validationInfo;
 719                 __le32             version[5];
 720         };
 721
 722         __le32                 ldCount;
 723         __le32                 Reserved1;
 724         u8                  ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
 725                                         MAX_RAIDMAP_VIEWS];
 726         u8                  fpPdIoTimeoutSec;
 727         u8                  reserved2[7];
 728         struct MR_ARRAY_INFO       arMapInfo[MAX_RAIDMAP_ARRAYS];
 729         struct MR_DEV_HANDLE_INFO  devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 730         struct MR_LD_SPAN_MAP      ldSpanMap[1];
 731 };
 732
 733 struct IO_REQUEST_INFO {
 734         u64 ldStartBlock;
 735         u32 numBlocks;
 736         u16 ldTgtId;
 737         u8 isRead;
 738         __le16 devHandle;
 739         u64 pdBlock;
 740         u8 fpOkForIo;
 741         u8 IoforUnevenSpan;
 742         u8 start_span;
 743         u8 do_fp_rlbypass;
 744         u64 start_row;
 745         u8  span_arm;   /* span[7:5], arm[4:0] */
 746         u8  pd_after_lb;
 747 };
 748
 749 struct MR_LD_TARGET_SYNC {
 750         u8  targetId;
 751         u8  reserved;
 752         __le16 seqNum;
 753 };
 754
 755 #define IEEE_SGE_FLAGS_ADDR_MASK            (0x03)
 756 #define IEEE_SGE_FLAGS_SYSTEM_ADDR          (0x00)
 757 #define IEEE_SGE_FLAGS_IOCDDR_ADDR          (0x01)
 758 #define IEEE_SGE_FLAGS_IOCPLB_ADDR          (0x02)
 759 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR       (0x03)
 760 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT        (0x80)
 761 #define IEEE_SGE_FLAGS_END_OF_LIST          (0x40)
 762
 763 struct megasas_register_set;
 764 struct megasas_instance;
 765
 766 union desc_word {
 767         u64 word;
 768         struct {
 769                 u32 low;
 770                 u32 high;
 771         } u;
 772 };
 773
 774 struct megasas_cmd_fusion {
 775         struct MPI2_RAID_SCSI_IO_REQUEST        *io_request;
 776         dma_addr_t                      io_request_phys_addr;
 777
 778         union MPI2_SGE_IO_UNION *sg_frame;
 779         dma_addr_t              sg_frame_phys_addr;
 780
 781         u8 *sense;
 782         dma_addr_t sense_phys_addr;
 783
 784         struct list_head list;
 785         struct scsi_cmnd *scmd;
 786         struct megasas_instance *instance;
 787
 788         u8 retry_for_fw_reset;
 789         union MEGASAS_REQUEST_DESCRIPTOR_UNION  *request_desc;
 790
 791         /*
 792          * Context for a MFI frame.
 793          * Used to get the mfi cmd from list when a MFI cmd is completed
 794          */
 795         u32 sync_cmd_idx;
 796         u32 index;
 797         u8 pd_r1_lb;
 798         struct completion done;
 799 };
 800
 801 struct LD_LOAD_BALANCE_INFO {
 802         u8      loadBalanceFlag;
 803         u8      reserved1;
 804         atomic_t     scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
 805         u64     last_accessed_block[MAX_PHYSICAL_DEVICES];
 806 };
 807
 808 /* SPAN_SET is info caclulated from span info from Raid map per LD */
 809 typedef struct _LD_SPAN_SET {
 810         u64  log_start_lba;
 811         u64  log_end_lba;
 812         u64  span_row_start;
 813         u64  span_row_end;
 814         u64  data_strip_start;
 815         u64  data_strip_end;
 816         u64  data_row_start;
 817         u64  data_row_end;
 818         u8   strip_offset[MAX_SPAN_DEPTH];
 819         u32    span_row_data_width;
 820         u32    diff;
 821         u32    reserved[2];
 822 } LD_SPAN_SET, *PLD_SPAN_SET;
 823
 824 typedef struct LOG_BLOCK_SPAN_INFO {
 825         LD_SPAN_SET  span_set[MAX_SPAN_DEPTH];
 826 } LD_SPAN_INFO, *PLD_SPAN_INFO;
 827
 828 struct MR_FW_RAID_MAP_ALL {
 829         struct MR_FW_RAID_MAP raidMap;
 830         struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
 831 } __attribute__ ((packed));
 832
 833 struct MR_DRV_RAID_MAP {
 834         /* total size of this structure, including this field.
 835          * This feild will be manupulated by driver for ext raid map,
 836          * else pick the value from firmware raid map.
 837          */
 838         __le32                 totalSize;
 839
 840         union {
 841         struct {
 842                 __le32         maxLd;
 843                 __le32         maxSpanDepth;
 844                 __le32         maxRowSize;
 845                 __le32         maxPdCount;
 846                 __le32         maxArrays;
 847         } validationInfo;
 848         __le32             version[5];
 849         };
 850
 851         /* timeout value used by driver in FP IOs*/
 852         u8                  fpPdIoTimeoutSec;
 853         u8                  reserved2[7];
 854
 855         __le16                 ldCount;
 856         __le16                 arCount;
 857         __le16                 spanCount;
 858         __le16                 reserve3;
 859
 860         struct MR_DEV_HANDLE_INFO  devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 861         u8                  ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
 862         struct MR_ARRAY_INFO       arMapInfo[MAX_API_ARRAYS_EXT];
 863         struct MR_LD_SPAN_MAP      ldSpanMap[1];
 864
 865 };
 866
 867 /* Driver raid map size is same as raid map ext
 868  * MR_DRV_RAID_MAP_ALL is created to sync with old raid.
 869  * And it is mainly for code re-use purpose.
 870  */
 871 struct MR_DRV_RAID_MAP_ALL {
 872
 873         struct MR_DRV_RAID_MAP raidMap;
 874         struct MR_LD_SPAN_MAP      ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1];
 875 } __packed;
 876
 877
 878
 879 struct MR_FW_RAID_MAP_EXT {
 880         /* Not usred in new map */
 881         u32                 reserved;
 882
 883         union {
 884         struct {
 885                 u32         maxLd;
 886                 u32         maxSpanDepth;
 887                 u32         maxRowSize;
 888                 u32         maxPdCount;
 889                 u32         maxArrays;
 890         } validationInfo;
 891         u32             version[5];
 892         };
 893
 894         u8                  fpPdIoTimeoutSec;
 895         u8                  reserved2[7];
 896
 897         __le16                 ldCount;
 898         __le16                 arCount;
 899         __le16                 spanCount;
 900         __le16                 reserve3;
 901
 902         struct MR_DEV_HANDLE_INFO  devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 903         u8                  ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
 904         struct MR_ARRAY_INFO       arMapInfo[MAX_API_ARRAYS_EXT];
 905         struct MR_LD_SPAN_MAP      ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
 906 };
 907
 908 /*
 909  *  * define MR_PD_CFG_SEQ structure for system PDs
 910  *   */
 911 struct MR_PD_CFG_SEQ {
 912         u16 seqNum;
 913         u16 devHandle;
 914         struct {
 915 #if   defined(__BIG_ENDIAN_BITFIELD)
 916                 u8     reserved:7;
 917                 u8     tmCapable:1;
 918 #else
 919                 u8     tmCapable:1;
 920                 u8     reserved:7;
 921 #endif
 922         } capability;
 923         u8  reserved[3];
 924 } __packed;
 925
 926 struct MR_PD_CFG_SEQ_NUM_SYNC {
 927         __le32 size;
 928         __le32 count;
 929         struct MR_PD_CFG_SEQ seq[1];
 930 } __packed;
 931
 932 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
 933         u64 RDPQBaseAddress;
 934         u32 Reserved1;
 935         u32 Reserved2;
 936 };
 937
 938 struct fusion_context {
 939         struct megasas_cmd_fusion **cmd_list;
 940         dma_addr_t req_frames_desc_phys;
 941         u8 *req_frames_desc;
 942
 943         struct dma_pool *io_request_frames_pool;
 944         dma_addr_t io_request_frames_phys;
 945         u8 *io_request_frames;
 946
 947         struct dma_pool *sg_dma_pool;
 948         struct dma_pool *sense_dma_pool;
 949
 950         dma_addr_t reply_frames_desc_phys[MAX_MSIX_QUEUES_FUSION];
 951         union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[MAX_MSIX_QUEUES_FUSION];
 952         struct dma_pool *reply_frames_desc_pool;
 953
 954         u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
 955
 956         u32 reply_q_depth;
 957         u32 request_alloc_sz;
 958         u32 reply_alloc_sz;
 959         u32 io_frames_alloc_sz;
 960
 961         struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt;
 962         dma_addr_t rdpq_phys;
 963         u16     max_sge_in_main_msg;
 964         u16     max_sge_in_chain;
 965
 966         u8      chain_offset_io_request;
 967         u8      chain_offset_mfi_pthru;
 968
 969         struct MR_FW_RAID_MAP_ALL *ld_map[2];
 970         dma_addr_t ld_map_phys[2];
 971
 972         /*Non dma-able memory. Driver local copy.*/
 973         struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
 974
 975         u32 max_map_sz;
 976         u32 current_map_sz;
 977         u32 drv_map_sz;
 978         u32 drv_map_pages;
 979         struct MR_PD_CFG_SEQ_NUM_SYNC   *pd_seq_sync[JBOD_MAPS_COUNT];
 980         dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT];
 981         u8 fast_path_io;
 982         struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT];
 983         LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
 984         u8 adapter_type;
 985 };
 986
 987 union desc_value {
 988         __le64 word;
 989         struct {
 990                 __le32 low;
 991                 __le32 high;
 992         } u;
 993 };
 994
 995 void megasas_free_cmds_fusion(struct megasas_instance *instance);
 996 int megasas_ioc_init_fusion(struct megasas_instance *instance);
 997 u8 megasas_get_map_info(struct megasas_instance *instance);
 998 int megasas_sync_map_info(struct megasas_instance *instance);
 999 void megasas_release_fusion(struct megasas_instance *instance);
1000 void megasas_reset_reply_desc(struct megasas_instance *instance);
1001 int megasas_check_mpio_paths(struct megasas_instance *instance,
1002                               struct scsi_cmnd *scmd);
1003 void megasas_fusion_ocr_wq(struct work_struct *work);
1004
1005 #endif /* _MEGARAID_SAS_FUSION_H_ */