1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2000-2015 Avago Technologies. All rights reserved.
7 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
8 * Creation Date: October 11, 2006
10 * mpi2_ioc.h Version: 02.00.34
12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
13 * prefix are for use only on MPI v2.5 products, and must not be used
14 * with MPI v2.0 products. Unless otherwise noted, names beginning with
15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
20 * Date Version Description
21 * -------- -------- ------------------------------------------------------
22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
23 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
25 * Added TotalImageSize field to FWDownload Request.
26 * Added reserved words to FWUpload Request.
27 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
28 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
29 * request and replaced it with
30 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
31 * Replaced the MinReplyQueueDepth field of the IOCFacts
32 * reply with MaxReplyDescriptorPostQueueDepth.
33 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
34 * depth for the Reply Descriptor Post Queue.
35 * Added SASAddress field to Initiator Device Table
36 * Overflow Event data.
37 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
38 * for SAS Initiator Device Status Change Event data.
39 * Modified Reason Code defines for SAS Topology Change
40 * List Event data, including adding a bit for PHY Vacant
41 * status, and adding a mask for the Reason Code.
43 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
44 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
45 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
47 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
48 * Moved MPI2_VERSION_UNION to mpi2.h.
49 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
50 * instead of enables, and added SASBroadcastPrimitiveMasks
52 * Added Log Entry Added Event and related structure.
53 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
54 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
55 * Added MaxVolumes and MaxPersistentEntries fields to
57 * Added ProtocalFlags and IOCCapabilities fields to
58 * MPI2_FW_IMAGE_HEADER.
59 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
60 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
62 * Removed extra 's' from EventMasks name.
63 * 06-27-08 02.00.08 Fixed an offset in a comment.
64 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
65 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
66 * renamed MinReplyFrameSize to ReplyFrameSize.
67 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
68 * Added two new RAIDOperation values for Integrated RAID
69 * Operations Status Event data.
70 * Added four new IR Configuration Change List Event data
72 * Added two new ReasonCode defines for SAS Device Status
74 * Added three new DiscoveryStatus bits for the SAS
75 * Discovery event data.
76 * Added Multiplexing Status Change bit to the PhyStatus
77 * field of the SAS Topology Change List event data.
78 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
79 * BootFlags are now product-specific.
80 * Added defines for the indivdual signature bytes
81 * for MPI2_INIT_IMAGE_FOOTER.
82 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
83 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
85 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
87 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
88 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
89 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
90 * Added two new reason codes for SAS Device Status Change
92 * Added new event: SAS PHY Counter.
93 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
94 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
95 * Added new product id family for 2208.
96 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
97 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
98 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
99 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
100 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
101 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
102 * Added Host Based Discovery Phy Event data.
103 * Added defines for ProductID Product field
104 * (MPI2_FW_HEADER_PID_).
105 * Modified values for SAS ProductID Family
106 * (MPI2_FW_HEADER_PID_FAMILY_).
107 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
108 * Added PowerManagementControl Request structures and
110 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
111 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
112 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
113 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added
114 * SASNotifyPrimitiveMasks field to
115 * MPI2_EVENT_NOTIFICATION_REQUEST.
116 * Added Temperature Threshold Event.
117 * Added Host Message Event.
118 * Added Send Host Message request and reply.
119 * 05-25-11 02.00.18 For Extended Image Header, added
120 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
121 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
122 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
123 * 08-24-11 02.00.19 Added PhysicalPort field to
124 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
125 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
126 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5.
127 * 03-29-12 02.00.21 Added a product specific range to event values.
128 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
129 * Added ElapsedSeconds field to
130 * MPI2_EVENT_DATA_IR_OPERATION_STATUS.
131 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
132 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
133 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
134 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
135 * Added Encrypted Hash Extended Image.
136 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS.
137 * 11-18-14 02.00.25 Updated copyright information.
138 * 03-16-15 02.00.26 Updated for MPI v2.6.
139 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and
140 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT.
141 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and
142 * MPI26_FW_HEADER_PID_FAMILY_3516_SAS.
143 * Added MPI26_CTRL_OP_SHUTDOWN.
144 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines.
145 * Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event.
146 * Added ConigurationFlags field to IOCInit message to
147 * support NVMe SGL format control.
148 * Added PCIe SRIOV support.
149 * 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support.
150 * Added PCIe 4 16.0 GT/sec speec support.
151 * Removed AHCI support.
152 * Removed SOP support.
153 * 07-01-16 02.00.29 Added Archclass for 4008 product.
154 * Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED
155 * 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload
157 * Added new defines for the ImageType field of FWUpload
159 * Added new values for the RegionType field in the Layout
160 * Data sections of the FLASH Layout Extended Image Data.
161 * Added new defines for the ReasonCode field of
162 * Active Cable Exception Event.
163 * Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and
164 * MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE.
165 * 11-23-16 02.00.31 Added MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR and
166 * MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR.
167 * 02-02-17 02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP.
168 * Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related
169 * defines for the ReasonCode field.
170 * 06-13-17 02.00.33 Added MPI2_FW_DOWNLOAD_ITYPE_CPLD.
171 * 09-29-17 02.00.34 Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED
172 * to the ReasonCode field in PCIe Device Status Change
174 * --------------------------------------------------------------------------
180 /*****************************************************************************
184 *****************************************************************************/
186 /****************************************************************************
188 ****************************************************************************/
190 /*IOCInit Request message */
191 typedef struct _MPI2_IOC_INIT_REQUEST {
192 U8 WhoInit; /*0x00 */
193 U8 Reserved1; /*0x01 */
194 U8 ChainOffset; /*0x02 */
195 U8 Function; /*0x03 */
196 U16 Reserved2; /*0x04 */
197 U8 Reserved3; /*0x06 */
198 U8 MsgFlags; /*0x07 */
201 U16 Reserved4; /*0x0A */
202 U16 MsgVersion; /*0x0C */
203 U16 HeaderVersion; /*0x0E */
204 U32 Reserved5; /*0x10 */
205 U16 ConfigurationFlags; /* 0x14 */
206 U8 HostPageSize; /*0x16 */
207 U8 HostMSIxVectors; /*0x17 */
208 U16 Reserved8; /*0x18 */
209 U16 SystemRequestFrameSize; /*0x1A */
210 U16 ReplyDescriptorPostQueueDepth; /*0x1C */
211 U16 ReplyFreeQueueDepth; /*0x1E */
212 U32 SenseBufferAddressHigh; /*0x20 */
213 U32 SystemReplyAddressHigh; /*0x24 */
214 U64 SystemRequestFrameBaseAddress; /*0x28 */
215 U64 ReplyDescriptorPostQueueAddress; /*0x30 */
216 U64 ReplyFreeQueueAddress; /*0x38 */
217 U64 TimeStamp; /*0x40 */
218 } MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,
219 Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;
222 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
223 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
224 #define MPI2_WHOINIT_ROM_BIOS (0x02)
225 #define MPI2_WHOINIT_PCI_PEER (0x03)
226 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
227 #define MPI2_WHOINIT_MANUFACTURER (0x05)
230 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
234 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
235 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
236 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
237 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
240 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
241 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
242 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
243 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
245 /*ConfigurationFlags */
246 #define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001)
248 /*minimum depth for a Reply Descriptor Post Queue */
249 #define MPI2_RDPQ_DEPTH_MIN (16)
251 /* Reply Descriptor Post Queue Array Entry */
252 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
253 U64 RDPQBaseAddress; /* 0x00 */
254 U32 Reserved1; /* 0x08 */
255 U32 Reserved2; /* 0x0C */
256 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
257 *PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
258 Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry;
261 /*IOCInit Reply message */
262 typedef struct _MPI2_IOC_INIT_REPLY {
263 U8 WhoInit; /*0x00 */
264 U8 Reserved1; /*0x01 */
265 U8 MsgLength; /*0x02 */
266 U8 Function; /*0x03 */
267 U16 Reserved2; /*0x04 */
268 U8 Reserved3; /*0x06 */
269 U8 MsgFlags; /*0x07 */
272 U16 Reserved4; /*0x0A */
273 U16 Reserved5; /*0x0C */
274 U16 IOCStatus; /*0x0E */
275 U32 IOCLogInfo; /*0x10 */
276 } MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY,
277 Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t;
279 /****************************************************************************
281 ****************************************************************************/
283 /*IOCFacts Request message */
284 typedef struct _MPI2_IOC_FACTS_REQUEST {
285 U16 Reserved1; /*0x00 */
286 U8 ChainOffset; /*0x02 */
287 U8 Function; /*0x03 */
288 U16 Reserved2; /*0x04 */
289 U8 Reserved3; /*0x06 */
290 U8 MsgFlags; /*0x07 */
293 U16 Reserved4; /*0x0A */
294 } MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST,
295 Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t;
297 /*IOCFacts Reply message */
298 typedef struct _MPI2_IOC_FACTS_REPLY {
299 U16 MsgVersion; /*0x00 */
300 U8 MsgLength; /*0x02 */
301 U8 Function; /*0x03 */
302 U16 HeaderVersion; /*0x04 */
303 U8 IOCNumber; /*0x06 */
304 U8 MsgFlags; /*0x07 */
307 U16 Reserved1; /*0x0A */
308 U16 IOCExceptions; /*0x0C */
309 U16 IOCStatus; /*0x0E */
310 U32 IOCLogInfo; /*0x10 */
311 U8 MaxChainDepth; /*0x14 */
312 U8 WhoInit; /*0x15 */
313 U8 NumberOfPorts; /*0x16 */
314 U8 MaxMSIxVectors; /*0x17 */
315 U16 RequestCredit; /*0x18 */
316 U16 ProductID; /*0x1A */
317 U32 IOCCapabilities; /*0x1C */
318 MPI2_VERSION_UNION FWVersion; /*0x20 */
319 U16 IOCRequestFrameSize; /*0x24 */
320 U16 IOCMaxChainSegmentSize; /*0x26 */
321 U16 MaxInitiators; /*0x28 */
322 U16 MaxTargets; /*0x2A */
323 U16 MaxSasExpanders; /*0x2C */
324 U16 MaxEnclosures; /*0x2E */
325 U16 ProtocolFlags; /*0x30 */
326 U16 HighPriorityCredit; /*0x32 */
327 U16 MaxReplyDescriptorPostQueueDepth; /*0x34 */
328 U8 ReplyFrameSize; /*0x36 */
329 U8 MaxVolumes; /*0x37 */
330 U16 MaxDevHandle; /*0x38 */
331 U16 MaxPersistentEntries; /*0x3A */
332 U16 MinDevHandle; /*0x3C */
333 U8 CurrentHostPageSize; /* 0x3E */
334 U8 Reserved4; /* 0x3F */
335 U8 SGEModifierMask; /*0x40 */
336 U8 SGEModifierValue; /*0x41 */
337 U8 SGEModifierShift; /*0x42 */
338 U8 Reserved5; /*0x43 */
339 } MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,
340 Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;
343 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
344 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
345 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
346 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
349 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
350 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
351 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
352 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
355 #define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0400)
356 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200)
357 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
359 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
360 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
361 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
362 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
363 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
365 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
366 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
367 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
368 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
369 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
371 /*defines for WhoInit field are after the IOCInit Request */
373 /*ProductID field uses MPI2_FW_HEADER_PID_ */
376 #define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000)
377 #define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000)
378 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000)
379 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000)
380 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
381 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
382 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
383 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
384 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
385 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
386 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
387 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
388 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
389 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
390 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
391 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
392 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
395 #define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES (0x0008)
396 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
397 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
399 /****************************************************************************
401 ****************************************************************************/
403 /*PortFacts Request message */
404 typedef struct _MPI2_PORT_FACTS_REQUEST {
405 U16 Reserved1; /*0x00 */
406 U8 ChainOffset; /*0x02 */
407 U8 Function; /*0x03 */
408 U16 Reserved2; /*0x04 */
409 U8 PortNumber; /*0x06 */
410 U8 MsgFlags; /*0x07 */
413 U16 Reserved3; /*0x0A */
414 } MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST,
415 Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t;
417 /*PortFacts Reply message */
418 typedef struct _MPI2_PORT_FACTS_REPLY {
419 U16 Reserved1; /*0x00 */
420 U8 MsgLength; /*0x02 */
421 U8 Function; /*0x03 */
422 U16 Reserved2; /*0x04 */
423 U8 PortNumber; /*0x06 */
424 U8 MsgFlags; /*0x07 */
427 U16 Reserved3; /*0x0A */
428 U16 Reserved4; /*0x0C */
429 U16 IOCStatus; /*0x0E */
430 U32 IOCLogInfo; /*0x10 */
431 U8 Reserved5; /*0x14 */
432 U8 PortType; /*0x15 */
433 U16 Reserved6; /*0x16 */
434 U16 MaxPostedCmdBuffers; /*0x18 */
435 U16 Reserved7; /*0x1A */
436 } MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY,
437 Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t;
440 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
441 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
442 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
443 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
444 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
445 #define MPI2_PORTFACTS_PORTTYPE_TRI_MODE (0x40)
448 /****************************************************************************
450 ****************************************************************************/
452 /*PortEnable Request message */
453 typedef struct _MPI2_PORT_ENABLE_REQUEST {
454 U16 Reserved1; /*0x00 */
455 U8 ChainOffset; /*0x02 */
456 U8 Function; /*0x03 */
457 U8 Reserved2; /*0x04 */
458 U8 PortFlags; /*0x05 */
459 U8 Reserved3; /*0x06 */
460 U8 MsgFlags; /*0x07 */
463 U16 Reserved4; /*0x0A */
464 } MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST,
465 Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t;
467 /*PortEnable Reply message */
468 typedef struct _MPI2_PORT_ENABLE_REPLY {
469 U16 Reserved1; /*0x00 */
470 U8 MsgLength; /*0x02 */
471 U8 Function; /*0x03 */
472 U8 Reserved2; /*0x04 */
473 U8 PortFlags; /*0x05 */
474 U8 Reserved3; /*0x06 */
475 U8 MsgFlags; /*0x07 */
478 U16 Reserved4; /*0x0A */
479 U16 Reserved5; /*0x0C */
480 U16 IOCStatus; /*0x0E */
481 U32 IOCLogInfo; /*0x10 */
482 } MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY,
483 Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t;
485 /****************************************************************************
486 * EventNotification message
487 ****************************************************************************/
489 /*EventNotification Request message */
490 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
492 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST {
493 U16 Reserved1; /*0x00 */
494 U8 ChainOffset; /*0x02 */
495 U8 Function; /*0x03 */
496 U16 Reserved2; /*0x04 */
497 U8 Reserved3; /*0x06 */
498 U8 MsgFlags; /*0x07 */
501 U16 Reserved4; /*0x0A */
502 U32 Reserved5; /*0x0C */
503 U32 Reserved6; /*0x10 */
504 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; /*0x14 */
505 U16 SASBroadcastPrimitiveMasks; /*0x24 */
506 U16 SASNotifyPrimitiveMasks; /*0x26 */
507 U32 Reserved8; /*0x28 */
508 } MPI2_EVENT_NOTIFICATION_REQUEST,
509 *PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
510 Mpi2EventNotificationRequest_t,
511 *pMpi2EventNotificationRequest_t;
513 /*EventNotification Reply message */
514 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
515 U16 EventDataLength; /*0x00 */
516 U8 MsgLength; /*0x02 */
517 U8 Function; /*0x03 */
518 U16 Reserved1; /*0x04 */
519 U8 AckRequired; /*0x06 */
520 U8 MsgFlags; /*0x07 */
523 U16 Reserved2; /*0x0A */
524 U16 Reserved3; /*0x0C */
525 U16 IOCStatus; /*0x0E */
526 U32 IOCLogInfo; /*0x10 */
528 U16 Reserved4; /*0x16 */
529 U32 EventContext; /*0x18 */
530 U32 EventData[1]; /*0x1C */
531 } MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY,
532 Mpi2EventNotificationReply_t,
533 *pMpi2EventNotificationReply_t;
536 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
537 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
540 #define MPI2_EVENT_LOG_DATA (0x0001)
541 #define MPI2_EVENT_STATE_CHANGE (0x0002)
542 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
543 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
544 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /*obsolete */
545 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
546 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
547 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
548 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
549 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
550 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
551 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
552 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
553 #define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x001D)
554 #define MPI2_EVENT_IR_VOLUME (0x001E)
555 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
556 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
557 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
558 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
559 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
560 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
561 #define MPI2_EVENT_SAS_QUIESCE (0x0025)
562 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
563 #define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
564 #define MPI2_EVENT_HOST_MESSAGE (0x0028)
565 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029)
566 #define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE (0x0030)
567 #define MPI2_EVENT_PCIE_ENUMERATION (0x0031)
568 #define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x0032)
569 #define MPI2_EVENT_PCIE_LINK_COUNTER (0x0033)
570 #define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034)
571 #define MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x0035)
572 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
573 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
575 /*Log Entry Added Event data */
577 /*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
578 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
580 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED {
581 U64 TimeStamp; /*0x00 */
582 U32 Reserved1; /*0x08 */
583 U16 LogSequence; /*0x0C */
584 U16 LogEntryQualifier; /*0x0E */
587 U16 Reserved2; /*0x12 */
588 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH]; /*0x14 */
589 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
590 *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
591 Mpi2EventDataLogEntryAdded_t,
592 *pMpi2EventDataLogEntryAdded_t;
594 /*GPIO Interrupt Event data */
596 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
597 U8 GPIONum; /*0x00 */
598 U8 Reserved1; /*0x01 */
599 U16 Reserved2; /*0x02 */
600 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
601 *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
602 Mpi2EventDataGpioInterrupt_t,
603 *pMpi2EventDataGpioInterrupt_t;
605 /*Temperature Threshold Event data */
607 typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
608 U16 Status; /*0x00 */
609 U8 SensorNum; /*0x02 */
610 U8 Reserved1; /*0x03 */
611 U16 CurrentTemperature; /*0x04 */
612 U16 Reserved2; /*0x06 */
613 U32 Reserved3; /*0x08 */
614 U32 Reserved4; /*0x0C */
615 } MPI2_EVENT_DATA_TEMPERATURE,
616 *PTR_MPI2_EVENT_DATA_TEMPERATURE,
617 Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t;
619 /*Temperature Threshold Event data Status bits */
620 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)
621 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)
622 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)
623 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)
625 /*Host Message Event data */
627 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
628 U8 SourceVF_ID; /*0x00 */
629 U8 Reserved1; /*0x01 */
630 U16 Reserved2; /*0x02 */
631 U32 Reserved3; /*0x04 */
632 U32 HostData[1]; /*0x08 */
633 } MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
634 Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t;
636 /*Power Performance Change Event data */
638 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE {
639 U8 CurrentPowerMode; /*0x00 */
640 U8 PreviousPowerMode; /*0x01 */
641 U16 Reserved1; /*0x02 */
642 } MPI2_EVENT_DATA_POWER_PERF_CHANGE,
643 *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
644 Mpi2EventDataPowerPerfChange_t,
645 *pMpi2EventDataPowerPerfChange_t;
647 /*defines for CurrentPowerMode and PreviousPowerMode fields */
648 #define MPI2_EVENT_PM_INIT_MASK (0xC0)
649 #define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00)
650 #define MPI2_EVENT_PM_INIT_HOST (0x40)
651 #define MPI2_EVENT_PM_INIT_IO_UNIT (0x80)
652 #define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0)
654 #define MPI2_EVENT_PM_MODE_MASK (0x07)
655 #define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00)
656 #define MPI2_EVENT_PM_MODE_UNKNOWN (0x01)
657 #define MPI2_EVENT_PM_MODE_FULL_POWER (0x04)
658 #define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05)
659 #define MPI2_EVENT_PM_MODE_STANDBY (0x06)
661 /* Active Cable Exception Event data */
663 typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT {
664 U32 ActiveCablePowerRequirement; /* 0x00 */
665 U8 ReasonCode; /* 0x04 */
666 U8 ReceptacleID; /* 0x05 */
667 U16 Reserved1; /* 0x06 */
668 } MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
669 *PTR_MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
670 Mpi25EventDataActiveCableExcept_t,
671 *pMpi25EventDataActiveCableExcept_t,
672 MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
673 *PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
674 Mpi26EventDataActiveCableExcept_t,
675 *pMpi26EventDataActiveCableExcept_t;
677 /*MPI2.5 defines for the ReasonCode field */
678 #define MPI25_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
679 #define MPI25_EVENT_ACTIVE_CABLE_PRESENT (0x01)
680 #define MPI25_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
682 /* defines for ReasonCode field */
683 #define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
684 #define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01)
685 #define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
687 /*Hard Reset Received Event data */
689 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED {
690 U8 Reserved1; /*0x00 */
692 U16 Reserved2; /*0x02 */
693 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
694 *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
695 Mpi2EventDataHardResetReceived_t,
696 *pMpi2EventDataHardResetReceived_t;
698 /*Task Set Full Event data */
699 /* this event is obsolete */
701 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL {
702 U16 DevHandle; /*0x00 */
703 U16 CurrentDepth; /*0x02 */
704 } MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
705 Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t;
707 /*SAS Device Status Change Event data */
709 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE {
710 U16 TaskTag; /*0x00 */
711 U8 ReasonCode; /*0x02 */
712 U8 PhysicalPort; /*0x03 */
715 U16 DevHandle; /*0x06 */
716 U32 Reserved2; /*0x08 */
717 U64 SASAddress; /*0x0C */
719 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
720 *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
721 Mpi2EventDataSasDeviceStatusChange_t,
722 *pMpi2EventDataSasDeviceStatusChange_t;
724 /*SAS Device Status Change Event data ReasonCode values */
725 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
726 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
727 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
728 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
729 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
730 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
731 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
732 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
733 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
734 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
735 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
736 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
737 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
739 /*Integrated RAID Operation Status Event data */
741 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS {
742 U16 VolDevHandle; /*0x00 */
743 U16 Reserved1; /*0x02 */
744 U8 RAIDOperation; /*0x04 */
745 U8 PercentComplete; /*0x05 */
746 U16 Reserved2; /*0x06 */
747 U32 ElapsedSeconds; /*0x08 */
748 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
749 *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
750 Mpi2EventDataIrOperationStatus_t,
751 *pMpi2EventDataIrOperationStatus_t;
753 /*Integrated RAID Operation Status Event data RAIDOperation values */
754 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
755 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
756 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
757 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
758 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
760 /*Integrated RAID Volume Event data */
762 typedef struct _MPI2_EVENT_DATA_IR_VOLUME {
763 U16 VolDevHandle; /*0x00 */
764 U8 ReasonCode; /*0x02 */
765 U8 Reserved1; /*0x03 */
766 U32 NewValue; /*0x04 */
767 U32 PreviousValue; /*0x08 */
768 } MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME,
769 Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t;
771 /*Integrated RAID Volume Event data ReasonCode values */
772 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
773 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
774 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
776 /*Integrated RAID Physical Disk Event data */
778 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK {
779 U16 Reserved1; /*0x00 */
780 U8 ReasonCode; /*0x02 */
781 U8 PhysDiskNum; /*0x03 */
782 U16 PhysDiskDevHandle; /*0x04 */
783 U16 Reserved2; /*0x06 */
785 U16 EnclosureHandle; /*0x0A */
786 U32 NewValue; /*0x0C */
787 U32 PreviousValue; /*0x10 */
788 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
789 *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
790 Mpi2EventDataIrPhysicalDisk_t,
791 *pMpi2EventDataIrPhysicalDisk_t;
793 /*Integrated RAID Physical Disk Event data ReasonCode values */
794 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
795 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
796 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
798 /*Integrated RAID Configuration Change List Event data */
801 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
802 *one and check NumElements at runtime.
804 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
805 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
808 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT {
809 U16 ElementFlags; /*0x00 */
810 U16 VolDevHandle; /*0x02 */
811 U8 ReasonCode; /*0x04 */
812 U8 PhysDiskNum; /*0x05 */
813 U16 PhysDiskDevHandle; /*0x06 */
814 } MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
815 Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t;
817 /*IR Configuration Change List Event data ElementFlags values */
818 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
819 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
820 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
821 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
823 /*IR Configuration Change List Event data ReasonCode values */
824 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
825 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
826 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
827 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
828 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
829 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
830 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
831 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
832 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
834 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST {
835 U8 NumElements; /*0x00 */
836 U8 Reserved1; /*0x01 */
837 U8 Reserved2; /*0x02 */
838 U8 ConfigNum; /*0x03 */
840 MPI2_EVENT_IR_CONFIG_ELEMENT
841 ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];/*0x08 */
842 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
843 *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
844 Mpi2EventDataIrConfigChangeList_t,
845 *pMpi2EventDataIrConfigChangeList_t;
847 /*IR Configuration Change List Event data Flags values */
848 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
850 /*SAS Discovery Event data */
852 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY {
854 U8 ReasonCode; /*0x01 */
855 U8 PhysicalPort; /*0x02 */
856 U8 Reserved1; /*0x03 */
857 U32 DiscoveryStatus; /*0x04 */
858 } MPI2_EVENT_DATA_SAS_DISCOVERY,
859 *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
860 Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t;
862 /*SAS Discovery Event data Flags values */
863 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
864 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
866 /*SAS Discovery Event data ReasonCode values */
867 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
868 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
870 /*SAS Discovery Event data DiscoveryStatus values */
871 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
872 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
873 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
874 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
875 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
876 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
877 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
878 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
879 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
880 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
881 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
882 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
883 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
884 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
885 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
886 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
887 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
888 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
889 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
890 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
892 /*SAS Broadcast Primitive Event data */
894 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE {
897 U8 PortWidth; /*0x02 */
898 U8 Primitive; /*0x03 */
899 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
900 *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
901 Mpi2EventDataSasBroadcastPrimitive_t,
902 *pMpi2EventDataSasBroadcastPrimitive_t;
904 /*defines for the Primitive field */
905 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
906 #define MPI2_EVENT_PRIMITIVE_SES (0x02)
907 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
908 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
909 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
910 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
911 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
912 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
914 /*SAS Notify Primitive Event data */
916 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
919 U8 Reserved1; /*0x02 */
920 U8 Primitive; /*0x03 */
921 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
922 *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
923 Mpi2EventDataSasNotifyPrimitive_t,
924 *pMpi2EventDataSasNotifyPrimitive_t;
926 /*defines for the Primitive field */
927 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)
928 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)
929 #define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)
930 #define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)
932 /*SAS Initiator Device Status Change Event data */
934 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE {
935 U8 ReasonCode; /*0x00 */
936 U8 PhysicalPort; /*0x01 */
937 U16 DevHandle; /*0x02 */
938 U64 SASAddress; /*0x04 */
939 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
940 *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
941 Mpi2EventDataSasInitDevStatusChange_t,
942 *pMpi2EventDataSasInitDevStatusChange_t;
944 /*SAS Initiator Device Status Change event ReasonCode values */
945 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
946 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
948 /*SAS Initiator Device Table Overflow Event data */
950 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW {
951 U16 MaxInit; /*0x00 */
952 U16 CurrentInit; /*0x02 */
953 U64 SASAddress; /*0x04 */
954 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
955 *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
956 Mpi2EventDataSasInitTableOverflow_t,
957 *pMpi2EventDataSasInitTableOverflow_t;
959 /*SAS Topology Change List Event data */
962 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
963 *one and check NumEntries at runtime.
965 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
966 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
969 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY {
970 U16 AttachedDevHandle; /*0x00 */
971 U8 LinkRate; /*0x02 */
972 U8 PhyStatus; /*0x03 */
973 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
974 Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t;
976 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {
977 U16 EnclosureHandle; /*0x00 */
978 U16 ExpanderDevHandle; /*0x02 */
979 U8 NumPhys; /*0x04 */
980 U8 Reserved1; /*0x05 */
981 U16 Reserved2; /*0x06 */
982 U8 NumEntries; /*0x08 */
983 U8 StartPhyNum; /*0x09 */
984 U8 ExpStatus; /*0x0A */
985 U8 PhysicalPort; /*0x0B */
986 MPI2_EVENT_SAS_TOPO_PHY_ENTRY
987 PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /*0x0C */
988 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
989 *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
990 Mpi2EventDataSasTopologyChangeList_t,
991 *pMpi2EventDataSasTopologyChangeList_t;
993 /*values for the ExpStatus field */
994 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
995 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
996 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
997 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
998 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
1000 /*defines for the LinkRate field */
1001 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
1002 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
1003 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
1004 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
1006 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
1007 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
1008 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
1009 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
1010 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
1011 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
1012 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
1013 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
1014 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
1015 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
1016 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B)
1017 #define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C)
1019 /*values for the PhyStatus field */
1020 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
1021 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
1022 /*values for the PhyStatus ReasonCode sub-field */
1023 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
1024 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
1025 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
1026 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
1027 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
1028 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
1030 /*SAS Enclosure Device Status Change Event data */
1032 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {
1033 U16 EnclosureHandle; /*0x00 */
1034 U8 ReasonCode; /*0x02 */
1035 U8 PhysicalPort; /*0x03 */
1036 U64 EnclosureLogicalID; /*0x04 */
1037 U16 NumSlots; /*0x0C */
1038 U16 StartSlot; /*0x0E */
1039 U32 PhyBits; /*0x10 */
1040 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1041 *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1042 Mpi2EventDataSasEnclDevStatusChange_t,
1043 *pMpi2EventDataSasEnclDevStatusChange_t,
1044 MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1045 *PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1046 Mpi26EventDataEnclDevStatusChange_t,
1047 *pMpi26EventDataEnclDevStatusChange_t;
1049 /*SAS Enclosure Device Status Change event ReasonCode values */
1050 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
1051 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
1053 /*Enclosure Device Status Change event ReasonCode values */
1054 #define MPI26_EVENT_ENCL_RC_ADDED (0x01)
1055 #define MPI26_EVENT_ENCL_RC_NOT_RESPONDING (0x02)
1058 typedef struct _MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR {
1059 U16 DevHandle; /*0x00 */
1060 U8 ReasonCode; /*0x02 */
1061 U8 PhysicalPort; /*0x03 */
1062 U32 Reserved1[2]; /*0x04 */
1063 U64 SASAddress; /*0x0C */
1064 U32 Reserved2[2]; /*0x14 */
1065 } MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1066 *PTR_MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1067 Mpi25EventDataSasDeviceDiscoveryError_t,
1068 *pMpi25EventDataSasDeviceDiscoveryError_t;
1070 /*SAS Device Discovery Error Event data ReasonCode values */
1071 #define MPI25_EVENT_SAS_DISC_ERR_SMP_FAILED (0x01)
1072 #define MPI25_EVENT_SAS_DISC_ERR_SMP_TIMEOUT (0x02)
1074 /*SAS PHY Counter Event data */
1076 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
1077 U64 TimeStamp; /*0x00 */
1078 U32 Reserved1; /*0x08 */
1079 U8 PhyEventCode; /*0x0C */
1080 U8 PhyNum; /*0x0D */
1081 U16 Reserved2; /*0x0E */
1082 U32 PhyEventInfo; /*0x10 */
1083 U8 CounterType; /*0x14 */
1084 U8 ThresholdWindow; /*0x15 */
1085 U8 TimeUnits; /*0x16 */
1086 U8 Reserved3; /*0x17 */
1087 U32 EventThreshold; /*0x18 */
1088 U16 ThresholdFlags; /*0x1C */
1089 U16 Reserved4; /*0x1E */
1090 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1091 *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1092 Mpi2EventDataSasPhyCounter_t,
1093 *pMpi2EventDataSasPhyCounter_t;
1095 /*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h
1096 *for the PhyEventCode field */
1098 /*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h
1099 *for the CounterType field */
1101 /*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h
1102 *for the TimeUnits field */
1104 /*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h
1105 *for the ThresholdFlags field */
1107 /*SAS Quiesce Event data */
1109 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
1110 U8 ReasonCode; /*0x00 */
1111 U8 Reserved1; /*0x01 */
1112 U16 Reserved2; /*0x02 */
1113 U32 Reserved3; /*0x04 */
1114 } MPI2_EVENT_DATA_SAS_QUIESCE,
1115 *PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1116 Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t;
1118 /*SAS Quiesce Event data ReasonCode values */
1119 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
1120 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
1122 /*Host Based Discovery Phy Event data */
1124 typedef struct _MPI2_EVENT_HBD_PHY_SAS {
1126 U8 NegotiatedLinkRate; /*0x01 */
1127 U8 PhyNum; /*0x02 */
1128 U8 PhysicalPort; /*0x03 */
1129 U32 Reserved1; /*0x04 */
1130 U8 InitialFrame[28]; /*0x08 */
1131 } MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS,
1132 Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t;
1134 /*values for the Flags field */
1135 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
1136 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
1138 /*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h
1139 *for the NegotiatedLinkRate field */
1141 typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1142 MPI2_EVENT_HBD_PHY_SAS Sas;
1143 } MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1144 Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t;
1146 typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1147 U8 DescriptorType; /*0x00 */
1148 U8 Reserved1; /*0x01 */
1149 U16 Reserved2; /*0x02 */
1150 U32 Reserved3; /*0x04 */
1151 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /*0x08 */
1152 } MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY,
1153 Mpi2EventDataHbdPhy_t,
1154 *pMpi2EventDataMpi2EventDataHbdPhy_t;
1156 /*values for the DescriptorType field */
1157 #define MPI2_EVENT_HBD_DT_SAS (0x01)
1160 /*PCIe Device Status Change Event data (MPI v2.6 and later) */
1162 typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE {
1163 U16 TaskTag; /*0x00 */
1164 U8 ReasonCode; /*0x02 */
1165 U8 PhysicalPort; /*0x03 */
1168 U16 DevHandle; /*0x06 */
1169 U32 Reserved2; /*0x08 */
1171 U8 LUN[8]; /*0x14 */
1172 } MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1173 *PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1174 Mpi26EventDataPCIeDeviceStatusChange_t,
1175 *pMpi26EventDataPCIeDeviceStatusChange_t;
1177 /*PCIe Device Status Change Event data ReasonCode values */
1178 #define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA (0x05)
1179 #define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED (0x07)
1180 #define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
1181 #define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
1182 #define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
1183 #define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
1184 #define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
1185 #define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
1186 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
1187 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
1188 #define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10)
1189 #define MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x11)
1192 /*PCIe Enumeration Event data (MPI v2.6 and later) */
1194 typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION {
1196 U8 ReasonCode; /*0x01 */
1197 U8 PhysicalPort; /*0x02 */
1198 U8 Reserved1; /*0x03 */
1199 U32 EnumerationStatus; /*0x04 */
1200 } MPI26_EVENT_DATA_PCIE_ENUMERATION,
1201 *PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION,
1202 Mpi26EventDataPCIeEnumeration_t,
1203 *pMpi26EventDataPCIeEnumeration_t;
1205 /*PCIe Enumeration Event data Flags values */
1206 #define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE (0x02)
1207 #define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS (0x01)
1209 /*PCIe Enumeration Event data ReasonCode values */
1210 #define MPI26_EVENT_PCIE_ENUM_RC_STARTED (0x01)
1211 #define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED (0x02)
1213 /*PCIe Enumeration Event data EnumerationStatus values */
1214 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000)
1215 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000)
1216 #define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000)
1219 /*PCIe Topology Change List Event data (MPI v2.6 and later) */
1222 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1223 *one and check NumEntries at runtime.
1225 #ifndef MPI26_EVENT_PCIE_TOPO_PORT_COUNT
1226 #define MPI26_EVENT_PCIE_TOPO_PORT_COUNT (1)
1229 typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY {
1230 U16 AttachedDevHandle; /*0x00 */
1231 U8 PortStatus; /*0x02 */
1232 U8 Reserved1; /*0x03 */
1233 U8 CurrentPortInfo; /*0x04 */
1234 U8 Reserved2; /*0x05 */
1235 U8 PreviousPortInfo; /*0x06 */
1236 U8 Reserved3; /*0x07 */
1237 } MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1238 *PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1239 Mpi26EventPCIeTopoPortEntry_t,
1240 *pMpi26EventPCIeTopoPortEntry_t;
1242 /*PCIe Topology Change List Event data PortStatus values */
1243 #define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED (0x01)
1244 #define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02)
1245 #define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03)
1246 #define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04)
1247 #define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05)
1249 /*PCIe Topology Change List Event data defines for CurrentPortInfo and
1252 #define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK (0xF0)
1253 #define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00)
1254 #define MPI26_EVENT_PCIE_TOPO_PI_1_LANE (0x10)
1255 #define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20)
1256 #define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30)
1257 #define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40)
1259 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F)
1260 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00)
1261 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01)
1262 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02)
1263 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03)
1264 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04)
1265 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05)
1267 typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST {
1268 U16 EnclosureHandle; /*0x00 */
1269 U16 SwitchDevHandle; /*0x02 */
1270 U8 NumPorts; /*0x04 */
1271 U8 Reserved1; /*0x05 */
1272 U16 Reserved2; /*0x06 */
1273 U8 NumEntries; /*0x08 */
1274 U8 StartPortNum; /*0x09 */
1275 U8 SwitchStatus; /*0x0A */
1276 U8 PhysicalPort; /*0x0B */
1277 MPI26_EVENT_PCIE_TOPO_PORT_ENTRY
1278 PortEntry[MPI26_EVENT_PCIE_TOPO_PORT_COUNT]; /*0x0C */
1279 } MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1280 *PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1281 Mpi26EventDataPCIeTopologyChangeList_t,
1282 *pMpi26EventDataPCIeTopologyChangeList_t;
1284 /*PCIe Topology Change List Event data SwitchStatus values */
1285 #define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00)
1286 #define MPI26_EVENT_PCIE_TOPO_SS_ADDED (0x01)
1287 #define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02)
1288 #define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING (0x03)
1289 #define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04)
1291 /*PCIe Link Counter Event data (MPI v2.6 and later) */
1293 typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER {
1294 U64 TimeStamp; /*0x00 */
1295 U32 Reserved1; /*0x08 */
1296 U8 LinkEventCode; /*0x0C */
1297 U8 LinkNum; /*0x0D */
1298 U16 Reserved2; /*0x0E */
1299 U32 LinkEventInfo; /*0x10 */
1300 U8 CounterType; /*0x14 */
1301 U8 ThresholdWindow; /*0x15 */
1302 U8 TimeUnits; /*0x16 */
1303 U8 Reserved3; /*0x17 */
1304 U32 EventThreshold; /*0x18 */
1305 U16 ThresholdFlags; /*0x1C */
1306 U16 Reserved4; /*0x1E */
1307 } MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1308 *PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1309 Mpi26EventDataPcieLinkCounter_t, *pMpi26EventDataPcieLinkCounter_t;
1312 /*use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode
1316 /*use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType
1320 /*use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits
1324 /*use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags
1328 /****************************************************************************
1330 ****************************************************************************/
1332 /*EventAck Request message */
1333 typedef struct _MPI2_EVENT_ACK_REQUEST {
1334 U16 Reserved1; /*0x00 */
1335 U8 ChainOffset; /*0x02 */
1336 U8 Function; /*0x03 */
1337 U16 Reserved2; /*0x04 */
1338 U8 Reserved3; /*0x06 */
1339 U8 MsgFlags; /*0x07 */
1342 U16 Reserved4; /*0x0A */
1343 U16 Event; /*0x0C */
1344 U16 Reserved5; /*0x0E */
1345 U32 EventContext; /*0x10 */
1346 } MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST,
1347 Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t;
1349 /*EventAck Reply message */
1350 typedef struct _MPI2_EVENT_ACK_REPLY {
1351 U16 Reserved1; /*0x00 */
1352 U8 MsgLength; /*0x02 */
1353 U8 Function; /*0x03 */
1354 U16 Reserved2; /*0x04 */
1355 U8 Reserved3; /*0x06 */
1356 U8 MsgFlags; /*0x07 */
1359 U16 Reserved4; /*0x0A */
1360 U16 Reserved5; /*0x0C */
1361 U16 IOCStatus; /*0x0E */
1362 U32 IOCLogInfo; /*0x10 */
1363 } MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY,
1364 Mpi2EventAckReply_t, *pMpi2EventAckReply_t;
1366 /****************************************************************************
1367 * SendHostMessage message
1368 ****************************************************************************/
1370 /*SendHostMessage Request message */
1371 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1372 U16 HostDataLength; /*0x00 */
1373 U8 ChainOffset; /*0x02 */
1374 U8 Function; /*0x03 */
1375 U16 Reserved1; /*0x04 */
1376 U8 Reserved2; /*0x06 */
1377 U8 MsgFlags; /*0x07 */
1380 U16 Reserved3; /*0x0A */
1381 U8 Reserved4; /*0x0C */
1382 U8 DestVF_ID; /*0x0D */
1383 U16 Reserved5; /*0x0E */
1384 U32 Reserved6; /*0x10 */
1385 U32 Reserved7; /*0x14 */
1386 U32 Reserved8; /*0x18 */
1387 U32 Reserved9; /*0x1C */
1388 U32 Reserved10; /*0x20 */
1389 U32 HostData[1]; /*0x24 */
1390 } MPI2_SEND_HOST_MESSAGE_REQUEST,
1391 *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1392 Mpi2SendHostMessageRequest_t,
1393 *pMpi2SendHostMessageRequest_t;
1395 /*SendHostMessage Reply message */
1396 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1397 U16 HostDataLength; /*0x00 */
1398 U8 MsgLength; /*0x02 */
1399 U8 Function; /*0x03 */
1400 U16 Reserved1; /*0x04 */
1401 U8 Reserved2; /*0x06 */
1402 U8 MsgFlags; /*0x07 */
1405 U16 Reserved3; /*0x0A */
1406 U16 Reserved4; /*0x0C */
1407 U16 IOCStatus; /*0x0E */
1408 U32 IOCLogInfo; /*0x10 */
1409 } MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1410 Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t;
1412 /****************************************************************************
1413 * FWDownload message
1414 ****************************************************************************/
1416 /*MPI v2.0 FWDownload Request message */
1417 typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
1418 U8 ImageType; /*0x00 */
1419 U8 Reserved1; /*0x01 */
1420 U8 ChainOffset; /*0x02 */
1421 U8 Function; /*0x03 */
1422 U16 Reserved2; /*0x04 */
1423 U8 Reserved3; /*0x06 */
1424 U8 MsgFlags; /*0x07 */
1427 U16 Reserved4; /*0x0A */
1428 U32 TotalImageSize; /*0x0C */
1429 U32 Reserved5; /*0x10 */
1430 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1431 } MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST,
1432 Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest;
1434 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1436 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1437 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1438 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1439 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1440 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1441 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1442 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1443 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1444 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C)
1445 #define MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP (0x0D)
1446 #define MPI2_FW_DOWNLOAD_ITYPE_SBR (0x0E)
1447 #define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP (0x0F)
1448 #define MPI2_FW_DOWNLOAD_ITYPE_HIIM (0x10)
1449 #define MPI2_FW_DOWNLOAD_ITYPE_HIIA (0x11)
1450 #define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12)
1451 #define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13)
1452 #define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14)
1453 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1455 /*MPI v2.0 FWDownload TransactionContext Element */
1456 typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
1457 U8 Reserved1; /*0x00 */
1458 U8 ContextSize; /*0x01 */
1459 U8 DetailsLength; /*0x02 */
1461 U32 Reserved2; /*0x04 */
1462 U32 ImageOffset; /*0x08 */
1463 U32 ImageSize; /*0x0C */
1464 } MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE,
1465 Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t;
1467 /*MPI v2.5 FWDownload Request message */
1468 typedef struct _MPI25_FW_DOWNLOAD_REQUEST {
1469 U8 ImageType; /*0x00 */
1470 U8 Reserved1; /*0x01 */
1471 U8 ChainOffset; /*0x02 */
1472 U8 Function; /*0x03 */
1473 U16 Reserved2; /*0x04 */
1474 U8 Reserved3; /*0x06 */
1475 U8 MsgFlags; /*0x07 */
1478 U16 Reserved4; /*0x0A */
1479 U32 TotalImageSize; /*0x0C */
1480 U32 Reserved5; /*0x10 */
1481 U32 Reserved6; /*0x14 */
1482 U32 ImageOffset; /*0x18 */
1483 U32 ImageSize; /*0x1C */
1484 MPI25_SGE_IO_UNION SGL; /*0x20 */
1485 } MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST,
1486 Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest;
1488 /*FWDownload Reply message */
1489 typedef struct _MPI2_FW_DOWNLOAD_REPLY {
1490 U8 ImageType; /*0x00 */
1491 U8 Reserved1; /*0x01 */
1492 U8 MsgLength; /*0x02 */
1493 U8 Function; /*0x03 */
1494 U16 Reserved2; /*0x04 */
1495 U8 Reserved3; /*0x06 */
1496 U8 MsgFlags; /*0x07 */
1499 U16 Reserved4; /*0x0A */
1500 U16 Reserved5; /*0x0C */
1501 U16 IOCStatus; /*0x0E */
1502 U32 IOCLogInfo; /*0x10 */
1503 } MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY,
1504 Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t;
1506 /****************************************************************************
1508 ****************************************************************************/
1510 /*MPI v2.0 FWUpload Request message */
1511 typedef struct _MPI2_FW_UPLOAD_REQUEST {
1512 U8 ImageType; /*0x00 */
1513 U8 Reserved1; /*0x01 */
1514 U8 ChainOffset; /*0x02 */
1515 U8 Function; /*0x03 */
1516 U16 Reserved2; /*0x04 */
1517 U8 Reserved3; /*0x06 */
1518 U8 MsgFlags; /*0x07 */
1521 U16 Reserved4; /*0x0A */
1522 U32 Reserved5; /*0x0C */
1523 U32 Reserved6; /*0x10 */
1524 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1525 } MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST,
1526 Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t;
1528 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1529 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1530 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1531 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1532 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1533 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1534 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1535 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1536 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1537 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1538 #define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D)
1539 #define MPI2_FW_UPLOAD_ITYPE_SBR (0x0E)
1540 #define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP (0x0F)
1541 #define MPI2_FW_UPLOAD_ITYPE_HIIM (0x10)
1542 #define MPI2_FW_UPLOAD_ITYPE_HIIA (0x11)
1543 #define MPI2_FW_UPLOAD_ITYPE_CTLR (0x12)
1544 #define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE (0x13)
1545 #define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA (0x14)
1548 /*MPI v2.0 FWUpload TransactionContext Element */
1549 typedef struct _MPI2_FW_UPLOAD_TCSGE {
1550 U8 Reserved1; /*0x00 */
1551 U8 ContextSize; /*0x01 */
1552 U8 DetailsLength; /*0x02 */
1554 U32 Reserved2; /*0x04 */
1555 U32 ImageOffset; /*0x08 */
1556 U32 ImageSize; /*0x0C */
1557 } MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE,
1558 Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t;
1560 /*MPI v2.5 FWUpload Request message */
1561 typedef struct _MPI25_FW_UPLOAD_REQUEST {
1562 U8 ImageType; /*0x00 */
1563 U8 Reserved1; /*0x01 */
1564 U8 ChainOffset; /*0x02 */
1565 U8 Function; /*0x03 */
1566 U16 Reserved2; /*0x04 */
1567 U8 Reserved3; /*0x06 */
1568 U8 MsgFlags; /*0x07 */
1571 U16 Reserved4; /*0x0A */
1572 U32 Reserved5; /*0x0C */
1573 U32 Reserved6; /*0x10 */
1574 U32 Reserved7; /*0x14 */
1575 U32 ImageOffset; /*0x18 */
1576 U32 ImageSize; /*0x1C */
1577 MPI25_SGE_IO_UNION SGL; /*0x20 */
1578 } MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST,
1579 Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t;
1581 /*FWUpload Reply message */
1582 typedef struct _MPI2_FW_UPLOAD_REPLY {
1583 U8 ImageType; /*0x00 */
1584 U8 Reserved1; /*0x01 */
1585 U8 MsgLength; /*0x02 */
1586 U8 Function; /*0x03 */
1587 U16 Reserved2; /*0x04 */
1588 U8 Reserved3; /*0x06 */
1589 U8 MsgFlags; /*0x07 */
1592 U16 Reserved4; /*0x0A */
1593 U16 Reserved5; /*0x0C */
1594 U16 IOCStatus; /*0x0E */
1595 U32 IOCLogInfo; /*0x10 */
1596 U32 ActualImageSize; /*0x14 */
1597 } MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,
1598 Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;
1600 /*FW Image Header */
1601 typedef struct _MPI2_FW_IMAGE_HEADER {
1602 U32 Signature; /*0x00 */
1603 U32 Signature0; /*0x04 */
1604 U32 Signature1; /*0x08 */
1605 U32 Signature2; /*0x0C */
1606 MPI2_VERSION_UNION MPIVersion; /*0x10 */
1607 MPI2_VERSION_UNION FWVersion; /*0x14 */
1608 MPI2_VERSION_UNION NVDATAVersion; /*0x18 */
1609 MPI2_VERSION_UNION PackageVersion; /*0x1C */
1610 U16 VendorID; /*0x20 */
1611 U16 ProductID; /*0x22 */
1612 U16 ProtocolFlags; /*0x24 */
1613 U16 Reserved26; /*0x26 */
1614 U32 IOCCapabilities; /*0x28 */
1615 U32 ImageSize; /*0x2C */
1616 U32 NextImageHeaderOffset; /*0x30 */
1617 U32 Checksum; /*0x34 */
1618 U32 Reserved38; /*0x38 */
1619 U32 Reserved3C; /*0x3C */
1620 U32 Reserved40; /*0x40 */
1621 U32 Reserved44; /*0x44 */
1622 U32 Reserved48; /*0x48 */
1623 U32 Reserved4C; /*0x4C */
1624 U32 Reserved50; /*0x50 */
1625 U32 Reserved54; /*0x54 */
1626 U32 Reserved58; /*0x58 */
1627 U32 Reserved5C; /*0x5C */
1628 U32 BootFlags; /*0x60 */
1629 U32 FirmwareVersionNameWhat; /*0x64 */
1630 U8 FirmwareVersionName[32]; /*0x68 */
1631 U32 VendorNameWhat; /*0x88 */
1632 U8 VendorName[32]; /*0x8C */
1633 U32 PackageNameWhat; /*0x88 */
1634 U8 PackageName[32]; /*0x8C */
1635 U32 ReservedD0; /*0xD0 */
1636 U32 ReservedD4; /*0xD4 */
1637 U32 ReservedD8; /*0xD8 */
1638 U32 ReservedDC; /*0xDC */
1639 U32 ReservedE0; /*0xE0 */
1640 U32 ReservedE4; /*0xE4 */
1641 U32 ReservedE8; /*0xE8 */
1642 U32 ReservedEC; /*0xEC */
1643 U32 ReservedF0; /*0xF0 */
1644 U32 ReservedF4; /*0xF4 */
1645 U32 ReservedF8; /*0xF8 */
1646 U32 ReservedFC; /*0xFC */
1647 } MPI2_FW_IMAGE_HEADER, *PTR_MPI2_FW_IMAGE_HEADER,
1648 Mpi2FWImageHeader_t, *pMpi2FWImageHeader_t;
1650 /*Signature field */
1651 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1652 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1653 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1654 #define MPI26_FW_HEADER_SIGNATURE (0xEB000000)
1656 /*Signature0 field */
1657 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1658 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1659 /* Last byte is defined by architecture */
1660 #define MPI26_FW_HEADER_SIGNATURE0_BASE (0x5AEAA500)
1661 #define MPI26_FW_HEADER_SIGNATURE0_ARC_0 (0x5A)
1662 #define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00)
1663 #define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01)
1664 /* legacy (0x5AEAA55A) */
1665 #define MPI26_FW_HEADER_SIGNATURE0_ARC_3 (0x02)
1666 #define MPI26_FW_HEADER_SIGNATURE0 \
1667 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0)
1668 #define MPI26_FW_HEADER_SIGNATURE0_3516 \
1669 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1)
1670 #define MPI26_FW_HEADER_SIGNATURE0_4008 \
1671 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_3)
1673 /*Signature1 field */
1674 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1675 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1676 #define MPI26_FW_HEADER_SIGNATURE1 (0xA55AEAA5)
1678 /*Signature2 field */
1679 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1680 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1681 #define MPI26_FW_HEADER_SIGNATURE2 (0x5AA55AEA)
1683 /*defines for using the ProductID field */
1684 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1685 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1687 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1688 #define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1689 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1690 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1692 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1693 /*SAS ProductID Family bits */
1694 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1695 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1696 #define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021)
1697 #define MPI26_FW_HEADER_PID_FAMILY_3324_SAS (0x0028)
1698 #define MPI26_FW_HEADER_PID_FAMILY_3516_SAS (0x0031)
1700 /*use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1702 /*use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1704 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1705 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1706 #define MPI26_FW_HEADER_BOOTFLAGS_OFFSET (0x60)
1707 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1709 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1711 #define MPI2_FW_HEADER_SIZE (0x100)
1713 /*Extended Image Header */
1714 typedef struct _MPI2_EXT_IMAGE_HEADER {
1715 U8 ImageType; /*0x00 */
1716 U8 Reserved1; /*0x01 */
1717 U16 Reserved2; /*0x02 */
1718 U32 Checksum; /*0x04 */
1719 U32 ImageSize; /*0x08 */
1720 U32 NextImageHeaderOffset; /*0x0C */
1721 U32 PackageVersion; /*0x10 */
1722 U32 Reserved3; /*0x14 */
1723 U32 Reserved4; /*0x18 */
1724 U32 Reserved5; /*0x1C */
1725 U8 IdentifyString[32]; /*0x20 */
1726 } MPI2_EXT_IMAGE_HEADER, *PTR_MPI2_EXT_IMAGE_HEADER,
1727 Mpi2ExtImageHeader_t, *pMpi2ExtImageHeader_t;
1730 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1731 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1732 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1734 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1736 /*defines for the ImageType field */
1737 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1738 #define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1739 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1740 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1741 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1742 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1743 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1744 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1745 #define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09)
1746 #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
1747 #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF)
1749 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)
1751 /*FLASH Layout Extended Image Data */
1754 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1755 *one and check RegionsPerLayout at runtime.
1757 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1758 #define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1762 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1763 *one and check NumberOfLayouts at runtime.
1765 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1766 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1769 typedef struct _MPI2_FLASH_REGION {
1770 U8 RegionType; /*0x00 */
1771 U8 Reserved1; /*0x01 */
1772 U16 Reserved2; /*0x02 */
1773 U32 RegionOffset; /*0x04 */
1774 U32 RegionSize; /*0x08 */
1775 U32 Reserved3; /*0x0C */
1776 } MPI2_FLASH_REGION, *PTR_MPI2_FLASH_REGION,
1777 Mpi2FlashRegion_t, *pMpi2FlashRegion_t;
1779 typedef struct _MPI2_FLASH_LAYOUT {
1780 U32 FlashSize; /*0x00 */
1781 U32 Reserved1; /*0x04 */
1782 U32 Reserved2; /*0x08 */
1783 U32 Reserved3; /*0x0C */
1784 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS]; /*0x10 */
1785 } MPI2_FLASH_LAYOUT, *PTR_MPI2_FLASH_LAYOUT,
1786 Mpi2FlashLayout_t, *pMpi2FlashLayout_t;
1788 typedef struct _MPI2_FLASH_LAYOUT_DATA {
1789 U8 ImageRevision; /*0x00 */
1790 U8 Reserved1; /*0x01 */
1791 U8 SizeOfRegion; /*0x02 */
1792 U8 Reserved2; /*0x03 */
1793 U16 NumberOfLayouts; /*0x04 */
1794 U16 RegionsPerLayout; /*0x06 */
1795 U16 MinimumSectorAlignment; /*0x08 */
1796 U16 Reserved3; /*0x0A */
1797 U32 Reserved4; /*0x0C */
1798 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS]; /*0x10 */
1799 } MPI2_FLASH_LAYOUT_DATA, *PTR_MPI2_FLASH_LAYOUT_DATA,
1800 Mpi2FlashLayoutData_t, *pMpi2FlashLayoutData_t;
1802 /*defines for the RegionType field */
1803 #define MPI2_FLASH_REGION_UNUSED (0x00)
1804 #define MPI2_FLASH_REGION_FIRMWARE (0x01)
1805 #define MPI2_FLASH_REGION_BIOS (0x02)
1806 #define MPI2_FLASH_REGION_NVDATA (0x03)
1807 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1808 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1809 #define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1810 #define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1811 #define MPI2_FLASH_REGION_MEGARAID (0x09)
1812 #define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A)
1813 #define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK)
1814 #define MPI2_FLASH_REGION_CBB_BACKUP (0x0D)
1815 #define MPI2_FLASH_REGION_SBR (0x0E)
1816 #define MPI2_FLASH_REGION_SBR_BACKUP (0x0F)
1817 #define MPI2_FLASH_REGION_HIIM (0x10)
1818 #define MPI2_FLASH_REGION_HIIA (0x11)
1819 #define MPI2_FLASH_REGION_CTLR (0x12)
1820 #define MPI2_FLASH_REGION_IMR_FIRMWARE (0x13)
1821 #define MPI2_FLASH_REGION_MR_NVDATA (0x14)
1824 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1826 /*Supported Devices Extended Image Data */
1829 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1830 *one and check NumberOfDevices at runtime.
1832 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1833 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1836 typedef struct _MPI2_SUPPORTED_DEVICE {
1837 U16 DeviceID; /*0x00 */
1838 U16 VendorID; /*0x02 */
1839 U16 DeviceIDMask; /*0x04 */
1840 U16 Reserved1; /*0x06 */
1841 U8 LowPCIRev; /*0x08 */
1842 U8 HighPCIRev; /*0x09 */
1843 U16 Reserved2; /*0x0A */
1844 U32 Reserved3; /*0x0C */
1845 } MPI2_SUPPORTED_DEVICE, *PTR_MPI2_SUPPORTED_DEVICE,
1846 Mpi2SupportedDevice_t, *pMpi2SupportedDevice_t;
1848 typedef struct _MPI2_SUPPORTED_DEVICES_DATA {
1849 U8 ImageRevision; /*0x00 */
1850 U8 Reserved1; /*0x01 */
1851 U8 NumberOfDevices; /*0x02 */
1852 U8 Reserved2; /*0x03 */
1853 U32 Reserved3; /*0x04 */
1854 MPI2_SUPPORTED_DEVICE
1855 SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES];/*0x08 */
1856 } MPI2_SUPPORTED_DEVICES_DATA, *PTR_MPI2_SUPPORTED_DEVICES_DATA,
1857 Mpi2SupportedDevicesData_t, *pMpi2SupportedDevicesData_t;
1860 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1862 /*Init Extended Image Data */
1864 typedef struct _MPI2_INIT_IMAGE_FOOTER {
1865 U32 BootFlags; /*0x00 */
1866 U32 ImageSize; /*0x04 */
1867 U32 Signature0; /*0x08 */
1868 U32 Signature1; /*0x0C */
1869 U32 Signature2; /*0x10 */
1870 U32 ResetVector; /*0x14 */
1871 } MPI2_INIT_IMAGE_FOOTER, *PTR_MPI2_INIT_IMAGE_FOOTER,
1872 Mpi2InitImageFooter_t, *pMpi2InitImageFooter_t;
1874 /*defines for the BootFlags field */
1875 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1877 /*defines for the ImageSize field */
1878 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1880 /*defines for the Signature0 field */
1881 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1882 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1884 /*defines for the Signature1 field */
1885 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1886 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1888 /*defines for the Signature2 field */
1889 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1890 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1892 /*Signature fields as individual bytes */
1893 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1894 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1895 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1896 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1898 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1899 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1900 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1901 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1903 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1904 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1905 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1906 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1908 /*defines for the ResetVector field */
1909 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1912 /* Encrypted Hash Extended Image Data */
1914 typedef struct _MPI25_ENCRYPTED_HASH_ENTRY {
1915 U8 HashImageType; /* 0x00 */
1916 U8 HashAlgorithm; /* 0x01 */
1917 U8 EncryptionAlgorithm; /* 0x02 */
1918 U8 Reserved1; /* 0x03 */
1919 U32 Reserved2; /* 0x04 */
1920 U32 EncryptedHash[1]; /* 0x08 */ /* variable length */
1921 } MPI25_ENCRYPTED_HASH_ENTRY, *PTR_MPI25_ENCRYPTED_HASH_ENTRY,
1922 Mpi25EncryptedHashEntry_t, *pMpi25EncryptedHashEntry_t;
1924 /* values for HashImageType */
1925 #define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00)
1926 #define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01)
1927 #define MPI25_HASH_IMAGE_TYPE_BIOS (0x02)
1929 /* values for HashAlgorithm */
1930 #define MPI25_HASH_ALGORITHM_UNUSED (0x00)
1931 #define MPI25_HASH_ALGORITHM_SHA256 (0x01)
1933 /* values for EncryptionAlgorithm */
1934 #define MPI25_ENCRYPTION_ALG_UNUSED (0x00)
1935 #define MPI25_ENCRYPTION_ALG_RSA256 (0x01)
1937 typedef struct _MPI25_ENCRYPTED_HASH_DATA {
1938 U8 ImageVersion; /* 0x00 */
1939 U8 NumHash; /* 0x01 */
1940 U16 Reserved1; /* 0x02 */
1941 U32 Reserved2; /* 0x04 */
1942 MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */
1943 } MPI25_ENCRYPTED_HASH_DATA, *PTR_MPI25_ENCRYPTED_HASH_DATA,
1944 Mpi25EncryptedHashData_t, *pMpi25EncryptedHashData_t;
1947 /****************************************************************************
1948 * PowerManagementControl message
1949 ****************************************************************************/
1951 /*PowerManagementControl Request message */
1952 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1953 U8 Feature; /*0x00 */
1954 U8 Reserved1; /*0x01 */
1955 U8 ChainOffset; /*0x02 */
1956 U8 Function; /*0x03 */
1957 U16 Reserved2; /*0x04 */
1958 U8 Reserved3; /*0x06 */
1959 U8 MsgFlags; /*0x07 */
1962 U16 Reserved4; /*0x0A */
1963 U8 Parameter1; /*0x0C */
1964 U8 Parameter2; /*0x0D */
1965 U8 Parameter3; /*0x0E */
1966 U8 Parameter4; /*0x0F */
1967 U32 Reserved5; /*0x10 */
1968 U32 Reserved6; /*0x14 */
1969 } MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1970 Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t;
1972 /*defines for the Feature field */
1973 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1974 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1975 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /*obsolete */
1976 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1977 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05)
1978 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1979 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1981 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1982 /*Parameter1 contains a PHY number */
1983 /*Parameter2 indicates power condition action using these defines */
1984 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1985 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1986 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1987 /*Parameter3 and Parameter4 are reserved */
1989 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1991 /*Parameter1 contains SAS port width modulation group number */
1992 /*Parameter2 indicates IOC action using these defines */
1993 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1994 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1995 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1996 /*Parameter3 indicates desired modulation level using these defines */
1997 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1998 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1999 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
2000 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
2001 /*Parameter4 is reserved */
2003 /*this next set (_PCIE_LINK) is obsolete */
2004 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
2005 /*Parameter1 indicates desired PCIe link speed using these defines */
2006 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /*obsolete */
2007 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /*obsolete */
2008 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /*obsolete */
2009 /*Parameter2 indicates desired PCIe link width using these defines */
2010 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /*obsolete */
2011 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /*obsolete */
2012 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /*obsolete */
2013 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /*obsolete */
2014 /*Parameter3 and Parameter4 are reserved */
2016 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
2017 /*Parameter1 indicates desired IOC hardware clock speed using these defines */
2018 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
2019 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
2020 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
2021 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
2022 /*Parameter2, Parameter3, and Parameter4 are reserved */
2024 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/
2025 /*Parameter1 indicates host action regarding global power management mode */
2026 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01)
2027 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02)
2028 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03)
2029 /*Parameter2 indicates the requested global power management mode */
2030 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01)
2031 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08)
2032 #define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40)
2033 /*Parameter3 and Parameter4 are reserved */
2035 /*PowerManagementControl Reply message */
2036 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
2037 U8 Feature; /*0x00 */
2038 U8 Reserved1; /*0x01 */
2039 U8 MsgLength; /*0x02 */
2040 U8 Function; /*0x03 */
2041 U16 Reserved2; /*0x04 */
2042 U8 Reserved3; /*0x06 */
2043 U8 MsgFlags; /*0x07 */
2046 U16 Reserved4; /*0x0A */
2047 U16 Reserved5; /*0x0C */
2048 U16 IOCStatus; /*0x0E */
2049 U32 IOCLogInfo; /*0x10 */
2050 } MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
2051 Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t;
2053 /****************************************************************************
2054 * IO Unit Control messages (MPI v2.6 and later only.)
2055 ****************************************************************************/
2057 /* IO Unit Control Request Message */
2058 typedef struct _MPI26_IOUNIT_CONTROL_REQUEST {
2059 U8 Operation; /* 0x00 */
2060 U8 Reserved1; /* 0x01 */
2061 U8 ChainOffset; /* 0x02 */
2062 U8 Function; /* 0x03 */
2063 U16 DevHandle; /* 0x04 */
2064 U8 IOCParameter; /* 0x06 */
2065 U8 MsgFlags; /* 0x07 */
2066 U8 VP_ID; /* 0x08 */
2067 U8 VF_ID; /* 0x09 */
2068 U16 Reserved3; /* 0x0A */
2069 U16 Reserved4; /* 0x0C */
2070 U8 PhyNum; /* 0x0E */
2071 U8 PrimFlags; /* 0x0F */
2072 U32 Primitive; /* 0x10 */
2073 U8 LookupMethod; /* 0x14 */
2074 U8 Reserved5; /* 0x15 */
2075 U16 SlotNumber; /* 0x16 */
2076 U64 LookupAddress; /* 0x18 */
2077 U32 IOCParameterValue; /* 0x20 */
2078 U32 Reserved7; /* 0x24 */
2079 U32 Reserved8; /* 0x28 */
2080 } MPI26_IOUNIT_CONTROL_REQUEST,
2081 *PTR_MPI26_IOUNIT_CONTROL_REQUEST,
2082 Mpi26IoUnitControlRequest_t,
2083 *pMpi26IoUnitControlRequest_t;
2085 /* values for the Operation field */
2086 #define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02)
2087 #define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06)
2088 #define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07)
2089 #define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08)
2090 #define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09)
2091 #define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A)
2092 #define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B)
2093 #define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D)
2094 #define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E)
2095 #define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F)
2096 #define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10)
2097 #define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11)
2098 #define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12)
2099 #define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13)
2100 #define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14)
2101 #define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15)
2102 #define MPI26_CTRL_OP_SHUTDOWN (0x16)
2103 #define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17)
2104 #define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18)
2105 #define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19)
2106 #define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT (0x1A)
2107 #define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT (0x1B)
2108 #define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80)
2110 /* values for the PrimFlags field */
2111 #define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08)
2112 #define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02)
2113 #define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01)
2115 /* values for the LookupMethod field */
2116 #define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01)
2117 #define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02)
2118 #define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
2121 /* IO Unit Control Reply Message */
2122 typedef struct _MPI26_IOUNIT_CONTROL_REPLY {
2123 U8 Operation; /* 0x00 */
2124 U8 Reserved1; /* 0x01 */
2125 U8 MsgLength; /* 0x02 */
2126 U8 Function; /* 0x03 */
2127 U16 DevHandle; /* 0x04 */
2128 U8 IOCParameter; /* 0x06 */
2129 U8 MsgFlags; /* 0x07 */
2130 U8 VP_ID; /* 0x08 */
2131 U8 VF_ID; /* 0x09 */
2132 U16 Reserved3; /* 0x0A */
2133 U16 Reserved4; /* 0x0C */
2134 U16 IOCStatus; /* 0x0E */
2135 U32 IOCLogInfo; /* 0x10 */
2136 } MPI26_IOUNIT_CONTROL_REPLY,
2137 *PTR_MPI26_IOUNIT_CONTROL_REPLY,
2138 Mpi26IoUnitControlReply_t,
2139 *pMpi26IoUnitControlReply_t;
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