drivers/scsi/pm8001/pm8001_hwi.c

   1 /*
   2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm8001_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 /**
  47  * read_main_config_table - read the configure table and save it.
  48  * @pm8001_ha: our hba card information
  49  */
  50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  51 {
  52         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  53         pm8001_ha->main_cfg_tbl.pm8001_tbl.signature    =
  54                                 pm8001_mr32(address, 0x00);
  55         pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
  56                                 pm8001_mr32(address, 0x04);
  57         pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
  58                                 pm8001_mr32(address, 0x08);
  59         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io   =
  60                                 pm8001_mr32(address, 0x0C);
  61         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl      =
  62                                 pm8001_mr32(address, 0x10);
  63         pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
  64                                 pm8001_mr32(address, 0x14);
  65         pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset   =
  66                                 pm8001_mr32(address, 0x18);
  67         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
  68                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
  69         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
  70                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
  71         pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag        =
  72                 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  73
  74         /* read analog Setting offset from the configuration table */
  75         pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
  76                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  77
  78         /* read Error Dump Offset and Length */
  79         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
  80                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  81         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
  82                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  83         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
  84                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  85         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
  86                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  87 }
  88
  89 /**
  90  * read_general_status_table - read the general status table and save it.
  91  * @pm8001_ha: our hba card information
  92  */
  93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  94 {
  95         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  96         pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate   =
  97                                 pm8001_mr32(address, 0x00);
  98         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0   =
  99                                 pm8001_mr32(address, 0x04);
 100         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1   =
 101                                 pm8001_mr32(address, 0x08);
 102         pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt          =
 103                                 pm8001_mr32(address, 0x0C);
 104         pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt           =
 105                                 pm8001_mr32(address, 0x10);
 106         pm8001_ha->gs_tbl.pm8001_tbl.rsvd               =
 107                                 pm8001_mr32(address, 0x14);
 108         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0]       =
 109                                 pm8001_mr32(address, 0x18);
 110         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1]       =
 111                                 pm8001_mr32(address, 0x1C);
 112         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2]       =
 113                                 pm8001_mr32(address, 0x20);
 114         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3]       =
 115                                 pm8001_mr32(address, 0x24);
 116         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4]       =
 117                                 pm8001_mr32(address, 0x28);
 118         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5]       =
 119                                 pm8001_mr32(address, 0x2C);
 120         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6]       =
 121                                 pm8001_mr32(address, 0x30);
 122         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7]       =
 123                                 pm8001_mr32(address, 0x34);
 124         pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val     =
 125                                 pm8001_mr32(address, 0x38);
 126         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0]           =
 127                                 pm8001_mr32(address, 0x3C);
 128         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1]           =
 129                                 pm8001_mr32(address, 0x40);
 130         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0]        =
 131                                 pm8001_mr32(address, 0x44);
 132         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1]        =
 133                                 pm8001_mr32(address, 0x48);
 134         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2]        =
 135                                 pm8001_mr32(address, 0x4C);
 136         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3]        =
 137                                 pm8001_mr32(address, 0x50);
 138         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4]        =
 139                                 pm8001_mr32(address, 0x54);
 140         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5]        =
 141                                 pm8001_mr32(address, 0x58);
 142         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6]        =
 143                                 pm8001_mr32(address, 0x5C);
 144         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7]        =
 145                                 pm8001_mr32(address, 0x60);
 146 }
 147
 148 /**
 149  * read_inbnd_queue_table - read the inbound queue table and save it.
 150  * @pm8001_ha: our hba card information
 151  */
 152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 153 {
 154         int i;
 155         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 156         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 157                 u32 offset = i * 0x20;
 158                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 159                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 160                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 161                         pm8001_mr32(address, (offset + 0x18));
 162         }
 163 }
 164
 165 /**
 166  * read_outbnd_queue_table - read the outbound queue table and save it.
 167  * @pm8001_ha: our hba card information
 168  */
 169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 170 {
 171         int i;
 172         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 173         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 174                 u32 offset = i * 0x24;
 175                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 176                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 177                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 178                         pm8001_mr32(address, (offset + 0x18));
 179         }
 180 }
 181
 182 /**
 183  * init_default_table_values - init the default table.
 184  * @pm8001_ha: our hba card information
 185  */
 186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 187 {
 188         int i;
 189         u32 offsetib, offsetob;
 190         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 191         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 192
 193         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd          = 0;
 194         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3     = 0;
 195         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7     = 0;
 196         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3    = 0;
 197         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7    = 0;
 198         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
 199                                                                          0;
 200         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
 201                                                                          0;
 202         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
 203         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
 204         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
 205         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
 206
 207         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr         =
 208                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 209         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr         =
 210                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 211         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size               =
 212                 PM8001_EVENT_LOG_SIZE;
 213         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option             = 0x01;
 214         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr     =
 215                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 216         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr     =
 217                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 218         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size           =
 219                 PM8001_EVENT_LOG_SIZE;
 220         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option         = 0x01;
 221         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt          = 0x01;
 222         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 223                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 224                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 225                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 226                         pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
 227                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 228                 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
 229                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 230                         (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
 231                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 232                         pm8001_ha->memoryMap.region[IB + i].total_len;
 233                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 234                         pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
 235                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 236                         pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
 237                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 238                         pm8001_ha->memoryMap.region[CI + i].virt_ptr;
 239                 offsetib = i * 0x20;
 240                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 241                         get_pci_bar_index(pm8001_mr32(addressib,
 242                                 (offsetib + 0x14)));
 243                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 244                         pm8001_mr32(addressib, (offsetib + 0x18));
 245                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 246                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 247         }
 248         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 249                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 250                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 251                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 252                         pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
 253                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 254                         pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
 255                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 256                         (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
 257                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 258                         pm8001_ha->memoryMap.region[OB + i].total_len;
 259                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 260                         pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
 261                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 262                         pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
 263                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay       =
 264                         0 | (10 << 16) | (i << 24);
 265                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 266                         pm8001_ha->memoryMap.region[PI + i].virt_ptr;
 267                 offsetob = i * 0x24;
 268                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 269                         get_pci_bar_index(pm8001_mr32(addressob,
 270                         offsetob + 0x14));
 271                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 272                         pm8001_mr32(addressob, (offsetob + 0x18));
 273                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 274                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 275         }
 276 }
 277
 278 /**
 279  * update_main_config_table - update the main default table to the HBA.
 280  * @pm8001_ha: our hba card information
 281  */
 282 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 283 {
 284         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 285         pm8001_mw32(address, 0x24,
 286                 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
 287         pm8001_mw32(address, 0x28,
 288                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
 289         pm8001_mw32(address, 0x2C,
 290                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
 291         pm8001_mw32(address, 0x30,
 292                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
 293         pm8001_mw32(address, 0x34,
 294                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
 295         pm8001_mw32(address, 0x38,
 296                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 297                                         outbound_tgt_ITNexus_event_pid0_3);
 298         pm8001_mw32(address, 0x3C,
 299                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 300                                         outbound_tgt_ITNexus_event_pid4_7);
 301         pm8001_mw32(address, 0x40,
 302                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 303                                         outbound_tgt_ssp_event_pid0_3);
 304         pm8001_mw32(address, 0x44,
 305                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 306                                         outbound_tgt_ssp_event_pid4_7);
 307         pm8001_mw32(address, 0x48,
 308                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 309                                         outbound_tgt_smp_event_pid0_3);
 310         pm8001_mw32(address, 0x4C,
 311                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 312                                         outbound_tgt_smp_event_pid4_7);
 313         pm8001_mw32(address, 0x50,
 314                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
 315         pm8001_mw32(address, 0x54,
 316                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
 317         pm8001_mw32(address, 0x58,
 318                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
 319         pm8001_mw32(address, 0x5C,
 320                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
 321         pm8001_mw32(address, 0x60,
 322                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
 323         pm8001_mw32(address, 0x64,
 324                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
 325         pm8001_mw32(address, 0x68,
 326                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
 327         pm8001_mw32(address, 0x6C,
 328                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
 329         pm8001_mw32(address, 0x70,
 330                 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
 331 }
 332
 333 /**
 334  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 335  * @pm8001_ha: our hba card information
 336  */
 337 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 338                                      int number)
 339 {
 340         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 341         u16 offset = number * 0x20;
 342         pm8001_mw32(address, offset + 0x00,
 343                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 344         pm8001_mw32(address, offset + 0x04,
 345                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 346         pm8001_mw32(address, offset + 0x08,
 347                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 348         pm8001_mw32(address, offset + 0x0C,
 349                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 350         pm8001_mw32(address, offset + 0x10,
 351                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 352 }
 353
 354 /**
 355  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 356  * @pm8001_ha: our hba card information
 357  */
 358 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 359                                       int number)
 360 {
 361         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 362         u16 offset = number * 0x24;
 363         pm8001_mw32(address, offset + 0x00,
 364                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 365         pm8001_mw32(address, offset + 0x04,
 366                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 367         pm8001_mw32(address, offset + 0x08,
 368                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 369         pm8001_mw32(address, offset + 0x0C,
 370                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 371         pm8001_mw32(address, offset + 0x10,
 372                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 373         pm8001_mw32(address, offset + 0x1C,
 374                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 375 }
 376
 377 /**
 378  * pm8001_bar4_shift - function is called to shift BAR base address
 379  * @pm8001_ha : our hba card infomation
 380  * @shiftValue : shifting value in memory bar.
 381  */
 382 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
 383 {
 384         u32 regVal;
 385         unsigned long start;
 386
 387         /* program the inbound AXI translation Lower Address */
 388         pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
 389
 390         /* confirm the setting is written */
 391         start = jiffies + HZ; /* 1 sec */
 392         do {
 393                 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
 394         } while ((regVal != shiftValue) && time_before(jiffies, start));
 395
 396         if (regVal != shiftValue) {
 397                 PM8001_INIT_DBG(pm8001_ha,
 398                         pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
 399                         " = 0x%x\n", regVal));
 400                 return -1;
 401         }
 402         return 0;
 403 }
 404
 405 /**
 406  * mpi_set_phys_g3_with_ssc
 407  * @pm8001_ha: our hba card information
 408  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
 409  */
 410 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
 411                                      u32 SSCbit)
 412 {
 413         u32 value, offset, i;
 414         unsigned long flags;
 415
 416 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
 417 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
 418 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
 419 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
 420 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
 421 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
 422 #define SNW3_PHY_CAPABILITIES_PARITY 31
 423
 424    /*
 425     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
 426     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
 427     */
 428         spin_lock_irqsave(&pm8001_ha->lock, flags);
 429         if (-1 == pm8001_bar4_shift(pm8001_ha,
 430                                 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
 431                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 432                 return;
 433         }
 434
 435         for (i = 0; i < 4; i++) {
 436                 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
 437                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 438         }
 439         /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
 440         if (-1 == pm8001_bar4_shift(pm8001_ha,
 441                                 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
 442                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 443                 return;
 444         }
 445         for (i = 4; i < 8; i++) {
 446                 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 447                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 448         }
 449         /*************************************************************
 450         Change the SSC upspreading value to 0x0 so that upspreading is disabled.
 451         Device MABC SMOD0 Controls
 452         Address: (via MEMBASE-III):
 453         Using shifted destination address 0x0_0000: with Offset 0xD8
 454
 455         31:28 R/W Reserved Do not change
 456         27:24 R/W SAS_SMOD_SPRDUP 0000
 457         23:20 R/W SAS_SMOD_SPRDDN 0000
 458         19:0  R/W  Reserved Do not change
 459         Upon power-up this register will read as 0x8990c016,
 460         and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
 461         so that the written value will be 0x8090c016.
 462         This will ensure only down-spreading SSC is enabled on the SPC.
 463         *************************************************************/
 464         value = pm8001_cr32(pm8001_ha, 2, 0xd8);
 465         pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
 466
 467         /*set the shifted destination address to 0x0 to avoid error operation */
 468         pm8001_bar4_shift(pm8001_ha, 0x0);
 469         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 470         return;
 471 }
 472
 473 /**
 474  * mpi_set_open_retry_interval_reg
 475  * @pm8001_ha: our hba card information
 476  * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
 477  */
 478 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
 479                                             u32 interval)
 480 {
 481         u32 offset;
 482         u32 value;
 483         u32 i;
 484         unsigned long flags;
 485
 486 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
 487 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
 488 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
 489 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
 490 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
 491
 492         value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
 493         spin_lock_irqsave(&pm8001_ha->lock, flags);
 494         /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
 495         if (-1 == pm8001_bar4_shift(pm8001_ha,
 496                              OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
 497                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 498                 return;
 499         }
 500         for (i = 0; i < 4; i++) {
 501                 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
 502                 pm8001_cw32(pm8001_ha, 2, offset, value);
 503         }
 504
 505         if (-1 == pm8001_bar4_shift(pm8001_ha,
 506                              OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
 507                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 508                 return;
 509         }
 510         for (i = 4; i < 8; i++) {
 511                 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 512                 pm8001_cw32(pm8001_ha, 2, offset, value);
 513         }
 514         /*set the shifted destination address to 0x0 to avoid error operation */
 515         pm8001_bar4_shift(pm8001_ha, 0x0);
 516         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 517         return;
 518 }
 519
 520 /**
 521  * mpi_init_check - check firmware initialization status.
 522  * @pm8001_ha: our hba card information
 523  */
 524 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 525 {
 526         u32 max_wait_count;
 527         u32 value;
 528         u32 gst_len_mpistate;
 529         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 530         table is updated */
 531         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
 532         /* wait until Inbound DoorBell Clear Register toggled */
 533         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 534         do {
 535                 udelay(1);
 536                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 537                 value &= SPC_MSGU_CFG_TABLE_UPDATE;
 538         } while ((value != 0) && (--max_wait_count));
 539
 540         if (!max_wait_count)
 541                 return -1;
 542         /* check the MPI-State for initialization */
 543         gst_len_mpistate =
 544                 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 545                 GST_GSTLEN_MPIS_OFFSET);
 546         if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
 547                 return -1;
 548         /* check MPI Initialization error */
 549         gst_len_mpistate = gst_len_mpistate >> 16;
 550         if (0x0000 != gst_len_mpistate)
 551                 return -1;
 552         return 0;
 553 }
 554
 555 /**
 556  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 557  * @pm8001_ha: our hba card information
 558  */
 559 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 560 {
 561         u32 value, value1;
 562         u32 max_wait_count;
 563         /* check error state */
 564         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 565         value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 566         /* check AAP error */
 567         if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
 568                 /* error state */
 569                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 570                 return -1;
 571         }
 572
 573         /* check IOP error */
 574         if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
 575                 /* error state */
 576                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 577                 return -1;
 578         }
 579
 580         /* bit 4-31 of scratch pad1 should be zeros if it is not
 581         in error state*/
 582         if (value & SCRATCH_PAD1_STATE_MASK) {
 583                 /* error case */
 584                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 585                 return -1;
 586         }
 587
 588         /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
 589         in error state */
 590         if (value1 & SCRATCH_PAD2_STATE_MASK) {
 591                 /* error case */
 592                 return -1;
 593         }
 594
 595         max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
 596
 597         /* wait until scratch pad 1 and 2 registers in ready state  */
 598         do {
 599                 udelay(1);
 600                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 601                         & SCRATCH_PAD1_RDY;
 602                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 603                         & SCRATCH_PAD2_RDY;
 604                 if ((--max_wait_count) == 0)
 605                         return -1;
 606         } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
 607         return 0;
 608 }
 609
 610 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 611 {
 612         void __iomem *base_addr;
 613         u32     value;
 614         u32     offset;
 615         u32     pcibar;
 616         u32     pcilogic;
 617
 618         value = pm8001_cr32(pm8001_ha, 0, 0x44);
 619         offset = value & 0x03FFFFFF;
 620         PM8001_INIT_DBG(pm8001_ha,
 621                 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
 622         pcilogic = (value & 0xFC000000) >> 26;
 623         pcibar = get_pci_bar_index(pcilogic);
 624         PM8001_INIT_DBG(pm8001_ha,
 625                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 626         pm8001_ha->main_cfg_tbl_addr = base_addr =
 627                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 628         pm8001_ha->general_stat_tbl_addr =
 629                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
 630         pm8001_ha->inbnd_q_tbl_addr =
 631                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
 632         pm8001_ha->outbnd_q_tbl_addr =
 633                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
 634 }
 635
 636 /**
 637  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 638  * @pm8001_ha: our hba card information
 639  */
 640 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
 641 {
 642         u8 i = 0;
 643         u16 deviceid;
 644         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 645         /* 8081 controllers need BAR shift to access MPI space
 646         * as this is shared with BIOS data */
 647         if (deviceid == 0x8081 || deviceid == 0x0042) {
 648                 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 649                         PM8001_FAIL_DBG(pm8001_ha,
 650                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 651                                         GSM_SM_BASE));
 652                         return -1;
 653                 }
 654         }
 655         /* check the firmware status */
 656         if (-1 == check_fw_ready(pm8001_ha)) {
 657                 PM8001_FAIL_DBG(pm8001_ha,
 658                         pm8001_printk("Firmware is not ready!\n"));
 659                 return -EBUSY;
 660         }
 661
 662         /* Initialize pci space address eg: mpi offset */
 663         init_pci_device_addresses(pm8001_ha);
 664         init_default_table_values(pm8001_ha);
 665         read_main_config_table(pm8001_ha);
 666         read_general_status_table(pm8001_ha);
 667         read_inbnd_queue_table(pm8001_ha);
 668         read_outbnd_queue_table(pm8001_ha);
 669         /* update main config table ,inbound table and outbound table */
 670         update_main_config_table(pm8001_ha);
 671         for (i = 0; i < PM8001_MAX_INB_NUM; i++)
 672                 update_inbnd_queue_table(pm8001_ha, i);
 673         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++)
 674                 update_outbnd_queue_table(pm8001_ha, i);
 675         /* 8081 controller donot require these operations */
 676         if (deviceid != 0x8081 && deviceid != 0x0042) {
 677                 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
 678                 /* 7->130ms, 34->500ms, 119->1.5s */
 679                 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
 680         }
 681         /* notify firmware update finished and check initialization status */
 682         if (0 == mpi_init_check(pm8001_ha)) {
 683                 PM8001_INIT_DBG(pm8001_ha,
 684                         pm8001_printk("MPI initialize successful!\n"));
 685         } else
 686                 return -EBUSY;
 687         /*This register is a 16-bit timer with a resolution of 1us. This is the
 688         timer used for interrupt delay/coalescing in the PCIe Application Layer.
 689         Zero is not a valid value. A value of 1 in the register will cause the
 690         interrupts to be normal. A value greater than 1 will cause coalescing
 691         delays.*/
 692         pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
 693         pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
 694         return 0;
 695 }
 696
 697 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 698 {
 699         u32 max_wait_count;
 700         u32 value;
 701         u32 gst_len_mpistate;
 702         u16 deviceid;
 703         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 704         if (deviceid == 0x8081 || deviceid == 0x0042) {
 705                 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 706                         PM8001_FAIL_DBG(pm8001_ha,
 707                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 708                                         GSM_SM_BASE));
 709                         return -1;
 710                 }
 711         }
 712         init_pci_device_addresses(pm8001_ha);
 713         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 714         table is stop */
 715         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
 716
 717         /* wait until Inbound DoorBell Clear Register toggled */
 718         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 719         do {
 720                 udelay(1);
 721                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 722                 value &= SPC_MSGU_CFG_TABLE_RESET;
 723         } while ((value != 0) && (--max_wait_count));
 724
 725         if (!max_wait_count) {
 726                 PM8001_FAIL_DBG(pm8001_ha,
 727                         pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
 728                 return -1;
 729         }
 730
 731         /* check the MPI-State for termination in progress */
 732         /* wait until Inbound DoorBell Clear Register toggled */
 733         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 734         do {
 735                 udelay(1);
 736                 gst_len_mpistate =
 737                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 738                         GST_GSTLEN_MPIS_OFFSET);
 739                 if (GST_MPI_STATE_UNINIT ==
 740                         (gst_len_mpistate & GST_MPI_STATE_MASK))
 741                         break;
 742         } while (--max_wait_count);
 743         if (!max_wait_count) {
 744                 PM8001_FAIL_DBG(pm8001_ha,
 745                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
 746                                 gst_len_mpistate & GST_MPI_STATE_MASK));
 747                 return -1;
 748         }
 749         return 0;
 750 }
 751
 752 /**
 753  * soft_reset_ready_check - Function to check FW is ready for soft reset.
 754  * @pm8001_ha: our hba card information
 755  */
 756 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
 757 {
 758         u32 regVal, regVal1, regVal2;
 759         if (mpi_uninit_check(pm8001_ha) != 0) {
 760                 PM8001_FAIL_DBG(pm8001_ha,
 761                         pm8001_printk("MPI state is not ready\n"));
 762                 return -1;
 763         }
 764         /* read the scratch pad 2 register bit 2 */
 765         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 766                 & SCRATCH_PAD2_FWRDY_RST;
 767         if (regVal == SCRATCH_PAD2_FWRDY_RST) {
 768                 PM8001_INIT_DBG(pm8001_ha,
 769                         pm8001_printk("Firmware is ready for reset .\n"));
 770         } else {
 771                 unsigned long flags;
 772                 /* Trigger NMI twice via RB6 */
 773                 spin_lock_irqsave(&pm8001_ha->lock, flags);
 774                 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
 775                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 776                         PM8001_FAIL_DBG(pm8001_ha,
 777                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 778                                         RB6_ACCESS_REG));
 779                         return -1;
 780                 }
 781                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
 782                         RB6_MAGIC_NUMBER_RST);
 783                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
 784                 /* wait for 100 ms */
 785                 mdelay(100);
 786                 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
 787                         SCRATCH_PAD2_FWRDY_RST;
 788                 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
 789                         regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 790                         regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 791                         PM8001_FAIL_DBG(pm8001_ha,
 792                                 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
 793                                 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
 794                                 regVal1, regVal2));
 795                         PM8001_FAIL_DBG(pm8001_ha,
 796                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
 797                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
 798                         PM8001_FAIL_DBG(pm8001_ha,
 799                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
 800                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
 801                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 802                         return -1;
 803                 }
 804                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 805         }
 806         return 0;
 807 }
 808
 809 /**
 810  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 811  * the FW register status to the originated status.
 812  * @pm8001_ha: our hba card information
 813  */
 814 static int
 815 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
 816 {
 817         u32     regVal, toggleVal;
 818         u32     max_wait_count;
 819         u32     regVal1, regVal2, regVal3;
 820         u32     signature = 0x252acbcd; /* for host scratch pad0 */
 821         unsigned long flags;
 822
 823         /* step1: Check FW is ready for soft reset */
 824         if (soft_reset_ready_check(pm8001_ha) != 0) {
 825                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
 826                 return -1;
 827         }
 828
 829         /* step 2: clear NMI status register on AAP1 and IOP, write the same
 830         value to clear */
 831         /* map 0x60000 to BAR4(0x20), BAR2(win) */
 832         spin_lock_irqsave(&pm8001_ha->lock, flags);
 833         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
 834                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 835                 PM8001_FAIL_DBG(pm8001_ha,
 836                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 837                         MBIC_AAP1_ADDR_BASE));
 838                 return -1;
 839         }
 840         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
 841         PM8001_INIT_DBG(pm8001_ha,
 842                 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
 843         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
 844         /* map 0x70000 to BAR4(0x20), BAR2(win) */
 845         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
 846                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 847                 PM8001_FAIL_DBG(pm8001_ha,
 848                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 849                         MBIC_IOP_ADDR_BASE));
 850                 return -1;
 851         }
 852         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
 853         PM8001_INIT_DBG(pm8001_ha,
 854                 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
 855         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
 856
 857         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
 858         PM8001_INIT_DBG(pm8001_ha,
 859                 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
 860         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
 861
 862         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
 863         PM8001_INIT_DBG(pm8001_ha,
 864                 pm8001_printk("PCIE - Event Interrupt  = 0x%x\n", regVal));
 865         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
 866
 867         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
 868         PM8001_INIT_DBG(pm8001_ha,
 869                 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
 870         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
 871
 872         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
 873         PM8001_INIT_DBG(pm8001_ha,
 874                 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
 875         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
 876
 877         /* read the scratch pad 1 register bit 2 */
 878         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 879                 & SCRATCH_PAD1_RST;
 880         toggleVal = regVal ^ SCRATCH_PAD1_RST;
 881
 882         /* set signature in host scratch pad0 register to tell SPC that the
 883         host performs the soft reset */
 884         pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
 885
 886         /* read required registers for confirmming */
 887         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 888         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 889                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 890                 PM8001_FAIL_DBG(pm8001_ha,
 891                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 892                         GSM_ADDR_BASE));
 893                 return -1;
 894         }
 895         PM8001_INIT_DBG(pm8001_ha,
 896                 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
 897                 " Reset = 0x%x\n",
 898                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 899
 900         /* step 3: host read GSM Configuration and Reset register */
 901         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 902         /* Put those bits to low */
 903         /* GSM XCBI offset = 0x70 0000
 904         0x00 Bit 13 COM_SLV_SW_RSTB 1
 905         0x00 Bit 12 QSSP_SW_RSTB 1
 906         0x00 Bit 11 RAAE_SW_RSTB 1
 907         0x00 Bit 9 RB_1_SW_RSTB 1
 908         0x00 Bit 8 SM_SW_RSTB 1
 909         */
 910         regVal &= ~(0x00003b00);
 911         /* host write GSM Configuration and Reset register */
 912         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 913         PM8001_INIT_DBG(pm8001_ha,
 914                 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
 915                 "Configuration and Reset is set to = 0x%x\n",
 916                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 917
 918         /* step 4: */
 919         /* disable GSM - Read Address Parity Check */
 920         regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 921         PM8001_INIT_DBG(pm8001_ha,
 922                 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
 923                 "Enable = 0x%x\n", regVal1));
 924         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
 925         PM8001_INIT_DBG(pm8001_ha,
 926                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 927                 "is set to = 0x%x\n",
 928                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 929
 930         /* disable GSM - Write Address Parity Check */
 931         regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 932         PM8001_INIT_DBG(pm8001_ha,
 933                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 934                 " Enable = 0x%x\n", regVal2));
 935         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
 936         PM8001_INIT_DBG(pm8001_ha,
 937                 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
 938                 "Enable is set to = 0x%x\n",
 939                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 940
 941         /* disable GSM - Write Data Parity Check */
 942         regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 943         PM8001_INIT_DBG(pm8001_ha,
 944                 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
 945                 " Enable = 0x%x\n", regVal3));
 946         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
 947         PM8001_INIT_DBG(pm8001_ha,
 948                 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
 949                 "is set to = 0x%x\n",
 950         pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 951
 952         /* step 5: delay 10 usec */
 953         udelay(10);
 954         /* step 5-b: set GPIO-0 output control to tristate anyway */
 955         if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
 956                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 957                 PM8001_INIT_DBG(pm8001_ha,
 958                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 959                                 GPIO_ADDR_BASE));
 960                 return -1;
 961         }
 962         regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
 963                 PM8001_INIT_DBG(pm8001_ha,
 964                                 pm8001_printk("GPIO Output Control Register:"
 965                                 " = 0x%x\n", regVal));
 966         /* set GPIO-0 output control to tri-state */
 967         regVal &= 0xFFFFFFFC;
 968         pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
 969
 970         /* Step 6: Reset the IOP and AAP1 */
 971         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 972         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 973                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 974                 PM8001_FAIL_DBG(pm8001_ha,
 975                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 976                         SPC_TOP_LEVEL_ADDR_BASE));
 977                 return -1;
 978         }
 979         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 980         PM8001_INIT_DBG(pm8001_ha,
 981                 pm8001_printk("Top Register before resetting IOP/AAP1"
 982                 ":= 0x%x\n", regVal));
 983         regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 984         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 985
 986         /* step 7: Reset the BDMA/OSSP */
 987         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 988         PM8001_INIT_DBG(pm8001_ha,
 989                 pm8001_printk("Top Register before resetting BDMA/OSSP"
 990                 ": = 0x%x\n", regVal));
 991         regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 992         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 993
 994         /* step 8: delay 10 usec */
 995         udelay(10);
 996
 997         /* step 9: bring the BDMA and OSSP out of reset */
 998         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 999         PM8001_INIT_DBG(pm8001_ha,
1000                 pm8001_printk("Top Register before bringing up BDMA/OSSP"
1001                 ":= 0x%x\n", regVal));
1002         regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
1003         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1004
1005         /* step 10: delay 10 usec */
1006         udelay(10);
1007
1008         /* step 11: reads and sets the GSM Configuration and Reset Register */
1009         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
1010         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
1011                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1012                 PM8001_FAIL_DBG(pm8001_ha,
1013                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
1014                         GSM_ADDR_BASE));
1015                 return -1;
1016         }
1017         PM8001_INIT_DBG(pm8001_ha,
1018                 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
1019                 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1020         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1021         /* Put those bits to high */
1022         /* GSM XCBI offset = 0x70 0000
1023         0x00 Bit 13 COM_SLV_SW_RSTB 1
1024         0x00 Bit 12 QSSP_SW_RSTB 1
1025         0x00 Bit 11 RAAE_SW_RSTB 1
1026         0x00 Bit 9   RB_1_SW_RSTB 1
1027         0x00 Bit 8   SM_SW_RSTB 1
1028         */
1029         regVal |= (GSM_CONFIG_RESET_VALUE);
1030         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1031         PM8001_INIT_DBG(pm8001_ha,
1032                 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
1033                 " Configuration and Reset is set to = 0x%x\n",
1034                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1035
1036         /* step 12: Restore GSM - Read Address Parity Check */
1037         regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1038         /* just for debugging */
1039         PM8001_INIT_DBG(pm8001_ha,
1040                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
1041                 " = 0x%x\n", regVal));
1042         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1043         PM8001_INIT_DBG(pm8001_ha,
1044                 pm8001_printk("GSM 0x700038 - Read Address Parity"
1045                 " Check Enable is set to = 0x%x\n",
1046                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
1047         /* Restore GSM - Write Address Parity Check */
1048         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1049         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1050         PM8001_INIT_DBG(pm8001_ha,
1051                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
1052                 " Enable is set to = 0x%x\n",
1053                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
1054         /* Restore GSM - Write Data Parity Check */
1055         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1056         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1057         PM8001_INIT_DBG(pm8001_ha,
1058                 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
1059                 "is set to = 0x%x\n",
1060                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
1061
1062         /* step 13: bring the IOP and AAP1 out of reset */
1063         /* map 0x00000 to BAR4(0x20), BAR2(win) */
1064         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1065                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1066                 PM8001_FAIL_DBG(pm8001_ha,
1067                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
1068                         SPC_TOP_LEVEL_ADDR_BASE));
1069                 return -1;
1070         }
1071         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1072         regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1073         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1074
1075         /* step 14: delay 10 usec - Normal Mode */
1076         udelay(10);
1077         /* check Soft Reset Normal mode or Soft Reset HDA mode */
1078         if (signature == SPC_SOFT_RESET_SIGNATURE) {
1079                 /* step 15 (Normal Mode): wait until scratch pad1 register
1080                 bit 2 toggled */
1081                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1082                 do {
1083                         udelay(1);
1084                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1085                                 SCRATCH_PAD1_RST;
1086                 } while ((regVal != toggleVal) && (--max_wait_count));
1087
1088                 if (!max_wait_count) {
1089                         regVal = pm8001_cr32(pm8001_ha, 0,
1090                                 MSGU_SCRATCH_PAD_1);
1091                         PM8001_FAIL_DBG(pm8001_ha,
1092                                 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1093                                 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1094                                 toggleVal, regVal));
1095                         PM8001_FAIL_DBG(pm8001_ha,
1096                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1097                                 pm8001_cr32(pm8001_ha, 0,
1098                                 MSGU_SCRATCH_PAD_0)));
1099                         PM8001_FAIL_DBG(pm8001_ha,
1100                                 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1101                                 pm8001_cr32(pm8001_ha, 0,
1102                                 MSGU_SCRATCH_PAD_2)));
1103                         PM8001_FAIL_DBG(pm8001_ha,
1104                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1105                                 pm8001_cr32(pm8001_ha, 0,
1106                                 MSGU_SCRATCH_PAD_3)));
1107                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1108                         return -1;
1109                 }
1110
1111                 /* step 16 (Normal) - Clear ODMR and ODCR */
1112                 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1113                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1114
1115                 /* step 17 (Normal Mode): wait for the FW and IOP to get
1116                 ready - 1 sec timeout */
1117                 /* Wait for the SPC Configuration Table to be ready */
1118                 if (check_fw_ready(pm8001_ha) == -1) {
1119                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1120                         /* return error if MPI Configuration Table not ready */
1121                         PM8001_INIT_DBG(pm8001_ha,
1122                                 pm8001_printk("FW not ready SCRATCH_PAD1"
1123                                 " = 0x%x\n", regVal));
1124                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1125                         /* return error if MPI Configuration Table not ready */
1126                         PM8001_INIT_DBG(pm8001_ha,
1127                                 pm8001_printk("FW not ready SCRATCH_PAD2"
1128                                 " = 0x%x\n", regVal));
1129                         PM8001_INIT_DBG(pm8001_ha,
1130                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1131                                 pm8001_cr32(pm8001_ha, 0,
1132                                 MSGU_SCRATCH_PAD_0)));
1133                         PM8001_INIT_DBG(pm8001_ha,
1134                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1135                                 pm8001_cr32(pm8001_ha, 0,
1136                                 MSGU_SCRATCH_PAD_3)));
1137                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1138                         return -1;
1139                 }
1140         }
1141         pm8001_bar4_shift(pm8001_ha, 0);
1142         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1143
1144         PM8001_INIT_DBG(pm8001_ha,
1145                 pm8001_printk("SPC soft reset Complete\n"));
1146         return 0;
1147 }
1148
1149 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1150 {
1151         u32 i;
1152         u32 regVal;
1153         PM8001_INIT_DBG(pm8001_ha,
1154                 pm8001_printk("chip reset start\n"));
1155
1156         /* do SPC chip reset. */
1157         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1158         regVal &= ~(SPC_REG_RESET_DEVICE);
1159         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1160
1161         /* delay 10 usec */
1162         udelay(10);
1163
1164         /* bring chip reset out of reset */
1165         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1166         regVal |= SPC_REG_RESET_DEVICE;
1167         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1168
1169         /* delay 10 usec */
1170         udelay(10);
1171
1172         /* wait for 20 msec until the firmware gets reloaded */
1173         i = 20;
1174         do {
1175                 mdelay(1);
1176         } while ((--i) != 0);
1177
1178         PM8001_INIT_DBG(pm8001_ha,
1179                 pm8001_printk("chip reset finished\n"));
1180 }
1181
1182 /**
1183  * pm8001_chip_iounmap - which maped when initialized.
1184  * @pm8001_ha: our hba card information
1185  */
1186 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1187 {
1188         s8 bar, logical = 0;
1189         for (bar = 0; bar < 6; bar++) {
1190                 /*
1191                 ** logical BARs for SPC:
1192                 ** bar 0 and 1 - logical BAR0
1193                 ** bar 2 and 3 - logical BAR1
1194                 ** bar4 - logical BAR2
1195                 ** bar5 - logical BAR3
1196                 ** Skip the appropriate assignments:
1197                 */
1198                 if ((bar == 1) || (bar == 3))
1199                         continue;
1200                 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1201                         iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1202                         logical++;
1203                 }
1204         }
1205 }
1206
1207 /**
1208  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1209  * @pm8001_ha: our hba card information
1210  */
1211 static void
1212 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1213 {
1214         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1215         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1216 }
1217
1218  /**
1219   * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1220   * @pm8001_ha: our hba card information
1221   */
1222 static void
1223 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1224 {
1225         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1226 }
1227
1228 /**
1229  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1230  * @pm8001_ha: our hba card information
1231  */
1232 static void
1233 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1234         u32 int_vec_idx)
1235 {
1236         u32 msi_index;
1237         u32 value;
1238         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1239         msi_index += MSIX_TABLE_BASE;
1240         pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1241         value = (1 << int_vec_idx);
1242         pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1243
1244 }
1245
1246 /**
1247  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1248  * @pm8001_ha: our hba card information
1249  */
1250 static void
1251 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1252         u32 int_vec_idx)
1253 {
1254         u32 msi_index;
1255         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1256         msi_index += MSIX_TABLE_BASE;
1257         pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1258 }
1259
1260 /**
1261  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1262  * @pm8001_ha: our hba card information
1263  */
1264 static void
1265 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1266 {
1267 #ifdef PM8001_USE_MSIX
1268         pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1269         return;
1270 #endif
1271         pm8001_chip_intx_interrupt_enable(pm8001_ha);
1272
1273 }
1274
1275 /**
1276  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1277  * @pm8001_ha: our hba card information
1278  */
1279 static void
1280 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1281 {
1282 #ifdef PM8001_USE_MSIX
1283         pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1284         return;
1285 #endif
1286         pm8001_chip_intx_interrupt_disable(pm8001_ha);
1287
1288 }
1289
1290 /**
1291  * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1292  * inbound queue.
1293  * @circularQ: the inbound queue  we want to transfer to HBA.
1294  * @messageSize: the message size of this transfer, normally it is 64 bytes
1295  * @messagePtr: the pointer to message.
1296  */
1297 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1298                             u16 messageSize, void **messagePtr)
1299 {
1300         u32 offset, consumer_index;
1301         struct mpi_msg_hdr *msgHeader;
1302         u8 bcCount = 1; /* only support single buffer */
1303
1304         /* Checks is the requested message size can be allocated in this queue*/
1305         if (messageSize > IOMB_SIZE_SPCV) {
1306                 *messagePtr = NULL;
1307                 return -1;
1308         }
1309
1310         /* Stores the new consumer index */
1311         consumer_index = pm8001_read_32(circularQ->ci_virt);
1312         circularQ->consumer_index = cpu_to_le32(consumer_index);
1313         if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1314                 le32_to_cpu(circularQ->consumer_index)) {
1315                 *messagePtr = NULL;
1316                 return -1;
1317         }
1318         /* get memory IOMB buffer address */
1319         offset = circularQ->producer_idx * messageSize;
1320         /* increment to next bcCount element */
1321         circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1322                                 % PM8001_MPI_QUEUE;
1323         /* Adds that distance to the base of the region virtual address plus
1324         the message header size*/
1325         msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1326         *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1327         return 0;
1328 }
1329
1330 /**
1331  * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1332  * FW to tell the fw to get this message from IOMB.
1333  * @pm8001_ha: our hba card information
1334  * @circularQ: the inbound queue we want to transfer to HBA.
1335  * @opCode: the operation code represents commands which LLDD and fw recognized.
1336  * @payload: the command payload of each operation command.
1337  */
1338 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1339                          struct inbound_queue_table *circularQ,
1340                          u32 opCode, void *payload, u32 responseQueue)
1341 {
1342         u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1343         void *pMessage;
1344
1345         if (pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1346                 &pMessage) < 0) {
1347                 PM8001_IO_DBG(pm8001_ha,
1348                         pm8001_printk("No free mpi buffer\n"));
1349                 return -ENOMEM;
1350         }
1351         BUG_ON(!payload);
1352         /*Copy to the payload*/
1353         memcpy(pMessage, payload, (pm8001_ha->iomb_size -
1354                                 sizeof(struct mpi_msg_hdr)));
1355
1356         /*Build the header*/
1357         Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1358                 | ((responseQueue & 0x3F) << 16)
1359                 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1360
1361         pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1362         /*Update the PI to the firmware*/
1363         pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1364                 circularQ->pi_offset, circularQ->producer_idx);
1365         PM8001_IO_DBG(pm8001_ha,
1366                 pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1367                         responseQueue, opCode, circularQ->producer_idx,
1368                         circularQ->consumer_index));
1369         return 0;
1370 }
1371
1372 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1373                             struct outbound_queue_table *circularQ, u8 bc)
1374 {
1375         u32 producer_index;
1376         struct mpi_msg_hdr *msgHeader;
1377         struct mpi_msg_hdr *pOutBoundMsgHeader;
1378
1379         msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1380         pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1381                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1382         if (pOutBoundMsgHeader != msgHeader) {
1383                 PM8001_FAIL_DBG(pm8001_ha,
1384                         pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1385                         circularQ->consumer_idx, msgHeader));
1386
1387                 /* Update the producer index from SPC */
1388                 producer_index = pm8001_read_32(circularQ->pi_virt);
1389                 circularQ->producer_index = cpu_to_le32(producer_index);
1390                 PM8001_FAIL_DBG(pm8001_ha,
1391                         pm8001_printk("consumer_idx = %d producer_index = %d"
1392                         "msgHeader = %p\n", circularQ->consumer_idx,
1393                         circularQ->producer_index, msgHeader));
1394                 return 0;
1395         }
1396         /* free the circular queue buffer elements associated with the message*/
1397         circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1398                                 % PM8001_MPI_QUEUE;
1399         /* update the CI of outbound queue */
1400         pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1401                 circularQ->consumer_idx);
1402         /* Update the producer index from SPC*/
1403         producer_index = pm8001_read_32(circularQ->pi_virt);
1404         circularQ->producer_index = cpu_to_le32(producer_index);
1405         PM8001_IO_DBG(pm8001_ha,
1406                 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1407                 circularQ->producer_index));
1408         return 0;
1409 }
1410
1411 /**
1412  * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1413  * message table.
1414  * @pm8001_ha: our hba card information
1415  * @circularQ: the outbound queue  table.
1416  * @messagePtr1: the message contents of this outbound message.
1417  * @pBC: the message size.
1418  */
1419 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1420                            struct outbound_queue_table *circularQ,
1421                            void **messagePtr1, u8 *pBC)
1422 {
1423         struct mpi_msg_hdr      *msgHeader;
1424         __le32  msgHeader_tmp;
1425         u32 header_tmp;
1426         do {
1427                 /* If there are not-yet-delivered messages ... */
1428                 if (le32_to_cpu(circularQ->producer_index)
1429                         != circularQ->consumer_idx) {
1430                         /*Get the pointer to the circular queue buffer element*/
1431                         msgHeader = (struct mpi_msg_hdr *)
1432                                 (circularQ->base_virt +
1433                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1434                         /* read header */
1435                         header_tmp = pm8001_read_32(msgHeader);
1436                         msgHeader_tmp = cpu_to_le32(header_tmp);
1437                         if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1438                                 if (OPC_OUB_SKIP_ENTRY !=
1439                                         (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1440                                         *messagePtr1 =
1441                                                 ((u8 *)msgHeader) +
1442                                                 sizeof(struct mpi_msg_hdr);
1443                                         *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1444                                                 >> 24) & 0x1f);
1445                                         PM8001_IO_DBG(pm8001_ha,
1446                                                 pm8001_printk(": CI=%d PI=%d "
1447                                                 "msgHeader=%x\n",
1448                                                 circularQ->consumer_idx,
1449                                                 circularQ->producer_index,
1450                                                 msgHeader_tmp));
1451                                         return MPI_IO_STATUS_SUCCESS;
1452                                 } else {
1453                                         circularQ->consumer_idx =
1454                                                 (circularQ->consumer_idx +
1455                                                 ((le32_to_cpu(msgHeader_tmp)
1456                                                  >> 24) & 0x1f))
1457                                                         % PM8001_MPI_QUEUE;
1458                                         msgHeader_tmp = 0;
1459                                         pm8001_write_32(msgHeader, 0, 0);
1460                                         /* update the CI of outbound queue */
1461                                         pm8001_cw32(pm8001_ha,
1462                                                 circularQ->ci_pci_bar,
1463                                                 circularQ->ci_offset,
1464                                                 circularQ->consumer_idx);
1465                                 }
1466                         } else {
1467                                 circularQ->consumer_idx =
1468                                         (circularQ->consumer_idx +
1469                                         ((le32_to_cpu(msgHeader_tmp) >> 24) &
1470                                         0x1f)) % PM8001_MPI_QUEUE;
1471                                 msgHeader_tmp = 0;
1472                                 pm8001_write_32(msgHeader, 0, 0);
1473                                 /* update the CI of outbound queue */
1474                                 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1475                                         circularQ->ci_offset,
1476                                         circularQ->consumer_idx);
1477                                 return MPI_IO_STATUS_FAIL;
1478                         }
1479                 } else {
1480                         u32 producer_index;
1481                         void *pi_virt = circularQ->pi_virt;
1482                         /* spurious interrupt during setup if
1483                          * kexec-ing and driver doing a doorbell access
1484                          * with the pre-kexec oq interrupt setup
1485                          */
1486                         if (!pi_virt)
1487                                 break;
1488                         /* Update the producer index from SPC */
1489                         producer_index = pm8001_read_32(pi_virt);
1490                         circularQ->producer_index = cpu_to_le32(producer_index);
1491                 }
1492         } while (le32_to_cpu(circularQ->producer_index) !=
1493                 circularQ->consumer_idx);
1494         /* while we don't have any more not-yet-delivered message */
1495         /* report empty */
1496         return MPI_IO_STATUS_BUSY;
1497 }
1498
1499 void pm8001_work_fn(struct work_struct *work)
1500 {
1501         struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1502         struct pm8001_device *pm8001_dev;
1503         struct domain_device *dev;
1504
1505         /*
1506          * So far, all users of this stash an associated structure here.
1507          * If we get here, and this pointer is null, then the action
1508          * was cancelled. This nullification happens when the device
1509          * goes away.
1510          */
1511         pm8001_dev = pw->data; /* Most stash device structure */
1512         if ((pm8001_dev == NULL)
1513          || ((pw->handler != IO_XFER_ERROR_BREAK)
1514           && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1515                 kfree(pw);
1516                 return;
1517         }
1518
1519         switch (pw->handler) {
1520         case IO_XFER_ERROR_BREAK:
1521         {       /* This one stashes the sas_task instead */
1522                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1523                 u32 tag;
1524                 struct pm8001_ccb_info *ccb;
1525                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1526                 unsigned long flags, flags1;
1527                 struct task_status_struct *ts;
1528                 int i;
1529
1530                 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1531                         break; /* Task still on lu */
1532                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1533
1534                 spin_lock_irqsave(&t->task_state_lock, flags1);
1535                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1536                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1537                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1538                         break; /* Task got completed by another */
1539                 }
1540                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1541
1542                 /* Search for a possible ccb that matches the task */
1543                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1544                         ccb = &pm8001_ha->ccb_info[i];
1545                         tag = ccb->ccb_tag;
1546                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1547                                 break;
1548                 }
1549                 if (!ccb) {
1550                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1551                         break; /* Task got freed by another */
1552                 }
1553                 ts = &t->task_status;
1554                 ts->resp = SAS_TASK_COMPLETE;
1555                 /* Force the midlayer to retry */
1556                 ts->stat = SAS_QUEUE_FULL;
1557                 pm8001_dev = ccb->device;
1558                 if (pm8001_dev)
1559                         pm8001_dev->running_req--;
1560                 spin_lock_irqsave(&t->task_state_lock, flags1);
1561                 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1562                 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1563                 t->task_state_flags |= SAS_TASK_STATE_DONE;
1564                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1565                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1566                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
1567                                 " done with event 0x%x resp 0x%x stat 0x%x but"
1568                                 " aborted by upper layer!\n",
1569                                 t, pw->handler, ts->resp, ts->stat));
1570                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1571                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1572                 } else {
1573                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1574                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1575                         mb();/* in order to force CPU ordering */
1576                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1577                         t->task_done(t);
1578                 }
1579         }       break;
1580         case IO_XFER_OPEN_RETRY_TIMEOUT:
1581         {       /* This one stashes the sas_task instead */
1582                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1583                 u32 tag;
1584                 struct pm8001_ccb_info *ccb;
1585                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1586                 unsigned long flags, flags1;
1587                 int i, ret = 0;
1588
1589                 PM8001_IO_DBG(pm8001_ha,
1590                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1591
1592                 ret = pm8001_query_task(t);
1593
1594                 PM8001_IO_DBG(pm8001_ha,
1595                         switch (ret) {
1596                         case TMF_RESP_FUNC_SUCC:
1597                                 pm8001_printk("...Task on lu\n");
1598                                 break;
1599
1600                         case TMF_RESP_FUNC_COMPLETE:
1601                                 pm8001_printk("...Task NOT on lu\n");
1602                                 break;
1603
1604                         default:
1605                                 pm8001_printk("...query task failed!!!\n");
1606                                 break;
1607                         });
1608
1609                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1610
1611                 spin_lock_irqsave(&t->task_state_lock, flags1);
1612
1613                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1614                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1615                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1616                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1617                                 (void)pm8001_abort_task(t);
1618                         break; /* Task got completed by another */
1619                 }
1620
1621                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1622
1623                 /* Search for a possible ccb that matches the task */
1624                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1625                         ccb = &pm8001_ha->ccb_info[i];
1626                         tag = ccb->ccb_tag;
1627                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1628                                 break;
1629                 }
1630                 if (!ccb) {
1631                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1632                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1633                                 (void)pm8001_abort_task(t);
1634                         break; /* Task got freed by another */
1635                 }
1636
1637                 pm8001_dev = ccb->device;
1638                 dev = pm8001_dev->sas_device;
1639
1640                 switch (ret) {
1641                 case TMF_RESP_FUNC_SUCC: /* task on lu */
1642                         ccb->open_retry = 1; /* Snub completion */
1643                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1644                         ret = pm8001_abort_task(t);
1645                         ccb->open_retry = 0;
1646                         switch (ret) {
1647                         case TMF_RESP_FUNC_SUCC:
1648                         case TMF_RESP_FUNC_COMPLETE:
1649                                 break;
1650                         default: /* device misbehavior */
1651                                 ret = TMF_RESP_FUNC_FAILED;
1652                                 PM8001_IO_DBG(pm8001_ha,
1653                                         pm8001_printk("...Reset phy\n"));
1654                                 pm8001_I_T_nexus_reset(dev);
1655                                 break;
1656                         }
1657                         break;
1658
1659                 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1660                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1661                         /* Do we need to abort the task locally? */
1662                         break;
1663
1664                 default: /* device misbehavior */
1665                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1666                         ret = TMF_RESP_FUNC_FAILED;
1667                         PM8001_IO_DBG(pm8001_ha,
1668                                 pm8001_printk("...Reset phy\n"));
1669                         pm8001_I_T_nexus_reset(dev);
1670                 }
1671
1672                 if (ret == TMF_RESP_FUNC_FAILED)
1673                         t = NULL;
1674                 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1675                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
1676         }       break;
1677         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1678                 dev = pm8001_dev->sas_device;
1679                 pm8001_I_T_nexus_event_handler(dev);
1680                 break;
1681         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1682                 dev = pm8001_dev->sas_device;
1683                 pm8001_I_T_nexus_reset(dev);
1684                 break;
1685         case IO_DS_IN_ERROR:
1686                 dev = pm8001_dev->sas_device;
1687                 pm8001_I_T_nexus_reset(dev);
1688                 break;
1689         case IO_DS_NON_OPERATIONAL:
1690                 dev = pm8001_dev->sas_device;
1691                 pm8001_I_T_nexus_reset(dev);
1692                 break;
1693         }
1694         kfree(pw);
1695 }
1696
1697 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1698                                int handler)
1699 {
1700         struct pm8001_work *pw;
1701         int ret = 0;
1702
1703         pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1704         if (pw) {
1705                 pw->pm8001_ha = pm8001_ha;
1706                 pw->data = data;
1707                 pw->handler = handler;
1708                 INIT_WORK(&pw->work, pm8001_work_fn);
1709                 queue_work(pm8001_wq, &pw->work);
1710         } else
1711                 ret = -ENOMEM;
1712
1713         return ret;
1714 }
1715
1716 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1717                 struct pm8001_device *pm8001_ha_dev)
1718 {
1719         int res;
1720         u32 ccb_tag;
1721         struct pm8001_ccb_info *ccb;
1722         struct sas_task *task = NULL;
1723         struct task_abort_req task_abort;
1724         struct inbound_queue_table *circularQ;
1725         u32 opc = OPC_INB_SATA_ABORT;
1726         int ret;
1727
1728         if (!pm8001_ha_dev) {
1729                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1730                 return;
1731         }
1732
1733         task = sas_alloc_slow_task(GFP_ATOMIC);
1734
1735         if (!task) {
1736                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1737                                                 "allocate task\n"));
1738                 return;
1739         }
1740
1741         task->task_done = pm8001_task_done;
1742
1743         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1744         if (res)
1745                 return;
1746
1747         ccb = &pm8001_ha->ccb_info[ccb_tag];
1748         ccb->device = pm8001_ha_dev;
1749         ccb->ccb_tag = ccb_tag;
1750         ccb->task = task;
1751         ccb->n_elem = 0;
1752
1753         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1754
1755         memset(&task_abort, 0, sizeof(task_abort));
1756         task_abort.abort_all = cpu_to_le32(1);
1757         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1758         task_abort.tag = cpu_to_le32(ccb_tag);
1759
1760         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1761         if (ret)
1762                 pm8001_tag_free(pm8001_ha, ccb_tag);
1763
1764 }
1765
1766 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1767                 struct pm8001_device *pm8001_ha_dev)
1768 {
1769         struct sata_start_req sata_cmd;
1770         int res;
1771         u32 ccb_tag;
1772         struct pm8001_ccb_info *ccb;
1773         struct sas_task *task = NULL;
1774         struct host_to_dev_fis fis;
1775         struct domain_device *dev;
1776         struct inbound_queue_table *circularQ;
1777         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1778
1779         task = sas_alloc_slow_task(GFP_ATOMIC);
1780
1781         if (!task) {
1782                 PM8001_FAIL_DBG(pm8001_ha,
1783                         pm8001_printk("cannot allocate task !!!\n"));
1784                 return;
1785         }
1786         task->task_done = pm8001_task_done;
1787
1788         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1789         if (res) {
1790                 sas_free_task(task);
1791                 PM8001_FAIL_DBG(pm8001_ha,
1792                         pm8001_printk("cannot allocate tag !!!\n"));
1793                 return;
1794         }
1795
1796         /* allocate domain device by ourselves as libsas
1797          * is not going to provide any
1798         */
1799         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1800         if (!dev) {
1801                 sas_free_task(task);
1802                 pm8001_tag_free(pm8001_ha, ccb_tag);
1803                 PM8001_FAIL_DBG(pm8001_ha,
1804                         pm8001_printk("Domain device cannot be allocated\n"));
1805                 return;
1806         }
1807         task->dev = dev;
1808         task->dev->lldd_dev = pm8001_ha_dev;
1809
1810         ccb = &pm8001_ha->ccb_info[ccb_tag];
1811         ccb->device = pm8001_ha_dev;
1812         ccb->ccb_tag = ccb_tag;
1813         ccb->task = task;
1814         ccb->n_elem = 0;
1815         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1816         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1817
1818         memset(&sata_cmd, 0, sizeof(sata_cmd));
1819         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1820
1821         /* construct read log FIS */
1822         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1823         fis.fis_type = 0x27;
1824         fis.flags = 0x80;
1825         fis.command = ATA_CMD_READ_LOG_EXT;
1826         fis.lbal = 0x10;
1827         fis.sector_count = 0x1;
1828
1829         sata_cmd.tag = cpu_to_le32(ccb_tag);
1830         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1831         sata_cmd.ncqtag_atap_dir_m = cpu_to_le32((0x1 << 7) | (0x5 << 9));
1832         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1833
1834         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1835         if (res) {
1836                 sas_free_task(task);
1837                 pm8001_tag_free(pm8001_ha, ccb_tag);
1838                 kfree(dev);
1839         }
1840 }
1841
1842 /**
1843  * mpi_ssp_completion- process the event that FW response to the SSP request.
1844  * @pm8001_ha: our hba card information
1845  * @piomb: the message contents of this outbound message.
1846  *
1847  * When FW has completed a ssp request for example a IO request, after it has
1848  * filled the SG data with the data, it will trigger this event represent
1849  * that he has finished the job,please check the coresponding buffer.
1850  * So we will tell the caller who maybe waiting the result to tell upper layer
1851  * that the task has been finished.
1852  */
1853 static void
1854 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1855 {
1856         struct sas_task *t;
1857         struct pm8001_ccb_info *ccb;
1858         unsigned long flags;
1859         u32 status;
1860         u32 param;
1861         u32 tag;
1862         struct ssp_completion_resp *psspPayload;
1863         struct task_status_struct *ts;
1864         struct ssp_response_iu *iu;
1865         struct pm8001_device *pm8001_dev;
1866         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1867         status = le32_to_cpu(psspPayload->status);
1868         tag = le32_to_cpu(psspPayload->tag);
1869         ccb = &pm8001_ha->ccb_info[tag];
1870         if ((status == IO_ABORTED) && ccb->open_retry) {
1871                 /* Being completed by another */
1872                 ccb->open_retry = 0;
1873                 return;
1874         }
1875         pm8001_dev = ccb->device;
1876         param = le32_to_cpu(psspPayload->param);
1877
1878         t = ccb->task;
1879
1880         if (status && status != IO_UNDERFLOW)
1881                 PM8001_FAIL_DBG(pm8001_ha,
1882                         pm8001_printk("sas IO status 0x%x\n", status));
1883         if (unlikely(!t || !t->lldd_task || !t->dev))
1884                 return;
1885         ts = &t->task_status;
1886         /* Print sas address of IO failed device */
1887         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1888                 (status != IO_UNDERFLOW))
1889                 PM8001_FAIL_DBG(pm8001_ha,
1890                         pm8001_printk("SAS Address of IO Failure Drive:"
1891                         "%016llx", SAS_ADDR(t->dev->sas_addr)));
1892
1893         switch (status) {
1894         case IO_SUCCESS:
1895                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1896                         ",param = %d\n", param));
1897                 if (param == 0) {
1898                         ts->resp = SAS_TASK_COMPLETE;
1899                         ts->stat = SAM_STAT_GOOD;
1900                 } else {
1901                         ts->resp = SAS_TASK_COMPLETE;
1902                         ts->stat = SAS_PROTO_RESPONSE;
1903                         ts->residual = param;
1904                         iu = &psspPayload->ssp_resp_iu;
1905                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1906                 }
1907                 if (pm8001_dev)
1908                         pm8001_dev->running_req--;
1909                 break;
1910         case IO_ABORTED:
1911                 PM8001_IO_DBG(pm8001_ha,
1912                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1913                 ts->resp = SAS_TASK_COMPLETE;
1914                 ts->stat = SAS_ABORTED_TASK;
1915                 break;
1916         case IO_UNDERFLOW:
1917                 /* SSP Completion with error */
1918                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1919                         ",param = %d\n", param));
1920                 ts->resp = SAS_TASK_COMPLETE;
1921                 ts->stat = SAS_DATA_UNDERRUN;
1922                 ts->residual = param;
1923                 if (pm8001_dev)
1924                         pm8001_dev->running_req--;
1925                 break;
1926         case IO_NO_DEVICE:
1927                 PM8001_IO_DBG(pm8001_ha,
1928                         pm8001_printk("IO_NO_DEVICE\n"));
1929                 ts->resp = SAS_TASK_UNDELIVERED;
1930                 ts->stat = SAS_PHY_DOWN;
1931                 break;
1932         case IO_XFER_ERROR_BREAK:
1933                 PM8001_IO_DBG(pm8001_ha,
1934                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1935                 ts->resp = SAS_TASK_COMPLETE;
1936                 ts->stat = SAS_OPEN_REJECT;
1937                 /* Force the midlayer to retry */
1938                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1939                 break;
1940         case IO_XFER_ERROR_PHY_NOT_READY:
1941                 PM8001_IO_DBG(pm8001_ha,
1942                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1943                 ts->resp = SAS_TASK_COMPLETE;
1944                 ts->stat = SAS_OPEN_REJECT;
1945                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1946                 break;
1947         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1948                 PM8001_IO_DBG(pm8001_ha,
1949                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1950                 ts->resp = SAS_TASK_COMPLETE;
1951                 ts->stat = SAS_OPEN_REJECT;
1952                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1953                 break;
1954         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1955                 PM8001_IO_DBG(pm8001_ha,
1956                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1957                 ts->resp = SAS_TASK_COMPLETE;
1958                 ts->stat = SAS_OPEN_REJECT;
1959                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1960                 break;
1961         case IO_OPEN_CNX_ERROR_BREAK:
1962                 PM8001_IO_DBG(pm8001_ha,
1963                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1964                 ts->resp = SAS_TASK_COMPLETE;
1965                 ts->stat = SAS_OPEN_REJECT;
1966                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1967                 break;
1968         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1969                 PM8001_IO_DBG(pm8001_ha,
1970                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1971                 ts->resp = SAS_TASK_COMPLETE;
1972                 ts->stat = SAS_OPEN_REJECT;
1973                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1974                 if (!t->uldd_task)
1975                         pm8001_handle_event(pm8001_ha,
1976                                 pm8001_dev,
1977                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1978                 break;
1979         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1980                 PM8001_IO_DBG(pm8001_ha,
1981                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1982                 ts->resp = SAS_TASK_COMPLETE;
1983                 ts->stat = SAS_OPEN_REJECT;
1984                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1985                 break;
1986         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1987                 PM8001_IO_DBG(pm8001_ha,
1988                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1989                         "NOT_SUPPORTED\n"));
1990                 ts->resp = SAS_TASK_COMPLETE;
1991                 ts->stat = SAS_OPEN_REJECT;
1992                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1993                 break;
1994         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1995                 PM8001_IO_DBG(pm8001_ha,
1996                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1997                 ts->resp = SAS_TASK_UNDELIVERED;
1998                 ts->stat = SAS_OPEN_REJECT;
1999                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2000                 break;
2001         case IO_XFER_ERROR_NAK_RECEIVED:
2002                 PM8001_IO_DBG(pm8001_ha,
2003                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2004                 ts->resp = SAS_TASK_COMPLETE;
2005                 ts->stat = SAS_OPEN_REJECT;
2006                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2007                 break;
2008         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2009                 PM8001_IO_DBG(pm8001_ha,
2010                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2011                 ts->resp = SAS_TASK_COMPLETE;
2012                 ts->stat = SAS_NAK_R_ERR;
2013                 break;
2014         case IO_XFER_ERROR_DMA:
2015                 PM8001_IO_DBG(pm8001_ha,
2016                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2017                 ts->resp = SAS_TASK_COMPLETE;
2018                 ts->stat = SAS_OPEN_REJECT;
2019                 break;
2020         case IO_XFER_OPEN_RETRY_TIMEOUT:
2021                 PM8001_IO_DBG(pm8001_ha,
2022                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2023                 ts->resp = SAS_TASK_COMPLETE;
2024                 ts->stat = SAS_OPEN_REJECT;
2025                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2026                 break;
2027         case IO_XFER_ERROR_OFFSET_MISMATCH:
2028                 PM8001_IO_DBG(pm8001_ha,
2029                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2030                 ts->resp = SAS_TASK_COMPLETE;
2031                 ts->stat = SAS_OPEN_REJECT;
2032                 break;
2033         case IO_PORT_IN_RESET:
2034                 PM8001_IO_DBG(pm8001_ha,
2035                         pm8001_printk("IO_PORT_IN_RESET\n"));
2036                 ts->resp = SAS_TASK_COMPLETE;
2037                 ts->stat = SAS_OPEN_REJECT;
2038                 break;
2039         case IO_DS_NON_OPERATIONAL:
2040                 PM8001_IO_DBG(pm8001_ha,
2041                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2042                 ts->resp = SAS_TASK_COMPLETE;
2043                 ts->stat = SAS_OPEN_REJECT;
2044                 if (!t->uldd_task)
2045                         pm8001_handle_event(pm8001_ha,
2046                                 pm8001_dev,
2047                                 IO_DS_NON_OPERATIONAL);
2048                 break;
2049         case IO_DS_IN_RECOVERY:
2050                 PM8001_IO_DBG(pm8001_ha,
2051                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2052                 ts->resp = SAS_TASK_COMPLETE;
2053                 ts->stat = SAS_OPEN_REJECT;
2054                 break;
2055         case IO_TM_TAG_NOT_FOUND:
2056                 PM8001_IO_DBG(pm8001_ha,
2057                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
2058                 ts->resp = SAS_TASK_COMPLETE;
2059                 ts->stat = SAS_OPEN_REJECT;
2060                 break;
2061         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2062                 PM8001_IO_DBG(pm8001_ha,
2063                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
2064                 ts->resp = SAS_TASK_COMPLETE;
2065                 ts->stat = SAS_OPEN_REJECT;
2066                 break;
2067         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2068                 PM8001_IO_DBG(pm8001_ha,
2069                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2070                 ts->resp = SAS_TASK_COMPLETE;
2071                 ts->stat = SAS_OPEN_REJECT;
2072                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2073                 break;
2074         default:
2075                 PM8001_IO_DBG(pm8001_ha,
2076                         pm8001_printk("Unknown status 0x%x\n", status));
2077                 /* not allowed case. Therefore, return failed status */
2078                 ts->resp = SAS_TASK_COMPLETE;
2079                 ts->stat = SAS_OPEN_REJECT;
2080                 break;
2081         }
2082         PM8001_IO_DBG(pm8001_ha,
2083                 pm8001_printk("scsi_status = %x\n ",
2084                 psspPayload->ssp_resp_iu.status));
2085         spin_lock_irqsave(&t->task_state_lock, flags);
2086         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2087         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2088         t->task_state_flags |= SAS_TASK_STATE_DONE;
2089         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2090                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2091                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2092                         " io_status 0x%x resp 0x%x "
2093                         "stat 0x%x but aborted by upper layer!\n",
2094                         t, status, ts->resp, ts->stat));
2095                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2096         } else {
2097                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2098                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2099                 mb();/* in order to force CPU ordering */
2100                 t->task_done(t);
2101         }
2102 }
2103
2104 /*See the comments for mpi_ssp_completion */
2105 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2106 {
2107         struct sas_task *t;
2108         unsigned long flags;
2109         struct task_status_struct *ts;
2110         struct pm8001_ccb_info *ccb;
2111         struct pm8001_device *pm8001_dev;
2112         struct ssp_event_resp *psspPayload =
2113                 (struct ssp_event_resp *)(piomb + 4);
2114         u32 event = le32_to_cpu(psspPayload->event);
2115         u32 tag = le32_to_cpu(psspPayload->tag);
2116         u32 port_id = le32_to_cpu(psspPayload->port_id);
2117         u32 dev_id = le32_to_cpu(psspPayload->device_id);
2118
2119         ccb = &pm8001_ha->ccb_info[tag];
2120         t = ccb->task;
2121         pm8001_dev = ccb->device;
2122         if (event)
2123                 PM8001_FAIL_DBG(pm8001_ha,
2124                         pm8001_printk("sas IO status 0x%x\n", event));
2125         if (unlikely(!t || !t->lldd_task || !t->dev))
2126                 return;
2127         ts = &t->task_status;
2128         PM8001_IO_DBG(pm8001_ha,
2129                 pm8001_printk("port_id = %x,device_id = %x\n",
2130                 port_id, dev_id));
2131         switch (event) {
2132         case IO_OVERFLOW:
2133                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
2134                 ts->resp = SAS_TASK_COMPLETE;
2135                 ts->stat = SAS_DATA_OVERRUN;
2136                 ts->residual = 0;
2137                 if (pm8001_dev)
2138                         pm8001_dev->running_req--;
2139                 break;
2140         case IO_XFER_ERROR_BREAK:
2141                 PM8001_IO_DBG(pm8001_ha,
2142                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2143                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2144                 return;
2145         case IO_XFER_ERROR_PHY_NOT_READY:
2146                 PM8001_IO_DBG(pm8001_ha,
2147                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2148                 ts->resp = SAS_TASK_COMPLETE;
2149                 ts->stat = SAS_OPEN_REJECT;
2150                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2151                 break;
2152         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2153                 PM8001_IO_DBG(pm8001_ha,
2154                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2155                         "_SUPPORTED\n"));
2156                 ts->resp = SAS_TASK_COMPLETE;
2157                 ts->stat = SAS_OPEN_REJECT;
2158                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2159                 break;
2160         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2161                 PM8001_IO_DBG(pm8001_ha,
2162                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2163                 ts->resp = SAS_TASK_COMPLETE;
2164                 ts->stat = SAS_OPEN_REJECT;
2165                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2166                 break;
2167         case IO_OPEN_CNX_ERROR_BREAK:
2168                 PM8001_IO_DBG(pm8001_ha,
2169                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2170                 ts->resp = SAS_TASK_COMPLETE;
2171                 ts->stat = SAS_OPEN_REJECT;
2172                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2173                 break;
2174         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2175                 PM8001_IO_DBG(pm8001_ha,
2176                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2177                 ts->resp = SAS_TASK_COMPLETE;
2178                 ts->stat = SAS_OPEN_REJECT;
2179                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2180                 if (!t->uldd_task)
2181                         pm8001_handle_event(pm8001_ha,
2182                                 pm8001_dev,
2183                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2184                 break;
2185         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2186                 PM8001_IO_DBG(pm8001_ha,
2187                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2188                 ts->resp = SAS_TASK_COMPLETE;
2189                 ts->stat = SAS_OPEN_REJECT;
2190                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2191                 break;
2192         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2193                 PM8001_IO_DBG(pm8001_ha,
2194                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2195                         "NOT_SUPPORTED\n"));
2196                 ts->resp = SAS_TASK_COMPLETE;
2197                 ts->stat = SAS_OPEN_REJECT;
2198                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2199                 break;
2200         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2201                 PM8001_IO_DBG(pm8001_ha,
2202                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2203                 ts->resp = SAS_TASK_COMPLETE;
2204                 ts->stat = SAS_OPEN_REJECT;
2205                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2206                 break;
2207         case IO_XFER_ERROR_NAK_RECEIVED:
2208                 PM8001_IO_DBG(pm8001_ha,
2209                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2210                 ts->resp = SAS_TASK_COMPLETE;
2211                 ts->stat = SAS_OPEN_REJECT;
2212                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2213                 break;
2214         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2215                 PM8001_IO_DBG(pm8001_ha,
2216                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2217                 ts->resp = SAS_TASK_COMPLETE;
2218                 ts->stat = SAS_NAK_R_ERR;
2219                 break;
2220         case IO_XFER_OPEN_RETRY_TIMEOUT:
2221                 PM8001_IO_DBG(pm8001_ha,
2222                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2223                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2224                 return;
2225         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2226                 PM8001_IO_DBG(pm8001_ha,
2227                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2228                 ts->resp = SAS_TASK_COMPLETE;
2229                 ts->stat = SAS_DATA_OVERRUN;
2230                 break;
2231         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2232                 PM8001_IO_DBG(pm8001_ha,
2233                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2234                 ts->resp = SAS_TASK_COMPLETE;
2235                 ts->stat = SAS_DATA_OVERRUN;
2236                 break;
2237         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2238                 PM8001_IO_DBG(pm8001_ha,
2239                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2240                 ts->resp = SAS_TASK_COMPLETE;
2241                 ts->stat = SAS_DATA_OVERRUN;
2242                 break;
2243         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2244                 PM8001_IO_DBG(pm8001_ha,
2245                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2246                 ts->resp = SAS_TASK_COMPLETE;
2247                 ts->stat = SAS_DATA_OVERRUN;
2248                 break;
2249         case IO_XFER_ERROR_OFFSET_MISMATCH:
2250                 PM8001_IO_DBG(pm8001_ha,
2251                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2252                 ts->resp = SAS_TASK_COMPLETE;
2253                 ts->stat = SAS_DATA_OVERRUN;
2254                 break;
2255         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2256                 PM8001_IO_DBG(pm8001_ha,
2257                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2258                 ts->resp = SAS_TASK_COMPLETE;
2259                 ts->stat = SAS_DATA_OVERRUN;
2260                 break;
2261         case IO_XFER_CMD_FRAME_ISSUED:
2262                 PM8001_IO_DBG(pm8001_ha,
2263                         pm8001_printk("  IO_XFER_CMD_FRAME_ISSUED\n"));
2264                 return;
2265         default:
2266                 PM8001_IO_DBG(pm8001_ha,
2267                         pm8001_printk("Unknown status 0x%x\n", event));
2268                 /* not allowed case. Therefore, return failed status */
2269                 ts->resp = SAS_TASK_COMPLETE;
2270                 ts->stat = SAS_DATA_OVERRUN;
2271                 break;
2272         }
2273         spin_lock_irqsave(&t->task_state_lock, flags);
2274         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2275         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2276         t->task_state_flags |= SAS_TASK_STATE_DONE;
2277         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2278                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2279                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2280                         " event 0x%x resp 0x%x "
2281                         "stat 0x%x but aborted by upper layer!\n",
2282                         t, event, ts->resp, ts->stat));
2283                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2284         } else {
2285                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2286                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2287                 mb();/* in order to force CPU ordering */
2288                 t->task_done(t);
2289         }
2290 }
2291
2292 /*See the comments for mpi_ssp_completion */
2293 static void
2294 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2295 {
2296         struct sas_task *t;
2297         struct pm8001_ccb_info *ccb;
2298         u32 param;
2299         u32 status;
2300         u32 tag;
2301         int i, j;
2302         u8 sata_addr_low[4];
2303         u32 temp_sata_addr_low;
2304         u8 sata_addr_hi[4];
2305         u32 temp_sata_addr_hi;
2306         struct sata_completion_resp *psataPayload;
2307         struct task_status_struct *ts;
2308         struct ata_task_resp *resp ;
2309         u32 *sata_resp;
2310         struct pm8001_device *pm8001_dev;
2311         unsigned long flags;
2312
2313         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2314         status = le32_to_cpu(psataPayload->status);
2315         tag = le32_to_cpu(psataPayload->tag);
2316
2317         if (!tag) {
2318                 PM8001_FAIL_DBG(pm8001_ha,
2319                         pm8001_printk("tag null\n"));
2320                 return;
2321         }
2322         ccb = &pm8001_ha->ccb_info[tag];
2323         param = le32_to_cpu(psataPayload->param);
2324         if (ccb) {
2325                 t = ccb->task;
2326                 pm8001_dev = ccb->device;
2327         } else {
2328                 PM8001_FAIL_DBG(pm8001_ha,
2329                         pm8001_printk("ccb null\n"));
2330                 return;
2331         }
2332
2333         if (t) {
2334                 if (t->dev && (t->dev->lldd_dev))
2335                         pm8001_dev = t->dev->lldd_dev;
2336         } else {
2337                 PM8001_FAIL_DBG(pm8001_ha,
2338                         pm8001_printk("task null\n"));
2339                 return;
2340         }
2341
2342         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2343                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2344                 PM8001_FAIL_DBG(pm8001_ha,
2345                         pm8001_printk("task or dev null\n"));
2346                 return;
2347         }
2348
2349         ts = &t->task_status;
2350         if (!ts) {
2351                 PM8001_FAIL_DBG(pm8001_ha,
2352                         pm8001_printk("ts null\n"));
2353                 return;
2354         }
2355         /* Print sas address of IO failed device */
2356         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2357                 (status != IO_UNDERFLOW)) {
2358                 if (!((t->dev->parent) &&
2359                         (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
2360                         for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++)
2361                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2362                         for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++)
2363                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2364                         memcpy(&temp_sata_addr_low, sata_addr_low,
2365                                 sizeof(sata_addr_low));
2366                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2367                                 sizeof(sata_addr_hi));
2368                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2369                                                 |((temp_sata_addr_hi << 8) &
2370                                                 0xff0000) |
2371                                                 ((temp_sata_addr_hi >> 8)
2372                                                 & 0xff00) |
2373                                                 ((temp_sata_addr_hi << 24) &
2374                                                 0xff000000));
2375                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2376                                                 & 0xff) |
2377                                                 ((temp_sata_addr_low << 8)
2378                                                 & 0xff0000) |
2379                                                 ((temp_sata_addr_low >> 8)
2380                                                 & 0xff00) |
2381                                                 ((temp_sata_addr_low << 24)
2382                                                 & 0xff000000)) +
2383                                                 pm8001_dev->attached_phy +
2384                                                 0x10);
2385                         PM8001_FAIL_DBG(pm8001_ha,
2386                                 pm8001_printk("SAS Address of IO Failure Drive:"
2387                                 "%08x%08x", temp_sata_addr_hi,
2388                                         temp_sata_addr_low));
2389                 } else {
2390                         PM8001_FAIL_DBG(pm8001_ha,
2391                                 pm8001_printk("SAS Address of IO Failure Drive:"
2392                                 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2393                 }
2394         }
2395         switch (status) {
2396         case IO_SUCCESS:
2397                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2398                 if (param == 0) {
2399                         ts->resp = SAS_TASK_COMPLETE;
2400                         ts->stat = SAM_STAT_GOOD;
2401                         /* check if response is for SEND READ LOG */
2402                         if (pm8001_dev &&
2403                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2404                                 /* set new bit for abort_all */
2405                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2406                                 /* clear bit for read log */
2407                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2408                                 pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2409                                 /* Free the tag */
2410                                 pm8001_tag_free(pm8001_ha, tag);
2411                                 sas_free_task(t);
2412                                 return;
2413                         }
2414                 } else {
2415                         u8 len;
2416                         ts->resp = SAS_TASK_COMPLETE;
2417                         ts->stat = SAS_PROTO_RESPONSE;
2418                         ts->residual = param;
2419                         PM8001_IO_DBG(pm8001_ha,
2420                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2421                                 param));
2422                         sata_resp = &psataPayload->sata_resp[0];
2423                         resp = (struct ata_task_resp *)ts->buf;
2424                         if (t->ata_task.dma_xfer == 0 &&
2425                         t->data_dir == PCI_DMA_FROMDEVICE) {
2426                                 len = sizeof(struct pio_setup_fis);
2427                                 PM8001_IO_DBG(pm8001_ha,
2428                                 pm8001_printk("PIO read len = %d\n", len));
2429                         } else if (t->ata_task.use_ncq) {
2430                                 len = sizeof(struct set_dev_bits_fis);
2431                                 PM8001_IO_DBG(pm8001_ha,
2432                                         pm8001_printk("FPDMA len = %d\n", len));
2433                         } else {
2434                                 len = sizeof(struct dev_to_host_fis);
2435                                 PM8001_IO_DBG(pm8001_ha,
2436                                 pm8001_printk("other len = %d\n", len));
2437                         }
2438                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2439                                 resp->frame_len = len;
2440                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2441                                 ts->buf_valid_size = sizeof(*resp);
2442                         } else
2443                                 PM8001_IO_DBG(pm8001_ha,
2444                                         pm8001_printk("response to large\n"));
2445                 }
2446                 if (pm8001_dev)
2447                         pm8001_dev->running_req--;
2448                 break;
2449         case IO_ABORTED:
2450                 PM8001_IO_DBG(pm8001_ha,
2451                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2452                 ts->resp = SAS_TASK_COMPLETE;
2453                 ts->stat = SAS_ABORTED_TASK;
2454                 if (pm8001_dev)
2455                         pm8001_dev->running_req--;
2456                 break;
2457                 /* following cases are to do cases */
2458         case IO_UNDERFLOW:
2459                 /* SATA Completion with error */
2460                 PM8001_IO_DBG(pm8001_ha,
2461                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2462                 ts->resp = SAS_TASK_COMPLETE;
2463                 ts->stat = SAS_DATA_UNDERRUN;
2464                 ts->residual =  param;
2465                 if (pm8001_dev)
2466                         pm8001_dev->running_req--;
2467                 break;
2468         case IO_NO_DEVICE:
2469                 PM8001_IO_DBG(pm8001_ha,
2470                         pm8001_printk("IO_NO_DEVICE\n"));
2471                 ts->resp = SAS_TASK_UNDELIVERED;
2472                 ts->stat = SAS_PHY_DOWN;
2473                 break;
2474         case IO_XFER_ERROR_BREAK:
2475                 PM8001_IO_DBG(pm8001_ha,
2476                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2477                 ts->resp = SAS_TASK_COMPLETE;
2478                 ts->stat = SAS_INTERRUPTED;
2479                 break;
2480         case IO_XFER_ERROR_PHY_NOT_READY:
2481                 PM8001_IO_DBG(pm8001_ha,
2482                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2483                 ts->resp = SAS_TASK_COMPLETE;
2484                 ts->stat = SAS_OPEN_REJECT;
2485                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2486                 break;
2487         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2488                 PM8001_IO_DBG(pm8001_ha,
2489                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2490                         "_SUPPORTED\n"));
2491                 ts->resp = SAS_TASK_COMPLETE;
2492                 ts->stat = SAS_OPEN_REJECT;
2493                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2494                 break;
2495         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2496                 PM8001_IO_DBG(pm8001_ha,
2497                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2498                 ts->resp = SAS_TASK_COMPLETE;
2499                 ts->stat = SAS_OPEN_REJECT;
2500                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2501                 break;
2502         case IO_OPEN_CNX_ERROR_BREAK:
2503                 PM8001_IO_DBG(pm8001_ha,
2504                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2505                 ts->resp = SAS_TASK_COMPLETE;
2506                 ts->stat = SAS_OPEN_REJECT;
2507                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2508                 break;
2509         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2510                 PM8001_IO_DBG(pm8001_ha,
2511                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2512                 ts->resp = SAS_TASK_COMPLETE;
2513                 ts->stat = SAS_DEV_NO_RESPONSE;
2514                 if (!t->uldd_task) {
2515                         pm8001_handle_event(pm8001_ha,
2516                                 pm8001_dev,
2517                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2518                         ts->resp = SAS_TASK_UNDELIVERED;
2519                         ts->stat = SAS_QUEUE_FULL;
2520                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2521                         return;
2522                 }
2523                 break;
2524         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2525                 PM8001_IO_DBG(pm8001_ha,
2526                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2527                 ts->resp = SAS_TASK_UNDELIVERED;
2528                 ts->stat = SAS_OPEN_REJECT;
2529                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2530                 if (!t->uldd_task) {
2531                         pm8001_handle_event(pm8001_ha,
2532                                 pm8001_dev,
2533                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2534                         ts->resp = SAS_TASK_UNDELIVERED;
2535                         ts->stat = SAS_QUEUE_FULL;
2536                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2537                         return;
2538                 }
2539                 break;
2540         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2541                 PM8001_IO_DBG(pm8001_ha,
2542                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2543                         "NOT_SUPPORTED\n"));
2544                 ts->resp = SAS_TASK_COMPLETE;
2545                 ts->stat = SAS_OPEN_REJECT;
2546                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2547                 break;
2548         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2549                 PM8001_IO_DBG(pm8001_ha,
2550                         pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2551                         "_BUSY\n"));
2552                 ts->resp = SAS_TASK_COMPLETE;
2553                 ts->stat = SAS_DEV_NO_RESPONSE;
2554                 if (!t->uldd_task) {
2555                         pm8001_handle_event(pm8001_ha,
2556                                 pm8001_dev,
2557                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2558                         ts->resp = SAS_TASK_UNDELIVERED;
2559                         ts->stat = SAS_QUEUE_FULL;
2560                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2561                         return;
2562                 }
2563                 break;
2564         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2565                 PM8001_IO_DBG(pm8001_ha,
2566                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2567                 ts->resp = SAS_TASK_COMPLETE;
2568                 ts->stat = SAS_OPEN_REJECT;
2569                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2570                 break;
2571         case IO_XFER_ERROR_NAK_RECEIVED:
2572                 PM8001_IO_DBG(pm8001_ha,
2573                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2574                 ts->resp = SAS_TASK_COMPLETE;
2575                 ts->stat = SAS_NAK_R_ERR;
2576                 break;
2577         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2578                 PM8001_IO_DBG(pm8001_ha,
2579                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2580                 ts->resp = SAS_TASK_COMPLETE;
2581                 ts->stat = SAS_NAK_R_ERR;
2582                 break;
2583         case IO_XFER_ERROR_DMA:
2584                 PM8001_IO_DBG(pm8001_ha,
2585                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2586                 ts->resp = SAS_TASK_COMPLETE;
2587                 ts->stat = SAS_ABORTED_TASK;
2588                 break;
2589         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2590                 PM8001_IO_DBG(pm8001_ha,
2591                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2592                 ts->resp = SAS_TASK_UNDELIVERED;
2593                 ts->stat = SAS_DEV_NO_RESPONSE;
2594                 break;
2595         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2596                 PM8001_IO_DBG(pm8001_ha,
2597                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2598                 ts->resp = SAS_TASK_COMPLETE;
2599                 ts->stat = SAS_DATA_UNDERRUN;
2600                 break;
2601         case IO_XFER_OPEN_RETRY_TIMEOUT:
2602                 PM8001_IO_DBG(pm8001_ha,
2603                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2604                 ts->resp = SAS_TASK_COMPLETE;
2605                 ts->stat = SAS_OPEN_TO;
2606                 break;
2607         case IO_PORT_IN_RESET:
2608                 PM8001_IO_DBG(pm8001_ha,
2609                         pm8001_printk("IO_PORT_IN_RESET\n"));
2610                 ts->resp = SAS_TASK_COMPLETE;
2611                 ts->stat = SAS_DEV_NO_RESPONSE;
2612                 break;
2613         case IO_DS_NON_OPERATIONAL:
2614                 PM8001_IO_DBG(pm8001_ha,
2615                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2616                 ts->resp = SAS_TASK_COMPLETE;
2617                 ts->stat = SAS_DEV_NO_RESPONSE;
2618                 if (!t->uldd_task) {
2619                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2620                                     IO_DS_NON_OPERATIONAL);
2621                         ts->resp = SAS_TASK_UNDELIVERED;
2622                         ts->stat = SAS_QUEUE_FULL;
2623                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2624                         return;
2625                 }
2626                 break;
2627         case IO_DS_IN_RECOVERY:
2628                 PM8001_IO_DBG(pm8001_ha,
2629                         pm8001_printk("  IO_DS_IN_RECOVERY\n"));
2630                 ts->resp = SAS_TASK_COMPLETE;
2631                 ts->stat = SAS_DEV_NO_RESPONSE;
2632                 break;
2633         case IO_DS_IN_ERROR:
2634                 PM8001_IO_DBG(pm8001_ha,
2635                         pm8001_printk("IO_DS_IN_ERROR\n"));
2636                 ts->resp = SAS_TASK_COMPLETE;
2637                 ts->stat = SAS_DEV_NO_RESPONSE;
2638                 if (!t->uldd_task) {
2639                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2640                                     IO_DS_IN_ERROR);
2641                         ts->resp = SAS_TASK_UNDELIVERED;
2642                         ts->stat = SAS_QUEUE_FULL;
2643                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2644                         return;
2645                 }
2646                 break;
2647         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2648                 PM8001_IO_DBG(pm8001_ha,
2649                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2650                 ts->resp = SAS_TASK_COMPLETE;
2651                 ts->stat = SAS_OPEN_REJECT;
2652                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2653                 break;
2654         default:
2655                 PM8001_IO_DBG(pm8001_ha,
2656                         pm8001_printk("Unknown status 0x%x\n", status));
2657                 /* not allowed case. Therefore, return failed status */
2658                 ts->resp = SAS_TASK_COMPLETE;
2659                 ts->stat = SAS_DEV_NO_RESPONSE;
2660                 break;
2661         }
2662         spin_lock_irqsave(&t->task_state_lock, flags);
2663         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2664         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2665         t->task_state_flags |= SAS_TASK_STATE_DONE;
2666         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2667                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2668                 PM8001_FAIL_DBG(pm8001_ha,
2669                         pm8001_printk("task 0x%p done with io_status 0x%x"
2670                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2671                         t, status, ts->resp, ts->stat));
2672                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2673         } else {
2674                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2675                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2676         }
2677 }
2678
2679 /*See the comments for mpi_ssp_completion */
2680 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2681 {
2682         struct sas_task *t;
2683         struct task_status_struct *ts;
2684         struct pm8001_ccb_info *ccb;
2685         struct pm8001_device *pm8001_dev;
2686         struct sata_event_resp *psataPayload =
2687                 (struct sata_event_resp *)(piomb + 4);
2688         u32 event = le32_to_cpu(psataPayload->event);
2689         u32 tag = le32_to_cpu(psataPayload->tag);
2690         u32 port_id = le32_to_cpu(psataPayload->port_id);
2691         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2692         unsigned long flags;
2693
2694         ccb = &pm8001_ha->ccb_info[tag];
2695
2696         if (ccb) {
2697                 t = ccb->task;
2698                 pm8001_dev = ccb->device;
2699         } else {
2700                 PM8001_FAIL_DBG(pm8001_ha,
2701                         pm8001_printk("No CCB !!!. returning\n"));
2702         }
2703         if (event)
2704                 PM8001_FAIL_DBG(pm8001_ha,
2705                         pm8001_printk("SATA EVENT 0x%x\n", event));
2706
2707         /* Check if this is NCQ error */
2708         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2709                 /* find device using device id */
2710                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2711                 /* send read log extension */
2712                 if (pm8001_dev)
2713                         pm8001_send_read_log(pm8001_ha, pm8001_dev);
2714                 return;
2715         }
2716
2717         ccb = &pm8001_ha->ccb_info[tag];
2718         t = ccb->task;
2719         pm8001_dev = ccb->device;
2720         if (event)
2721                 PM8001_FAIL_DBG(pm8001_ha,
2722                         pm8001_printk("sata IO status 0x%x\n", event));
2723         if (unlikely(!t || !t->lldd_task || !t->dev))
2724                 return;
2725         ts = &t->task_status;
2726         PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2727                 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2728                 port_id, dev_id, tag, event));
2729         switch (event) {
2730         case IO_OVERFLOW:
2731                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2732                 ts->resp = SAS_TASK_COMPLETE;
2733                 ts->stat = SAS_DATA_OVERRUN;
2734                 ts->residual = 0;
2735                 if (pm8001_dev)
2736                         pm8001_dev->running_req--;
2737                 break;
2738         case IO_XFER_ERROR_BREAK:
2739                 PM8001_IO_DBG(pm8001_ha,
2740                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2741                 ts->resp = SAS_TASK_COMPLETE;
2742                 ts->stat = SAS_INTERRUPTED;
2743                 break;
2744         case IO_XFER_ERROR_PHY_NOT_READY:
2745                 PM8001_IO_DBG(pm8001_ha,
2746                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2747                 ts->resp = SAS_TASK_COMPLETE;
2748                 ts->stat = SAS_OPEN_REJECT;
2749                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2750                 break;
2751         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2752                 PM8001_IO_DBG(pm8001_ha,
2753                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2754                         "_SUPPORTED\n"));
2755                 ts->resp = SAS_TASK_COMPLETE;
2756                 ts->stat = SAS_OPEN_REJECT;
2757                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2758                 break;
2759         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2760                 PM8001_IO_DBG(pm8001_ha,
2761                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2762                 ts->resp = SAS_TASK_COMPLETE;
2763                 ts->stat = SAS_OPEN_REJECT;
2764                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2765                 break;
2766         case IO_OPEN_CNX_ERROR_BREAK:
2767                 PM8001_IO_DBG(pm8001_ha,
2768                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2769                 ts->resp = SAS_TASK_COMPLETE;
2770                 ts->stat = SAS_OPEN_REJECT;
2771                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2772                 break;
2773         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2774                 PM8001_IO_DBG(pm8001_ha,
2775                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2776                 ts->resp = SAS_TASK_UNDELIVERED;
2777                 ts->stat = SAS_DEV_NO_RESPONSE;
2778                 if (!t->uldd_task) {
2779                         pm8001_handle_event(pm8001_ha,
2780                                 pm8001_dev,
2781                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2782                         ts->resp = SAS_TASK_COMPLETE;
2783                         ts->stat = SAS_QUEUE_FULL;
2784                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2785                         return;
2786                 }
2787                 break;
2788         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2789                 PM8001_IO_DBG(pm8001_ha,
2790                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2791                 ts->resp = SAS_TASK_UNDELIVERED;
2792                 ts->stat = SAS_OPEN_REJECT;
2793                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2794                 break;
2795         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2796                 PM8001_IO_DBG(pm8001_ha,
2797                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2798                         "NOT_SUPPORTED\n"));
2799                 ts->resp = SAS_TASK_COMPLETE;
2800                 ts->stat = SAS_OPEN_REJECT;
2801                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2802                 break;
2803         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2804                 PM8001_IO_DBG(pm8001_ha,
2805                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2806                 ts->resp = SAS_TASK_COMPLETE;
2807                 ts->stat = SAS_OPEN_REJECT;
2808                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2809                 break;
2810         case IO_XFER_ERROR_NAK_RECEIVED:
2811                 PM8001_IO_DBG(pm8001_ha,
2812                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2813                 ts->resp = SAS_TASK_COMPLETE;
2814                 ts->stat = SAS_NAK_R_ERR;
2815                 break;
2816         case IO_XFER_ERROR_PEER_ABORTED:
2817                 PM8001_IO_DBG(pm8001_ha,
2818                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2819                 ts->resp = SAS_TASK_COMPLETE;
2820                 ts->stat = SAS_NAK_R_ERR;
2821                 break;
2822         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2823                 PM8001_IO_DBG(pm8001_ha,
2824                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2825                 ts->resp = SAS_TASK_COMPLETE;
2826                 ts->stat = SAS_DATA_UNDERRUN;
2827                 break;
2828         case IO_XFER_OPEN_RETRY_TIMEOUT:
2829                 PM8001_IO_DBG(pm8001_ha,
2830                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2831                 ts->resp = SAS_TASK_COMPLETE;
2832                 ts->stat = SAS_OPEN_TO;
2833                 break;
2834         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2835                 PM8001_IO_DBG(pm8001_ha,
2836                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2837                 ts->resp = SAS_TASK_COMPLETE;
2838                 ts->stat = SAS_OPEN_TO;
2839                 break;
2840         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2841                 PM8001_IO_DBG(pm8001_ha,
2842                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2843                 ts->resp = SAS_TASK_COMPLETE;
2844                 ts->stat = SAS_OPEN_TO;
2845                 break;
2846         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2847                 PM8001_IO_DBG(pm8001_ha,
2848                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2849                 ts->resp = SAS_TASK_COMPLETE;
2850                 ts->stat = SAS_OPEN_TO;
2851                 break;
2852         case IO_XFER_ERROR_OFFSET_MISMATCH:
2853                 PM8001_IO_DBG(pm8001_ha,
2854                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2855                 ts->resp = SAS_TASK_COMPLETE;
2856                 ts->stat = SAS_OPEN_TO;
2857                 break;
2858         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2859                 PM8001_IO_DBG(pm8001_ha,
2860                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2861                 ts->resp = SAS_TASK_COMPLETE;
2862                 ts->stat = SAS_OPEN_TO;
2863                 break;
2864         case IO_XFER_CMD_FRAME_ISSUED:
2865                 PM8001_IO_DBG(pm8001_ha,
2866                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2867                 break;
2868         case IO_XFER_PIO_SETUP_ERROR:
2869                 PM8001_IO_DBG(pm8001_ha,
2870                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2871                 ts->resp = SAS_TASK_COMPLETE;
2872                 ts->stat = SAS_OPEN_TO;
2873                 break;
2874         default:
2875                 PM8001_IO_DBG(pm8001_ha,
2876                         pm8001_printk("Unknown status 0x%x\n", event));
2877                 /* not allowed case. Therefore, return failed status */
2878                 ts->resp = SAS_TASK_COMPLETE;
2879                 ts->stat = SAS_OPEN_TO;
2880                 break;
2881         }
2882         spin_lock_irqsave(&t->task_state_lock, flags);
2883         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2884         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2885         t->task_state_flags |= SAS_TASK_STATE_DONE;
2886         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2887                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2888                 PM8001_FAIL_DBG(pm8001_ha,
2889                         pm8001_printk("task 0x%p done with io_status 0x%x"
2890                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2891                         t, event, ts->resp, ts->stat));
2892                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2893         } else {
2894                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2895                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2896         }
2897 }
2898
2899 /*See the comments for mpi_ssp_completion */
2900 static void
2901 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2902 {
2903         u32 param;
2904         struct sas_task *t;
2905         struct pm8001_ccb_info *ccb;
2906         unsigned long flags;
2907         u32 status;
2908         u32 tag;
2909         struct smp_completion_resp *psmpPayload;
2910         struct task_status_struct *ts;
2911         struct pm8001_device *pm8001_dev;
2912
2913         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2914         status = le32_to_cpu(psmpPayload->status);
2915         tag = le32_to_cpu(psmpPayload->tag);
2916
2917         ccb = &pm8001_ha->ccb_info[tag];
2918         param = le32_to_cpu(psmpPayload->param);
2919         t = ccb->task;
2920         ts = &t->task_status;
2921         pm8001_dev = ccb->device;
2922         if (status)
2923                 PM8001_FAIL_DBG(pm8001_ha,
2924                         pm8001_printk("smp IO status 0x%x\n", status));
2925         if (unlikely(!t || !t->lldd_task || !t->dev))
2926                 return;
2927
2928         switch (status) {
2929         case IO_SUCCESS:
2930                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2931                 ts->resp = SAS_TASK_COMPLETE;
2932                 ts->stat = SAM_STAT_GOOD;
2933         if (pm8001_dev)
2934                         pm8001_dev->running_req--;
2935                 break;
2936         case IO_ABORTED:
2937                 PM8001_IO_DBG(pm8001_ha,
2938                         pm8001_printk("IO_ABORTED IOMB\n"));
2939                 ts->resp = SAS_TASK_COMPLETE;
2940                 ts->stat = SAS_ABORTED_TASK;
2941                 if (pm8001_dev)
2942                         pm8001_dev->running_req--;
2943                 break;
2944         case IO_OVERFLOW:
2945                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2946                 ts->resp = SAS_TASK_COMPLETE;
2947                 ts->stat = SAS_DATA_OVERRUN;
2948                 ts->residual = 0;
2949                 if (pm8001_dev)
2950                         pm8001_dev->running_req--;
2951                 break;
2952         case IO_NO_DEVICE:
2953                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2954                 ts->resp = SAS_TASK_COMPLETE;
2955                 ts->stat = SAS_PHY_DOWN;
2956                 break;
2957         case IO_ERROR_HW_TIMEOUT:
2958                 PM8001_IO_DBG(pm8001_ha,
2959                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2960                 ts->resp = SAS_TASK_COMPLETE;
2961                 ts->stat = SAM_STAT_BUSY;
2962                 break;
2963         case IO_XFER_ERROR_BREAK:
2964                 PM8001_IO_DBG(pm8001_ha,
2965                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2966                 ts->resp = SAS_TASK_COMPLETE;
2967                 ts->stat = SAM_STAT_BUSY;
2968                 break;
2969         case IO_XFER_ERROR_PHY_NOT_READY:
2970                 PM8001_IO_DBG(pm8001_ha,
2971                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2972                 ts->resp = SAS_TASK_COMPLETE;
2973                 ts->stat = SAM_STAT_BUSY;
2974                 break;
2975         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2976                 PM8001_IO_DBG(pm8001_ha,
2977                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2978                 ts->resp = SAS_TASK_COMPLETE;
2979                 ts->stat = SAS_OPEN_REJECT;
2980                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2981                 break;
2982         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2983                 PM8001_IO_DBG(pm8001_ha,
2984                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2985                 ts->resp = SAS_TASK_COMPLETE;
2986                 ts->stat = SAS_OPEN_REJECT;
2987                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2988                 break;
2989         case IO_OPEN_CNX_ERROR_BREAK:
2990                 PM8001_IO_DBG(pm8001_ha,
2991                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2992                 ts->resp = SAS_TASK_COMPLETE;
2993                 ts->stat = SAS_OPEN_REJECT;
2994                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2995                 break;
2996         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2997                 PM8001_IO_DBG(pm8001_ha,
2998                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2999                 ts->resp = SAS_TASK_COMPLETE;
3000                 ts->stat = SAS_OPEN_REJECT;
3001                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3002                 pm8001_handle_event(pm8001_ha,
3003                                 pm8001_dev,
3004                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3005                 break;
3006         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3007                 PM8001_IO_DBG(pm8001_ha,
3008                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
3009                 ts->resp = SAS_TASK_COMPLETE;
3010                 ts->stat = SAS_OPEN_REJECT;
3011                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3012                 break;
3013         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3014                 PM8001_IO_DBG(pm8001_ha,
3015                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
3016                         "NOT_SUPPORTED\n"));
3017                 ts->resp = SAS_TASK_COMPLETE;
3018                 ts->stat = SAS_OPEN_REJECT;
3019                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3020                 break;
3021         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3022                 PM8001_IO_DBG(pm8001_ha,
3023                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
3024                 ts->resp = SAS_TASK_COMPLETE;
3025                 ts->stat = SAS_OPEN_REJECT;
3026                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3027                 break;
3028         case IO_XFER_ERROR_RX_FRAME:
3029                 PM8001_IO_DBG(pm8001_ha,
3030                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
3031                 ts->resp = SAS_TASK_COMPLETE;
3032                 ts->stat = SAS_DEV_NO_RESPONSE;
3033                 break;
3034         case IO_XFER_OPEN_RETRY_TIMEOUT:
3035                 PM8001_IO_DBG(pm8001_ha,
3036                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
3037                 ts->resp = SAS_TASK_COMPLETE;
3038                 ts->stat = SAS_OPEN_REJECT;
3039                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3040                 break;
3041         case IO_ERROR_INTERNAL_SMP_RESOURCE:
3042                 PM8001_IO_DBG(pm8001_ha,
3043                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
3044                 ts->resp = SAS_TASK_COMPLETE;
3045                 ts->stat = SAS_QUEUE_FULL;
3046                 break;
3047         case IO_PORT_IN_RESET:
3048                 PM8001_IO_DBG(pm8001_ha,
3049                         pm8001_printk("IO_PORT_IN_RESET\n"));
3050                 ts->resp = SAS_TASK_COMPLETE;
3051                 ts->stat = SAS_OPEN_REJECT;
3052                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3053                 break;
3054         case IO_DS_NON_OPERATIONAL:
3055                 PM8001_IO_DBG(pm8001_ha,
3056                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
3057                 ts->resp = SAS_TASK_COMPLETE;
3058                 ts->stat = SAS_DEV_NO_RESPONSE;
3059                 break;
3060         case IO_DS_IN_RECOVERY:
3061                 PM8001_IO_DBG(pm8001_ha,
3062                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
3063                 ts->resp = SAS_TASK_COMPLETE;
3064                 ts->stat = SAS_OPEN_REJECT;
3065                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3066                 break;
3067         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3068                 PM8001_IO_DBG(pm8001_ha,
3069                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
3070                 ts->resp = SAS_TASK_COMPLETE;
3071                 ts->stat = SAS_OPEN_REJECT;
3072                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3073                 break;
3074         default:
3075                 PM8001_IO_DBG(pm8001_ha,
3076                         pm8001_printk("Unknown status 0x%x\n", status));
3077                 ts->resp = SAS_TASK_COMPLETE;
3078                 ts->stat = SAS_DEV_NO_RESPONSE;
3079                 /* not allowed case. Therefore, return failed status */
3080                 break;
3081         }
3082         spin_lock_irqsave(&t->task_state_lock, flags);
3083         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3084         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3085         t->task_state_flags |= SAS_TASK_STATE_DONE;
3086         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3087                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3088                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
3089                         " io_status 0x%x resp 0x%x "
3090                         "stat 0x%x but aborted by upper layer!\n",
3091                         t, status, ts->resp, ts->stat));
3092                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3093         } else {
3094                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3095                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3096                 mb();/* in order to force CPU ordering */
3097                 t->task_done(t);
3098         }
3099 }
3100
3101 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
3102                 void *piomb)
3103 {
3104         struct set_dev_state_resp *pPayload =
3105                 (struct set_dev_state_resp *)(piomb + 4);
3106         u32 tag = le32_to_cpu(pPayload->tag);
3107         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3108         struct pm8001_device *pm8001_dev = ccb->device;
3109         u32 status = le32_to_cpu(pPayload->status);
3110         u32 device_id = le32_to_cpu(pPayload->device_id);
3111         u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
3112         u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
3113         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
3114                 "from 0x%x to 0x%x status = 0x%x!\n",
3115                 device_id, pds, nds, status));
3116         complete(pm8001_dev->setds_completion);
3117         ccb->task = NULL;
3118         ccb->ccb_tag = 0xFFFFFFFF;
3119         pm8001_tag_free(pm8001_ha, tag);
3120 }
3121
3122 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3123 {
3124         struct get_nvm_data_resp *pPayload =
3125                 (struct get_nvm_data_resp *)(piomb + 4);
3126         u32 tag = le32_to_cpu(pPayload->tag);
3127         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3128         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3129         complete(pm8001_ha->nvmd_completion);
3130         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
3131         if ((dlen_status & NVMD_STAT) != 0) {
3132                 PM8001_FAIL_DBG(pm8001_ha,
3133                         pm8001_printk("Set nvm data error!\n"));
3134                 return;
3135         }
3136         ccb->task = NULL;
3137         ccb->ccb_tag = 0xFFFFFFFF;
3138         pm8001_tag_free(pm8001_ha, tag);
3139 }
3140
3141 void
3142 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3143 {
3144         struct fw_control_ex    *fw_control_context;
3145         struct get_nvm_data_resp *pPayload =
3146                 (struct get_nvm_data_resp *)(piomb + 4);
3147         u32 tag = le32_to_cpu(pPayload->tag);
3148         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3149         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3150         u32 ir_tds_bn_dps_das_nvm =
3151                 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3152         void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3153         fw_control_context = ccb->fw_control_context;
3154
3155         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
3156         if ((dlen_status & NVMD_STAT) != 0) {
3157                 PM8001_FAIL_DBG(pm8001_ha,
3158                         pm8001_printk("Get nvm data error!\n"));
3159                 complete(pm8001_ha->nvmd_completion);
3160                 return;
3161         }
3162
3163         if (ir_tds_bn_dps_das_nvm & IPMode) {
3164                 /* indirect mode - IR bit set */
3165                 PM8001_MSG_DBG(pm8001_ha,
3166                         pm8001_printk("Get NVMD success, IR=1\n"));
3167                 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3168                         if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3169                                 memcpy(pm8001_ha->sas_addr,
3170                                       ((u8 *)virt_addr + 4),
3171                                        SAS_ADDR_SIZE);
3172                                 PM8001_MSG_DBG(pm8001_ha,
3173                                         pm8001_printk("Get SAS address"
3174                                         " from VPD successfully!\n"));
3175                         }
3176                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3177                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3178                         ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3179                                 ;
3180                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3181                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3182                         ;
3183                 } else {
3184                         /* Should not be happened*/
3185                         PM8001_MSG_DBG(pm8001_ha,
3186                                 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
3187                                 ir_tds_bn_dps_das_nvm));
3188                 }
3189         } else /* direct mode */{
3190                 PM8001_MSG_DBG(pm8001_ha,
3191                         pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
3192                         (dlen_status & NVMD_LEN) >> 24));
3193         }
3194         /* Though fw_control_context is freed below, usrAddr still needs
3195          * to be updated as this holds the response to the request function
3196          */
3197         memcpy(fw_control_context->usrAddr,
3198                 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3199                 fw_control_context->len);
3200         kfree(ccb->fw_control_context);
3201         ccb->task = NULL;
3202         ccb->ccb_tag = 0xFFFFFFFF;
3203         pm8001_tag_free(pm8001_ha, tag);
3204         complete(pm8001_ha->nvmd_completion);
3205 }
3206
3207 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3208 {
3209         u32 tag;
3210         struct local_phy_ctl_resp *pPayload =
3211                 (struct local_phy_ctl_resp *)(piomb + 4);
3212         u32 status = le32_to_cpu(pPayload->status);
3213         u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3214         u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3215         tag = le32_to_cpu(pPayload->tag);
3216         if (status != 0) {
3217                 PM8001_MSG_DBG(pm8001_ha,
3218                         pm8001_printk("%x phy execute %x phy op failed!\n",
3219                         phy_id, phy_op));
3220         } else {
3221                 PM8001_MSG_DBG(pm8001_ha,
3222                         pm8001_printk("%x phy execute %x phy op success!\n",
3223                         phy_id, phy_op));
3224                 pm8001_ha->phy[phy_id].reset_success = true;
3225         }
3226         if (pm8001_ha->phy[phy_id].enable_completion) {
3227                 complete(pm8001_ha->phy[phy_id].enable_completion);
3228                 pm8001_ha->phy[phy_id].enable_completion = NULL;
3229         }
3230         pm8001_tag_free(pm8001_ha, tag);
3231         return 0;
3232 }
3233
3234 /**
3235  * pm8001_bytes_dmaed - one of the interface function communication with libsas
3236  * @pm8001_ha: our hba card information
3237  * @i: which phy that received the event.
3238  *
3239  * when HBA driver received the identify done event or initiate FIS received
3240  * event(for SATA), it will invoke this function to notify the sas layer that
3241  * the sas toplogy has formed, please discover the the whole sas domain,
3242  * while receive a broadcast(change) primitive just tell the sas
3243  * layer to discover the changed domain rather than the whole domain.
3244  */
3245 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3246 {
3247         struct pm8001_phy *phy = &pm8001_ha->phy[i];
3248         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3249         struct sas_ha_struct *sas_ha;
3250         if (!phy->phy_attached)
3251                 return;
3252
3253         sas_ha = pm8001_ha->sas;
3254         if (sas_phy->phy) {
3255                 struct sas_phy *sphy = sas_phy->phy;
3256                 sphy->negotiated_linkrate = sas_phy->linkrate;
3257                 sphy->minimum_linkrate = phy->minimum_linkrate;
3258                 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3259                 sphy->maximum_linkrate = phy->maximum_linkrate;
3260                 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3261         }
3262
3263         if (phy->phy_type & PORT_TYPE_SAS) {
3264                 struct sas_identify_frame *id;
3265                 id = (struct sas_identify_frame *)phy->frame_rcvd;
3266                 id->dev_type = phy->identify.device_type;
3267                 id->initiator_bits = SAS_PROTOCOL_ALL;
3268                 id->target_bits = phy->identify.target_port_protocols;
3269         } else if (phy->phy_type & PORT_TYPE_SATA) {
3270                 /*Nothing*/
3271         }
3272         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
3273
3274         sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3275         pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
3276 }
3277
3278 /* Get the link rate speed  */
3279 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3280 {
3281         struct sas_phy *sas_phy = phy->sas_phy.phy;
3282
3283         switch (link_rate) {
3284         case PHY_SPEED_120:
3285                 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS;
3286                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS;
3287                 break;
3288         case PHY_SPEED_60:
3289                 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3290                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3291                 break;
3292         case PHY_SPEED_30:
3293                 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3294                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3295                 break;
3296         case PHY_SPEED_15:
3297                 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3298                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3299                 break;
3300         }
3301         sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3302         sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3303         sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3304         sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3305         sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3306 }
3307
3308 /**
3309  * asd_get_attached_sas_addr -- extract/generate attached SAS address
3310  * @phy: pointer to asd_phy
3311  * @sas_addr: pointer to buffer where the SAS address is to be written
3312  *
3313  * This function extracts the SAS address from an IDENTIFY frame
3314  * received.  If OOB is SATA, then a SAS address is generated from the
3315  * HA tables.
3316  *
3317  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3318  * buffer.
3319  */
3320 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3321         u8 *sas_addr)
3322 {
3323         if (phy->sas_phy.frame_rcvd[0] == 0x34
3324                 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3325                 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3326                 /* FIS device-to-host */
3327                 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3328                 addr += phy->sas_phy.id;
3329                 *(__be64 *)sas_addr = cpu_to_be64(addr);
3330         } else {
3331                 struct sas_identify_frame *idframe =
3332                         (void *) phy->sas_phy.frame_rcvd;
3333                 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3334         }
3335 }
3336
3337 /**
3338  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3339  * @pm8001_ha: our hba card information
3340  * @Qnum: the outbound queue message number.
3341  * @SEA: source of event to ack
3342  * @port_id: port id.
3343  * @phyId: phy id.
3344  * @param0: parameter 0.
3345  * @param1: parameter 1.
3346  */
3347 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3348         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3349 {
3350         struct hw_event_ack_req  payload;
3351         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3352
3353         struct inbound_queue_table *circularQ;
3354
3355         memset((u8 *)&payload, 0, sizeof(payload));
3356         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3357         payload.tag = cpu_to_le32(1);
3358         payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3359                 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3360         payload.param0 = cpu_to_le32(param0);
3361         payload.param1 = cpu_to_le32(param1);
3362         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
3363 }
3364
3365 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3366         u32 phyId, u32 phy_op);
3367
3368 /**
3369  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3370  * @pm8001_ha: our hba card information
3371  * @piomb: IO message buffer
3372  */
3373 static void
3374 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3375 {
3376         struct hw_event_resp *pPayload =
3377                 (struct hw_event_resp *)(piomb + 4);
3378         u32 lr_evt_status_phyid_portid =
3379                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3380         u8 link_rate =
3381                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3382         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3383         u8 phy_id =
3384                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3385         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3386         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3387         struct pm8001_port *port = &pm8001_ha->port[port_id];
3388         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3389         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3390         unsigned long flags;
3391         u8 deviceType = pPayload->sas_identify.dev_type;
3392         port->port_state =  portstate;
3393         phy->phy_state = PHY_STATE_LINK_UP_SPC;
3394         PM8001_MSG_DBG(pm8001_ha,
3395                 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3396                 port_id, phy_id));
3397
3398         switch (deviceType) {
3399         case SAS_PHY_UNUSED:
3400                 PM8001_MSG_DBG(pm8001_ha,
3401                         pm8001_printk("device type no device.\n"));
3402                 break;
3403         case SAS_END_DEVICE:
3404                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3405                 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3406                         PHY_NOTIFY_ENABLE_SPINUP);
3407                 port->port_attached = 1;
3408                 pm8001_get_lrate_mode(phy, link_rate);
3409                 break;
3410         case SAS_EDGE_EXPANDER_DEVICE:
3411                 PM8001_MSG_DBG(pm8001_ha,
3412                         pm8001_printk("expander device.\n"));
3413                 port->port_attached = 1;
3414                 pm8001_get_lrate_mode(phy, link_rate);
3415                 break;
3416         case SAS_FANOUT_EXPANDER_DEVICE:
3417                 PM8001_MSG_DBG(pm8001_ha,
3418                         pm8001_printk("fanout expander device.\n"));
3419                 port->port_attached = 1;
3420                 pm8001_get_lrate_mode(phy, link_rate);
3421                 break;
3422         default:
3423                 PM8001_MSG_DBG(pm8001_ha,
3424                         pm8001_printk("unknown device type(%x)\n", deviceType));
3425                 break;
3426         }
3427         phy->phy_type |= PORT_TYPE_SAS;
3428         phy->identify.device_type = deviceType;
3429         phy->phy_attached = 1;
3430         if (phy->identify.device_type == SAS_END_DEVICE)
3431                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3432         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3433                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3434         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3435         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3436         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3437         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3438                 sizeof(struct sas_identify_frame)-4);
3439         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3440         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3441         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3442         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3443                 mdelay(200);/*delay a moment to wait disk to spinup*/
3444         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3445 }
3446
3447 /**
3448  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3449  * @pm8001_ha: our hba card information
3450  * @piomb: IO message buffer
3451  */
3452 static void
3453 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3454 {
3455         struct hw_event_resp *pPayload =
3456                 (struct hw_event_resp *)(piomb + 4);
3457         u32 lr_evt_status_phyid_portid =
3458                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3459         u8 link_rate =
3460                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3461         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3462         u8 phy_id =
3463                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3464         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3465         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3466         struct pm8001_port *port = &pm8001_ha->port[port_id];
3467         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3468         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3469         unsigned long flags;
3470         PM8001_MSG_DBG(pm8001_ha,
3471                 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3472                 " phy id = %d\n", port_id, phy_id));
3473         port->port_state =  portstate;
3474         phy->phy_state = PHY_STATE_LINK_UP_SPC;
3475         port->port_attached = 1;
3476         pm8001_get_lrate_mode(phy, link_rate);
3477         phy->phy_type |= PORT_TYPE_SATA;
3478         phy->phy_attached = 1;
3479         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3480         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3481         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3482         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3483                 sizeof(struct dev_to_host_fis));
3484         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3485         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3486         phy->identify.device_type = SAS_SATA_DEV;
3487         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3488         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3489         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3490 }
3491
3492 /**
3493  * hw_event_phy_down -we should notify the libsas the phy is down.
3494  * @pm8001_ha: our hba card information
3495  * @piomb: IO message buffer
3496  */
3497 static void
3498 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3499 {
3500         struct hw_event_resp *pPayload =
3501                 (struct hw_event_resp *)(piomb + 4);
3502         u32 lr_evt_status_phyid_portid =
3503                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3504         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3505         u8 phy_id =
3506                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3507         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3508         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3509         struct pm8001_port *port = &pm8001_ha->port[port_id];
3510         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3511         port->port_state =  portstate;
3512         phy->phy_type = 0;
3513         phy->identify.device_type = 0;
3514         phy->phy_attached = 0;
3515         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3516         switch (portstate) {
3517         case PORT_VALID:
3518                 break;
3519         case PORT_INVALID:
3520                 PM8001_MSG_DBG(pm8001_ha,
3521                         pm8001_printk(" PortInvalid portID %d\n", port_id));
3522                 PM8001_MSG_DBG(pm8001_ha,
3523                         pm8001_printk(" Last phy Down and port invalid\n"));
3524                 port->port_attached = 0;
3525                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3526                         port_id, phy_id, 0, 0);
3527                 break;
3528         case PORT_IN_RESET:
3529                 PM8001_MSG_DBG(pm8001_ha,
3530                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3531                 break;
3532         case PORT_NOT_ESTABLISHED:
3533                 PM8001_MSG_DBG(pm8001_ha,
3534                         pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3535                 port->port_attached = 0;
3536                 break;
3537         case PORT_LOSTCOMM:
3538                 PM8001_MSG_DBG(pm8001_ha,
3539                         pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3540                 PM8001_MSG_DBG(pm8001_ha,
3541                         pm8001_printk(" Last phy Down and port invalid\n"));
3542                 port->port_attached = 0;
3543                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3544                         port_id, phy_id, 0, 0);
3545                 break;
3546         default:
3547                 port->port_attached = 0;
3548                 PM8001_MSG_DBG(pm8001_ha,
3549                         pm8001_printk(" phy Down and(default) = %x\n",
3550                         portstate));
3551                 break;
3552
3553         }
3554 }
3555
3556 /**
3557  * pm8001_mpi_reg_resp -process register device ID response.
3558  * @pm8001_ha: our hba card information
3559  * @piomb: IO message buffer
3560  *
3561  * when sas layer find a device it will notify LLDD, then the driver register
3562  * the domain device to FW, this event is the return device ID which the FW
3563  * has assigned, from now,inter-communication with FW is no longer using the
3564  * SAS address, use device ID which FW assigned.
3565  */
3566 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3567 {
3568         u32 status;
3569         u32 device_id;
3570         u32 htag;
3571         struct pm8001_ccb_info *ccb;
3572         struct pm8001_device *pm8001_dev;
3573         struct dev_reg_resp *registerRespPayload =
3574                 (struct dev_reg_resp *)(piomb + 4);
3575
3576         htag = le32_to_cpu(registerRespPayload->tag);
3577         ccb = &pm8001_ha->ccb_info[htag];
3578         pm8001_dev = ccb->device;
3579         status = le32_to_cpu(registerRespPayload->status);
3580         device_id = le32_to_cpu(registerRespPayload->device_id);
3581         PM8001_MSG_DBG(pm8001_ha,
3582                 pm8001_printk(" register device is status = %d\n", status));
3583         switch (status) {
3584         case DEVREG_SUCCESS:
3585                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3586                 pm8001_dev->device_id = device_id;
3587                 break;
3588         case DEVREG_FAILURE_OUT_OF_RESOURCE:
3589                 PM8001_MSG_DBG(pm8001_ha,
3590                         pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3591                 break;
3592         case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3593                 PM8001_MSG_DBG(pm8001_ha,
3594                    pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3595                 break;
3596         case DEVREG_FAILURE_INVALID_PHY_ID:
3597                 PM8001_MSG_DBG(pm8001_ha,
3598                         pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3599                 break;
3600         case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3601                 PM8001_MSG_DBG(pm8001_ha,
3602                    pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3603                 break;
3604         case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3605                 PM8001_MSG_DBG(pm8001_ha,
3606                         pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3607                 break;
3608         case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3609                 PM8001_MSG_DBG(pm8001_ha,
3610                         pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3611                 break;
3612         case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3613                 PM8001_MSG_DBG(pm8001_ha,
3614                        pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3615                 break;
3616         default:
3617                 PM8001_MSG_DBG(pm8001_ha,
3618                         pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n"));
3619                 break;
3620         }
3621         complete(pm8001_dev->dcompletion);
3622         ccb->task = NULL;
3623         ccb->ccb_tag = 0xFFFFFFFF;
3624         pm8001_tag_free(pm8001_ha, htag);
3625         return 0;
3626 }
3627
3628 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3629 {
3630         u32 status;
3631         u32 device_id;
3632         struct dev_reg_resp *registerRespPayload =
3633                 (struct dev_reg_resp *)(piomb + 4);
3634
3635         status = le32_to_cpu(registerRespPayload->status);
3636         device_id = le32_to_cpu(registerRespPayload->device_id);
3637         if (status != 0)
3638                 PM8001_MSG_DBG(pm8001_ha,
3639                         pm8001_printk(" deregister device failed ,status = %x"
3640                         ", device_id = %x\n", status, device_id));
3641         return 0;
3642 }
3643
3644 /**
3645  * fw_flash_update_resp - Response from FW for flash update command.
3646  * @pm8001_ha: our hba card information
3647  * @piomb: IO message buffer
3648  */
3649 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3650                 void *piomb)
3651 {
3652         u32 status;
3653         struct fw_flash_Update_resp *ppayload =
3654                 (struct fw_flash_Update_resp *)(piomb + 4);
3655         u32 tag = le32_to_cpu(ppayload->tag);
3656         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3657         status = le32_to_cpu(ppayload->status);
3658         switch (status) {
3659         case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3660                 PM8001_MSG_DBG(pm8001_ha,
3661                 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3662                 break;
3663         case FLASH_UPDATE_IN_PROGRESS:
3664                 PM8001_MSG_DBG(pm8001_ha,
3665                         pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3666                 break;
3667         case FLASH_UPDATE_HDR_ERR:
3668                 PM8001_MSG_DBG(pm8001_ha,
3669                         pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3670                 break;
3671         case FLASH_UPDATE_OFFSET_ERR:
3672                 PM8001_MSG_DBG(pm8001_ha,
3673                         pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3674                 break;
3675         case FLASH_UPDATE_CRC_ERR:
3676                 PM8001_MSG_DBG(pm8001_ha,
3677                         pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3678                 break;
3679         case FLASH_UPDATE_LENGTH_ERR:
3680                 PM8001_MSG_DBG(pm8001_ha,
3681                         pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3682                 break;
3683         case FLASH_UPDATE_HW_ERR:
3684                 PM8001_MSG_DBG(pm8001_ha,
3685                         pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3686                 break;
3687         case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3688                 PM8001_MSG_DBG(pm8001_ha,
3689                         pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3690                 break;
3691         case FLASH_UPDATE_DISABLED:
3692                 PM8001_MSG_DBG(pm8001_ha,
3693                         pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3694                 break;
3695         default:
3696                 PM8001_MSG_DBG(pm8001_ha,
3697                         pm8001_printk("No matched status = %d\n", status));
3698                 break;
3699         }
3700         kfree(ccb->fw_control_context);
3701         ccb->task = NULL;
3702         ccb->ccb_tag = 0xFFFFFFFF;
3703         pm8001_tag_free(pm8001_ha, tag);
3704         complete(pm8001_ha->nvmd_completion);
3705         return 0;
3706 }
3707
3708 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3709 {
3710         u32 status;
3711         int i;
3712         struct general_event_resp *pPayload =
3713                 (struct general_event_resp *)(piomb + 4);
3714         status = le32_to_cpu(pPayload->status);
3715         PM8001_MSG_DBG(pm8001_ha,
3716                 pm8001_printk(" status = 0x%x\n", status));
3717         for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3718                 PM8001_MSG_DBG(pm8001_ha,
3719                         pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3720                         pPayload->inb_IOMB_payload[i]));
3721         return 0;
3722 }
3723
3724 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3725 {
3726         struct sas_task *t;
3727         struct pm8001_ccb_info *ccb;
3728         unsigned long flags;
3729         u32 status ;
3730         u32 tag, scp;
3731         struct task_status_struct *ts;
3732         struct pm8001_device *pm8001_dev;
3733
3734         struct task_abort_resp *pPayload =
3735                 (struct task_abort_resp *)(piomb + 4);
3736
3737         status = le32_to_cpu(pPayload->status);
3738         tag = le32_to_cpu(pPayload->tag);
3739         if (!tag) {
3740                 PM8001_FAIL_DBG(pm8001_ha,
3741                         pm8001_printk(" TAG NULL. RETURNING !!!"));
3742                 return -1;
3743         }
3744
3745         scp = le32_to_cpu(pPayload->scp);
3746         ccb = &pm8001_ha->ccb_info[tag];
3747         t = ccb->task;
3748         pm8001_dev = ccb->device; /* retrieve device */
3749
3750         if (!t) {
3751                 PM8001_FAIL_DBG(pm8001_ha,
3752                         pm8001_printk(" TASK NULL. RETURNING !!!"));
3753                 return -1;
3754         }
3755         ts = &t->task_status;
3756         if (status != 0)
3757                 PM8001_FAIL_DBG(pm8001_ha,
3758                         pm8001_printk("task abort failed status 0x%x ,"
3759                         "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3760         switch (status) {
3761         case IO_SUCCESS:
3762                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3763                 ts->resp = SAS_TASK_COMPLETE;
3764                 ts->stat = SAM_STAT_GOOD;
3765                 break;
3766         case IO_NOT_VALID:
3767                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3768                 ts->resp = TMF_RESP_FUNC_FAILED;
3769                 break;
3770         }
3771         spin_lock_irqsave(&t->task_state_lock, flags);
3772         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3773         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3774         t->task_state_flags |= SAS_TASK_STATE_DONE;
3775         spin_unlock_irqrestore(&t->task_state_lock, flags);
3776         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3777         mb();
3778
3779         if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
3780                 sas_free_task(t);
3781                 pm8001_dev->id &= ~NCQ_ABORT_ALL_FLAG;
3782         } else {
3783                 t->task_done(t);
3784         }
3785
3786         return 0;
3787 }
3788
3789 /**
3790  * mpi_hw_event -The hw event has come.
3791  * @pm8001_ha: our hba card information
3792  * @piomb: IO message buffer
3793  */
3794 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3795 {
3796         unsigned long flags;
3797         struct hw_event_resp *pPayload =
3798                 (struct hw_event_resp *)(piomb + 4);
3799         u32 lr_evt_status_phyid_portid =
3800                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3801         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3802         u8 phy_id =
3803                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3804         u16 eventType =
3805                 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3806         u8 status =
3807                 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3808         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3809         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3810         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3811         PM8001_MSG_DBG(pm8001_ha,
3812                 pm8001_printk("outbound queue HW event & event type : "));
3813         switch (eventType) {
3814         case HW_EVENT_PHY_START_STATUS:
3815                 PM8001_MSG_DBG(pm8001_ha,
3816                 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3817                         " status = %x\n", status));
3818                 if (status == 0) {
3819                         phy->phy_state = 1;
3820                         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3821                                 complete(phy->enable_completion);
3822                 }
3823                 break;
3824         case HW_EVENT_SAS_PHY_UP:
3825                 PM8001_MSG_DBG(pm8001_ha,
3826                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3827                 hw_event_sas_phy_up(pm8001_ha, piomb);
3828                 break;
3829         case HW_EVENT_SATA_PHY_UP:
3830                 PM8001_MSG_DBG(pm8001_ha,
3831                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3832                 hw_event_sata_phy_up(pm8001_ha, piomb);
3833                 break;
3834         case HW_EVENT_PHY_STOP_STATUS:
3835                 PM8001_MSG_DBG(pm8001_ha,
3836                         pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3837                         "status = %x\n", status));
3838                 if (status == 0)
3839                         phy->phy_state = 0;
3840                 break;
3841         case HW_EVENT_SATA_SPINUP_HOLD:
3842                 PM8001_MSG_DBG(pm8001_ha,
3843                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3844                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3845                 break;
3846         case HW_EVENT_PHY_DOWN:
3847                 PM8001_MSG_DBG(pm8001_ha,
3848                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3849                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3850                 phy->phy_attached = 0;
3851                 phy->phy_state = 0;
3852                 hw_event_phy_down(pm8001_ha, piomb);
3853                 break;
3854         case HW_EVENT_PORT_INVALID:
3855                 PM8001_MSG_DBG(pm8001_ha,
3856                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3857                 sas_phy_disconnected(sas_phy);
3858                 phy->phy_attached = 0;
3859                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3860                 break;
3861         /* the broadcast change primitive received, tell the LIBSAS this event
3862         to revalidate the sas domain*/
3863         case HW_EVENT_BROADCAST_CHANGE:
3864                 PM8001_MSG_DBG(pm8001_ha,
3865                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3866                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3867                         port_id, phy_id, 1, 0);
3868                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3869                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3870                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3871                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3872                 break;
3873         case HW_EVENT_PHY_ERROR:
3874                 PM8001_MSG_DBG(pm8001_ha,
3875                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3876                 sas_phy_disconnected(&phy->sas_phy);
3877                 phy->phy_attached = 0;
3878                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3879                 break;
3880         case HW_EVENT_BROADCAST_EXP:
3881                 PM8001_MSG_DBG(pm8001_ha,
3882                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3883                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3884                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3885                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3886                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3887                 break;
3888         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3889                 PM8001_MSG_DBG(pm8001_ha,
3890                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3891                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3892                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3893                 sas_phy_disconnected(sas_phy);
3894                 phy->phy_attached = 0;
3895                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3896                 break;
3897         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3898                 PM8001_MSG_DBG(pm8001_ha,
3899                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3900                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3901                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3902                         port_id, phy_id, 0, 0);
3903                 sas_phy_disconnected(sas_phy);
3904                 phy->phy_attached = 0;
3905                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3906                 break;
3907         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3908                 PM8001_MSG_DBG(pm8001_ha,
3909                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3910                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3911                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3912                         port_id, phy_id, 0, 0);
3913                 sas_phy_disconnected(sas_phy);
3914                 phy->phy_attached = 0;
3915                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3916                 break;
3917         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3918                 PM8001_MSG_DBG(pm8001_ha,
3919                       pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3920                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3921                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3922                         port_id, phy_id, 0, 0);
3923                 sas_phy_disconnected(sas_phy);
3924                 phy->phy_attached = 0;
3925                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3926                 break;
3927         case HW_EVENT_MALFUNCTION:
3928                 PM8001_MSG_DBG(pm8001_ha,
3929                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3930                 break;
3931         case HW_EVENT_BROADCAST_SES:
3932                 PM8001_MSG_DBG(pm8001_ha,
3933                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3934                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3935                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3936                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3937                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3938                 break;
3939         case HW_EVENT_INBOUND_CRC_ERROR:
3940                 PM8001_MSG_DBG(pm8001_ha,
3941                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3942                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3943                         HW_EVENT_INBOUND_CRC_ERROR,
3944                         port_id, phy_id, 0, 0);
3945                 break;
3946         case HW_EVENT_HARD_RESET_RECEIVED:
3947                 PM8001_MSG_DBG(pm8001_ha,
3948                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3949                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3950                 break;
3951         case HW_EVENT_ID_FRAME_TIMEOUT:
3952                 PM8001_MSG_DBG(pm8001_ha,
3953                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3954                 sas_phy_disconnected(sas_phy);
3955                 phy->phy_attached = 0;
3956                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3957                 break;
3958         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3959                 PM8001_MSG_DBG(pm8001_ha,
3960                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3961                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3962                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3963                         port_id, phy_id, 0, 0);
3964                 sas_phy_disconnected(sas_phy);
3965                 phy->phy_attached = 0;
3966                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3967                 break;
3968         case HW_EVENT_PORT_RESET_TIMER_TMO:
3969                 PM8001_MSG_DBG(pm8001_ha,
3970                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3971                 sas_phy_disconnected(sas_phy);
3972                 phy->phy_attached = 0;
3973                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3974                 break;
3975         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3976                 PM8001_MSG_DBG(pm8001_ha,
3977                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3978                 sas_phy_disconnected(sas_phy);
3979                 phy->phy_attached = 0;
3980                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3981                 break;
3982         case HW_EVENT_PORT_RECOVER:
3983                 PM8001_MSG_DBG(pm8001_ha,
3984                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3985                 break;
3986         case HW_EVENT_PORT_RESET_COMPLETE:
3987                 PM8001_MSG_DBG(pm8001_ha,
3988                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3989                 break;
3990         case EVENT_BROADCAST_ASYNCH_EVENT:
3991                 PM8001_MSG_DBG(pm8001_ha,
3992                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3993                 break;
3994         default:
3995                 PM8001_MSG_DBG(pm8001_ha,
3996                         pm8001_printk("Unknown event type = %x\n", eventType));
3997                 break;
3998         }
3999         return 0;
4000 }
4001
4002 /**
4003  * process_one_iomb - process one outbound Queue memory block
4004  * @pm8001_ha: our hba card information
4005  * @piomb: IO message buffer
4006  */
4007 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
4008 {
4009         __le32 pHeader = *(__le32 *)piomb;
4010         u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
4011
4012         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
4013
4014         switch (opc) {
4015         case OPC_OUB_ECHO:
4016                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
4017                 break;
4018         case OPC_OUB_HW_EVENT:
4019                 PM8001_MSG_DBG(pm8001_ha,
4020                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
4021                 mpi_hw_event(pm8001_ha, piomb);
4022                 break;
4023         case OPC_OUB_SSP_COMP:
4024                 PM8001_MSG_DBG(pm8001_ha,
4025                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
4026                 mpi_ssp_completion(pm8001_ha, piomb);
4027                 break;
4028         case OPC_OUB_SMP_COMP:
4029                 PM8001_MSG_DBG(pm8001_ha,
4030                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
4031                 mpi_smp_completion(pm8001_ha, piomb);
4032                 break;
4033         case OPC_OUB_LOCAL_PHY_CNTRL:
4034                 PM8001_MSG_DBG(pm8001_ha,
4035                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
4036                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
4037                 break;
4038         case OPC_OUB_DEV_REGIST:
4039                 PM8001_MSG_DBG(pm8001_ha,
4040                         pm8001_printk("OPC_OUB_DEV_REGIST\n"));
4041                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
4042                 break;
4043         case OPC_OUB_DEREG_DEV:
4044                 PM8001_MSG_DBG(pm8001_ha,
4045                         pm8001_printk("unregister the device\n"));
4046                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
4047                 break;
4048         case OPC_OUB_GET_DEV_HANDLE:
4049                 PM8001_MSG_DBG(pm8001_ha,
4050                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
4051                 break;
4052         case OPC_OUB_SATA_COMP:
4053                 PM8001_MSG_DBG(pm8001_ha,
4054                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
4055                 mpi_sata_completion(pm8001_ha, piomb);
4056                 break;
4057         case OPC_OUB_SATA_EVENT:
4058                 PM8001_MSG_DBG(pm8001_ha,
4059                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
4060                 mpi_sata_event(pm8001_ha, piomb);
4061                 break;
4062         case OPC_OUB_SSP_EVENT:
4063                 PM8001_MSG_DBG(pm8001_ha,
4064                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
4065                 mpi_ssp_event(pm8001_ha, piomb);
4066                 break;
4067         case OPC_OUB_DEV_HANDLE_ARRIV:
4068                 PM8001_MSG_DBG(pm8001_ha,
4069                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
4070                 /*This is for target*/
4071                 break;
4072         case OPC_OUB_SSP_RECV_EVENT:
4073                 PM8001_MSG_DBG(pm8001_ha,
4074                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
4075                 /*This is for target*/
4076                 break;
4077         case OPC_OUB_DEV_INFO:
4078                 PM8001_MSG_DBG(pm8001_ha,
4079                         pm8001_printk("OPC_OUB_DEV_INFO\n"));
4080                 break;
4081         case OPC_OUB_FW_FLASH_UPDATE:
4082                 PM8001_MSG_DBG(pm8001_ha,
4083                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
4084                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
4085                 break;
4086         case OPC_OUB_GPIO_RESPONSE:
4087                 PM8001_MSG_DBG(pm8001_ha,
4088                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
4089                 break;
4090         case OPC_OUB_GPIO_EVENT:
4091                 PM8001_MSG_DBG(pm8001_ha,
4092                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
4093                 break;
4094         case OPC_OUB_GENERAL_EVENT:
4095                 PM8001_MSG_DBG(pm8001_ha,
4096                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
4097                 pm8001_mpi_general_event(pm8001_ha, piomb);
4098                 break;
4099         case OPC_OUB_SSP_ABORT_RSP:
4100                 PM8001_MSG_DBG(pm8001_ha,
4101                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
4102                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4103                 break;
4104         case OPC_OUB_SATA_ABORT_RSP:
4105                 PM8001_MSG_DBG(pm8001_ha,
4106                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
4107                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4108                 break;
4109         case OPC_OUB_SAS_DIAG_MODE_START_END:
4110                 PM8001_MSG_DBG(pm8001_ha,
4111                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
4112                 break;
4113         case OPC_OUB_SAS_DIAG_EXECUTE:
4114                 PM8001_MSG_DBG(pm8001_ha,
4115                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
4116                 break;
4117         case OPC_OUB_GET_TIME_STAMP:
4118                 PM8001_MSG_DBG(pm8001_ha,
4119                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
4120                 break;
4121         case OPC_OUB_SAS_HW_EVENT_ACK:
4122                 PM8001_MSG_DBG(pm8001_ha,
4123                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
4124                 break;
4125         case OPC_OUB_PORT_CONTROL:
4126                 PM8001_MSG_DBG(pm8001_ha,
4127                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
4128                 break;
4129         case OPC_OUB_SMP_ABORT_RSP:
4130                 PM8001_MSG_DBG(pm8001_ha,
4131                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
4132                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4133                 break;
4134         case OPC_OUB_GET_NVMD_DATA:
4135                 PM8001_MSG_DBG(pm8001_ha,
4136                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
4137                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
4138                 break;
4139         case OPC_OUB_SET_NVMD_DATA:
4140                 PM8001_MSG_DBG(pm8001_ha,
4141                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
4142                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
4143                 break;
4144         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
4145                 PM8001_MSG_DBG(pm8001_ha,
4146                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
4147                 break;
4148         case OPC_OUB_SET_DEVICE_STATE:
4149                 PM8001_MSG_DBG(pm8001_ha,
4150                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
4151                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4152                 break;
4153         case OPC_OUB_GET_DEVICE_STATE:
4154                 PM8001_MSG_DBG(pm8001_ha,
4155                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
4156                 break;
4157         case OPC_OUB_SET_DEV_INFO:
4158                 PM8001_MSG_DBG(pm8001_ha,
4159                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
4160                 break;
4161         case OPC_OUB_SAS_RE_INITIALIZE:
4162                 PM8001_MSG_DBG(pm8001_ha,
4163                         pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
4164                 break;
4165         default:
4166                 PM8001_MSG_DBG(pm8001_ha,
4167                         pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
4168                         opc));
4169                 break;
4170         }
4171 }
4172
4173 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4174 {
4175         struct outbound_queue_table *circularQ;
4176         void *pMsg1 = NULL;
4177         u8 uninitialized_var(bc);
4178         u32 ret = MPI_IO_STATUS_FAIL;
4179         unsigned long flags;
4180
4181         spin_lock_irqsave(&pm8001_ha->lock, flags);
4182         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4183         do {
4184                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4185                 if (MPI_IO_STATUS_SUCCESS == ret) {
4186                         /* process the outbound message */
4187                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4188                         /* free the message from the outbound circular buffer */
4189                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4190                                                         circularQ, bc);
4191                 }
4192                 if (MPI_IO_STATUS_BUSY == ret) {
4193                         /* Update the producer index from SPC */
4194                         circularQ->producer_index =
4195                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4196                         if (le32_to_cpu(circularQ->producer_index) ==
4197                                 circularQ->consumer_idx)
4198                                 /* OQ is empty */
4199                                 break;
4200                 }
4201         } while (1);
4202         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4203         return ret;
4204 }
4205
4206 /* PCI_DMA_... to our direction translation. */
4207 static const u8 data_dir_flags[] = {
4208         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
4209         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
4210         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
4211         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
4212 };
4213 void
4214 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
4215 {
4216         int i;
4217         struct scatterlist *sg;
4218         struct pm8001_prd *buf_prd = prd;
4219
4220         for_each_sg(scatter, sg, nr, i) {
4221                 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
4222                 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
4223                 buf_prd->im_len.e = 0;
4224                 buf_prd++;
4225         }
4226 }
4227
4228 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
4229 {
4230         psmp_cmd->tag = hTag;
4231         psmp_cmd->device_id = cpu_to_le32(deviceID);
4232         psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4233 }
4234
4235 /**
4236  * pm8001_chip_smp_req - send a SMP task to FW
4237  * @pm8001_ha: our hba card information.
4238  * @ccb: the ccb information this request used.
4239  */
4240 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4241         struct pm8001_ccb_info *ccb)
4242 {
4243         int elem, rc;
4244         struct sas_task *task = ccb->task;
4245         struct domain_device *dev = task->dev;
4246         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4247         struct scatterlist *sg_req, *sg_resp;
4248         u32 req_len, resp_len;
4249         struct smp_req smp_cmd;
4250         u32 opc;
4251         struct inbound_queue_table *circularQ;
4252
4253         memset(&smp_cmd, 0, sizeof(smp_cmd));
4254         /*
4255          * DMA-map SMP request, response buffers
4256          */
4257         sg_req = &task->smp_task.smp_req;
4258         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
4259         if (!elem)
4260                 return -ENOMEM;
4261         req_len = sg_dma_len(sg_req);
4262
4263         sg_resp = &task->smp_task.smp_resp;
4264         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
4265         if (!elem) {
4266                 rc = -ENOMEM;
4267                 goto err_out;
4268         }
4269         resp_len = sg_dma_len(sg_resp);
4270         /* must be in dwords */
4271         if ((req_len & 0x3) || (resp_len & 0x3)) {
4272                 rc = -EINVAL;
4273                 goto err_out_2;
4274         }
4275
4276         opc = OPC_INB_SMP_REQUEST;
4277         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4278         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4279         smp_cmd.long_smp_req.long_req_addr =
4280                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4281         smp_cmd.long_smp_req.long_req_size =
4282                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4283         smp_cmd.long_smp_req.long_resp_addr =
4284                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4285         smp_cmd.long_smp_req.long_resp_size =
4286                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4287         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4288         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4289                                         (u32 *)&smp_cmd, 0);
4290         if (rc)
4291                 goto err_out_2;
4292
4293         return 0;
4294
4295 err_out_2:
4296         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4297                         PCI_DMA_FROMDEVICE);
4298 err_out:
4299         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4300                         PCI_DMA_TODEVICE);
4301         return rc;
4302 }
4303
4304 /**
4305  * pm8001_chip_ssp_io_req - send a SSP task to FW
4306  * @pm8001_ha: our hba card information.
4307  * @ccb: the ccb information this request used.
4308  */
4309 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4310         struct pm8001_ccb_info *ccb)
4311 {
4312         struct sas_task *task = ccb->task;
4313         struct domain_device *dev = task->dev;
4314         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4315         struct ssp_ini_io_start_req ssp_cmd;
4316         u32 tag = ccb->ccb_tag;
4317         int ret;
4318         u64 phys_addr;
4319         struct inbound_queue_table *circularQ;
4320         u32 opc = OPC_INB_SSPINIIOSTART;
4321         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4322         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4323         ssp_cmd.dir_m_tlr =
4324                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4325         SAS 1.1 compatible TLR*/
4326         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4327         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4328         ssp_cmd.tag = cpu_to_le32(tag);
4329         if (task->ssp_task.enable_first_burst)
4330                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4331         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4332         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4333         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4334                task->ssp_task.cmd->cmd_len);
4335         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4336
4337         /* fill in PRD (scatter/gather) table, if any */
4338         if (task->num_scatter > 1) {
4339                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4340                 phys_addr = ccb->ccb_dma_handle +
4341                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4342                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4343                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4344                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4345         } else if (task->num_scatter == 1) {
4346                 u64 dma_addr = sg_dma_address(task->scatter);
4347                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4348                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4349                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4350                 ssp_cmd.esgl = 0;
4351         } else if (task->num_scatter == 0) {
4352                 ssp_cmd.addr_low = 0;
4353                 ssp_cmd.addr_high = 0;
4354                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4355                 ssp_cmd.esgl = 0;
4356         }
4357         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, 0);
4358         return ret;
4359 }
4360
4361 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4362         struct pm8001_ccb_info *ccb)
4363 {
4364         struct sas_task *task = ccb->task;
4365         struct domain_device *dev = task->dev;
4366         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4367         u32 tag = ccb->ccb_tag;
4368         int ret;
4369         struct sata_start_req sata_cmd;
4370         u32 hdr_tag, ncg_tag = 0;
4371         u64 phys_addr;
4372         u32 ATAP = 0x0;
4373         u32 dir;
4374         struct inbound_queue_table *circularQ;
4375         unsigned long flags;
4376         u32  opc = OPC_INB_SATA_HOST_OPSTART;
4377         memset(&sata_cmd, 0, sizeof(sata_cmd));
4378         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4379         if (task->data_dir == PCI_DMA_NONE) {
4380                 ATAP = 0x04;  /* no data*/
4381                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4382         } else if (likely(!task->ata_task.device_control_reg_update)) {
4383                 if (task->ata_task.dma_xfer) {
4384                         ATAP = 0x06; /* DMA */
4385                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4386                 } else {
4387                         ATAP = 0x05; /* PIO*/
4388                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4389                 }
4390                 if (task->ata_task.use_ncq &&
4391                         dev->sata_dev.class != ATA_DEV_ATAPI) {
4392                         ATAP = 0x07; /* FPDMA */
4393                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4394                 }
4395         }
4396         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4397                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4398                 ncg_tag = hdr_tag;
4399         }
4400         dir = data_dir_flags[task->data_dir] << 8;
4401         sata_cmd.tag = cpu_to_le32(tag);
4402         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4403         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4404         sata_cmd.ncqtag_atap_dir_m =
4405                 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4406         sata_cmd.sata_fis = task->ata_task.fis;
4407         if (likely(!task->ata_task.device_control_reg_update))
4408                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4409         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4410         /* fill in PRD (scatter/gather) table, if any */
4411         if (task->num_scatter > 1) {
4412                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4413                 phys_addr = ccb->ccb_dma_handle +
4414                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4415                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4416                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4417                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4418         } else if (task->num_scatter == 1) {
4419                 u64 dma_addr = sg_dma_address(task->scatter);
4420                 sata_cmd.addr_low = lower_32_bits(dma_addr);
4421                 sata_cmd.addr_high = upper_32_bits(dma_addr);
4422                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4423                 sata_cmd.esgl = 0;
4424         } else if (task->num_scatter == 0) {
4425                 sata_cmd.addr_low = 0;
4426                 sata_cmd.addr_high = 0;
4427                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4428                 sata_cmd.esgl = 0;
4429         }
4430
4431         /* Check for read log for failed drive and return */
4432         if (sata_cmd.sata_fis.command == 0x2f) {
4433                 if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4434                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4435                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4436                         struct task_status_struct *ts;
4437
4438                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4439                         ts = &task->task_status;
4440
4441                         spin_lock_irqsave(&task->task_state_lock, flags);
4442                         ts->resp = SAS_TASK_COMPLETE;
4443                         ts->stat = SAM_STAT_GOOD;
4444                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4445                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4446                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4447                         if (unlikely((task->task_state_flags &
4448                                         SAS_TASK_STATE_ABORTED))) {
4449                                 spin_unlock_irqrestore(&task->task_state_lock,
4450                                                         flags);
4451                                 PM8001_FAIL_DBG(pm8001_ha,
4452                                         pm8001_printk("task 0x%p resp 0x%x "
4453                                         " stat 0x%x but aborted by upper layer "
4454                                         "\n", task, ts->resp, ts->stat));
4455                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4456                         } else {
4457                                 spin_unlock_irqrestore(&task->task_state_lock,
4458                                                         flags);
4459                                 pm8001_ccb_task_free_done(pm8001_ha, task,
4460                                                                 ccb, tag);
4461                                 return 0;
4462                         }
4463                 }
4464         }
4465
4466         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
4467         return ret;
4468 }
4469
4470 /**
4471  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4472  * @pm8001_ha: our hba card information.
4473  * @num: the inbound queue number
4474  * @phy_id: the phy id which we wanted to start up.
4475  */
4476 static int
4477 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4478 {
4479         struct phy_start_req payload;
4480         struct inbound_queue_table *circularQ;
4481         int ret;
4482         u32 tag = 0x01;
4483         u32 opcode = OPC_INB_PHYSTART;
4484         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4485         memset(&payload, 0, sizeof(payload));
4486         payload.tag = cpu_to_le32(tag);
4487         /*
4488          ** [0:7]   PHY Identifier
4489          ** [8:11]  link rate 1.5G, 3G, 6G
4490          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4491          ** [14]    0b disable spin up hold; 1b enable spin up hold
4492          */
4493         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4494                 LINKMODE_AUTO | LINKRATE_15 |
4495                 LINKRATE_30 | LINKRATE_60 | phy_id);
4496         payload.sas_identify.dev_type = SAS_END_DEVICE;
4497         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4498         memcpy(payload.sas_identify.sas_addr,
4499                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4500         payload.sas_identify.phy_id = phy_id;
4501         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4502         return ret;
4503 }
4504
4505 /**
4506  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4507  * @pm8001_ha: our hba card information.
4508  * @num: the inbound queue number
4509  * @phy_id: the phy id which we wanted to start up.
4510  */
4511 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4512                                     u8 phy_id)
4513 {
4514         struct phy_stop_req payload;
4515         struct inbound_queue_table *circularQ;
4516         int ret;
4517         u32 tag = 0x01;
4518         u32 opcode = OPC_INB_PHYSTOP;
4519         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4520         memset(&payload, 0, sizeof(payload));
4521         payload.tag = cpu_to_le32(tag);
4522         payload.phy_id = cpu_to_le32(phy_id);
4523         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4524         return ret;
4525 }
4526
4527 /**
4528  * see comments on pm8001_mpi_reg_resp.
4529  */
4530 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4531         struct pm8001_device *pm8001_dev, u32 flag)
4532 {
4533         struct reg_dev_req payload;
4534         u32     opc;
4535         u32 stp_sspsmp_sata = 0x4;
4536         struct inbound_queue_table *circularQ;
4537         u32 linkrate, phy_id;
4538         int rc, tag = 0xdeadbeef;
4539         struct pm8001_ccb_info *ccb;
4540         u8 retryFlag = 0x1;
4541         u16 firstBurstSize = 0;
4542         u16 ITNT = 2000;
4543         struct domain_device *dev = pm8001_dev->sas_device;
4544         struct domain_device *parent_dev = dev->parent;
4545         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4546
4547         memset(&payload, 0, sizeof(payload));
4548         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4549         if (rc)
4550                 return rc;
4551         ccb = &pm8001_ha->ccb_info[tag];
4552         ccb->device = pm8001_dev;
4553         ccb->ccb_tag = tag;
4554         payload.tag = cpu_to_le32(tag);
4555         if (flag == 1)
4556                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4557         else {
4558                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4559                         stp_sspsmp_sata = 0x00; /* stp*/
4560                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4561                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4562                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4563                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4564         }
4565         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4566                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4567         else
4568                 phy_id = pm8001_dev->attached_phy;
4569         opc = OPC_INB_REG_DEV;
4570         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4571                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4572         payload.phyid_portid =
4573                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4574                 ((phy_id & 0x0F) << 4));
4575         payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4576                 ((linkrate & 0x0F) * 0x1000000) |
4577                 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4578         payload.firstburstsize_ITNexustimeout =
4579                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4580         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4581                 SAS_ADDR_SIZE);
4582         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4583         return rc;
4584 }
4585
4586 /**
4587  * see comments on pm8001_mpi_reg_resp.
4588  */
4589 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4590         u32 device_id)
4591 {
4592         struct dereg_dev_req payload;
4593         u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4594         int ret;
4595         struct inbound_queue_table *circularQ;
4596
4597         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4598         memset(&payload, 0, sizeof(payload));
4599         payload.tag = cpu_to_le32(1);
4600         payload.device_id = cpu_to_le32(device_id);
4601         PM8001_MSG_DBG(pm8001_ha,
4602                 pm8001_printk("unregister device device_id = %d\n", device_id));
4603         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4604         return ret;
4605 }
4606
4607 /**
4608  * pm8001_chip_phy_ctl_req - support the local phy operation
4609  * @pm8001_ha: our hba card information.
4610  * @num: the inbound queue number
4611  * @phy_id: the phy id which we wanted to operate
4612  * @phy_op:
4613  */
4614 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4615         u32 phyId, u32 phy_op)
4616 {
4617         struct local_phy_ctl_req payload;
4618         struct inbound_queue_table *circularQ;
4619         int ret;
4620         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4621         memset(&payload, 0, sizeof(payload));
4622         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4623         payload.tag = cpu_to_le32(1);
4624         payload.phyop_phyid =
4625                 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4626         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4627         return ret;
4628 }
4629
4630 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4631 {
4632         u32 value;
4633 #ifdef PM8001_USE_MSIX
4634         return 1;
4635 #endif
4636         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4637         if (value)
4638                 return 1;
4639         return 0;
4640
4641 }
4642
4643 /**
4644  * pm8001_chip_isr - PM8001 isr handler.
4645  * @pm8001_ha: our hba card information.
4646  * @irq: irq number.
4647  * @stat: stat.
4648  */
4649 static irqreturn_t
4650 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4651 {
4652         pm8001_chip_interrupt_disable(pm8001_ha, vec);
4653         process_oq(pm8001_ha, vec);
4654         pm8001_chip_interrupt_enable(pm8001_ha, vec);
4655         return IRQ_HANDLED;
4656 }
4657
4658 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4659         u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4660 {
4661         struct task_abort_req task_abort;
4662         struct inbound_queue_table *circularQ;
4663         int ret;
4664         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4665         memset(&task_abort, 0, sizeof(task_abort));
4666         if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4667                 task_abort.abort_all = 0;
4668                 task_abort.device_id = cpu_to_le32(dev_id);
4669                 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4670                 task_abort.tag = cpu_to_le32(cmd_tag);
4671         } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4672                 task_abort.abort_all = cpu_to_le32(1);
4673                 task_abort.device_id = cpu_to_le32(dev_id);
4674                 task_abort.tag = cpu_to_le32(cmd_tag);
4675         }
4676         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
4677         return ret;
4678 }
4679
4680 /**
4681  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4682  * @task: the task we wanted to aborted.
4683  * @flag: the abort flag.
4684  */
4685 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4686         struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4687 {
4688         u32 opc, device_id;
4689         int rc = TMF_RESP_FUNC_FAILED;
4690         PM8001_EH_DBG(pm8001_ha,
4691                 pm8001_printk("cmd_tag = %x, abort task tag = 0x%x",
4692                         cmd_tag, task_tag));
4693         if (pm8001_dev->dev_type == SAS_END_DEVICE)
4694                 opc = OPC_INB_SSP_ABORT;
4695         else if (pm8001_dev->dev_type == SAS_SATA_DEV)
4696                 opc = OPC_INB_SATA_ABORT;
4697         else
4698                 opc = OPC_INB_SMP_ABORT;/* SMP */
4699         device_id = pm8001_dev->device_id;
4700         rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4701                 task_tag, cmd_tag);
4702         if (rc != TMF_RESP_FUNC_COMPLETE)
4703                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4704         return rc;
4705 }
4706
4707 /**
4708  * pm8001_chip_ssp_tm_req - built the task management command.
4709  * @pm8001_ha: our hba card information.
4710  * @ccb: the ccb information.
4711  * @tmf: task management function.
4712  */
4713 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4714         struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4715 {
4716         struct sas_task *task = ccb->task;
4717         struct domain_device *dev = task->dev;
4718         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4719         u32 opc = OPC_INB_SSPINITMSTART;
4720         struct inbound_queue_table *circularQ;
4721         struct ssp_ini_tm_start_req sspTMCmd;
4722         int ret;
4723
4724         memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4725         sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4726         sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4727         sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4728         memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4729         sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4730         if (pm8001_ha->chip_id != chip_8001)
4731                 sspTMCmd.ds_ads_m = cpu_to_le32(0x08);
4732         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4733         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, 0);
4734         return ret;
4735 }
4736
4737 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4738         void *payload)
4739 {
4740         u32 opc = OPC_INB_GET_NVMD_DATA;
4741         u32 nvmd_type;
4742         int rc;
4743         u32 tag;
4744         struct pm8001_ccb_info *ccb;
4745         struct inbound_queue_table *circularQ;
4746         struct get_nvm_data_req nvmd_req;
4747         struct fw_control_ex *fw_control_context;
4748         struct pm8001_ioctl_payload *ioctl_payload = payload;
4749
4750         nvmd_type = ioctl_payload->minor_function;
4751         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4752         if (!fw_control_context)
4753                 return -ENOMEM;
4754         fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
4755         fw_control_context->len = ioctl_payload->length;
4756         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4757         memset(&nvmd_req, 0, sizeof(nvmd_req));
4758         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4759         if (rc) {
4760                 kfree(fw_control_context);
4761                 return rc;
4762         }
4763         ccb = &pm8001_ha->ccb_info[tag];
4764         ccb->ccb_tag = tag;
4765         ccb->fw_control_context = fw_control_context;
4766         nvmd_req.tag = cpu_to_le32(tag);
4767
4768         switch (nvmd_type) {
4769         case TWI_DEVICE: {
4770                 u32 twi_addr, twi_page_size;
4771                 twi_addr = 0xa8;
4772                 twi_page_size = 2;
4773
4774                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4775                         twi_page_size << 8 | TWI_DEVICE);
4776                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4777                 nvmd_req.resp_addr_hi =
4778                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4779                 nvmd_req.resp_addr_lo =
4780                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4781                 break;
4782         }
4783         case C_SEEPROM: {
4784                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4785                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4786                 nvmd_req.resp_addr_hi =
4787                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4788                 nvmd_req.resp_addr_lo =
4789                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4790                 break;
4791         }
4792         case VPD_FLASH: {
4793                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4794                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4795                 nvmd_req.resp_addr_hi =
4796                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4797                 nvmd_req.resp_addr_lo =
4798                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4799                 break;
4800         }
4801         case EXPAN_ROM: {
4802                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4803                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4804                 nvmd_req.resp_addr_hi =
4805                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4806                 nvmd_req.resp_addr_lo =
4807                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4808                 break;
4809         }
4810         case IOP_RDUMP: {
4811                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
4812                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4813                 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
4814                 nvmd_req.resp_addr_hi =
4815                 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4816                 nvmd_req.resp_addr_lo =
4817                 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4818                 break;
4819         }
4820         default:
4821                 break;
4822         }
4823         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
4824         if (rc) {
4825                 kfree(fw_control_context);
4826                 pm8001_tag_free(pm8001_ha, tag);
4827         }
4828         return rc;
4829 }
4830
4831 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4832         void *payload)
4833 {
4834         u32 opc = OPC_INB_SET_NVMD_DATA;
4835         u32 nvmd_type;
4836         int rc;
4837         u32 tag;
4838         struct pm8001_ccb_info *ccb;
4839         struct inbound_queue_table *circularQ;
4840         struct set_nvm_data_req nvmd_req;
4841         struct fw_control_ex *fw_control_context;
4842         struct pm8001_ioctl_payload *ioctl_payload = payload;
4843
4844         nvmd_type = ioctl_payload->minor_function;
4845         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4846         if (!fw_control_context)
4847                 return -ENOMEM;
4848         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4849         memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4850                 &ioctl_payload->func_specific,
4851                 ioctl_payload->length);
4852         memset(&nvmd_req, 0, sizeof(nvmd_req));
4853         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4854         if (rc) {
4855                 kfree(fw_control_context);
4856                 return -EBUSY;
4857         }
4858         ccb = &pm8001_ha->ccb_info[tag];
4859         ccb->fw_control_context = fw_control_context;
4860         ccb->ccb_tag = tag;
4861         nvmd_req.tag = cpu_to_le32(tag);
4862         switch (nvmd_type) {
4863         case TWI_DEVICE: {
4864                 u32 twi_addr, twi_page_size;
4865                 twi_addr = 0xa8;
4866                 twi_page_size = 2;
4867                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4868                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4869                         twi_page_size << 8 | TWI_DEVICE);
4870                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4871                 nvmd_req.resp_addr_hi =
4872                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4873                 nvmd_req.resp_addr_lo =
4874                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4875                 break;
4876         }
4877         case C_SEEPROM:
4878                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4879                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4880                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4881                 nvmd_req.resp_addr_hi =
4882                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4883                 nvmd_req.resp_addr_lo =
4884                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4885                 break;
4886         case VPD_FLASH:
4887                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4888                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4889                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4890                 nvmd_req.resp_addr_hi =
4891                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4892                 nvmd_req.resp_addr_lo =
4893                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4894                 break;
4895         case EXPAN_ROM:
4896                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4897                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4898                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4899                 nvmd_req.resp_addr_hi =
4900                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4901                 nvmd_req.resp_addr_lo =
4902                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4903                 break;
4904         default:
4905                 break;
4906         }
4907         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
4908         if (rc) {
4909                 kfree(fw_control_context);
4910                 pm8001_tag_free(pm8001_ha, tag);
4911         }
4912         return rc;
4913 }
4914
4915 /**
4916  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4917  * @pm8001_ha: our hba card information.
4918  * @fw_flash_updata_info: firmware flash update param
4919  */
4920 int
4921 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4922         void *fw_flash_updata_info, u32 tag)
4923 {
4924         struct fw_flash_Update_req payload;
4925         struct fw_flash_updata_info *info;
4926         struct inbound_queue_table *circularQ;
4927         int ret;
4928         u32 opc = OPC_INB_FW_FLASH_UPDATE;
4929
4930         memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4931         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4932         info = fw_flash_updata_info;
4933         payload.tag = cpu_to_le32(tag);
4934         payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4935         payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4936         payload.total_image_len = cpu_to_le32(info->total_image_len);
4937         payload.len = info->sgl.im_len.len ;
4938         payload.sgl_addr_lo =
4939                 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4940         payload.sgl_addr_hi =
4941                 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4942         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4943         return ret;
4944 }
4945
4946 int
4947 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4948         void *payload)
4949 {
4950         struct fw_flash_updata_info flash_update_info;
4951         struct fw_control_info *fw_control;
4952         struct fw_control_ex *fw_control_context;
4953         int rc;
4954         u32 tag;
4955         struct pm8001_ccb_info *ccb;
4956         void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
4957         dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
4958         struct pm8001_ioctl_payload *ioctl_payload = payload;
4959
4960         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4961         if (!fw_control_context)
4962                 return -ENOMEM;
4963         fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
4964         memcpy(buffer, fw_control->buffer, fw_control->len);
4965         flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4966         flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4967         flash_update_info.sgl.im_len.e = 0;
4968         flash_update_info.cur_image_offset = fw_control->offset;
4969         flash_update_info.cur_image_len = fw_control->len;
4970         flash_update_info.total_image_len = fw_control->size;
4971         fw_control_context->fw_control = fw_control;
4972         fw_control_context->virtAddr = buffer;
4973         fw_control_context->phys_addr = phys_addr;
4974         fw_control_context->len = fw_control->len;
4975         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4976         if (rc) {
4977                 kfree(fw_control_context);
4978                 return -EBUSY;
4979         }
4980         ccb = &pm8001_ha->ccb_info[tag];
4981         ccb->fw_control_context = fw_control_context;
4982         ccb->ccb_tag = tag;
4983         rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4984                 tag);
4985         return rc;
4986 }
4987
4988 ssize_t
4989 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
4990 {
4991         u32 value, rem, offset = 0, bar = 0;
4992         u32 index, work_offset, dw_length;
4993         u32 shift_value, gsm_base, gsm_dump_offset;
4994         char *direct_data;
4995         struct Scsi_Host *shost = class_to_shost(cdev);
4996         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
4997         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
4998
4999         direct_data = buf;
5000         gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
5001
5002         /* check max is 1 Mbytes */
5003         if ((length > 0x100000) || (gsm_dump_offset & 3) ||
5004                 ((gsm_dump_offset + length) > 0x1000000))
5005                         return -EINVAL;
5006
5007         if (pm8001_ha->chip_id == chip_8001)
5008                 bar = 2;
5009         else
5010                 bar = 1;
5011
5012         work_offset = gsm_dump_offset & 0xFFFF0000;
5013         offset = gsm_dump_offset & 0x0000FFFF;
5014         gsm_dump_offset = work_offset;
5015         /* adjust length to dword boundary */
5016         rem = length & 3;
5017         dw_length = length >> 2;
5018
5019         for (index = 0; index < dw_length; index++) {
5020                 if ((work_offset + offset) & 0xFFFF0000) {
5021                         if (pm8001_ha->chip_id == chip_8001)
5022                                 shift_value = ((gsm_dump_offset + offset) &
5023                                                 SHIFT_REG_64K_MASK);
5024                         else
5025                                 shift_value = (((gsm_dump_offset + offset) &
5026                                                 SHIFT_REG_64K_MASK) >>
5027                                                 SHIFT_REG_BIT_SHIFT);
5028
5029                         if (pm8001_ha->chip_id == chip_8001) {
5030                                 gsm_base = GSM_BASE;
5031                                 if (-1 == pm8001_bar4_shift(pm8001_ha,
5032                                                 (gsm_base + shift_value)))
5033                                         return -EIO;
5034                         } else {
5035                                 gsm_base = 0;
5036                                 if (-1 == pm80xx_bar4_shift(pm8001_ha,
5037                                                 (gsm_base + shift_value)))
5038                                         return -EIO;
5039                         }
5040                         gsm_dump_offset = (gsm_dump_offset + offset) &
5041                                                 0xFFFF0000;
5042                         work_offset = 0;
5043                         offset = offset & 0x0000FFFF;
5044                 }
5045                 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
5046                                                 0x0000FFFF);
5047                 direct_data += sprintf(direct_data, "%08x ", value);
5048                 offset += 4;
5049         }
5050         if (rem != 0) {
5051                 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
5052                                                 0x0000FFFF);
5053                 /* xfr for non_dw */
5054                 direct_data += sprintf(direct_data, "%08x ", value);
5055         }
5056         /* Shift back to BAR4 original address */
5057         if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
5058                         return -EIO;
5059         pm8001_ha->fatal_forensic_shift_offset += 1024;
5060
5061         if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
5062                 pm8001_ha->fatal_forensic_shift_offset = 0;
5063         return direct_data - buf;
5064 }
5065
5066 int
5067 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
5068         struct pm8001_device *pm8001_dev, u32 state)
5069 {
5070         struct set_dev_state_req payload;
5071         struct inbound_queue_table *circularQ;
5072         struct pm8001_ccb_info *ccb;
5073         int rc;
5074         u32 tag;
5075         u32 opc = OPC_INB_SET_DEVICE_STATE;
5076         memset(&payload, 0, sizeof(payload));
5077         rc = pm8001_tag_alloc(pm8001_ha, &tag);
5078         if (rc)
5079                 return -1;
5080         ccb = &pm8001_ha->ccb_info[tag];
5081         ccb->ccb_tag = tag;
5082         ccb->device = pm8001_dev;
5083         circularQ = &pm8001_ha->inbnd_q_tbl[0];
5084         payload.tag = cpu_to_le32(tag);
5085         payload.device_id = cpu_to_le32(pm8001_dev->device_id);
5086         payload.nds = cpu_to_le32(state);
5087         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
5088         return rc;
5089
5090 }
5091
5092 static int
5093 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
5094 {
5095         struct sas_re_initialization_req payload;
5096         struct inbound_queue_table *circularQ;
5097         struct pm8001_ccb_info *ccb;
5098         int rc;
5099         u32 tag;
5100         u32 opc = OPC_INB_SAS_RE_INITIALIZE;
5101         memset(&payload, 0, sizeof(payload));
5102         rc = pm8001_tag_alloc(pm8001_ha, &tag);
5103         if (rc)
5104                 return -ENOMEM;
5105         ccb = &pm8001_ha->ccb_info[tag];
5106         ccb->ccb_tag = tag;
5107         circularQ = &pm8001_ha->inbnd_q_tbl[0];
5108         payload.tag = cpu_to_le32(tag);
5109         payload.SSAHOLT = cpu_to_le32(0xd << 25);
5110         payload.sata_hol_tmo = cpu_to_le32(80);
5111         payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
5112         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
5113         if (rc)
5114                 pm8001_tag_free(pm8001_ha, tag);
5115         return rc;
5116
5117 }
5118
5119 const struct pm8001_dispatch pm8001_8001_dispatch = {
5120         .name                   = "pmc8001",
5121         .chip_init              = pm8001_chip_init,
5122         .chip_soft_rst          = pm8001_chip_soft_rst,
5123         .chip_rst               = pm8001_hw_chip_rst,
5124         .chip_iounmap           = pm8001_chip_iounmap,
5125         .isr                    = pm8001_chip_isr,
5126         .is_our_interupt        = pm8001_chip_is_our_interupt,
5127         .isr_process_oq         = process_oq,
5128         .interrupt_enable       = pm8001_chip_interrupt_enable,
5129         .interrupt_disable      = pm8001_chip_interrupt_disable,
5130         .make_prd               = pm8001_chip_make_sg,
5131         .smp_req                = pm8001_chip_smp_req,
5132         .ssp_io_req             = pm8001_chip_ssp_io_req,
5133         .sata_req               = pm8001_chip_sata_req,
5134         .phy_start_req          = pm8001_chip_phy_start_req,
5135         .phy_stop_req           = pm8001_chip_phy_stop_req,
5136         .reg_dev_req            = pm8001_chip_reg_dev_req,
5137         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
5138         .phy_ctl_req            = pm8001_chip_phy_ctl_req,
5139         .task_abort             = pm8001_chip_abort_task,
5140         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
5141         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
5142         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
5143         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
5144         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
5145         .sas_re_init_req        = pm8001_chip_sas_re_initialization,
5146 };