drivers/scsi/pm8001/pm80xx_hwi.c

   1 /*
   2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  * notice, this list of conditions, and the following disclaimer,
  12  * without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  * substantially similar to the "NO WARRANTY" disclaimer below
  15  * ("Disclaimer") and any redistribution must be conditioned upon
  16  * including a substantially similar Disclaimer requirement for further
  17  * binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  * of any contributors may be used to endorse or promote products derived
  20  * from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm80xx_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 #define SMP_DIRECT 1
  47 #define SMP_INDIRECT 2
  48
  49
  50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
  51 {
  52         u32 reg_val;
  53         unsigned long start;
  54         pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
  55         /* confirm the setting is written */
  56         start = jiffies + HZ; /* 1 sec */
  57         do {
  58                 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
  59         } while ((reg_val != shift_value) && time_before(jiffies, start));
  60         if (reg_val != shift_value) {
  61                 PM8001_FAIL_DBG(pm8001_ha,
  62                         pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
  63                         " = 0x%x\n", reg_val));
  64                 return -1;
  65         }
  66         return 0;
  67 }
  68
  69 void pm80xx_pci_mem_copy(struct pm8001_hba_info  *pm8001_ha, u32 soffset,
  70                                 const void *destination,
  71                                 u32 dw_count, u32 bus_base_number)
  72 {
  73         u32 index, value, offset;
  74         u32 *destination1;
  75         destination1 = (u32 *)destination;
  76
  77         for (index = 0; index < dw_count; index += 4, destination1++) {
  78                 offset = (soffset + index / 4);
  79                 if (offset < (64 * 1024)) {
  80                         value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
  81                         *destination1 =  cpu_to_le32(value);
  82                 }
  83         }
  84         return;
  85 }
  86
  87 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
  88         struct device_attribute *attr, char *buf)
  89 {
  90         struct Scsi_Host *shost = class_to_shost(cdev);
  91         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  92         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
  93         void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
  94         u32 accum_len , reg_val, index, *temp;
  95         unsigned long start;
  96         u8 *direct_data;
  97         char *fatal_error_data = buf;
  98
  99         pm8001_ha->forensic_info.data_buf.direct_data = buf;
 100         if (pm8001_ha->chip_id == chip_8001) {
 101                 pm8001_ha->forensic_info.data_buf.direct_data +=
 102                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 103                         "Not supported for SPC controller");
 104                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 105                         (char *)buf;
 106         }
 107         if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
 108                 PM8001_IO_DBG(pm8001_ha,
 109                 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
 110                 direct_data = (u8 *)fatal_error_data;
 111                 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
 112                 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
 113                 pm8001_ha->forensic_info.data_buf.read_len = 0;
 114
 115                 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
 116
 117                 /* start to get data */
 118                 /* Program the MEMBASE II Shifting Register with 0x00.*/
 119                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 120                                 pm8001_ha->fatal_forensic_shift_offset);
 121                 pm8001_ha->forensic_last_offset = 0;
 122                 pm8001_ha->forensic_fatal_step = 0;
 123                 pm8001_ha->fatal_bar_loc = 0;
 124         }
 125
 126         /* Read until accum_len is retrived */
 127         accum_len = pm8001_mr32(fatal_table_address,
 128                                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 129         PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n",
 130                                                 accum_len));
 131         if (accum_len == 0xFFFFFFFF) {
 132                 PM8001_IO_DBG(pm8001_ha,
 133                         pm8001_printk("Possible PCI issue 0x%x not expected\n",
 134                                 accum_len));
 135                 return -EIO;
 136         }
 137         if (accum_len == 0 || accum_len >= 0x100000) {
 138                 pm8001_ha->forensic_info.data_buf.direct_data +=
 139                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 140                                 "%08x ", 0xFFFFFFFF);
 141                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 142                         (char *)buf;
 143         }
 144         temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
 145         if (pm8001_ha->forensic_fatal_step == 0) {
 146 moreData:
 147                 if (pm8001_ha->forensic_info.data_buf.direct_data) {
 148                         /* Data is in bar, copy to host memory */
 149                         pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc,
 150                          pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
 151                                 pm8001_ha->forensic_info.data_buf.direct_len ,
 152                                         1);
 153                 }
 154                 pm8001_ha->fatal_bar_loc +=
 155                         pm8001_ha->forensic_info.data_buf.direct_len;
 156                 pm8001_ha->forensic_info.data_buf.direct_offset +=
 157                         pm8001_ha->forensic_info.data_buf.direct_len;
 158                 pm8001_ha->forensic_last_offset +=
 159                         pm8001_ha->forensic_info.data_buf.direct_len;
 160                 pm8001_ha->forensic_info.data_buf.read_len =
 161                         pm8001_ha->forensic_info.data_buf.direct_len;
 162
 163                 if (pm8001_ha->forensic_last_offset  >= accum_len) {
 164                         pm8001_ha->forensic_info.data_buf.direct_data +=
 165                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 166                                 "%08x ", 3);
 167                         for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
 168                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 169                                         sprintf(pm8001_ha->
 170                                          forensic_info.data_buf.direct_data,
 171                                                 "%08x ", *(temp + index));
 172                         }
 173
 174                         pm8001_ha->fatal_bar_loc = 0;
 175                         pm8001_ha->forensic_fatal_step = 1;
 176                         pm8001_ha->fatal_forensic_shift_offset = 0;
 177                         pm8001_ha->forensic_last_offset = 0;
 178                         return (char *)pm8001_ha->
 179                                 forensic_info.data_buf.direct_data -
 180                                 (char *)buf;
 181                 }
 182                 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
 183                         pm8001_ha->forensic_info.data_buf.direct_data +=
 184                                 sprintf(pm8001_ha->
 185                                         forensic_info.data_buf.direct_data,
 186                                         "%08x ", 2);
 187                         for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
 188                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 189                                         sprintf(pm8001_ha->
 190                                         forensic_info.data_buf.direct_data,
 191                                         "%08x ", *(temp + index));
 192                         }
 193                         return (char *)pm8001_ha->
 194                                 forensic_info.data_buf.direct_data -
 195                                 (char *)buf;
 196                 }
 197
 198                 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
 199                 pm8001_ha->forensic_info.data_buf.direct_data +=
 200                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 201                                 "%08x ", 2);
 202                 for (index = 0; index < 256; index++) {
 203                         pm8001_ha->forensic_info.data_buf.direct_data +=
 204                                 sprintf(pm8001_ha->
 205                                         forensic_info.data_buf.direct_data,
 206                                                 "%08x ", *(temp + index));
 207                 }
 208                 pm8001_ha->fatal_forensic_shift_offset += 0x100;
 209                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 210                         pm8001_ha->fatal_forensic_shift_offset);
 211                 pm8001_ha->fatal_bar_loc = 0;
 212                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 213                         (char *)buf;
 214         }
 215         if (pm8001_ha->forensic_fatal_step == 1) {
 216                 pm8001_ha->fatal_forensic_shift_offset = 0;
 217                 /* Read 64K of the debug data. */
 218                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 219                         pm8001_ha->fatal_forensic_shift_offset);
 220                 pm8001_mw32(fatal_table_address,
 221                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
 222                                 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
 223
 224                 /* Poll FDDHSHK  until clear  */
 225                 start = jiffies + (2 * HZ); /* 2 sec */
 226
 227                 do {
 228                         reg_val = pm8001_mr32(fatal_table_address,
 229                                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
 230                 } while ((reg_val) && time_before(jiffies, start));
 231
 232                 if (reg_val != 0) {
 233                         PM8001_FAIL_DBG(pm8001_ha,
 234                         pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
 235                         " = 0x%x\n", reg_val));
 236                         return -EIO;
 237                 }
 238
 239                 /* Read the next 64K of the debug data. */
 240                 pm8001_ha->forensic_fatal_step = 0;
 241                 if (pm8001_mr32(fatal_table_address,
 242                         MPI_FATAL_EDUMP_TABLE_STATUS) !=
 243                                 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
 244                         pm8001_mw32(fatal_table_address,
 245                                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0);
 246                         goto moreData;
 247                 } else {
 248                         pm8001_ha->forensic_info.data_buf.direct_data +=
 249                                 sprintf(pm8001_ha->
 250                                         forensic_info.data_buf.direct_data,
 251                                                 "%08x ", 4);
 252                         pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
 253                         pm8001_ha->forensic_info.data_buf.direct_len =  0;
 254                         pm8001_ha->forensic_info.data_buf.direct_offset = 0;
 255                         pm8001_ha->forensic_info.data_buf.read_len = 0;
 256                 }
 257         }
 258
 259         return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 260                 (char *)buf;
 261 }
 262
 263 /**
 264  * read_main_config_table - read the configure table and save it.
 265  * @pm8001_ha: our hba card information
 266  */
 267 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
 268 {
 269         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 270
 271         pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature    =
 272                 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
 273         pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
 274                 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
 275         pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
 276                 pm8001_mr32(address, MAIN_FW_REVISION);
 277         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io   =
 278                 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
 279         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl      =
 280                 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
 281         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
 282                 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
 283         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset   =
 284                 pm8001_mr32(address, MAIN_GST_OFFSET);
 285         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
 286                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
 287         pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
 288                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
 289
 290         /* read Error Dump Offset and Length */
 291         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
 292                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
 293         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
 294                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
 295         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
 296                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
 297         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
 298                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
 299
 300         /* read GPIO LED settings from the configuration table */
 301         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
 302                 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
 303
 304         /* read analog Setting offset from the configuration table */
 305         pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
 306                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
 307
 308         pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
 309                 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
 310         pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
 311                 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
 312         /* read port recover and reset timeout */
 313         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
 314                 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
 315         /* read ILA and inactive firmware version */
 316         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
 317                 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
 318         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
 319                 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
 320 }
 321
 322 /**
 323  * read_general_status_table - read the general status table and save it.
 324  * @pm8001_ha: our hba card information
 325  */
 326 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
 327 {
 328         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
 329         pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate   =
 330                         pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
 331         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0   =
 332                         pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
 333         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1   =
 334                         pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
 335         pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt          =
 336                         pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
 337         pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt           =
 338                         pm8001_mr32(address, GST_IOPTCNT_OFFSET);
 339         pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val     =
 340                         pm8001_mr32(address, GST_GPIO_INPUT_VAL);
 341         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
 342                         pm8001_mr32(address, GST_RERRINFO_OFFSET0);
 343         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
 344                         pm8001_mr32(address, GST_RERRINFO_OFFSET1);
 345         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
 346                         pm8001_mr32(address, GST_RERRINFO_OFFSET2);
 347         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
 348                         pm8001_mr32(address, GST_RERRINFO_OFFSET3);
 349         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
 350                         pm8001_mr32(address, GST_RERRINFO_OFFSET4);
 351         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
 352                         pm8001_mr32(address, GST_RERRINFO_OFFSET5);
 353         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
 354                         pm8001_mr32(address, GST_RERRINFO_OFFSET6);
 355         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
 356                          pm8001_mr32(address, GST_RERRINFO_OFFSET7);
 357 }
 358 /**
 359  * read_phy_attr_table - read the phy attribute table and save it.
 360  * @pm8001_ha: our hba card information
 361  */
 362 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
 363 {
 364         void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
 365         pm8001_ha->phy_attr_table.phystart1_16[0] =
 366                         pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
 367         pm8001_ha->phy_attr_table.phystart1_16[1] =
 368                         pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
 369         pm8001_ha->phy_attr_table.phystart1_16[2] =
 370                         pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
 371         pm8001_ha->phy_attr_table.phystart1_16[3] =
 372                         pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
 373         pm8001_ha->phy_attr_table.phystart1_16[4] =
 374                         pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
 375         pm8001_ha->phy_attr_table.phystart1_16[5] =
 376                         pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
 377         pm8001_ha->phy_attr_table.phystart1_16[6] =
 378                         pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
 379         pm8001_ha->phy_attr_table.phystart1_16[7] =
 380                         pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
 381         pm8001_ha->phy_attr_table.phystart1_16[8] =
 382                         pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
 383         pm8001_ha->phy_attr_table.phystart1_16[9] =
 384                         pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
 385         pm8001_ha->phy_attr_table.phystart1_16[10] =
 386                         pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
 387         pm8001_ha->phy_attr_table.phystart1_16[11] =
 388                         pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
 389         pm8001_ha->phy_attr_table.phystart1_16[12] =
 390                         pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
 391         pm8001_ha->phy_attr_table.phystart1_16[13] =
 392                         pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
 393         pm8001_ha->phy_attr_table.phystart1_16[14] =
 394                         pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
 395         pm8001_ha->phy_attr_table.phystart1_16[15] =
 396                         pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
 397
 398         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
 399                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
 400         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
 401                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
 402         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
 403                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
 404         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
 405                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
 406         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
 407                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
 408         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
 409                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
 410         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
 411                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
 412         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
 413                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
 414         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
 415                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
 416         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
 417                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
 418         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
 419                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
 420         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
 421                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
 422         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
 423                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
 424         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
 425                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
 426         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
 427                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
 428         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
 429                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
 430
 431 }
 432
 433 /**
 434  * read_inbnd_queue_table - read the inbound queue table and save it.
 435  * @pm8001_ha: our hba card information
 436  */
 437 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 438 {
 439         int i;
 440         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 441         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 442                 u32 offset = i * 0x20;
 443                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 444                         get_pci_bar_index(pm8001_mr32(address,
 445                                 (offset + IB_PIPCI_BAR)));
 446                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 447                         pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
 448         }
 449 }
 450
 451 /**
 452  * read_outbnd_queue_table - read the outbound queue table and save it.
 453  * @pm8001_ha: our hba card information
 454  */
 455 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 456 {
 457         int i;
 458         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 459         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 460                 u32 offset = i * 0x24;
 461                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 462                         get_pci_bar_index(pm8001_mr32(address,
 463                                 (offset + OB_CIPCI_BAR)));
 464                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 465                         pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
 466         }
 467 }
 468
 469 /**
 470  * init_default_table_values - init the default table.
 471  * @pm8001_ha: our hba card information
 472  */
 473 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 474 {
 475         int i;
 476         u32 offsetib, offsetob;
 477         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 478         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 479
 480         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr         =
 481                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 482         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr         =
 483                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 484         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size               =
 485                                                         PM8001_EVENT_LOG_SIZE;
 486         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity           = 0x01;
 487         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr     =
 488                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 489         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr     =
 490                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 491         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size           =
 492                                                         PM8001_EVENT_LOG_SIZE;
 493         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity       = 0x01;
 494         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt          = 0x01;
 495
 496         /* Disable end to end CRC checking */
 497         pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
 498
 499         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 500                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 501                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 502                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 503                         pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
 504                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 505                 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
 506                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 507                         (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
 508                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 509                         pm8001_ha->memoryMap.region[IB + i].total_len;
 510                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 511                         pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
 512                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 513                         pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
 514                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 515                         pm8001_ha->memoryMap.region[CI + i].virt_ptr;
 516                 offsetib = i * 0x20;
 517                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 518                         get_pci_bar_index(pm8001_mr32(addressib,
 519                                 (offsetib + 0x14)));
 520                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 521                         pm8001_mr32(addressib, (offsetib + 0x18));
 522                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 523                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 524         }
 525         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 526                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 527                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 528                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 529                         pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
 530                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 531                         pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
 532                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 533                         (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
 534                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 535                         pm8001_ha->memoryMap.region[OB + i].total_len;
 536                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 537                         pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
 538                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 539                         pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
 540                 /* interrupt vector based on oq */
 541                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
 542                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 543                         pm8001_ha->memoryMap.region[PI + i].virt_ptr;
 544                 offsetob = i * 0x24;
 545                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 546                         get_pci_bar_index(pm8001_mr32(addressob,
 547                         offsetob + 0x14));
 548                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 549                         pm8001_mr32(addressob, (offsetob + 0x18));
 550                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 551                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 552         }
 553 }
 554
 555 /**
 556  * update_main_config_table - update the main default table to the HBA.
 557  * @pm8001_ha: our hba card information
 558  */
 559 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 560 {
 561         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 562         pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
 563                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
 564         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
 565                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
 566         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
 567                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
 568         pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
 569                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
 570         pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
 571                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
 572         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
 573                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
 574         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
 575                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
 576         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
 577                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
 578         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
 579                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
 580         /* Update Fatal error interrupt vector */
 581         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
 582                                         ((pm8001_ha->number_of_intr - 1) << 8);
 583         pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
 584                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
 585         pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
 586                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
 587
 588         /* SPCv specific */
 589         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
 590         /* Set GPIOLED to 0x2 for LED indicator */
 591         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
 592         pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
 593                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
 594
 595         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 596                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 597         pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
 598                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
 599
 600         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
 601         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
 602                                                         PORT_RECOVERY_TIMEOUT;
 603         if (pm8001_ha->chip_id == chip_8006) {
 604                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
 605                                         0x0000ffff;
 606                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
 607                                         CHIP_8006_PORT_RECOVERY_TIMEOUT;
 608         }
 609         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 610                         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 611 }
 612
 613 /**
 614  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 615  * @pm8001_ha: our hba card information
 616  */
 617 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 618                                          int number)
 619 {
 620         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 621         u16 offset = number * 0x20;
 622         pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
 623                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 624         pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
 625                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 626         pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
 627                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 628         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
 629                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 630         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
 631                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 632 }
 633
 634 /**
 635  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 636  * @pm8001_ha: our hba card information
 637  */
 638 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 639                                                  int number)
 640 {
 641         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 642         u16 offset = number * 0x24;
 643         pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
 644                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 645         pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
 646                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 647         pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
 648                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 649         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
 650                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 651         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
 652                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 653         pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
 654                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 655 }
 656
 657 /**
 658  * mpi_init_check - check firmware initialization status.
 659  * @pm8001_ha: our hba card information
 660  */
 661 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 662 {
 663         u32 max_wait_count;
 664         u32 value;
 665         u32 gst_len_mpistate;
 666
 667         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 668         table is updated */
 669         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
 670         /* wait until Inbound DoorBell Clear Register toggled */
 671         if (IS_SPCV_12G(pm8001_ha->pdev)) {
 672                 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
 673         } else {
 674                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
 675         }
 676         do {
 677                 udelay(1);
 678                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 679                 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
 680         } while ((value != 0) && (--max_wait_count));
 681
 682         if (!max_wait_count)
 683                 return -1;
 684         /* check the MPI-State for initialization upto 100ms*/
 685         max_wait_count = 100 * 1000;/* 100 msec */
 686         do {
 687                 udelay(1);
 688                 gst_len_mpistate =
 689                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 690                                         GST_GSTLEN_MPIS_OFFSET);
 691         } while ((GST_MPI_STATE_INIT !=
 692                 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
 693         if (!max_wait_count)
 694                 return -1;
 695
 696         /* check MPI Initialization error */
 697         gst_len_mpistate = gst_len_mpistate >> 16;
 698         if (0x0000 != gst_len_mpistate)
 699                 return -1;
 700
 701         return 0;
 702 }
 703
 704 /**
 705  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 706  * @pm8001_ha: our hba card information
 707  */
 708 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 709 {
 710         u32 value;
 711         u32 max_wait_count;
 712         u32 max_wait_time;
 713         int ret = 0;
 714
 715         /* reset / PCIe ready */
 716         max_wait_time = max_wait_count = 100 * 1000;    /* 100 milli sec */
 717         do {
 718                 udelay(1);
 719                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 720         } while ((value == 0xFFFFFFFF) && (--max_wait_count));
 721
 722         /* check ila status */
 723         max_wait_time = max_wait_count = 1000 * 1000;   /* 1000 milli sec */
 724         do {
 725                 udelay(1);
 726                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 727         } while (((value & SCRATCH_PAD_ILA_READY) !=
 728                         SCRATCH_PAD_ILA_READY) && (--max_wait_count));
 729         if (!max_wait_count)
 730                 ret = -1;
 731         else {
 732                 PM8001_MSG_DBG(pm8001_ha,
 733                         pm8001_printk(" ila ready status in %d millisec\n",
 734                                 (max_wait_time - max_wait_count)));
 735         }
 736
 737         /* check RAAE status */
 738         max_wait_time = max_wait_count = 1800 * 1000;   /* 1800 milli sec */
 739         do {
 740                 udelay(1);
 741                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 742         } while (((value & SCRATCH_PAD_RAAE_READY) !=
 743                                 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
 744         if (!max_wait_count)
 745                 ret = -1;
 746         else {
 747                 PM8001_MSG_DBG(pm8001_ha,
 748                         pm8001_printk(" raae ready status in %d millisec\n",
 749                                         (max_wait_time - max_wait_count)));
 750         }
 751
 752         /* check iop0 status */
 753         max_wait_time = max_wait_count = 600 * 1000;    /* 600 milli sec */
 754         do {
 755                 udelay(1);
 756                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 757         } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
 758                         (--max_wait_count));
 759         if (!max_wait_count)
 760                 ret = -1;
 761         else {
 762                 PM8001_MSG_DBG(pm8001_ha,
 763                         pm8001_printk(" iop0 ready status in %d millisec\n",
 764                                 (max_wait_time - max_wait_count)));
 765         }
 766
 767         /* check iop1 status only for 16 port controllers */
 768         if ((pm8001_ha->chip_id != chip_8008) &&
 769                         (pm8001_ha->chip_id != chip_8009)) {
 770                 /* 200 milli sec */
 771                 max_wait_time = max_wait_count = 200 * 1000;
 772                 do {
 773                         udelay(1);
 774                         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 775                 } while (((value & SCRATCH_PAD_IOP1_READY) !=
 776                                 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
 777                 if (!max_wait_count)
 778                         ret = -1;
 779                 else {
 780                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
 781                                 "iop1 ready status in %d millisec\n",
 782                                 (max_wait_time - max_wait_count)));
 783                 }
 784         }
 785
 786         return ret;
 787 }
 788
 789 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 790 {
 791         void __iomem *base_addr;
 792         u32     value;
 793         u32     offset;
 794         u32     pcibar;
 795         u32     pcilogic;
 796
 797         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 798         offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
 799
 800         PM8001_INIT_DBG(pm8001_ha,
 801                 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
 802                                 offset, value));
 803         pcilogic = (value & 0xFC000000) >> 26;
 804         pcibar = get_pci_bar_index(pcilogic);
 805         PM8001_INIT_DBG(pm8001_ha,
 806                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 807         pm8001_ha->main_cfg_tbl_addr = base_addr =
 808                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 809         pm8001_ha->general_stat_tbl_addr =
 810                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
 811                                         0xFFFFFF);
 812         pm8001_ha->inbnd_q_tbl_addr =
 813                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
 814                                         0xFFFFFF);
 815         pm8001_ha->outbnd_q_tbl_addr =
 816                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
 817                                         0xFFFFFF);
 818         pm8001_ha->ivt_tbl_addr =
 819                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
 820                                         0xFFFFFF);
 821         pm8001_ha->pspa_q_tbl_addr =
 822                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
 823                                         0xFFFFFF);
 824         pm8001_ha->fatal_tbl_addr =
 825                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
 826                                         0xFFFFFF);
 827
 828         PM8001_INIT_DBG(pm8001_ha,
 829                         pm8001_printk("GST OFFSET 0x%x\n",
 830                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
 831         PM8001_INIT_DBG(pm8001_ha,
 832                         pm8001_printk("INBND OFFSET 0x%x\n",
 833                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
 834         PM8001_INIT_DBG(pm8001_ha,
 835                         pm8001_printk("OBND OFFSET 0x%x\n",
 836                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
 837         PM8001_INIT_DBG(pm8001_ha,
 838                         pm8001_printk("IVT OFFSET 0x%x\n",
 839                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
 840         PM8001_INIT_DBG(pm8001_ha,
 841                         pm8001_printk("PSPA OFFSET 0x%x\n",
 842                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
 843         PM8001_INIT_DBG(pm8001_ha,
 844                         pm8001_printk("addr - main cfg %p general status %p\n",
 845                         pm8001_ha->main_cfg_tbl_addr,
 846                         pm8001_ha->general_stat_tbl_addr));
 847         PM8001_INIT_DBG(pm8001_ha,
 848                         pm8001_printk("addr - inbnd %p obnd %p\n",
 849                         pm8001_ha->inbnd_q_tbl_addr,
 850                         pm8001_ha->outbnd_q_tbl_addr));
 851         PM8001_INIT_DBG(pm8001_ha,
 852                         pm8001_printk("addr - pspa %p ivt %p\n",
 853                         pm8001_ha->pspa_q_tbl_addr,
 854                         pm8001_ha->ivt_tbl_addr));
 855 }
 856
 857 /**
 858  * pm80xx_set_thermal_config - support the thermal configuration
 859  * @pm8001_ha: our hba card information.
 860  */
 861 int
 862 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
 863 {
 864         struct set_ctrl_cfg_req payload;
 865         struct inbound_queue_table *circularQ;
 866         int rc;
 867         u32 tag;
 868         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
 869         u32 page_code;
 870
 871         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
 872         rc = pm8001_tag_alloc(pm8001_ha, &tag);
 873         if (rc)
 874                 return -1;
 875
 876         circularQ = &pm8001_ha->inbnd_q_tbl[0];
 877         payload.tag = cpu_to_le32(tag);
 878
 879         if (IS_SPCV_12G(pm8001_ha->pdev))
 880                 page_code = THERMAL_PAGE_CODE_7H;
 881         else
 882                 page_code = THERMAL_PAGE_CODE_8H;
 883
 884         payload.cfg_pg[0] =
 885                 cpu_to_le32((THERMAL_LOG_ENABLE << 9) |
 886                             (THERMAL_ENABLE << 8) | page_code);
 887         payload.cfg_pg[1] =
 888                 cpu_to_le32((LTEMPHIL << 24) | (RTEMPHIL << 8));
 889
 890         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
 891         if (rc)
 892                 pm8001_tag_free(pm8001_ha, tag);
 893         return rc;
 894
 895 }
 896
 897 /**
 898 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
 899 * Timer configuration page
 900 * @pm8001_ha: our hba card information.
 901 */
 902 static int
 903 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
 904 {
 905         struct set_ctrl_cfg_req payload;
 906         struct inbound_queue_table *circularQ;
 907         SASProtocolTimerConfig_t SASConfigPage;
 908         int rc;
 909         u32 tag;
 910         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
 911
 912         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
 913         memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
 914
 915         rc = pm8001_tag_alloc(pm8001_ha, &tag);
 916
 917         if (rc)
 918                 return -1;
 919
 920         circularQ = &pm8001_ha->inbnd_q_tbl[0];
 921         payload.tag = cpu_to_le32(tag);
 922
 923         SASConfigPage.pageCode        =  SAS_PROTOCOL_TIMER_CONFIG_PAGE;
 924         SASConfigPage.MST_MSI         =  3 << 15;
 925         SASConfigPage.STP_SSP_MCT_TMO =  (STP_MCT_TMO << 16) | SSP_MCT_TMO;
 926         SASConfigPage.STP_FRM_TMO     = (SAS_MAX_OPEN_TIME << 24) |
 927                                 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
 928         SASConfigPage.STP_IDLE_TMO    =  STP_IDLE_TIME;
 929
 930         if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
 931                 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
 932
 933
 934         SASConfigPage.OPNRJT_RTRY_INTVL =         (SAS_MFD << 16) |
 935                                                 SAS_OPNRJT_RTRY_INTVL;
 936         SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =  (SAS_DOPNRJT_RTRY_TMO << 16)
 937                                                 | SAS_COPNRJT_RTRY_TMO;
 938         SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =  (SAS_DOPNRJT_RTRY_THR << 16)
 939                                                 | SAS_COPNRJT_RTRY_THR;
 940         SASConfigPage.MAX_AIP =  SAS_MAX_AIP;
 941
 942         PM8001_INIT_DBG(pm8001_ha,
 943                         pm8001_printk("SASConfigPage.pageCode "
 944                         "0x%08x\n", SASConfigPage.pageCode));
 945         PM8001_INIT_DBG(pm8001_ha,
 946                         pm8001_printk("SASConfigPage.MST_MSI "
 947                         " 0x%08x\n", SASConfigPage.MST_MSI));
 948         PM8001_INIT_DBG(pm8001_ha,
 949                         pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
 950                         " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
 951         PM8001_INIT_DBG(pm8001_ha,
 952                         pm8001_printk("SASConfigPage.STP_FRM_TMO "
 953                         " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
 954         PM8001_INIT_DBG(pm8001_ha,
 955                         pm8001_printk("SASConfigPage.STP_IDLE_TMO "
 956                         " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
 957         PM8001_INIT_DBG(pm8001_ha,
 958                         pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
 959                         " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
 960         PM8001_INIT_DBG(pm8001_ha,
 961                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
 962                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
 963         PM8001_INIT_DBG(pm8001_ha,
 964                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
 965                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
 966         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
 967                         " 0x%08x\n", SASConfigPage.MAX_AIP));
 968
 969         memcpy(&payload.cfg_pg, &SASConfigPage,
 970                          sizeof(SASProtocolTimerConfig_t));
 971
 972         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
 973         if (rc)
 974                 pm8001_tag_free(pm8001_ha, tag);
 975
 976         return rc;
 977 }
 978
 979 /**
 980  * pm80xx_get_encrypt_info - Check for encryption
 981  * @pm8001_ha: our hba card information.
 982  */
 983 static int
 984 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
 985 {
 986         u32 scratch3_value;
 987         int ret = -1;
 988
 989         /* Read encryption status from SCRATCH PAD 3 */
 990         scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 991
 992         if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
 993                                         SCRATCH_PAD3_ENC_READY) {
 994                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
 995                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
 996                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 997                                                 SCRATCH_PAD3_SMF_ENABLED)
 998                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
 999                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1000                                                 SCRATCH_PAD3_SMA_ENABLED)
1001                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1002                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1003                                                 SCRATCH_PAD3_SMB_ENABLED)
1004                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1005                 pm8001_ha->encrypt_info.status = 0;
1006                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1007                         "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
1008                         "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1009                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1010                         pm8001_ha->encrypt_info.sec_mode,
1011                         pm8001_ha->encrypt_info.status));
1012                 ret = 0;
1013         } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1014                                         SCRATCH_PAD3_ENC_DISABLED) {
1015                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1016                         "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1017                         scratch3_value));
1018                 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1019                 pm8001_ha->encrypt_info.cipher_mode = 0;
1020                 pm8001_ha->encrypt_info.sec_mode = 0;
1021                 ret = 0;
1022         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1023                                 SCRATCH_PAD3_ENC_DIS_ERR) {
1024                 pm8001_ha->encrypt_info.status =
1025                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1026                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1027                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1028                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1029                                         SCRATCH_PAD3_SMF_ENABLED)
1030                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1031                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1032                                         SCRATCH_PAD3_SMA_ENABLED)
1033                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1034                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1035                                         SCRATCH_PAD3_SMB_ENABLED)
1036                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1037                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1038                         "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1039                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1040                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1041                         pm8001_ha->encrypt_info.sec_mode,
1042                         pm8001_ha->encrypt_info.status));
1043         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1044                                  SCRATCH_PAD3_ENC_ENA_ERR) {
1045
1046                 pm8001_ha->encrypt_info.status =
1047                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1048                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1049                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1050                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1051                                         SCRATCH_PAD3_SMF_ENABLED)
1052                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1053                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1054                                         SCRATCH_PAD3_SMA_ENABLED)
1055                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1056                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1057                                         SCRATCH_PAD3_SMB_ENABLED)
1058                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1059
1060                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1061                         "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1062                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1063                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1064                         pm8001_ha->encrypt_info.sec_mode,
1065                         pm8001_ha->encrypt_info.status));
1066         }
1067         return ret;
1068 }
1069
1070 /**
1071  * pm80xx_encrypt_update - update flash with encryption informtion
1072  * @pm8001_ha: our hba card information.
1073  */
1074 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1075 {
1076         struct kek_mgmt_req payload;
1077         struct inbound_queue_table *circularQ;
1078         int rc;
1079         u32 tag;
1080         u32 opc = OPC_INB_KEK_MANAGEMENT;
1081
1082         memset(&payload, 0, sizeof(struct kek_mgmt_req));
1083         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1084         if (rc)
1085                 return -1;
1086
1087         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1088         payload.tag = cpu_to_le32(tag);
1089         /* Currently only one key is used. New KEK index is 1.
1090          * Current KEK index is 1. Store KEK to NVRAM is 1.
1091          */
1092         payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1093                                         KEK_MGMT_SUBOP_KEYCARDUPDATE);
1094
1095         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
1096         if (rc)
1097                 pm8001_tag_free(pm8001_ha, tag);
1098
1099         return rc;
1100 }
1101
1102 /**
1103  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1104  * @pm8001_ha: our hba card information
1105  */
1106 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1107 {
1108         int ret;
1109         u8 i = 0;
1110
1111         /* check the firmware status */
1112         if (-1 == check_fw_ready(pm8001_ha)) {
1113                 PM8001_FAIL_DBG(pm8001_ha,
1114                         pm8001_printk("Firmware is not ready!\n"));
1115                 return -EBUSY;
1116         }
1117
1118         /* Initialize the controller fatal error flag */
1119         pm8001_ha->controller_fatal_error = false;
1120
1121         /* Initialize pci space address eg: mpi offset */
1122         init_pci_device_addresses(pm8001_ha);
1123         init_default_table_values(pm8001_ha);
1124         read_main_config_table(pm8001_ha);
1125         read_general_status_table(pm8001_ha);
1126         read_inbnd_queue_table(pm8001_ha);
1127         read_outbnd_queue_table(pm8001_ha);
1128         read_phy_attr_table(pm8001_ha);
1129
1130         /* update main config table ,inbound table and outbound table */
1131         update_main_config_table(pm8001_ha);
1132         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1133                 update_inbnd_queue_table(pm8001_ha, i);
1134         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1135                 update_outbnd_queue_table(pm8001_ha, i);
1136
1137         /* notify firmware update finished and check initialization status */
1138         if (0 == mpi_init_check(pm8001_ha)) {
1139                 PM8001_INIT_DBG(pm8001_ha,
1140                         pm8001_printk("MPI initialize successful!\n"));
1141         } else
1142                 return -EBUSY;
1143
1144         /* send SAS protocol timer configuration page to FW */
1145         ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1146
1147         /* Check for encryption */
1148         if (pm8001_ha->chip->encrypt) {
1149                 PM8001_INIT_DBG(pm8001_ha,
1150                         pm8001_printk("Checking for encryption\n"));
1151                 ret = pm80xx_get_encrypt_info(pm8001_ha);
1152                 if (ret == -1) {
1153                         PM8001_INIT_DBG(pm8001_ha,
1154                                 pm8001_printk("Encryption error !!\n"));
1155                         if (pm8001_ha->encrypt_info.status == 0x81) {
1156                                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1157                                         "Encryption enabled with error."
1158                                         "Saving encryption key to flash\n"));
1159                                 pm80xx_encrypt_update(pm8001_ha);
1160                         }
1161                 }
1162         }
1163         return 0;
1164 }
1165
1166 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1167 {
1168         u32 max_wait_count;
1169         u32 value;
1170         u32 gst_len_mpistate;
1171         init_pci_device_addresses(pm8001_ha);
1172         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1173         table is stop */
1174         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1175
1176         /* wait until Inbound DoorBell Clear Register toggled */
1177         if (IS_SPCV_12G(pm8001_ha->pdev)) {
1178                 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1179         } else {
1180                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1181         }
1182         do {
1183                 udelay(1);
1184                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1185                 value &= SPCv_MSGU_CFG_TABLE_RESET;
1186         } while ((value != 0) && (--max_wait_count));
1187
1188         if (!max_wait_count) {
1189                 PM8001_FAIL_DBG(pm8001_ha,
1190                         pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1191                 return -1;
1192         }
1193
1194         /* check the MPI-State for termination in progress */
1195         /* wait until Inbound DoorBell Clear Register toggled */
1196         max_wait_count = 2 * 1000 * 1000;       /* 2 sec for spcv/ve */
1197         do {
1198                 udelay(1);
1199                 gst_len_mpistate =
1200                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1201                         GST_GSTLEN_MPIS_OFFSET);
1202                 if (GST_MPI_STATE_UNINIT ==
1203                         (gst_len_mpistate & GST_MPI_STATE_MASK))
1204                         break;
1205         } while (--max_wait_count);
1206         if (!max_wait_count) {
1207                 PM8001_FAIL_DBG(pm8001_ha,
1208                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1209                                 gst_len_mpistate & GST_MPI_STATE_MASK));
1210                 return -1;
1211         }
1212
1213         return 0;
1214 }
1215
1216 /**
1217  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1218  * the FW register status to the originated status.
1219  * @pm8001_ha: our hba card information
1220  */
1221
1222 static int
1223 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1224 {
1225         u32 regval;
1226         u32 bootloader_state;
1227         u32 ibutton0, ibutton1;
1228
1229         /* Process MPI table uninitialization only if FW is ready */
1230         if (!pm8001_ha->controller_fatal_error) {
1231                 /* Check if MPI is in ready state to reset */
1232                 if (mpi_uninit_check(pm8001_ha) != 0) {
1233                         regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1234                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1235                                 "MPI state is not ready scratch1 :0x%x\n",
1236                                 regval));
1237                         return -1;
1238                 }
1239         }
1240         /* checked for reset register normal state; 0x0 */
1241         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1242         PM8001_INIT_DBG(pm8001_ha,
1243                 pm8001_printk("reset register before write : 0x%x\n", regval));
1244
1245         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1246         mdelay(500);
1247
1248         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1249         PM8001_INIT_DBG(pm8001_ha,
1250         pm8001_printk("reset register after write 0x%x\n", regval));
1251
1252         if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1253                         SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1254                 PM8001_MSG_DBG(pm8001_ha,
1255                         pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1256                                         regval));
1257         } else {
1258                 PM8001_MSG_DBG(pm8001_ha,
1259                         pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1260                                         regval));
1261
1262                 /* check bootloader is successfully executed or in HDA mode */
1263                 bootloader_state =
1264                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1265                         SCRATCH_PAD1_BOOTSTATE_MASK;
1266
1267                 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1268                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1269                                 "Bootloader state - HDA mode SEEPROM\n"));
1270                 } else if (bootloader_state ==
1271                                 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1272                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1273                                 "Bootloader state - HDA mode Bootstrap Pin\n"));
1274                 } else if (bootloader_state ==
1275                                 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1276                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1277                                 "Bootloader state - HDA mode soft reset\n"));
1278                 } else if (bootloader_state ==
1279                                         SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1280                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1281                                 "Bootloader state-HDA mode critical error\n"));
1282                 }
1283                 return -EBUSY;
1284         }
1285
1286         /* check the firmware status after reset */
1287         if (-1 == check_fw_ready(pm8001_ha)) {
1288                 PM8001_FAIL_DBG(pm8001_ha,
1289                         pm8001_printk("Firmware is not ready!\n"));
1290                 /* check iButton feature support for motherboard controller */
1291                 if (pm8001_ha->pdev->subsystem_vendor !=
1292                         PCI_VENDOR_ID_ADAPTEC2 &&
1293                         pm8001_ha->pdev->subsystem_vendor !=
1294                         PCI_VENDOR_ID_ATTO &&
1295                         pm8001_ha->pdev->subsystem_vendor != 0) {
1296                         ibutton0 = pm8001_cr32(pm8001_ha, 0,
1297                                         MSGU_HOST_SCRATCH_PAD_6);
1298                         ibutton1 = pm8001_cr32(pm8001_ha, 0,
1299                                         MSGU_HOST_SCRATCH_PAD_7);
1300                         if (!ibutton0 && !ibutton1) {
1301                                 PM8001_FAIL_DBG(pm8001_ha,
1302                                         pm8001_printk("iButton Feature is"
1303                                         " not Available!!!\n"));
1304                                 return -EBUSY;
1305                         }
1306                         if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1307                                 PM8001_FAIL_DBG(pm8001_ha,
1308                                         pm8001_printk("CRC Check for iButton"
1309                                         " Feature Failed!!!\n"));
1310                                 return -EBUSY;
1311                         }
1312                 }
1313         }
1314         PM8001_INIT_DBG(pm8001_ha,
1315                 pm8001_printk("SPCv soft reset Complete\n"));
1316         return 0;
1317 }
1318
1319 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1320 {
1321          u32 i;
1322
1323         PM8001_INIT_DBG(pm8001_ha,
1324                 pm8001_printk("chip reset start\n"));
1325
1326         /* do SPCv chip reset. */
1327         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1328         PM8001_INIT_DBG(pm8001_ha,
1329                 pm8001_printk("SPC soft reset Complete\n"));
1330
1331         /* Check this ..whether delay is required or no */
1332         /* delay 10 usec */
1333         udelay(10);
1334
1335         /* wait for 20 msec until the firmware gets reloaded */
1336         i = 20;
1337         do {
1338                 mdelay(1);
1339         } while ((--i) != 0);
1340
1341         PM8001_INIT_DBG(pm8001_ha,
1342                 pm8001_printk("chip reset finished\n"));
1343 }
1344
1345 /**
1346  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1347  * @pm8001_ha: our hba card information
1348  */
1349 static void
1350 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1351 {
1352         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1353         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1354 }
1355
1356 /**
1357  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1358  * @pm8001_ha: our hba card information
1359  */
1360 static void
1361 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1362 {
1363         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1364 }
1365
1366 /**
1367  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1368  * @pm8001_ha: our hba card information
1369  */
1370 static void
1371 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1372 {
1373 #ifdef PM8001_USE_MSIX
1374         u32 mask;
1375         mask = (u32)(1 << vec);
1376
1377         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1378         return;
1379 #endif
1380         pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1381
1382 }
1383
1384 /**
1385  * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1386  * @pm8001_ha: our hba card information
1387  */
1388 static void
1389 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1390 {
1391 #ifdef PM8001_USE_MSIX
1392         u32 mask;
1393         if (vec == 0xFF)
1394                 mask = 0xFFFFFFFF;
1395         else
1396                 mask = (u32)(1 << vec);
1397         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1398         return;
1399 #endif
1400         pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1401 }
1402
1403 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1404                 struct pm8001_device *pm8001_ha_dev)
1405 {
1406         int res;
1407         u32 ccb_tag;
1408         struct pm8001_ccb_info *ccb;
1409         struct sas_task *task = NULL;
1410         struct task_abort_req task_abort;
1411         struct inbound_queue_table *circularQ;
1412         u32 opc = OPC_INB_SATA_ABORT;
1413         int ret;
1414
1415         if (!pm8001_ha_dev) {
1416                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1417                 return;
1418         }
1419
1420         task = sas_alloc_slow_task(GFP_ATOMIC);
1421
1422         if (!task) {
1423                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1424                                                 "allocate task\n"));
1425                 return;
1426         }
1427
1428         task->task_done = pm8001_task_done;
1429
1430         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1431         if (res) {
1432                 sas_free_task(task);
1433                 return;
1434         }
1435
1436         ccb = &pm8001_ha->ccb_info[ccb_tag];
1437         ccb->device = pm8001_ha_dev;
1438         ccb->ccb_tag = ccb_tag;
1439         ccb->task = task;
1440         ccb->n_elem = 0;
1441
1442         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1443
1444         memset(&task_abort, 0, sizeof(task_abort));
1445         task_abort.abort_all = cpu_to_le32(1);
1446         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1447         task_abort.tag = cpu_to_le32(ccb_tag);
1448
1449         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1450         if (ret) {
1451                 sas_free_task(task);
1452                 pm8001_tag_free(pm8001_ha, ccb_tag);
1453         }
1454 }
1455
1456 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1457                 struct pm8001_device *pm8001_ha_dev)
1458 {
1459         struct sata_start_req sata_cmd;
1460         int res;
1461         u32 ccb_tag;
1462         struct pm8001_ccb_info *ccb;
1463         struct sas_task *task = NULL;
1464         struct host_to_dev_fis fis;
1465         struct domain_device *dev;
1466         struct inbound_queue_table *circularQ;
1467         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1468
1469         task = sas_alloc_slow_task(GFP_ATOMIC);
1470
1471         if (!task) {
1472                 PM8001_FAIL_DBG(pm8001_ha,
1473                         pm8001_printk("cannot allocate task !!!\n"));
1474                 return;
1475         }
1476         task->task_done = pm8001_task_done;
1477
1478         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1479         if (res) {
1480                 sas_free_task(task);
1481                 PM8001_FAIL_DBG(pm8001_ha,
1482                         pm8001_printk("cannot allocate tag !!!\n"));
1483                 return;
1484         }
1485
1486         /* allocate domain device by ourselves as libsas
1487          * is not going to provide any
1488         */
1489         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1490         if (!dev) {
1491                 sas_free_task(task);
1492                 pm8001_tag_free(pm8001_ha, ccb_tag);
1493                 PM8001_FAIL_DBG(pm8001_ha,
1494                         pm8001_printk("Domain device cannot be allocated\n"));
1495                 return;
1496         }
1497
1498         task->dev = dev;
1499         task->dev->lldd_dev = pm8001_ha_dev;
1500
1501         ccb = &pm8001_ha->ccb_info[ccb_tag];
1502         ccb->device = pm8001_ha_dev;
1503         ccb->ccb_tag = ccb_tag;
1504         ccb->task = task;
1505         ccb->n_elem = 0;
1506         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1507         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1508
1509         memset(&sata_cmd, 0, sizeof(sata_cmd));
1510         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1511
1512         /* construct read log FIS */
1513         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1514         fis.fis_type = 0x27;
1515         fis.flags = 0x80;
1516         fis.command = ATA_CMD_READ_LOG_EXT;
1517         fis.lbal = 0x10;
1518         fis.sector_count = 0x1;
1519
1520         sata_cmd.tag = cpu_to_le32(ccb_tag);
1521         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1522         sata_cmd.ncqtag_atap_dir_m_dad = cpu_to_le32(((0x1 << 7) | (0x5 << 9)));
1523         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1524
1525         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1526         if (res) {
1527                 sas_free_task(task);
1528                 pm8001_tag_free(pm8001_ha, ccb_tag);
1529                 kfree(dev);
1530         }
1531 }
1532
1533 /**
1534  * mpi_ssp_completion- process the event that FW response to the SSP request.
1535  * @pm8001_ha: our hba card information
1536  * @piomb: the message contents of this outbound message.
1537  *
1538  * When FW has completed a ssp request for example a IO request, after it has
1539  * filled the SG data with the data, it will trigger this event represent
1540  * that he has finished the job,please check the coresponding buffer.
1541  * So we will tell the caller who maybe waiting the result to tell upper layer
1542  * that the task has been finished.
1543  */
1544 static void
1545 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1546 {
1547         struct sas_task *t;
1548         struct pm8001_ccb_info *ccb;
1549         unsigned long flags;
1550         u32 status;
1551         u32 param;
1552         u32 tag;
1553         struct ssp_completion_resp *psspPayload;
1554         struct task_status_struct *ts;
1555         struct ssp_response_iu *iu;
1556         struct pm8001_device *pm8001_dev;
1557         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1558         status = le32_to_cpu(psspPayload->status);
1559         tag = le32_to_cpu(psspPayload->tag);
1560         ccb = &pm8001_ha->ccb_info[tag];
1561         if ((status == IO_ABORTED) && ccb->open_retry) {
1562                 /* Being completed by another */
1563                 ccb->open_retry = 0;
1564                 return;
1565         }
1566         pm8001_dev = ccb->device;
1567         param = le32_to_cpu(psspPayload->param);
1568         t = ccb->task;
1569
1570         if (status && status != IO_UNDERFLOW)
1571                 PM8001_FAIL_DBG(pm8001_ha,
1572                         pm8001_printk("sas IO status 0x%x\n", status));
1573         if (unlikely(!t || !t->lldd_task || !t->dev))
1574                 return;
1575         ts = &t->task_status;
1576         /* Print sas address of IO failed device */
1577         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1578                 (status != IO_UNDERFLOW))
1579                 PM8001_FAIL_DBG(pm8001_ha,
1580                         pm8001_printk("SAS Address of IO Failure Drive"
1581                         ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1582
1583         switch (status) {
1584         case IO_SUCCESS:
1585                 PM8001_IO_DBG(pm8001_ha,
1586                         pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1587                                 param));
1588                 if (param == 0) {
1589                         ts->resp = SAS_TASK_COMPLETE;
1590                         ts->stat = SAM_STAT_GOOD;
1591                 } else {
1592                         ts->resp = SAS_TASK_COMPLETE;
1593                         ts->stat = SAS_PROTO_RESPONSE;
1594                         ts->residual = param;
1595                         iu = &psspPayload->ssp_resp_iu;
1596                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1597                 }
1598                 if (pm8001_dev)
1599                         pm8001_dev->running_req--;
1600                 break;
1601         case IO_ABORTED:
1602                 PM8001_IO_DBG(pm8001_ha,
1603                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1604                 ts->resp = SAS_TASK_COMPLETE;
1605                 ts->stat = SAS_ABORTED_TASK;
1606                 break;
1607         case IO_UNDERFLOW:
1608                 /* SSP Completion with error */
1609                 PM8001_IO_DBG(pm8001_ha,
1610                         pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1611                                 param));
1612                 ts->resp = SAS_TASK_COMPLETE;
1613                 ts->stat = SAS_DATA_UNDERRUN;
1614                 ts->residual = param;
1615                 if (pm8001_dev)
1616                         pm8001_dev->running_req--;
1617                 break;
1618         case IO_NO_DEVICE:
1619                 PM8001_IO_DBG(pm8001_ha,
1620                         pm8001_printk("IO_NO_DEVICE\n"));
1621                 ts->resp = SAS_TASK_UNDELIVERED;
1622                 ts->stat = SAS_PHY_DOWN;
1623                 break;
1624         case IO_XFER_ERROR_BREAK:
1625                 PM8001_IO_DBG(pm8001_ha,
1626                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1627                 ts->resp = SAS_TASK_COMPLETE;
1628                 ts->stat = SAS_OPEN_REJECT;
1629                 /* Force the midlayer to retry */
1630                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1631                 break;
1632         case IO_XFER_ERROR_PHY_NOT_READY:
1633                 PM8001_IO_DBG(pm8001_ha,
1634                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1635                 ts->resp = SAS_TASK_COMPLETE;
1636                 ts->stat = SAS_OPEN_REJECT;
1637                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1638                 break;
1639         case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1640                 PM8001_IO_DBG(pm8001_ha,
1641                         pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"));
1642                 ts->resp = SAS_TASK_COMPLETE;
1643                 ts->stat = SAS_OPEN_REJECT;
1644                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1645                 break;
1646         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1647                 PM8001_IO_DBG(pm8001_ha,
1648                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1649                 ts->resp = SAS_TASK_COMPLETE;
1650                 ts->stat = SAS_OPEN_REJECT;
1651                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1652                 break;
1653         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1654                 PM8001_IO_DBG(pm8001_ha,
1655                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1656                 ts->resp = SAS_TASK_COMPLETE;
1657                 ts->stat = SAS_OPEN_REJECT;
1658                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1659                 break;
1660         case IO_OPEN_CNX_ERROR_BREAK:
1661                 PM8001_IO_DBG(pm8001_ha,
1662                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1663                 ts->resp = SAS_TASK_COMPLETE;
1664                 ts->stat = SAS_OPEN_REJECT;
1665                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1666                 break;
1667         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1668         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1669         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1670         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1671         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1672         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1673                 PM8001_IO_DBG(pm8001_ha,
1674                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1675                 ts->resp = SAS_TASK_COMPLETE;
1676                 ts->stat = SAS_OPEN_REJECT;
1677                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1678                 if (!t->uldd_task)
1679                         pm8001_handle_event(pm8001_ha,
1680                                 pm8001_dev,
1681                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1682                 break;
1683         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1684                 PM8001_IO_DBG(pm8001_ha,
1685                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1686                 ts->resp = SAS_TASK_COMPLETE;
1687                 ts->stat = SAS_OPEN_REJECT;
1688                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1689                 break;
1690         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1691                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1692                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1693                 ts->resp = SAS_TASK_COMPLETE;
1694                 ts->stat = SAS_OPEN_REJECT;
1695                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1696                 break;
1697         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1698                 PM8001_IO_DBG(pm8001_ha,
1699                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1700                 ts->resp = SAS_TASK_UNDELIVERED;
1701                 ts->stat = SAS_OPEN_REJECT;
1702                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1703                 break;
1704         case IO_XFER_ERROR_NAK_RECEIVED:
1705                 PM8001_IO_DBG(pm8001_ha,
1706                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1707                 ts->resp = SAS_TASK_COMPLETE;
1708                 ts->stat = SAS_OPEN_REJECT;
1709                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1710                 break;
1711         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1712                 PM8001_IO_DBG(pm8001_ha,
1713                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1714                 ts->resp = SAS_TASK_COMPLETE;
1715                 ts->stat = SAS_NAK_R_ERR;
1716                 break;
1717         case IO_XFER_ERROR_DMA:
1718                 PM8001_IO_DBG(pm8001_ha,
1719                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1720                 ts->resp = SAS_TASK_COMPLETE;
1721                 ts->stat = SAS_OPEN_REJECT;
1722                 break;
1723         case IO_XFER_OPEN_RETRY_TIMEOUT:
1724                 PM8001_IO_DBG(pm8001_ha,
1725                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1726                 ts->resp = SAS_TASK_COMPLETE;
1727                 ts->stat = SAS_OPEN_REJECT;
1728                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1729                 break;
1730         case IO_XFER_ERROR_OFFSET_MISMATCH:
1731                 PM8001_IO_DBG(pm8001_ha,
1732                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1733                 ts->resp = SAS_TASK_COMPLETE;
1734                 ts->stat = SAS_OPEN_REJECT;
1735                 break;
1736         case IO_PORT_IN_RESET:
1737                 PM8001_IO_DBG(pm8001_ha,
1738                         pm8001_printk("IO_PORT_IN_RESET\n"));
1739                 ts->resp = SAS_TASK_COMPLETE;
1740                 ts->stat = SAS_OPEN_REJECT;
1741                 break;
1742         case IO_DS_NON_OPERATIONAL:
1743                 PM8001_IO_DBG(pm8001_ha,
1744                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1745                 ts->resp = SAS_TASK_COMPLETE;
1746                 ts->stat = SAS_OPEN_REJECT;
1747                 if (!t->uldd_task)
1748                         pm8001_handle_event(pm8001_ha,
1749                                 pm8001_dev,
1750                                 IO_DS_NON_OPERATIONAL);
1751                 break;
1752         case IO_DS_IN_RECOVERY:
1753                 PM8001_IO_DBG(pm8001_ha,
1754                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
1755                 ts->resp = SAS_TASK_COMPLETE;
1756                 ts->stat = SAS_OPEN_REJECT;
1757                 break;
1758         case IO_TM_TAG_NOT_FOUND:
1759                 PM8001_IO_DBG(pm8001_ha,
1760                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1761                 ts->resp = SAS_TASK_COMPLETE;
1762                 ts->stat = SAS_OPEN_REJECT;
1763                 break;
1764         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1765                 PM8001_IO_DBG(pm8001_ha,
1766                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1767                 ts->resp = SAS_TASK_COMPLETE;
1768                 ts->stat = SAS_OPEN_REJECT;
1769                 break;
1770         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1771                 PM8001_IO_DBG(pm8001_ha,
1772                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1773                 ts->resp = SAS_TASK_COMPLETE;
1774                 ts->stat = SAS_OPEN_REJECT;
1775                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1776                 break;
1777         default:
1778                 PM8001_IO_DBG(pm8001_ha,
1779                         pm8001_printk("Unknown status 0x%x\n", status));
1780                 /* not allowed case. Therefore, return failed status */
1781                 ts->resp = SAS_TASK_COMPLETE;
1782                 ts->stat = SAS_OPEN_REJECT;
1783                 break;
1784         }
1785         PM8001_IO_DBG(pm8001_ha,
1786                 pm8001_printk("scsi_status = 0x%x\n ",
1787                 psspPayload->ssp_resp_iu.status));
1788         spin_lock_irqsave(&t->task_state_lock, flags);
1789         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1790         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1791         t->task_state_flags |= SAS_TASK_STATE_DONE;
1792         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1793                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1794                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1795                         "task 0x%p done with io_status 0x%x resp 0x%x "
1796                         "stat 0x%x but aborted by upper layer!\n",
1797                         t, status, ts->resp, ts->stat));
1798                 if (t->slow_task)
1799                         complete(&t->slow_task->completion);
1800                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1801         } else {
1802                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1803                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1804                 mb();/* in order to force CPU ordering */
1805                 t->task_done(t);
1806         }
1807 }
1808
1809 /*See the comments for mpi_ssp_completion */
1810 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1811 {
1812         struct sas_task *t;
1813         unsigned long flags;
1814         struct task_status_struct *ts;
1815         struct pm8001_ccb_info *ccb;
1816         struct pm8001_device *pm8001_dev;
1817         struct ssp_event_resp *psspPayload =
1818                 (struct ssp_event_resp *)(piomb + 4);
1819         u32 event = le32_to_cpu(psspPayload->event);
1820         u32 tag = le32_to_cpu(psspPayload->tag);
1821         u32 port_id = le32_to_cpu(psspPayload->port_id);
1822
1823         ccb = &pm8001_ha->ccb_info[tag];
1824         t = ccb->task;
1825         pm8001_dev = ccb->device;
1826         if (event)
1827                 PM8001_FAIL_DBG(pm8001_ha,
1828                         pm8001_printk("sas IO status 0x%x\n", event));
1829         if (unlikely(!t || !t->lldd_task || !t->dev))
1830                 return;
1831         ts = &t->task_status;
1832         PM8001_IO_DBG(pm8001_ha,
1833                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1834                                 port_id, tag, event));
1835         switch (event) {
1836         case IO_OVERFLOW:
1837                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1838                 ts->resp = SAS_TASK_COMPLETE;
1839                 ts->stat = SAS_DATA_OVERRUN;
1840                 ts->residual = 0;
1841                 if (pm8001_dev)
1842                         pm8001_dev->running_req--;
1843                 break;
1844         case IO_XFER_ERROR_BREAK:
1845                 PM8001_IO_DBG(pm8001_ha,
1846                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1847                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1848                 return;
1849         case IO_XFER_ERROR_PHY_NOT_READY:
1850                 PM8001_IO_DBG(pm8001_ha,
1851                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1852                 ts->resp = SAS_TASK_COMPLETE;
1853                 ts->stat = SAS_OPEN_REJECT;
1854                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1855                 break;
1856         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1857                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1858                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1859                 ts->resp = SAS_TASK_COMPLETE;
1860                 ts->stat = SAS_OPEN_REJECT;
1861                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1862                 break;
1863         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1864                 PM8001_IO_DBG(pm8001_ha,
1865                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1866                 ts->resp = SAS_TASK_COMPLETE;
1867                 ts->stat = SAS_OPEN_REJECT;
1868                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1869                 break;
1870         case IO_OPEN_CNX_ERROR_BREAK:
1871                 PM8001_IO_DBG(pm8001_ha,
1872                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1873                 ts->resp = SAS_TASK_COMPLETE;
1874                 ts->stat = SAS_OPEN_REJECT;
1875                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1876                 break;
1877         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1878         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1879         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1880         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1881         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1882         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1883                 PM8001_IO_DBG(pm8001_ha,
1884                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1885                 ts->resp = SAS_TASK_COMPLETE;
1886                 ts->stat = SAS_OPEN_REJECT;
1887                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1888                 if (!t->uldd_task)
1889                         pm8001_handle_event(pm8001_ha,
1890                                 pm8001_dev,
1891                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1892                 break;
1893         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1894                 PM8001_IO_DBG(pm8001_ha,
1895                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1896                 ts->resp = SAS_TASK_COMPLETE;
1897                 ts->stat = SAS_OPEN_REJECT;
1898                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1899                 break;
1900         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1901                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1902                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1903                 ts->resp = SAS_TASK_COMPLETE;
1904                 ts->stat = SAS_OPEN_REJECT;
1905                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1906                 break;
1907         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1908                 PM8001_IO_DBG(pm8001_ha,
1909                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1910                 ts->resp = SAS_TASK_COMPLETE;
1911                 ts->stat = SAS_OPEN_REJECT;
1912                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1913                 break;
1914         case IO_XFER_ERROR_NAK_RECEIVED:
1915                 PM8001_IO_DBG(pm8001_ha,
1916                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1917                 ts->resp = SAS_TASK_COMPLETE;
1918                 ts->stat = SAS_OPEN_REJECT;
1919                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1920                 break;
1921         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1922                 PM8001_IO_DBG(pm8001_ha,
1923                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1924                 ts->resp = SAS_TASK_COMPLETE;
1925                 ts->stat = SAS_NAK_R_ERR;
1926                 break;
1927         case IO_XFER_OPEN_RETRY_TIMEOUT:
1928                 PM8001_IO_DBG(pm8001_ha,
1929                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1930                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1931                 return;
1932         case IO_XFER_ERROR_UNEXPECTED_PHASE:
1933                 PM8001_IO_DBG(pm8001_ha,
1934                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1935                 ts->resp = SAS_TASK_COMPLETE;
1936                 ts->stat = SAS_DATA_OVERRUN;
1937                 break;
1938         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1939                 PM8001_IO_DBG(pm8001_ha,
1940                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1941                 ts->resp = SAS_TASK_COMPLETE;
1942                 ts->stat = SAS_DATA_OVERRUN;
1943                 break;
1944         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1945                 PM8001_IO_DBG(pm8001_ha,
1946                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1947                 ts->resp = SAS_TASK_COMPLETE;
1948                 ts->stat = SAS_DATA_OVERRUN;
1949                 break;
1950         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1951                 PM8001_IO_DBG(pm8001_ha,
1952                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1953                 ts->resp = SAS_TASK_COMPLETE;
1954                 ts->stat = SAS_DATA_OVERRUN;
1955                 break;
1956         case IO_XFER_ERROR_OFFSET_MISMATCH:
1957                 PM8001_IO_DBG(pm8001_ha,
1958                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1959                 ts->resp = SAS_TASK_COMPLETE;
1960                 ts->stat = SAS_DATA_OVERRUN;
1961                 break;
1962         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1963                 PM8001_IO_DBG(pm8001_ha,
1964                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1965                 ts->resp = SAS_TASK_COMPLETE;
1966                 ts->stat = SAS_DATA_OVERRUN;
1967                 break;
1968         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
1969                 PM8001_IO_DBG(pm8001_ha,
1970                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
1971                 /* TBC: used default set values */
1972                 ts->resp = SAS_TASK_COMPLETE;
1973                 ts->stat = SAS_DATA_OVERRUN;
1974                 break;
1975         case IO_XFER_CMD_FRAME_ISSUED:
1976                 PM8001_IO_DBG(pm8001_ha,
1977                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1978                 return;
1979         default:
1980                 PM8001_IO_DBG(pm8001_ha,
1981                         pm8001_printk("Unknown status 0x%x\n", event));
1982                 /* not allowed case. Therefore, return failed status */
1983                 ts->resp = SAS_TASK_COMPLETE;
1984                 ts->stat = SAS_DATA_OVERRUN;
1985                 break;
1986         }
1987         spin_lock_irqsave(&t->task_state_lock, flags);
1988         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1989         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1990         t->task_state_flags |= SAS_TASK_STATE_DONE;
1991         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1992                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1993                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1994                         "task 0x%p done with event 0x%x resp 0x%x "
1995                         "stat 0x%x but aborted by upper layer!\n",
1996                         t, event, ts->resp, ts->stat));
1997                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1998         } else {
1999                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2000                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2001                 mb();/* in order to force CPU ordering */
2002                 t->task_done(t);
2003         }
2004 }
2005
2006 /*See the comments for mpi_ssp_completion */
2007 static void
2008 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2009 {
2010         struct sas_task *t;
2011         struct pm8001_ccb_info *ccb;
2012         u32 param;
2013         u32 status;
2014         u32 tag;
2015         int i, j;
2016         u8 sata_addr_low[4];
2017         u32 temp_sata_addr_low, temp_sata_addr_hi;
2018         u8 sata_addr_hi[4];
2019         struct sata_completion_resp *psataPayload;
2020         struct task_status_struct *ts;
2021         struct ata_task_resp *resp ;
2022         u32 *sata_resp;
2023         struct pm8001_device *pm8001_dev;
2024         unsigned long flags;
2025
2026         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2027         status = le32_to_cpu(psataPayload->status);
2028         tag = le32_to_cpu(psataPayload->tag);
2029
2030         if (!tag) {
2031                 PM8001_FAIL_DBG(pm8001_ha,
2032                         pm8001_printk("tag null\n"));
2033                 return;
2034         }
2035         ccb = &pm8001_ha->ccb_info[tag];
2036         param = le32_to_cpu(psataPayload->param);
2037         if (ccb) {
2038                 t = ccb->task;
2039                 pm8001_dev = ccb->device;
2040         } else {
2041                 PM8001_FAIL_DBG(pm8001_ha,
2042                         pm8001_printk("ccb null\n"));
2043                 return;
2044         }
2045
2046         if (t) {
2047                 if (t->dev && (t->dev->lldd_dev))
2048                         pm8001_dev = t->dev->lldd_dev;
2049         } else {
2050                 PM8001_FAIL_DBG(pm8001_ha,
2051                         pm8001_printk("task null\n"));
2052                 return;
2053         }
2054
2055         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2056                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2057                 PM8001_FAIL_DBG(pm8001_ha,
2058                         pm8001_printk("task or dev null\n"));
2059                 return;
2060         }
2061
2062         ts = &t->task_status;
2063         if (!ts) {
2064                 PM8001_FAIL_DBG(pm8001_ha,
2065                         pm8001_printk("ts null\n"));
2066                 return;
2067         }
2068         /* Print sas address of IO failed device */
2069         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2070                 (status != IO_UNDERFLOW)) {
2071                 if (!((t->dev->parent) &&
2072                         (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
2073                         for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2074                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2075                         for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2076                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2077                         memcpy(&temp_sata_addr_low, sata_addr_low,
2078                                 sizeof(sata_addr_low));
2079                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2080                                 sizeof(sata_addr_hi));
2081                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2082                                                 |((temp_sata_addr_hi << 8) &
2083                                                 0xff0000) |
2084                                                 ((temp_sata_addr_hi >> 8)
2085                                                 & 0xff00) |
2086                                                 ((temp_sata_addr_hi << 24) &
2087                                                 0xff000000));
2088                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2089                                                 & 0xff) |
2090                                                 ((temp_sata_addr_low << 8)
2091                                                 & 0xff0000) |
2092                                                 ((temp_sata_addr_low >> 8)
2093                                                 & 0xff00) |
2094                                                 ((temp_sata_addr_low << 24)
2095                                                 & 0xff000000)) +
2096                                                 pm8001_dev->attached_phy +
2097                                                 0x10);
2098                         PM8001_FAIL_DBG(pm8001_ha,
2099                                 pm8001_printk("SAS Address of IO Failure Drive:"
2100                                 "%08x%08x", temp_sata_addr_hi,
2101                                         temp_sata_addr_low));
2102
2103                 } else {
2104                         PM8001_FAIL_DBG(pm8001_ha,
2105                                 pm8001_printk("SAS Address of IO Failure Drive:"
2106                                 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2107                 }
2108         }
2109         switch (status) {
2110         case IO_SUCCESS:
2111                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2112                 if (param == 0) {
2113                         ts->resp = SAS_TASK_COMPLETE;
2114                         ts->stat = SAM_STAT_GOOD;
2115                         /* check if response is for SEND READ LOG */
2116                         if (pm8001_dev &&
2117                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2118                                 /* set new bit for abort_all */
2119                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2120                                 /* clear bit for read log */
2121                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2122                                 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2123                                 /* Free the tag */
2124                                 pm8001_tag_free(pm8001_ha, tag);
2125                                 sas_free_task(t);
2126                                 return;
2127                         }
2128                 } else {
2129                         u8 len;
2130                         ts->resp = SAS_TASK_COMPLETE;
2131                         ts->stat = SAS_PROTO_RESPONSE;
2132                         ts->residual = param;
2133                         PM8001_IO_DBG(pm8001_ha,
2134                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2135                                 param));
2136                         sata_resp = &psataPayload->sata_resp[0];
2137                         resp = (struct ata_task_resp *)ts->buf;
2138                         if (t->ata_task.dma_xfer == 0 &&
2139                         t->data_dir == PCI_DMA_FROMDEVICE) {
2140                                 len = sizeof(struct pio_setup_fis);
2141                                 PM8001_IO_DBG(pm8001_ha,
2142                                 pm8001_printk("PIO read len = %d\n", len));
2143                         } else if (t->ata_task.use_ncq) {
2144                                 len = sizeof(struct set_dev_bits_fis);
2145                                 PM8001_IO_DBG(pm8001_ha,
2146                                         pm8001_printk("FPDMA len = %d\n", len));
2147                         } else {
2148                                 len = sizeof(struct dev_to_host_fis);
2149                                 PM8001_IO_DBG(pm8001_ha,
2150                                 pm8001_printk("other len = %d\n", len));
2151                         }
2152                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2153                                 resp->frame_len = len;
2154                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2155                                 ts->buf_valid_size = sizeof(*resp);
2156                         } else
2157                                 PM8001_IO_DBG(pm8001_ha,
2158                                         pm8001_printk("response to large\n"));
2159                 }
2160                 if (pm8001_dev)
2161                         pm8001_dev->running_req--;
2162                 break;
2163         case IO_ABORTED:
2164                 PM8001_IO_DBG(pm8001_ha,
2165                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2166                 ts->resp = SAS_TASK_COMPLETE;
2167                 ts->stat = SAS_ABORTED_TASK;
2168                 if (pm8001_dev)
2169                         pm8001_dev->running_req--;
2170                 break;
2171                 /* following cases are to do cases */
2172         case IO_UNDERFLOW:
2173                 /* SATA Completion with error */
2174                 PM8001_IO_DBG(pm8001_ha,
2175                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2176                 ts->resp = SAS_TASK_COMPLETE;
2177                 ts->stat = SAS_DATA_UNDERRUN;
2178                 ts->residual = param;
2179                 if (pm8001_dev)
2180                         pm8001_dev->running_req--;
2181                 break;
2182         case IO_NO_DEVICE:
2183                 PM8001_IO_DBG(pm8001_ha,
2184                         pm8001_printk("IO_NO_DEVICE\n"));
2185                 ts->resp = SAS_TASK_UNDELIVERED;
2186                 ts->stat = SAS_PHY_DOWN;
2187                 break;
2188         case IO_XFER_ERROR_BREAK:
2189                 PM8001_IO_DBG(pm8001_ha,
2190                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2191                 ts->resp = SAS_TASK_COMPLETE;
2192                 ts->stat = SAS_INTERRUPTED;
2193                 break;
2194         case IO_XFER_ERROR_PHY_NOT_READY:
2195                 PM8001_IO_DBG(pm8001_ha,
2196                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2197                 ts->resp = SAS_TASK_COMPLETE;
2198                 ts->stat = SAS_OPEN_REJECT;
2199                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2200                 break;
2201         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2202                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2203                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2204                 ts->resp = SAS_TASK_COMPLETE;
2205                 ts->stat = SAS_OPEN_REJECT;
2206                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2207                 break;
2208         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2209                 PM8001_IO_DBG(pm8001_ha,
2210                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2211                 ts->resp = SAS_TASK_COMPLETE;
2212                 ts->stat = SAS_OPEN_REJECT;
2213                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2214                 break;
2215         case IO_OPEN_CNX_ERROR_BREAK:
2216                 PM8001_IO_DBG(pm8001_ha,
2217                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2218                 ts->resp = SAS_TASK_COMPLETE;
2219                 ts->stat = SAS_OPEN_REJECT;
2220                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2221                 break;
2222         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2223         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2224         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2225         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2226         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2227         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2228                 PM8001_IO_DBG(pm8001_ha,
2229                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2230                 ts->resp = SAS_TASK_COMPLETE;
2231                 ts->stat = SAS_DEV_NO_RESPONSE;
2232                 if (!t->uldd_task) {
2233                         pm8001_handle_event(pm8001_ha,
2234                                 pm8001_dev,
2235                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2236                         ts->resp = SAS_TASK_UNDELIVERED;
2237                         ts->stat = SAS_QUEUE_FULL;
2238                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2239                         return;
2240                 }
2241                 break;
2242         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2243                 PM8001_IO_DBG(pm8001_ha,
2244                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2245                 ts->resp = SAS_TASK_UNDELIVERED;
2246                 ts->stat = SAS_OPEN_REJECT;
2247                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2248                 if (!t->uldd_task) {
2249                         pm8001_handle_event(pm8001_ha,
2250                                 pm8001_dev,
2251                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2252                         ts->resp = SAS_TASK_UNDELIVERED;
2253                         ts->stat = SAS_QUEUE_FULL;
2254                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2255                         return;
2256                 }
2257                 break;
2258         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2259                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2260                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2261                 ts->resp = SAS_TASK_COMPLETE;
2262                 ts->stat = SAS_OPEN_REJECT;
2263                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2264                 break;
2265         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2266                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2267                         "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2268                 ts->resp = SAS_TASK_COMPLETE;
2269                 ts->stat = SAS_DEV_NO_RESPONSE;
2270                 if (!t->uldd_task) {
2271                         pm8001_handle_event(pm8001_ha,
2272                                 pm8001_dev,
2273                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2274                         ts->resp = SAS_TASK_UNDELIVERED;
2275                         ts->stat = SAS_QUEUE_FULL;
2276                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2277                         return;
2278                 }
2279                 break;
2280         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2281                 PM8001_IO_DBG(pm8001_ha,
2282                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2283                 ts->resp = SAS_TASK_COMPLETE;
2284                 ts->stat = SAS_OPEN_REJECT;
2285                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2286                 break;
2287         case IO_XFER_ERROR_NAK_RECEIVED:
2288                 PM8001_IO_DBG(pm8001_ha,
2289                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2290                 ts->resp = SAS_TASK_COMPLETE;
2291                 ts->stat = SAS_NAK_R_ERR;
2292                 break;
2293         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2294                 PM8001_IO_DBG(pm8001_ha,
2295                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2296                 ts->resp = SAS_TASK_COMPLETE;
2297                 ts->stat = SAS_NAK_R_ERR;
2298                 break;
2299         case IO_XFER_ERROR_DMA:
2300                 PM8001_IO_DBG(pm8001_ha,
2301                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2302                 ts->resp = SAS_TASK_COMPLETE;
2303                 ts->stat = SAS_ABORTED_TASK;
2304                 break;
2305         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2306                 PM8001_IO_DBG(pm8001_ha,
2307                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2308                 ts->resp = SAS_TASK_UNDELIVERED;
2309                 ts->stat = SAS_DEV_NO_RESPONSE;
2310                 break;
2311         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2312                 PM8001_IO_DBG(pm8001_ha,
2313                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2314                 ts->resp = SAS_TASK_COMPLETE;
2315                 ts->stat = SAS_DATA_UNDERRUN;
2316                 break;
2317         case IO_XFER_OPEN_RETRY_TIMEOUT:
2318                 PM8001_IO_DBG(pm8001_ha,
2319                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2320                 ts->resp = SAS_TASK_COMPLETE;
2321                 ts->stat = SAS_OPEN_TO;
2322                 break;
2323         case IO_PORT_IN_RESET:
2324                 PM8001_IO_DBG(pm8001_ha,
2325                         pm8001_printk("IO_PORT_IN_RESET\n"));
2326                 ts->resp = SAS_TASK_COMPLETE;
2327                 ts->stat = SAS_DEV_NO_RESPONSE;
2328                 break;
2329         case IO_DS_NON_OPERATIONAL:
2330                 PM8001_IO_DBG(pm8001_ha,
2331                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2332                 ts->resp = SAS_TASK_COMPLETE;
2333                 ts->stat = SAS_DEV_NO_RESPONSE;
2334                 if (!t->uldd_task) {
2335                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2336                                         IO_DS_NON_OPERATIONAL);
2337                         ts->resp = SAS_TASK_UNDELIVERED;
2338                         ts->stat = SAS_QUEUE_FULL;
2339                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2340                         return;
2341                 }
2342                 break;
2343         case IO_DS_IN_RECOVERY:
2344                 PM8001_IO_DBG(pm8001_ha,
2345                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2346                 ts->resp = SAS_TASK_COMPLETE;
2347                 ts->stat = SAS_DEV_NO_RESPONSE;
2348                 break;
2349         case IO_DS_IN_ERROR:
2350                 PM8001_IO_DBG(pm8001_ha,
2351                         pm8001_printk("IO_DS_IN_ERROR\n"));
2352                 ts->resp = SAS_TASK_COMPLETE;
2353                 ts->stat = SAS_DEV_NO_RESPONSE;
2354                 if (!t->uldd_task) {
2355                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2356                                         IO_DS_IN_ERROR);
2357                         ts->resp = SAS_TASK_UNDELIVERED;
2358                         ts->stat = SAS_QUEUE_FULL;
2359                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2360                         return;
2361                 }
2362                 break;
2363         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2364                 PM8001_IO_DBG(pm8001_ha,
2365                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2366                 ts->resp = SAS_TASK_COMPLETE;
2367                 ts->stat = SAS_OPEN_REJECT;
2368                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2369                 break;
2370         default:
2371                 PM8001_IO_DBG(pm8001_ha,
2372                         pm8001_printk("Unknown status 0x%x\n", status));
2373                 /* not allowed case. Therefore, return failed status */
2374                 ts->resp = SAS_TASK_COMPLETE;
2375                 ts->stat = SAS_DEV_NO_RESPONSE;
2376                 break;
2377         }
2378         spin_lock_irqsave(&t->task_state_lock, flags);
2379         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2380         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2381         t->task_state_flags |= SAS_TASK_STATE_DONE;
2382         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2383                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2384                 PM8001_FAIL_DBG(pm8001_ha,
2385                         pm8001_printk("task 0x%p done with io_status 0x%x"
2386                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2387                         t, status, ts->resp, ts->stat));
2388                 if (t->slow_task)
2389                         complete(&t->slow_task->completion);
2390                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2391         } else {
2392                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2393                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2394         }
2395 }
2396
2397 /*See the comments for mpi_ssp_completion */
2398 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2399 {
2400         struct sas_task *t;
2401         struct task_status_struct *ts;
2402         struct pm8001_ccb_info *ccb;
2403         struct pm8001_device *pm8001_dev;
2404         struct sata_event_resp *psataPayload =
2405                 (struct sata_event_resp *)(piomb + 4);
2406         u32 event = le32_to_cpu(psataPayload->event);
2407         u32 tag = le32_to_cpu(psataPayload->tag);
2408         u32 port_id = le32_to_cpu(psataPayload->port_id);
2409         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2410         unsigned long flags;
2411
2412         ccb = &pm8001_ha->ccb_info[tag];
2413
2414         if (ccb) {
2415                 t = ccb->task;
2416                 pm8001_dev = ccb->device;
2417         } else {
2418                 PM8001_FAIL_DBG(pm8001_ha,
2419                         pm8001_printk("No CCB !!!. returning\n"));
2420                 return;
2421         }
2422         if (event)
2423                 PM8001_FAIL_DBG(pm8001_ha,
2424                         pm8001_printk("SATA EVENT 0x%x\n", event));
2425
2426         /* Check if this is NCQ error */
2427         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2428                 /* find device using device id */
2429                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2430                 /* send read log extension */
2431                 if (pm8001_dev)
2432                         pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2433                 return;
2434         }
2435
2436         if (unlikely(!t || !t->lldd_task || !t->dev)) {
2437                 PM8001_FAIL_DBG(pm8001_ha,
2438                         pm8001_printk("task or dev null\n"));
2439                 return;
2440         }
2441
2442         ts = &t->task_status;
2443         PM8001_IO_DBG(pm8001_ha,
2444                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2445                                 port_id, tag, event));
2446         switch (event) {
2447         case IO_OVERFLOW:
2448                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2449                 ts->resp = SAS_TASK_COMPLETE;
2450                 ts->stat = SAS_DATA_OVERRUN;
2451                 ts->residual = 0;
2452                 if (pm8001_dev)
2453                         pm8001_dev->running_req--;
2454                 break;
2455         case IO_XFER_ERROR_BREAK:
2456                 PM8001_IO_DBG(pm8001_ha,
2457                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2458                 ts->resp = SAS_TASK_COMPLETE;
2459                 ts->stat = SAS_INTERRUPTED;
2460                 break;
2461         case IO_XFER_ERROR_PHY_NOT_READY:
2462                 PM8001_IO_DBG(pm8001_ha,
2463                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2464                 ts->resp = SAS_TASK_COMPLETE;
2465                 ts->stat = SAS_OPEN_REJECT;
2466                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2467                 break;
2468         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2469                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2470                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2471                 ts->resp = SAS_TASK_COMPLETE;
2472                 ts->stat = SAS_OPEN_REJECT;
2473                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2474                 break;
2475         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2476                 PM8001_IO_DBG(pm8001_ha,
2477                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2478                 ts->resp = SAS_TASK_COMPLETE;
2479                 ts->stat = SAS_OPEN_REJECT;
2480                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2481                 break;
2482         case IO_OPEN_CNX_ERROR_BREAK:
2483                 PM8001_IO_DBG(pm8001_ha,
2484                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2485                 ts->resp = SAS_TASK_COMPLETE;
2486                 ts->stat = SAS_OPEN_REJECT;
2487                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2488                 break;
2489         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2490         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2491         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2492         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2493         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2494         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2495                 PM8001_FAIL_DBG(pm8001_ha,
2496                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2497                 ts->resp = SAS_TASK_UNDELIVERED;
2498                 ts->stat = SAS_DEV_NO_RESPONSE;
2499                 if (!t->uldd_task) {
2500                         pm8001_handle_event(pm8001_ha,
2501                                 pm8001_dev,
2502                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2503                         ts->resp = SAS_TASK_COMPLETE;
2504                         ts->stat = SAS_QUEUE_FULL;
2505                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2506                         return;
2507                 }
2508                 break;
2509         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2510                 PM8001_IO_DBG(pm8001_ha,
2511                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2512                 ts->resp = SAS_TASK_UNDELIVERED;
2513                 ts->stat = SAS_OPEN_REJECT;
2514                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2515                 break;
2516         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2517                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2518                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2519                 ts->resp = SAS_TASK_COMPLETE;
2520                 ts->stat = SAS_OPEN_REJECT;
2521                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2522                 break;
2523         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2524                 PM8001_IO_DBG(pm8001_ha,
2525                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2526                 ts->resp = SAS_TASK_COMPLETE;
2527                 ts->stat = SAS_OPEN_REJECT;
2528                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2529                 break;
2530         case IO_XFER_ERROR_NAK_RECEIVED:
2531                 PM8001_IO_DBG(pm8001_ha,
2532                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2533                 ts->resp = SAS_TASK_COMPLETE;
2534                 ts->stat = SAS_NAK_R_ERR;
2535                 break;
2536         case IO_XFER_ERROR_PEER_ABORTED:
2537                 PM8001_IO_DBG(pm8001_ha,
2538                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2539                 ts->resp = SAS_TASK_COMPLETE;
2540                 ts->stat = SAS_NAK_R_ERR;
2541                 break;
2542         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2543                 PM8001_IO_DBG(pm8001_ha,
2544                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2545                 ts->resp = SAS_TASK_COMPLETE;
2546                 ts->stat = SAS_DATA_UNDERRUN;
2547                 break;
2548         case IO_XFER_OPEN_RETRY_TIMEOUT:
2549                 PM8001_IO_DBG(pm8001_ha,
2550                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2551                 ts->resp = SAS_TASK_COMPLETE;
2552                 ts->stat = SAS_OPEN_TO;
2553                 break;
2554         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2555                 PM8001_IO_DBG(pm8001_ha,
2556                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2557                 ts->resp = SAS_TASK_COMPLETE;
2558                 ts->stat = SAS_OPEN_TO;
2559                 break;
2560         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2561                 PM8001_IO_DBG(pm8001_ha,
2562                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2563                 ts->resp = SAS_TASK_COMPLETE;
2564                 ts->stat = SAS_OPEN_TO;
2565                 break;
2566         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2567                 PM8001_IO_DBG(pm8001_ha,
2568                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2569                 ts->resp = SAS_TASK_COMPLETE;
2570                 ts->stat = SAS_OPEN_TO;
2571                 break;
2572         case IO_XFER_ERROR_OFFSET_MISMATCH:
2573                 PM8001_IO_DBG(pm8001_ha,
2574                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2575                 ts->resp = SAS_TASK_COMPLETE;
2576                 ts->stat = SAS_OPEN_TO;
2577                 break;
2578         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2579                 PM8001_IO_DBG(pm8001_ha,
2580                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2581                 ts->resp = SAS_TASK_COMPLETE;
2582                 ts->stat = SAS_OPEN_TO;
2583                 break;
2584         case IO_XFER_CMD_FRAME_ISSUED:
2585                 PM8001_IO_DBG(pm8001_ha,
2586                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2587                 break;
2588         case IO_XFER_PIO_SETUP_ERROR:
2589                 PM8001_IO_DBG(pm8001_ha,
2590                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2591                 ts->resp = SAS_TASK_COMPLETE;
2592                 ts->stat = SAS_OPEN_TO;
2593                 break;
2594         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2595                 PM8001_FAIL_DBG(pm8001_ha,
2596                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2597                 /* TBC: used default set values */
2598                 ts->resp = SAS_TASK_COMPLETE;
2599                 ts->stat = SAS_OPEN_TO;
2600                 break;
2601         case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2602                 PM8001_FAIL_DBG(pm8001_ha,
2603                         pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2604                 /* TBC: used default set values */
2605                 ts->resp = SAS_TASK_COMPLETE;
2606                 ts->stat = SAS_OPEN_TO;
2607                 break;
2608         default:
2609                 PM8001_IO_DBG(pm8001_ha,
2610                         pm8001_printk("Unknown status 0x%x\n", event));
2611                 /* not allowed case. Therefore, return failed status */
2612                 ts->resp = SAS_TASK_COMPLETE;
2613                 ts->stat = SAS_OPEN_TO;
2614                 break;
2615         }
2616         spin_lock_irqsave(&t->task_state_lock, flags);
2617         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2618         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2619         t->task_state_flags |= SAS_TASK_STATE_DONE;
2620         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2621                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2622                 PM8001_FAIL_DBG(pm8001_ha,
2623                         pm8001_printk("task 0x%p done with io_status 0x%x"
2624                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2625                         t, event, ts->resp, ts->stat));
2626                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2627         } else {
2628                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2629                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2630         }
2631 }
2632
2633 /*See the comments for mpi_ssp_completion */
2634 static void
2635 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2636 {
2637         u32 param, i;
2638         struct sas_task *t;
2639         struct pm8001_ccb_info *ccb;
2640         unsigned long flags;
2641         u32 status;
2642         u32 tag;
2643         struct smp_completion_resp *psmpPayload;
2644         struct task_status_struct *ts;
2645         struct pm8001_device *pm8001_dev;
2646         char *pdma_respaddr = NULL;
2647
2648         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2649         status = le32_to_cpu(psmpPayload->status);
2650         tag = le32_to_cpu(psmpPayload->tag);
2651
2652         ccb = &pm8001_ha->ccb_info[tag];
2653         param = le32_to_cpu(psmpPayload->param);
2654         t = ccb->task;
2655         ts = &t->task_status;
2656         pm8001_dev = ccb->device;
2657         if (status)
2658                 PM8001_FAIL_DBG(pm8001_ha,
2659                         pm8001_printk("smp IO status 0x%x\n", status));
2660         if (unlikely(!t || !t->lldd_task || !t->dev))
2661                 return;
2662
2663         switch (status) {
2664
2665         case IO_SUCCESS:
2666                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2667                 ts->resp = SAS_TASK_COMPLETE;
2668                 ts->stat = SAM_STAT_GOOD;
2669                 if (pm8001_dev)
2670                         pm8001_dev->running_req--;
2671                 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2672                         PM8001_IO_DBG(pm8001_ha,
2673                                 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2674                                                 param));
2675                         pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2676                                                 ((u64)sg_dma_address
2677                                                 (&t->smp_task.smp_resp))));
2678                         for (i = 0; i < param; i++) {
2679                                 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2680                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2681                                         "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2682                                         i, *(pdma_respaddr+i),
2683                                         psmpPayload->_r_a[i]));
2684                         }
2685                 }
2686                 break;
2687         case IO_ABORTED:
2688                 PM8001_IO_DBG(pm8001_ha,
2689                         pm8001_printk("IO_ABORTED IOMB\n"));
2690                 ts->resp = SAS_TASK_COMPLETE;
2691                 ts->stat = SAS_ABORTED_TASK;
2692                 if (pm8001_dev)
2693                         pm8001_dev->running_req--;
2694                 break;
2695         case IO_OVERFLOW:
2696                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2697                 ts->resp = SAS_TASK_COMPLETE;
2698                 ts->stat = SAS_DATA_OVERRUN;
2699                 ts->residual = 0;
2700                 if (pm8001_dev)
2701                         pm8001_dev->running_req--;
2702                 break;
2703         case IO_NO_DEVICE:
2704                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2705                 ts->resp = SAS_TASK_COMPLETE;
2706                 ts->stat = SAS_PHY_DOWN;
2707                 break;
2708         case IO_ERROR_HW_TIMEOUT:
2709                 PM8001_IO_DBG(pm8001_ha,
2710                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2711                 ts->resp = SAS_TASK_COMPLETE;
2712                 ts->stat = SAM_STAT_BUSY;
2713                 break;
2714         case IO_XFER_ERROR_BREAK:
2715                 PM8001_IO_DBG(pm8001_ha,
2716                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2717                 ts->resp = SAS_TASK_COMPLETE;
2718                 ts->stat = SAM_STAT_BUSY;
2719                 break;
2720         case IO_XFER_ERROR_PHY_NOT_READY:
2721                 PM8001_IO_DBG(pm8001_ha,
2722                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2723                 ts->resp = SAS_TASK_COMPLETE;
2724                 ts->stat = SAM_STAT_BUSY;
2725                 break;
2726         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2727                 PM8001_IO_DBG(pm8001_ha,
2728                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2729                 ts->resp = SAS_TASK_COMPLETE;
2730                 ts->stat = SAS_OPEN_REJECT;
2731                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2732                 break;
2733         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2734                 PM8001_IO_DBG(pm8001_ha,
2735                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2736                 ts->resp = SAS_TASK_COMPLETE;
2737                 ts->stat = SAS_OPEN_REJECT;
2738                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2739                 break;
2740         case IO_OPEN_CNX_ERROR_BREAK:
2741                 PM8001_IO_DBG(pm8001_ha,
2742                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2743                 ts->resp = SAS_TASK_COMPLETE;
2744                 ts->stat = SAS_OPEN_REJECT;
2745                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2746                 break;
2747         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2748         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2749         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2750         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2751         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2752         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2753                 PM8001_IO_DBG(pm8001_ha,
2754                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2755                 ts->resp = SAS_TASK_COMPLETE;
2756                 ts->stat = SAS_OPEN_REJECT;
2757                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2758                 pm8001_handle_event(pm8001_ha,
2759                                 pm8001_dev,
2760                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2761                 break;
2762         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2763                 PM8001_IO_DBG(pm8001_ha,
2764                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2765                 ts->resp = SAS_TASK_COMPLETE;
2766                 ts->stat = SAS_OPEN_REJECT;
2767                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2768                 break;
2769         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2770                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2771                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2772                 ts->resp = SAS_TASK_COMPLETE;
2773                 ts->stat = SAS_OPEN_REJECT;
2774                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2775                 break;
2776         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2777                 PM8001_IO_DBG(pm8001_ha,
2778                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2779                 ts->resp = SAS_TASK_COMPLETE;
2780                 ts->stat = SAS_OPEN_REJECT;
2781                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2782                 break;
2783         case IO_XFER_ERROR_RX_FRAME:
2784                 PM8001_IO_DBG(pm8001_ha,
2785                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2786                 ts->resp = SAS_TASK_COMPLETE;
2787                 ts->stat = SAS_DEV_NO_RESPONSE;
2788                 break;
2789         case IO_XFER_OPEN_RETRY_TIMEOUT:
2790                 PM8001_IO_DBG(pm8001_ha,
2791                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2792                 ts->resp = SAS_TASK_COMPLETE;
2793                 ts->stat = SAS_OPEN_REJECT;
2794                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2795                 break;
2796         case IO_ERROR_INTERNAL_SMP_RESOURCE:
2797                 PM8001_IO_DBG(pm8001_ha,
2798                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2799                 ts->resp = SAS_TASK_COMPLETE;
2800                 ts->stat = SAS_QUEUE_FULL;
2801                 break;
2802         case IO_PORT_IN_RESET:
2803                 PM8001_IO_DBG(pm8001_ha,
2804                         pm8001_printk("IO_PORT_IN_RESET\n"));
2805                 ts->resp = SAS_TASK_COMPLETE;
2806                 ts->stat = SAS_OPEN_REJECT;
2807                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2808                 break;
2809         case IO_DS_NON_OPERATIONAL:
2810                 PM8001_IO_DBG(pm8001_ha,
2811                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2812                 ts->resp = SAS_TASK_COMPLETE;
2813                 ts->stat = SAS_DEV_NO_RESPONSE;
2814                 break;
2815         case IO_DS_IN_RECOVERY:
2816                 PM8001_IO_DBG(pm8001_ha,
2817                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2818                 ts->resp = SAS_TASK_COMPLETE;
2819                 ts->stat = SAS_OPEN_REJECT;
2820                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2821                 break;
2822         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2823                 PM8001_IO_DBG(pm8001_ha,
2824                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2825                 ts->resp = SAS_TASK_COMPLETE;
2826                 ts->stat = SAS_OPEN_REJECT;
2827                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2828                 break;
2829         default:
2830                 PM8001_IO_DBG(pm8001_ha,
2831                         pm8001_printk("Unknown status 0x%x\n", status));
2832                 ts->resp = SAS_TASK_COMPLETE;
2833                 ts->stat = SAS_DEV_NO_RESPONSE;
2834                 /* not allowed case. Therefore, return failed status */
2835                 break;
2836         }
2837         spin_lock_irqsave(&t->task_state_lock, flags);
2838         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2839         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2840         t->task_state_flags |= SAS_TASK_STATE_DONE;
2841         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2842                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2843                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2844                         "task 0x%p done with io_status 0x%x resp 0x%x"
2845                         "stat 0x%x but aborted by upper layer!\n",
2846                         t, status, ts->resp, ts->stat));
2847                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2848         } else {
2849                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2850                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2851                 mb();/* in order to force CPU ordering */
2852                 t->task_done(t);
2853         }
2854 }
2855
2856 /**
2857  * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2858  * @pm8001_ha: our hba card information
2859  * @Qnum: the outbound queue message number.
2860  * @SEA: source of event to ack
2861  * @port_id: port id.
2862  * @phyId: phy id.
2863  * @param0: parameter 0.
2864  * @param1: parameter 1.
2865  */
2866 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2867         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2868 {
2869         struct hw_event_ack_req  payload;
2870         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2871
2872         struct inbound_queue_table *circularQ;
2873
2874         memset((u8 *)&payload, 0, sizeof(payload));
2875         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2876         payload.tag = cpu_to_le32(1);
2877         payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2878                 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2879         payload.param0 = cpu_to_le32(param0);
2880         payload.param1 = cpu_to_le32(param1);
2881         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2882 }
2883
2884 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2885         u32 phyId, u32 phy_op);
2886
2887 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
2888                                         void *piomb)
2889 {
2890         struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
2891         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2892         u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2893         u32 lr_status_evt_portid =
2894                 le32_to_cpu(pPayload->lr_status_evt_portid);
2895         u8 deviceType = pPayload->sas_identify.dev_type;
2896         u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2897         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2898         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2899         struct pm8001_port *port = &pm8001_ha->port[port_id];
2900
2901         if (deviceType == SAS_END_DEVICE) {
2902                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2903                                         PHY_NOTIFY_ENABLE_SPINUP);
2904         }
2905
2906         port->wide_port_phymap |= (1U << phy_id);
2907         pm8001_get_lrate_mode(phy, link_rate);
2908         phy->sas_phy.oob_mode = SAS_OOB_MODE;
2909         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2910         phy->phy_attached = 1;
2911 }
2912
2913 /**
2914  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2915  * @pm8001_ha: our hba card information
2916  * @piomb: IO message buffer
2917  */
2918 static void
2919 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2920 {
2921         struct hw_event_resp *pPayload =
2922                 (struct hw_event_resp *)(piomb + 4);
2923         u32 lr_status_evt_portid =
2924                 le32_to_cpu(pPayload->lr_status_evt_portid);
2925         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2926
2927         u8 link_rate =
2928                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2929         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2930         u8 phy_id =
2931                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2932         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2933
2934         struct pm8001_port *port = &pm8001_ha->port[port_id];
2935         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2936         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2937         unsigned long flags;
2938         u8 deviceType = pPayload->sas_identify.dev_type;
2939         port->port_state = portstate;
2940         port->wide_port_phymap |= (1U << phy_id);
2941         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2942         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2943                 "portid:%d; phyid:%d; linkrate:%d; "
2944                 "portstate:%x; devicetype:%x\n",
2945                 port_id, phy_id, link_rate, portstate, deviceType));
2946
2947         switch (deviceType) {
2948         case SAS_PHY_UNUSED:
2949                 PM8001_MSG_DBG(pm8001_ha,
2950                         pm8001_printk("device type no device.\n"));
2951                 break;
2952         case SAS_END_DEVICE:
2953                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2954                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2955                         PHY_NOTIFY_ENABLE_SPINUP);
2956                 port->port_attached = 1;
2957                 pm8001_get_lrate_mode(phy, link_rate);
2958                 break;
2959         case SAS_EDGE_EXPANDER_DEVICE:
2960                 PM8001_MSG_DBG(pm8001_ha,
2961                         pm8001_printk("expander device.\n"));
2962                 port->port_attached = 1;
2963                 pm8001_get_lrate_mode(phy, link_rate);
2964                 break;
2965         case SAS_FANOUT_EXPANDER_DEVICE:
2966                 PM8001_MSG_DBG(pm8001_ha,
2967                         pm8001_printk("fanout expander device.\n"));
2968                 port->port_attached = 1;
2969                 pm8001_get_lrate_mode(phy, link_rate);
2970                 break;
2971         default:
2972                 PM8001_MSG_DBG(pm8001_ha,
2973                         pm8001_printk("unknown device type(%x)\n", deviceType));
2974                 break;
2975         }
2976         phy->phy_type |= PORT_TYPE_SAS;
2977         phy->identify.device_type = deviceType;
2978         phy->phy_attached = 1;
2979         if (phy->identify.device_type == SAS_END_DEVICE)
2980                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2981         else if (phy->identify.device_type != SAS_PHY_UNUSED)
2982                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2983         phy->sas_phy.oob_mode = SAS_OOB_MODE;
2984         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2985         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2986         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2987                 sizeof(struct sas_identify_frame)-4);
2988         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2989         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2990         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2991         if (pm8001_ha->flags == PM8001F_RUN_TIME)
2992                 mdelay(200);/*delay a moment to wait disk to spinup*/
2993         pm8001_bytes_dmaed(pm8001_ha, phy_id);
2994 }
2995
2996 /**
2997  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2998  * @pm8001_ha: our hba card information
2999  * @piomb: IO message buffer
3000  */
3001 static void
3002 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3003 {
3004         struct hw_event_resp *pPayload =
3005                 (struct hw_event_resp *)(piomb + 4);
3006         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3007         u32 lr_status_evt_portid =
3008                 le32_to_cpu(pPayload->lr_status_evt_portid);
3009         u8 link_rate =
3010                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3011         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3012         u8 phy_id =
3013                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3014
3015         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3016
3017         struct pm8001_port *port = &pm8001_ha->port[port_id];
3018         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3019         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3020         unsigned long flags;
3021         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3022                 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3023                                 port_id, phy_id, link_rate, portstate));
3024
3025         port->port_state = portstate;
3026         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3027         port->port_attached = 1;
3028         pm8001_get_lrate_mode(phy, link_rate);
3029         phy->phy_type |= PORT_TYPE_SATA;
3030         phy->phy_attached = 1;
3031         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3032         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3033         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3034         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3035                 sizeof(struct dev_to_host_fis));
3036         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3037         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3038         phy->identify.device_type = SAS_SATA_DEV;
3039         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3040         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3041         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3042 }
3043
3044 /**
3045  * hw_event_phy_down -we should notify the libsas the phy is down.
3046  * @pm8001_ha: our hba card information
3047  * @piomb: IO message buffer
3048  */
3049 static void
3050 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3051 {
3052         struct hw_event_resp *pPayload =
3053                 (struct hw_event_resp *)(piomb + 4);
3054
3055         u32 lr_status_evt_portid =
3056                 le32_to_cpu(pPayload->lr_status_evt_portid);
3057         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3058         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3059         u8 phy_id =
3060                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3061         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3062
3063         struct pm8001_port *port = &pm8001_ha->port[port_id];
3064         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3065         u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3066         port->port_state = portstate;
3067         phy->identify.device_type = 0;
3068         phy->phy_attached = 0;
3069         switch (portstate) {
3070         case PORT_VALID:
3071                 break;
3072         case PORT_INVALID:
3073                 PM8001_MSG_DBG(pm8001_ha,
3074                         pm8001_printk(" PortInvalid portID %d\n", port_id));
3075                 PM8001_MSG_DBG(pm8001_ha,
3076                         pm8001_printk(" Last phy Down and port invalid\n"));
3077                 if (port_sata) {
3078                         phy->phy_type = 0;
3079                         port->port_attached = 0;
3080                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3081                                         port_id, phy_id, 0, 0);
3082                 }
3083                 sas_phy_disconnected(&phy->sas_phy);
3084                 break;
3085         case PORT_IN_RESET:
3086                 PM8001_MSG_DBG(pm8001_ha,
3087                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3088                 break;
3089         case PORT_NOT_ESTABLISHED:
3090                 PM8001_MSG_DBG(pm8001_ha,
3091                         pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n"));
3092                 port->port_attached = 0;
3093                 break;
3094         case PORT_LOSTCOMM:
3095                 PM8001_MSG_DBG(pm8001_ha,
3096                         pm8001_printk(" Phy Down and PORT_LOSTCOMM\n"));
3097                 PM8001_MSG_DBG(pm8001_ha,
3098                         pm8001_printk(" Last phy Down and port invalid\n"));
3099                 if (port_sata) {
3100                         port->port_attached = 0;
3101                         phy->phy_type = 0;
3102                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3103                                         port_id, phy_id, 0, 0);
3104                 }
3105                 sas_phy_disconnected(&phy->sas_phy);
3106                 break;
3107         default:
3108                 port->port_attached = 0;
3109                 PM8001_MSG_DBG(pm8001_ha,
3110                         pm8001_printk(" Phy Down and(default) = 0x%x\n",
3111                         portstate));
3112                 break;
3113
3114         }
3115         if (port_sata && (portstate != PORT_IN_RESET)) {
3116                 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3117
3118                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3119         }
3120 }
3121
3122 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3123 {
3124         struct phy_start_resp *pPayload =
3125                 (struct phy_start_resp *)(piomb + 4);
3126         u32 status =
3127                 le32_to_cpu(pPayload->status);
3128         u32 phy_id =
3129                 le32_to_cpu(pPayload->phyid);
3130         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3131
3132         PM8001_INIT_DBG(pm8001_ha,
3133                 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3134                                 status, phy_id));
3135         if (status == 0) {
3136                 phy->phy_state = 1;
3137                 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3138                         complete(phy->enable_completion);
3139         }
3140         return 0;
3141
3142 }
3143
3144 /**
3145  * mpi_thermal_hw_event -The hw event has come.
3146  * @pm8001_ha: our hba card information
3147  * @piomb: IO message buffer
3148  */
3149 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3150 {
3151         struct thermal_hw_event *pPayload =
3152                 (struct thermal_hw_event *)(piomb + 4);
3153
3154         u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3155         u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3156
3157         if (thermal_event & 0x40) {
3158                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3159                         "Thermal Event: Local high temperature violated!\n"));
3160                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3161                         "Thermal Event: Measured local high temperature %d\n",
3162                                 ((rht_lht & 0xFF00) >> 8)));
3163         }
3164         if (thermal_event & 0x10) {
3165                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3166                         "Thermal Event: Remote high temperature violated!\n"));
3167                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3168                         "Thermal Event: Measured remote high temperature %d\n",
3169                                 ((rht_lht & 0xFF000000) >> 24)));
3170         }
3171         return 0;
3172 }
3173
3174 /**
3175  * mpi_hw_event -The hw event has come.
3176  * @pm8001_ha: our hba card information
3177  * @piomb: IO message buffer
3178  */
3179 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3180 {
3181         unsigned long flags, i;
3182         struct hw_event_resp *pPayload =
3183                 (struct hw_event_resp *)(piomb + 4);
3184         u32 lr_status_evt_portid =
3185                 le32_to_cpu(pPayload->lr_status_evt_portid);
3186         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3187         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3188         u8 phy_id =
3189                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3190         u16 eventType =
3191                 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3192         u8 status =
3193                 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3194         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3195         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3196         struct pm8001_port *port = &pm8001_ha->port[port_id];
3197         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3198         PM8001_MSG_DBG(pm8001_ha,
3199                 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3200                                 port_id, phy_id, eventType, status));
3201
3202         switch (eventType) {
3203
3204         case HW_EVENT_SAS_PHY_UP:
3205                 PM8001_MSG_DBG(pm8001_ha,
3206                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3207                 hw_event_sas_phy_up(pm8001_ha, piomb);
3208                 break;
3209         case HW_EVENT_SATA_PHY_UP:
3210                 PM8001_MSG_DBG(pm8001_ha,
3211                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3212                 hw_event_sata_phy_up(pm8001_ha, piomb);
3213                 break;
3214         case HW_EVENT_SATA_SPINUP_HOLD:
3215                 PM8001_MSG_DBG(pm8001_ha,
3216                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3217                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3218                 break;
3219         case HW_EVENT_PHY_DOWN:
3220                 PM8001_MSG_DBG(pm8001_ha,
3221                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3222                 hw_event_phy_down(pm8001_ha, piomb);
3223                 if (pm8001_ha->reset_in_progress) {
3224                         PM8001_MSG_DBG(pm8001_ha,
3225                                 pm8001_printk("Reset in progress\n"));
3226                         return 0;
3227                 }
3228                 phy->phy_attached = 0;
3229                 phy->phy_state = 0;
3230                 break;
3231         case HW_EVENT_PORT_INVALID:
3232                 PM8001_MSG_DBG(pm8001_ha,
3233                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3234                 sas_phy_disconnected(sas_phy);
3235                 phy->phy_attached = 0;
3236                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3237                 break;
3238         /* the broadcast change primitive received, tell the LIBSAS this event
3239         to revalidate the sas domain*/
3240         case HW_EVENT_BROADCAST_CHANGE:
3241                 PM8001_MSG_DBG(pm8001_ha,
3242                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3243                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3244                         port_id, phy_id, 1, 0);
3245                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3246                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3247                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3248                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3249                 break;
3250         case HW_EVENT_PHY_ERROR:
3251                 PM8001_MSG_DBG(pm8001_ha,
3252                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3253                 sas_phy_disconnected(&phy->sas_phy);
3254                 phy->phy_attached = 0;
3255                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3256                 break;
3257         case HW_EVENT_BROADCAST_EXP:
3258                 PM8001_MSG_DBG(pm8001_ha,
3259                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3260                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3261                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3262                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3263                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3264                 break;
3265         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3266                 PM8001_MSG_DBG(pm8001_ha,
3267                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3268                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3269                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3270                 break;
3271         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3272                 PM8001_MSG_DBG(pm8001_ha,
3273                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3274                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3275                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3276                         port_id, phy_id, 0, 0);
3277                 break;
3278         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3279                 PM8001_MSG_DBG(pm8001_ha,
3280                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3281                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3282                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3283                         port_id, phy_id, 0, 0);
3284                 break;
3285         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3286                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3287                                 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3288                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3289                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3290                         port_id, phy_id, 0, 0);
3291                 break;
3292         case HW_EVENT_MALFUNCTION:
3293                 PM8001_MSG_DBG(pm8001_ha,
3294                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3295                 break;
3296         case HW_EVENT_BROADCAST_SES:
3297                 PM8001_MSG_DBG(pm8001_ha,
3298                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3299                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3300                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3301                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3302                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3303                 break;
3304         case HW_EVENT_INBOUND_CRC_ERROR:
3305                 PM8001_MSG_DBG(pm8001_ha,
3306                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3307                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3308                         HW_EVENT_INBOUND_CRC_ERROR,
3309                         port_id, phy_id, 0, 0);
3310                 break;
3311         case HW_EVENT_HARD_RESET_RECEIVED:
3312                 PM8001_MSG_DBG(pm8001_ha,
3313                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3314                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3315                 break;
3316         case HW_EVENT_ID_FRAME_TIMEOUT:
3317                 PM8001_MSG_DBG(pm8001_ha,
3318                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3319                 sas_phy_disconnected(sas_phy);
3320                 phy->phy_attached = 0;
3321                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3322                 break;
3323         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3324                 PM8001_MSG_DBG(pm8001_ha,
3325                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3326                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3327                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3328                         port_id, phy_id, 0, 0);
3329                 sas_phy_disconnected(sas_phy);
3330                 phy->phy_attached = 0;
3331                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3332                 break;
3333         case HW_EVENT_PORT_RESET_TIMER_TMO:
3334                 PM8001_MSG_DBG(pm8001_ha,
3335                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3336                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3337                         port_id, phy_id, 0, 0);
3338                 sas_phy_disconnected(sas_phy);
3339                 phy->phy_attached = 0;
3340                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3341                 if (pm8001_ha->phy[phy_id].reset_completion) {
3342                         pm8001_ha->phy[phy_id].port_reset_status =
3343                                         PORT_RESET_TMO;
3344                         complete(pm8001_ha->phy[phy_id].reset_completion);
3345                         pm8001_ha->phy[phy_id].reset_completion = NULL;
3346                 }
3347                 break;
3348         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3349                 PM8001_MSG_DBG(pm8001_ha,
3350                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3351                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3352                         HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3353                         port_id, phy_id, 0, 0);
3354                 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3355                         if (port->wide_port_phymap & (1 << i)) {
3356                                 phy = &pm8001_ha->phy[i];
3357                                 sas_ha->notify_phy_event(&phy->sas_phy,
3358                                                 PHYE_LOSS_OF_SIGNAL);
3359                                 port->wide_port_phymap &= ~(1 << i);
3360                         }
3361                 }
3362                 break;
3363         case HW_EVENT_PORT_RECOVER:
3364                 PM8001_MSG_DBG(pm8001_ha,
3365                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3366                 hw_event_port_recover(pm8001_ha, piomb);
3367                 break;
3368         case HW_EVENT_PORT_RESET_COMPLETE:
3369                 PM8001_MSG_DBG(pm8001_ha,
3370                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3371                 if (pm8001_ha->phy[phy_id].reset_completion) {
3372                         pm8001_ha->phy[phy_id].port_reset_status =
3373                                         PORT_RESET_SUCCESS;
3374                         complete(pm8001_ha->phy[phy_id].reset_completion);
3375                         pm8001_ha->phy[phy_id].reset_completion = NULL;
3376                 }
3377                 break;
3378         case EVENT_BROADCAST_ASYNCH_EVENT:
3379                 PM8001_MSG_DBG(pm8001_ha,
3380                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3381                 break;
3382         default:
3383                 PM8001_MSG_DBG(pm8001_ha,
3384                         pm8001_printk("Unknown event type 0x%x\n", eventType));
3385                 break;
3386         }
3387         return 0;
3388 }
3389
3390 /**
3391  * mpi_phy_stop_resp - SPCv specific
3392  * @pm8001_ha: our hba card information
3393  * @piomb: IO message buffer
3394  */
3395 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3396 {
3397         struct phy_stop_resp *pPayload =
3398                 (struct phy_stop_resp *)(piomb + 4);
3399         u32 status =
3400                 le32_to_cpu(pPayload->status);
3401         u32 phyid =
3402                 le32_to_cpu(pPayload->phyid);
3403         struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3404         PM8001_MSG_DBG(pm8001_ha,
3405                         pm8001_printk("phy:0x%x status:0x%x\n",
3406                                         phyid, status));
3407         if (status == 0)
3408                 phy->phy_state = 0;
3409         return 0;
3410 }
3411
3412 /**
3413  * mpi_set_controller_config_resp - SPCv specific
3414  * @pm8001_ha: our hba card information
3415  * @piomb: IO message buffer
3416  */
3417 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3418                         void *piomb)
3419 {
3420         struct set_ctrl_cfg_resp *pPayload =
3421                         (struct set_ctrl_cfg_resp *)(piomb + 4);
3422         u32 status = le32_to_cpu(pPayload->status);
3423         u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3424
3425         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3426                         "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3427                         status, err_qlfr_pgcd));
3428
3429         return 0;
3430 }
3431
3432 /**
3433  * mpi_get_controller_config_resp - SPCv specific
3434  * @pm8001_ha: our hba card information
3435  * @piomb: IO message buffer
3436  */
3437 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3438                         void *piomb)
3439 {
3440         PM8001_MSG_DBG(pm8001_ha,
3441                         pm8001_printk(" pm80xx_addition_functionality\n"));
3442
3443         return 0;
3444 }
3445
3446 /**
3447  * mpi_get_phy_profile_resp - SPCv specific
3448  * @pm8001_ha: our hba card information
3449  * @piomb: IO message buffer
3450  */
3451 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3452                         void *piomb)
3453 {
3454         PM8001_MSG_DBG(pm8001_ha,
3455                         pm8001_printk(" pm80xx_addition_functionality\n"));
3456
3457         return 0;
3458 }
3459
3460 /**
3461  * mpi_flash_op_ext_resp - SPCv specific
3462  * @pm8001_ha: our hba card information
3463  * @piomb: IO message buffer
3464  */
3465 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3466 {
3467         PM8001_MSG_DBG(pm8001_ha,
3468                         pm8001_printk(" pm80xx_addition_functionality\n"));
3469
3470         return 0;
3471 }
3472
3473 /**
3474  * mpi_set_phy_profile_resp - SPCv specific
3475  * @pm8001_ha: our hba card information
3476  * @piomb: IO message buffer
3477  */
3478 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3479                         void *piomb)
3480 {
3481         u8 page_code;
3482         struct set_phy_profile_resp *pPayload =
3483                 (struct set_phy_profile_resp *)(piomb + 4);
3484         u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3485         u32 status = le32_to_cpu(pPayload->status);
3486
3487         page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3488         if (status) {
3489                 /* status is FAILED */
3490                 PM8001_FAIL_DBG(pm8001_ha,
3491                         pm8001_printk("PhyProfile command failed  with status "
3492                         "0x%08X \n", status));
3493                 return -1;
3494         } else {
3495                 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3496                         PM8001_FAIL_DBG(pm8001_ha,
3497                                 pm8001_printk("Invalid page code 0x%X\n",
3498                                         page_code));
3499                         return -1;
3500                 }
3501         }
3502         return 0;
3503 }
3504
3505 /**
3506  * mpi_kek_management_resp - SPCv specific
3507  * @pm8001_ha: our hba card information
3508  * @piomb: IO message buffer
3509  */
3510 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3511                         void *piomb)
3512 {
3513         struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3514
3515         u32 status = le32_to_cpu(pPayload->status);
3516         u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3517         u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3518
3519         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3520                 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3521                 status, kidx_new_curr_ksop, err_qlfr));
3522
3523         return 0;
3524 }
3525
3526 /**
3527  * mpi_dek_management_resp - SPCv specific
3528  * @pm8001_ha: our hba card information
3529  * @piomb: IO message buffer
3530  */
3531 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3532                         void *piomb)
3533 {
3534         PM8001_MSG_DBG(pm8001_ha,
3535                         pm8001_printk(" pm80xx_addition_functionality\n"));
3536
3537         return 0;
3538 }
3539
3540 /**
3541  * ssp_coalesced_comp_resp - SPCv specific
3542  * @pm8001_ha: our hba card information
3543  * @piomb: IO message buffer
3544  */
3545 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3546                         void *piomb)
3547 {
3548         PM8001_MSG_DBG(pm8001_ha,
3549                         pm8001_printk(" pm80xx_addition_functionality\n"));
3550
3551         return 0;
3552 }
3553
3554 /**
3555  * process_one_iomb - process one outbound Queue memory block
3556  * @pm8001_ha: our hba card information
3557  * @piomb: IO message buffer
3558  */
3559 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3560 {
3561         __le32 pHeader = *(__le32 *)piomb;
3562         u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3563
3564         switch (opc) {
3565         case OPC_OUB_ECHO:
3566                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3567                 break;
3568         case OPC_OUB_HW_EVENT:
3569                 PM8001_MSG_DBG(pm8001_ha,
3570                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
3571                 mpi_hw_event(pm8001_ha, piomb);
3572                 break;
3573         case OPC_OUB_THERM_HW_EVENT:
3574                 PM8001_MSG_DBG(pm8001_ha,
3575                         pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3576                 mpi_thermal_hw_event(pm8001_ha, piomb);
3577                 break;
3578         case OPC_OUB_SSP_COMP:
3579                 PM8001_MSG_DBG(pm8001_ha,
3580                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
3581                 mpi_ssp_completion(pm8001_ha, piomb);
3582                 break;
3583         case OPC_OUB_SMP_COMP:
3584                 PM8001_MSG_DBG(pm8001_ha,
3585                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
3586                 mpi_smp_completion(pm8001_ha, piomb);
3587                 break;
3588         case OPC_OUB_LOCAL_PHY_CNTRL:
3589                 PM8001_MSG_DBG(pm8001_ha,
3590                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3591                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3592                 break;
3593         case OPC_OUB_DEV_REGIST:
3594                 PM8001_MSG_DBG(pm8001_ha,
3595                 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3596                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3597                 break;
3598         case OPC_OUB_DEREG_DEV:
3599                 PM8001_MSG_DBG(pm8001_ha,
3600                         pm8001_printk("unregister the device\n"));
3601                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3602                 break;
3603         case OPC_OUB_GET_DEV_HANDLE:
3604                 PM8001_MSG_DBG(pm8001_ha,
3605                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3606                 break;
3607         case OPC_OUB_SATA_COMP:
3608                 PM8001_MSG_DBG(pm8001_ha,
3609                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
3610                 mpi_sata_completion(pm8001_ha, piomb);
3611                 break;
3612         case OPC_OUB_SATA_EVENT:
3613                 PM8001_MSG_DBG(pm8001_ha,
3614                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3615                 mpi_sata_event(pm8001_ha, piomb);
3616                 break;
3617         case OPC_OUB_SSP_EVENT:
3618                 PM8001_MSG_DBG(pm8001_ha,
3619                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3620                 mpi_ssp_event(pm8001_ha, piomb);
3621                 break;
3622         case OPC_OUB_DEV_HANDLE_ARRIV:
3623                 PM8001_MSG_DBG(pm8001_ha,
3624                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3625                 /*This is for target*/
3626                 break;
3627         case OPC_OUB_SSP_RECV_EVENT:
3628                 PM8001_MSG_DBG(pm8001_ha,
3629                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3630                 /*This is for target*/
3631                 break;
3632         case OPC_OUB_FW_FLASH_UPDATE:
3633                 PM8001_MSG_DBG(pm8001_ha,
3634                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3635                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3636                 break;
3637         case OPC_OUB_GPIO_RESPONSE:
3638                 PM8001_MSG_DBG(pm8001_ha,
3639                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3640                 break;
3641         case OPC_OUB_GPIO_EVENT:
3642                 PM8001_MSG_DBG(pm8001_ha,
3643                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3644                 break;
3645         case OPC_OUB_GENERAL_EVENT:
3646                 PM8001_MSG_DBG(pm8001_ha,
3647                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3648                 pm8001_mpi_general_event(pm8001_ha, piomb);
3649                 break;
3650         case OPC_OUB_SSP_ABORT_RSP:
3651                 PM8001_MSG_DBG(pm8001_ha,
3652                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3653                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3654                 break;
3655         case OPC_OUB_SATA_ABORT_RSP:
3656                 PM8001_MSG_DBG(pm8001_ha,
3657                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3658                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3659                 break;
3660         case OPC_OUB_SAS_DIAG_MODE_START_END:
3661                 PM8001_MSG_DBG(pm8001_ha,
3662                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3663                 break;
3664         case OPC_OUB_SAS_DIAG_EXECUTE:
3665                 PM8001_MSG_DBG(pm8001_ha,
3666                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3667                 break;
3668         case OPC_OUB_GET_TIME_STAMP:
3669                 PM8001_MSG_DBG(pm8001_ha,
3670                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3671                 break;
3672         case OPC_OUB_SAS_HW_EVENT_ACK:
3673                 PM8001_MSG_DBG(pm8001_ha,
3674                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3675                 break;
3676         case OPC_OUB_PORT_CONTROL:
3677                 PM8001_MSG_DBG(pm8001_ha,
3678                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3679                 break;
3680         case OPC_OUB_SMP_ABORT_RSP:
3681                 PM8001_MSG_DBG(pm8001_ha,
3682                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3683                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3684                 break;
3685         case OPC_OUB_GET_NVMD_DATA:
3686                 PM8001_MSG_DBG(pm8001_ha,
3687                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3688                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3689                 break;
3690         case OPC_OUB_SET_NVMD_DATA:
3691                 PM8001_MSG_DBG(pm8001_ha,
3692                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3693                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3694                 break;
3695         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3696                 PM8001_MSG_DBG(pm8001_ha,
3697                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3698                 break;
3699         case OPC_OUB_SET_DEVICE_STATE:
3700                 PM8001_MSG_DBG(pm8001_ha,
3701                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3702                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3703                 break;
3704         case OPC_OUB_GET_DEVICE_STATE:
3705                 PM8001_MSG_DBG(pm8001_ha,
3706                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3707                 break;
3708         case OPC_OUB_SET_DEV_INFO:
3709                 PM8001_MSG_DBG(pm8001_ha,
3710                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3711                 break;
3712         /* spcv specifc commands */
3713         case OPC_OUB_PHY_START_RESP:
3714                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3715                         "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3716                 mpi_phy_start_resp(pm8001_ha, piomb);
3717                 break;
3718         case OPC_OUB_PHY_STOP_RESP:
3719                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3720                         "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3721                 mpi_phy_stop_resp(pm8001_ha, piomb);
3722                 break;
3723         case OPC_OUB_SET_CONTROLLER_CONFIG:
3724                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3725                         "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3726                 mpi_set_controller_config_resp(pm8001_ha, piomb);
3727                 break;
3728         case OPC_OUB_GET_CONTROLLER_CONFIG:
3729                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3730                         "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3731                 mpi_get_controller_config_resp(pm8001_ha, piomb);
3732                 break;
3733         case OPC_OUB_GET_PHY_PROFILE:
3734                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3735                         "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3736                 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3737                 break;
3738         case OPC_OUB_FLASH_OP_EXT:
3739                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3740                         "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3741                 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3742                 break;
3743         case OPC_OUB_SET_PHY_PROFILE:
3744                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3745                         "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3746                 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3747                 break;
3748         case OPC_OUB_KEK_MANAGEMENT_RESP:
3749                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3750                         "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3751                 mpi_kek_management_resp(pm8001_ha, piomb);
3752                 break;
3753         case OPC_OUB_DEK_MANAGEMENT_RESP:
3754                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3755                         "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3756                 mpi_dek_management_resp(pm8001_ha, piomb);
3757                 break;
3758         case OPC_OUB_SSP_COALESCED_COMP_RESP:
3759                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3760                         "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3761                 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3762                 break;
3763         default:
3764                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3765                         "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3766                 break;
3767         }
3768 }
3769
3770 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
3771 {
3772         PM8001_FAIL_DBG(pm8001_ha,
3773                 pm8001_printk("MSGU_SCRATCH_PAD_0: 0x%x\n",
3774                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
3775         PM8001_FAIL_DBG(pm8001_ha,
3776                 pm8001_printk("MSGU_SCRATCH_PAD_1:0x%x\n",
3777                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)));
3778         PM8001_FAIL_DBG(pm8001_ha,
3779                 pm8001_printk("MSGU_SCRATCH_PAD_2: 0x%x\n",
3780                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)));
3781         PM8001_FAIL_DBG(pm8001_ha,
3782                 pm8001_printk("MSGU_SCRATCH_PAD_3: 0x%x\n",
3783                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
3784         PM8001_FAIL_DBG(pm8001_ha,
3785                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
3786                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)));
3787         PM8001_FAIL_DBG(pm8001_ha,
3788                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
3789                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)));
3790         PM8001_FAIL_DBG(pm8001_ha,
3791                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
3792                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)));
3793         PM8001_FAIL_DBG(pm8001_ha,
3794                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
3795                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)));
3796         PM8001_FAIL_DBG(pm8001_ha,
3797                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
3798                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)));
3799         PM8001_FAIL_DBG(pm8001_ha,
3800                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
3801                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)));
3802         PM8001_FAIL_DBG(pm8001_ha,
3803                 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
3804                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)));
3805         PM8001_FAIL_DBG(pm8001_ha,
3806                 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
3807                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)));
3808 }
3809
3810 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3811 {
3812         struct outbound_queue_table *circularQ;
3813         void *pMsg1 = NULL;
3814         u8 uninitialized_var(bc);
3815         u32 ret = MPI_IO_STATUS_FAIL;
3816         unsigned long flags;
3817         u32 regval;
3818
3819         if (vec == (pm8001_ha->number_of_intr - 1)) {
3820                 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
3821                 if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
3822                                         SCRATCH_PAD_MIPSALL_READY) {
3823                         pm8001_ha->controller_fatal_error = true;
3824                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
3825                                 "Firmware Fatal error! Regval:0x%x\n", regval));
3826                         print_scratchpad_registers(pm8001_ha);
3827                         return ret;
3828                 }
3829         }
3830         spin_lock_irqsave(&pm8001_ha->lock, flags);
3831         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3832         do {
3833                 /* spurious interrupt during setup if kexec-ing and
3834                  * driver doing a doorbell access w/ the pre-kexec oq
3835                  * interrupt setup.
3836                  */
3837                 if (!circularQ->pi_virt)
3838                         break;
3839                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3840                 if (MPI_IO_STATUS_SUCCESS == ret) {
3841                         /* process the outbound message */
3842                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3843                         /* free the message from the outbound circular buffer */
3844                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3845                                                         circularQ, bc);
3846                 }
3847                 if (MPI_IO_STATUS_BUSY == ret) {
3848                         /* Update the producer index from SPC */
3849                         circularQ->producer_index =
3850                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3851                         if (le32_to_cpu(circularQ->producer_index) ==
3852                                 circularQ->consumer_idx)
3853                                 /* OQ is empty */
3854                                 break;
3855                 }
3856         } while (1);
3857         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3858         return ret;
3859 }
3860
3861 /* PCI_DMA_... to our direction translation. */
3862 static const u8 data_dir_flags[] = {
3863         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3864         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
3865         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
3866         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
3867 };
3868
3869 static void build_smp_cmd(u32 deviceID, __le32 hTag,
3870                         struct smp_req *psmp_cmd, int mode, int length)
3871 {
3872         psmp_cmd->tag = hTag;
3873         psmp_cmd->device_id = cpu_to_le32(deviceID);
3874         if (mode == SMP_DIRECT) {
3875                 length = length - 4; /* subtract crc */
3876                 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3877         } else {
3878                 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3879         }
3880 }
3881
3882 /**
3883  * pm8001_chip_smp_req - send a SMP task to FW
3884  * @pm8001_ha: our hba card information.
3885  * @ccb: the ccb information this request used.
3886  */
3887 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3888         struct pm8001_ccb_info *ccb)
3889 {
3890         int elem, rc;
3891         struct sas_task *task = ccb->task;
3892         struct domain_device *dev = task->dev;
3893         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3894         struct scatterlist *sg_req, *sg_resp;
3895         u32 req_len, resp_len;
3896         struct smp_req smp_cmd;
3897         u32 opc;
3898         struct inbound_queue_table *circularQ;
3899         char *preq_dma_addr = NULL;
3900         __le64 tmp_addr;
3901         u32 i, length;
3902
3903         memset(&smp_cmd, 0, sizeof(smp_cmd));
3904         /*
3905          * DMA-map SMP request, response buffers
3906          */
3907         sg_req = &task->smp_task.smp_req;
3908         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3909         if (!elem)
3910                 return -ENOMEM;
3911         req_len = sg_dma_len(sg_req);
3912
3913         sg_resp = &task->smp_task.smp_resp;
3914         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3915         if (!elem) {
3916                 rc = -ENOMEM;
3917                 goto err_out;
3918         }
3919         resp_len = sg_dma_len(sg_resp);
3920         /* must be in dwords */
3921         if ((req_len & 0x3) || (resp_len & 0x3)) {
3922                 rc = -EINVAL;
3923                 goto err_out_2;
3924         }
3925
3926         opc = OPC_INB_SMP_REQUEST;
3927         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3928         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3929
3930         length = sg_req->length;
3931         PM8001_IO_DBG(pm8001_ha,
3932                 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3933         if (!(length - 8))
3934                 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3935         else
3936                 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3937
3938
3939         tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3940         preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3941
3942         /* INDIRECT MODE command settings. Use DMA */
3943         if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3944                 PM8001_IO_DBG(pm8001_ha,
3945                         pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3946                 /* for SPCv indirect mode. Place the top 4 bytes of
3947                  * SMP Request header here. */
3948                 for (i = 0; i < 4; i++)
3949                         smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3950                 /* exclude top 4 bytes for SMP req header */
3951                 smp_cmd.long_smp_req.long_req_addr =
3952                         cpu_to_le64((u64)sg_dma_address
3953                                 (&task->smp_task.smp_req) + 4);
3954                 /* exclude 4 bytes for SMP req header and CRC */
3955                 smp_cmd.long_smp_req.long_req_size =
3956                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3957                 smp_cmd.long_smp_req.long_resp_addr =
3958                                 cpu_to_le64((u64)sg_dma_address
3959                                         (&task->smp_task.smp_resp));
3960                 smp_cmd.long_smp_req.long_resp_size =
3961                                 cpu_to_le32((u32)sg_dma_len
3962                                         (&task->smp_task.smp_resp)-4);
3963         } else { /* DIRECT MODE */
3964                 smp_cmd.long_smp_req.long_req_addr =
3965                         cpu_to_le64((u64)sg_dma_address
3966                                         (&task->smp_task.smp_req));
3967                 smp_cmd.long_smp_req.long_req_size =
3968                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3969                 smp_cmd.long_smp_req.long_resp_addr =
3970                         cpu_to_le64((u64)sg_dma_address
3971                                 (&task->smp_task.smp_resp));
3972                 smp_cmd.long_smp_req.long_resp_size =
3973                         cpu_to_le32
3974                         ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3975         }
3976         if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3977                 PM8001_IO_DBG(pm8001_ha,
3978                         pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3979                 for (i = 0; i < length; i++)
3980                         if (i < 16) {
3981                                 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3982                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3983                                         "Byte[%d]:%x (DMA data:%x)\n",
3984                                         i, smp_cmd.smp_req16[i],
3985                                         *(preq_dma_addr)));
3986                         } else {
3987                                 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3988                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3989                                         "Byte[%d]:%x (DMA data:%x)\n",
3990                                         i, smp_cmd.smp_req[i],
3991                                         *(preq_dma_addr)));
3992                         }
3993         }
3994
3995         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3996                                 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3997         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
3998                                         (u32 *)&smp_cmd, 0);
3999         if (rc)
4000                 goto err_out_2;
4001         return 0;
4002
4003 err_out_2:
4004         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4005                         PCI_DMA_FROMDEVICE);
4006 err_out:
4007         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4008                         PCI_DMA_TODEVICE);
4009         return rc;
4010 }
4011
4012 static int check_enc_sas_cmd(struct sas_task *task)
4013 {
4014         u8 cmd = task->ssp_task.cmd->cmnd[0];
4015
4016         if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4017                 return 1;
4018         else
4019                 return 0;
4020 }
4021
4022 static int check_enc_sat_cmd(struct sas_task *task)
4023 {
4024         int ret = 0;
4025         switch (task->ata_task.fis.command) {
4026         case ATA_CMD_FPDMA_READ:
4027         case ATA_CMD_READ_EXT:
4028         case ATA_CMD_READ:
4029         case ATA_CMD_FPDMA_WRITE:
4030         case ATA_CMD_WRITE_EXT:
4031         case ATA_CMD_WRITE:
4032         case ATA_CMD_PIO_READ:
4033         case ATA_CMD_PIO_READ_EXT:
4034         case ATA_CMD_PIO_WRITE:
4035         case ATA_CMD_PIO_WRITE_EXT:
4036                 ret = 1;
4037                 break;
4038         default:
4039                 ret = 0;
4040                 break;
4041         }
4042         return ret;
4043 }
4044
4045 /**
4046  * pm80xx_chip_ssp_io_req - send a SSP task to FW
4047  * @pm8001_ha: our hba card information.
4048  * @ccb: the ccb information this request used.
4049  */
4050 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4051         struct pm8001_ccb_info *ccb)
4052 {
4053         struct sas_task *task = ccb->task;
4054         struct domain_device *dev = task->dev;
4055         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4056         struct ssp_ini_io_start_req ssp_cmd;
4057         u32 tag = ccb->ccb_tag;
4058         int ret;
4059         u64 phys_addr, start_addr, end_addr;
4060         u32 end_addr_high, end_addr_low;
4061         struct inbound_queue_table *circularQ;
4062         u32 q_index;
4063         u32 opc = OPC_INB_SSPINIIOSTART;
4064         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4065         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4066         /* data address domain added for spcv; set to 0 by host,
4067          * used internally by controller
4068          * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4069          */
4070         ssp_cmd.dad_dir_m_tlr =
4071                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4072         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4073         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4074         ssp_cmd.tag = cpu_to_le32(tag);
4075         if (task->ssp_task.enable_first_burst)
4076                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4077         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4078         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4079         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4080                        task->ssp_task.cmd->cmd_len);
4081         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4082         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4083
4084         /* Check if encryption is set */
4085         if (pm8001_ha->chip->encrypt &&
4086                 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4087                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4088                         "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4089                         task->ssp_task.cmd->cmnd[0]));
4090                 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4091                 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4092                 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4093                         ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4094
4095                 /* fill in PRD (scatter/gather) table, if any */
4096                 if (task->num_scatter > 1) {
4097                         pm8001_chip_make_sg(task->scatter,
4098                                                 ccb->n_elem, ccb->buf_prd);
4099                         phys_addr = ccb->ccb_dma_handle +
4100                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4101                         ssp_cmd.enc_addr_low =
4102                                 cpu_to_le32(lower_32_bits(phys_addr));
4103                         ssp_cmd.enc_addr_high =
4104                                 cpu_to_le32(upper_32_bits(phys_addr));
4105                         ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4106                 } else if (task->num_scatter == 1) {
4107                         u64 dma_addr = sg_dma_address(task->scatter);
4108                         ssp_cmd.enc_addr_low =
4109                                 cpu_to_le32(lower_32_bits(dma_addr));
4110                         ssp_cmd.enc_addr_high =
4111                                 cpu_to_le32(upper_32_bits(dma_addr));
4112                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4113                         ssp_cmd.enc_esgl = 0;
4114                         /* Check 4G Boundary */
4115                         start_addr = cpu_to_le64(dma_addr);
4116                         end_addr = (start_addr + ssp_cmd.enc_len) - 1;
4117                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4118                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4119                         if (end_addr_high != ssp_cmd.enc_addr_high) {
4120                                 PM8001_FAIL_DBG(pm8001_ha,
4121                                         pm8001_printk("The sg list address "
4122                                         "start_addr=0x%016llx data_len=0x%x "
4123                                         "end_addr_high=0x%08x end_addr_low="
4124                                         "0x%08x has crossed 4G boundary\n",
4125                                                 start_addr, ssp_cmd.enc_len,
4126                                                 end_addr_high, end_addr_low));
4127                                 pm8001_chip_make_sg(task->scatter, 1,
4128                                         ccb->buf_prd);
4129                                 phys_addr = ccb->ccb_dma_handle +
4130                                         offsetof(struct pm8001_ccb_info,
4131                                                 buf_prd[0]);
4132                                 ssp_cmd.enc_addr_low =
4133                                         cpu_to_le32(lower_32_bits(phys_addr));
4134                                 ssp_cmd.enc_addr_high =
4135                                         cpu_to_le32(upper_32_bits(phys_addr));
4136                                 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4137                         }
4138                 } else if (task->num_scatter == 0) {
4139                         ssp_cmd.enc_addr_low = 0;
4140                         ssp_cmd.enc_addr_high = 0;
4141                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4142                         ssp_cmd.enc_esgl = 0;
4143                 }
4144                 /* XTS mode. All other fields are 0 */
4145                 ssp_cmd.key_cmode = 0x6 << 4;
4146                 /* set tweak values. Should be the start lba */
4147                 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4148                                                 (task->ssp_task.cmd->cmnd[3] << 16) |
4149                                                 (task->ssp_task.cmd->cmnd[4] << 8) |
4150                                                 (task->ssp_task.cmd->cmnd[5]));
4151         } else {
4152                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4153                         "Sending Normal SAS command 0x%x inb q %x\n",
4154                         task->ssp_task.cmd->cmnd[0], q_index));
4155                 /* fill in PRD (scatter/gather) table, if any */
4156                 if (task->num_scatter > 1) {
4157                         pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4158                                         ccb->buf_prd);
4159                         phys_addr = ccb->ccb_dma_handle +
4160                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4161                         ssp_cmd.addr_low =
4162                                 cpu_to_le32(lower_32_bits(phys_addr));
4163                         ssp_cmd.addr_high =
4164                                 cpu_to_le32(upper_32_bits(phys_addr));
4165                         ssp_cmd.esgl = cpu_to_le32(1<<31);
4166                 } else if (task->num_scatter == 1) {
4167                         u64 dma_addr = sg_dma_address(task->scatter);
4168                         ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4169                         ssp_cmd.addr_high =
4170                                 cpu_to_le32(upper_32_bits(dma_addr));
4171                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4172                         ssp_cmd.esgl = 0;
4173                         /* Check 4G Boundary */
4174                         start_addr = cpu_to_le64(dma_addr);
4175                         end_addr = (start_addr + ssp_cmd.len) - 1;
4176                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4177                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4178                         if (end_addr_high != ssp_cmd.addr_high) {
4179                                 PM8001_FAIL_DBG(pm8001_ha,
4180                                         pm8001_printk("The sg list address "
4181                                         "start_addr=0x%016llx data_len=0x%x "
4182                                         "end_addr_high=0x%08x end_addr_low="
4183                                         "0x%08x has crossed 4G boundary\n",
4184                                                  start_addr, ssp_cmd.len,
4185                                                  end_addr_high, end_addr_low));
4186                                 pm8001_chip_make_sg(task->scatter, 1,
4187                                         ccb->buf_prd);
4188                                 phys_addr = ccb->ccb_dma_handle +
4189                                         offsetof(struct pm8001_ccb_info,
4190                                                  buf_prd[0]);
4191                                 ssp_cmd.addr_low =
4192                                         cpu_to_le32(lower_32_bits(phys_addr));
4193                                 ssp_cmd.addr_high =
4194                                         cpu_to_le32(upper_32_bits(phys_addr));
4195                                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4196                         }
4197                 } else if (task->num_scatter == 0) {
4198                         ssp_cmd.addr_low = 0;
4199                         ssp_cmd.addr_high = 0;
4200                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4201                         ssp_cmd.esgl = 0;
4202                 }
4203         }
4204         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4205         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4206                                                 &ssp_cmd, q_index);
4207         return ret;
4208 }
4209
4210 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4211         struct pm8001_ccb_info *ccb)
4212 {
4213         struct sas_task *task = ccb->task;
4214         struct domain_device *dev = task->dev;
4215         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4216         u32 tag = ccb->ccb_tag;
4217         int ret;
4218         u32 q_index;
4219         struct sata_start_req sata_cmd;
4220         u32 hdr_tag, ncg_tag = 0;
4221         u64 phys_addr, start_addr, end_addr;
4222         u32 end_addr_high, end_addr_low;
4223         u32 ATAP = 0x0;
4224         u32 dir;
4225         struct inbound_queue_table *circularQ;
4226         unsigned long flags;
4227         u32 opc = OPC_INB_SATA_HOST_OPSTART;
4228         memset(&sata_cmd, 0, sizeof(sata_cmd));
4229         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4230         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4231
4232         if (task->data_dir == PCI_DMA_NONE) {
4233                 ATAP = 0x04; /* no data*/
4234                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4235         } else if (likely(!task->ata_task.device_control_reg_update)) {
4236                 if (task->ata_task.dma_xfer) {
4237                         ATAP = 0x06; /* DMA */
4238                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4239                 } else {
4240                         ATAP = 0x05; /* PIO*/
4241                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4242                 }
4243                 if (task->ata_task.use_ncq &&
4244                     dev->sata_dev.class != ATA_DEV_ATAPI) {
4245                         ATAP = 0x07; /* FPDMA */
4246                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4247                 }
4248         }
4249         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4250                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4251                 ncg_tag = hdr_tag;
4252         }
4253         dir = data_dir_flags[task->data_dir] << 8;
4254         sata_cmd.tag = cpu_to_le32(tag);
4255         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4256         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4257
4258         sata_cmd.sata_fis = task->ata_task.fis;
4259         if (likely(!task->ata_task.device_control_reg_update))
4260                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4261         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4262
4263         /* Check if encryption is set */
4264         if (pm8001_ha->chip->encrypt &&
4265                 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4266                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4267                         "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4268                         sata_cmd.sata_fis.command));
4269                 opc = OPC_INB_SATA_DIF_ENC_IO;
4270
4271                 /* set encryption bit */
4272                 sata_cmd.ncqtag_atap_dir_m_dad =
4273                         cpu_to_le32(((ncg_tag & 0xff)<<16)|
4274                                 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4275                                                         /* dad (bit 0-1) is 0 */
4276                 /* fill in PRD (scatter/gather) table, if any */
4277                 if (task->num_scatter > 1) {
4278                         pm8001_chip_make_sg(task->scatter,
4279                                                 ccb->n_elem, ccb->buf_prd);
4280                         phys_addr = ccb->ccb_dma_handle +
4281                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4282                         sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4283                         sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4284                         sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4285                 } else if (task->num_scatter == 1) {
4286                         u64 dma_addr = sg_dma_address(task->scatter);
4287                         sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4288                         sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4289                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4290                         sata_cmd.enc_esgl = 0;
4291                         /* Check 4G Boundary */
4292                         start_addr = cpu_to_le64(dma_addr);
4293                         end_addr = (start_addr + sata_cmd.enc_len) - 1;
4294                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4295                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4296                         if (end_addr_high != sata_cmd.enc_addr_high) {
4297                                 PM8001_FAIL_DBG(pm8001_ha,
4298                                         pm8001_printk("The sg list address "
4299                                         "start_addr=0x%016llx data_len=0x%x "
4300                                         "end_addr_high=0x%08x end_addr_low"
4301                                         "=0x%08x has crossed 4G boundary\n",
4302                                                 start_addr, sata_cmd.enc_len,
4303                                                 end_addr_high, end_addr_low));
4304                                 pm8001_chip_make_sg(task->scatter, 1,
4305                                         ccb->buf_prd);
4306                                 phys_addr = ccb->ccb_dma_handle +
4307                                                 offsetof(struct pm8001_ccb_info,
4308                                                 buf_prd[0]);
4309                                 sata_cmd.enc_addr_low =
4310                                         lower_32_bits(phys_addr);
4311                                 sata_cmd.enc_addr_high =
4312                                         upper_32_bits(phys_addr);
4313                                 sata_cmd.enc_esgl =
4314                                         cpu_to_le32(1 << 31);
4315                         }
4316                 } else if (task->num_scatter == 0) {
4317                         sata_cmd.enc_addr_low = 0;
4318                         sata_cmd.enc_addr_high = 0;
4319                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4320                         sata_cmd.enc_esgl = 0;
4321                 }
4322                 /* XTS mode. All other fields are 0 */
4323                 sata_cmd.key_index_mode = 0x6 << 4;
4324                 /* set tweak values. Should be the start lba */
4325                 sata_cmd.twk_val0 =
4326                         cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4327                                         (sata_cmd.sata_fis.lbah << 16) |
4328                                         (sata_cmd.sata_fis.lbam << 8) |
4329                                         (sata_cmd.sata_fis.lbal));
4330                 sata_cmd.twk_val1 =
4331                         cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4332                                          (sata_cmd.sata_fis.lbam_exp));
4333         } else {
4334                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4335                         "Sending Normal SATA command 0x%x inb %x\n",
4336                         sata_cmd.sata_fis.command, q_index));
4337                 /* dad (bit 0-1) is 0 */
4338                 sata_cmd.ncqtag_atap_dir_m_dad =
4339                         cpu_to_le32(((ncg_tag & 0xff)<<16) |
4340                                         ((ATAP & 0x3f) << 10) | dir);
4341
4342                 /* fill in PRD (scatter/gather) table, if any */
4343                 if (task->num_scatter > 1) {
4344                         pm8001_chip_make_sg(task->scatter,
4345                                         ccb->n_elem, ccb->buf_prd);
4346                         phys_addr = ccb->ccb_dma_handle +
4347                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4348                         sata_cmd.addr_low = lower_32_bits(phys_addr);
4349                         sata_cmd.addr_high = upper_32_bits(phys_addr);
4350                         sata_cmd.esgl = cpu_to_le32(1 << 31);
4351                 } else if (task->num_scatter == 1) {
4352                         u64 dma_addr = sg_dma_address(task->scatter);
4353                         sata_cmd.addr_low = lower_32_bits(dma_addr);
4354                         sata_cmd.addr_high = upper_32_bits(dma_addr);
4355                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4356                         sata_cmd.esgl = 0;
4357                         /* Check 4G Boundary */
4358                         start_addr = cpu_to_le64(dma_addr);
4359                         end_addr = (start_addr + sata_cmd.len) - 1;
4360                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4361                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4362                         if (end_addr_high != sata_cmd.addr_high) {
4363                                 PM8001_FAIL_DBG(pm8001_ha,
4364                                         pm8001_printk("The sg list address "
4365                                         "start_addr=0x%016llx data_len=0x%x"
4366                                         "end_addr_high=0x%08x end_addr_low="
4367                                         "0x%08x has crossed 4G boundary\n",
4368                                                 start_addr, sata_cmd.len,
4369                                                 end_addr_high, end_addr_low));
4370                                 pm8001_chip_make_sg(task->scatter, 1,
4371                                         ccb->buf_prd);
4372                                 phys_addr = ccb->ccb_dma_handle +
4373                                         offsetof(struct pm8001_ccb_info,
4374                                         buf_prd[0]);
4375                                 sata_cmd.addr_low =
4376                                         lower_32_bits(phys_addr);
4377                                 sata_cmd.addr_high =
4378                                         upper_32_bits(phys_addr);
4379                                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4380                         }
4381                 } else if (task->num_scatter == 0) {
4382                         sata_cmd.addr_low = 0;
4383                         sata_cmd.addr_high = 0;
4384                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4385                         sata_cmd.esgl = 0;
4386                 }
4387                         /* scsi cdb */
4388                         sata_cmd.atapi_scsi_cdb[0] =
4389                                 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4390                                 (task->ata_task.atapi_packet[1] << 8) |
4391                                 (task->ata_task.atapi_packet[2] << 16) |
4392                                 (task->ata_task.atapi_packet[3] << 24)));
4393                         sata_cmd.atapi_scsi_cdb[1] =
4394                                 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4395                                 (task->ata_task.atapi_packet[5] << 8) |
4396                                 (task->ata_task.atapi_packet[6] << 16) |
4397                                 (task->ata_task.atapi_packet[7] << 24)));
4398                         sata_cmd.atapi_scsi_cdb[2] =
4399                                 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4400                                 (task->ata_task.atapi_packet[9] << 8) |
4401                                 (task->ata_task.atapi_packet[10] << 16) |
4402                                 (task->ata_task.atapi_packet[11] << 24)));
4403                         sata_cmd.atapi_scsi_cdb[3] =
4404                                 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4405                                 (task->ata_task.atapi_packet[13] << 8) |
4406                                 (task->ata_task.atapi_packet[14] << 16) |
4407                                 (task->ata_task.atapi_packet[15] << 24)));
4408         }
4409
4410         /* Check for read log for failed drive and return */
4411         if (sata_cmd.sata_fis.command == 0x2f) {
4412                 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4413                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4414                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4415                         struct task_status_struct *ts;
4416
4417                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4418                         ts = &task->task_status;
4419
4420                         spin_lock_irqsave(&task->task_state_lock, flags);
4421                         ts->resp = SAS_TASK_COMPLETE;
4422                         ts->stat = SAM_STAT_GOOD;
4423                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4424                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4425                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4426                         if (unlikely((task->task_state_flags &
4427                                         SAS_TASK_STATE_ABORTED))) {
4428                                 spin_unlock_irqrestore(&task->task_state_lock,
4429                                                         flags);
4430                                 PM8001_FAIL_DBG(pm8001_ha,
4431                                         pm8001_printk("task 0x%p resp 0x%x "
4432                                         " stat 0x%x but aborted by upper layer "
4433                                         "\n", task, ts->resp, ts->stat));
4434                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4435                                 return 0;
4436                         } else {
4437                                 spin_unlock_irqrestore(&task->task_state_lock,
4438                                                         flags);
4439                                 pm8001_ccb_task_free_done(pm8001_ha, task,
4440                                                                 ccb, tag);
4441                                 return 0;
4442                         }
4443                 }
4444         }
4445         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4446         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4447                                                 &sata_cmd, q_index);
4448         return ret;
4449 }
4450
4451 /**
4452  * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4453  * @pm8001_ha: our hba card information.
4454  * @num: the inbound queue number
4455  * @phy_id: the phy id which we wanted to start up.
4456  */
4457 static int
4458 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4459 {
4460         struct phy_start_req payload;
4461         struct inbound_queue_table *circularQ;
4462         int ret;
4463         u32 tag = 0x01;
4464         u32 opcode = OPC_INB_PHYSTART;
4465         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4466         memset(&payload, 0, sizeof(payload));
4467         payload.tag = cpu_to_le32(tag);
4468
4469         PM8001_INIT_DBG(pm8001_ha,
4470                 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4471         /*
4472          ** [0:7]       PHY Identifier
4473          ** [8:11]      link rate 1.5G, 3G, 6G
4474          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
4475          ** [14]        0b disable spin up hold; 1b enable spin up hold
4476          ** [15] ob no change in current PHY analig setup 1b enable using SPAST
4477          */
4478         if (!IS_SPCV_12G(pm8001_ha->pdev))
4479                 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4480                                 LINKMODE_AUTO | LINKRATE_15 |
4481                                 LINKRATE_30 | LINKRATE_60 | phy_id);
4482         else
4483                 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4484                                 LINKMODE_AUTO | LINKRATE_15 |
4485                                 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
4486                                 phy_id);
4487
4488         /* SSC Disable and SAS Analog ST configuration */
4489         /**
4490         payload.ase_sh_lm_slr_phyid =
4491                 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4492                 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4493                 phy_id);
4494         Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4495         **/
4496
4497         payload.sas_identify.dev_type = SAS_END_DEVICE;
4498         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4499         memcpy(payload.sas_identify.sas_addr,
4500           &pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE);
4501         payload.sas_identify.phy_id = phy_id;
4502         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4503         return ret;
4504 }
4505
4506 /**
4507  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4508  * @pm8001_ha: our hba card information.
4509  * @num: the inbound queue number
4510  * @phy_id: the phy id which we wanted to start up.
4511  */
4512 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4513         u8 phy_id)
4514 {
4515         struct phy_stop_req payload;
4516         struct inbound_queue_table *circularQ;
4517         int ret;
4518         u32 tag = 0x01;
4519         u32 opcode = OPC_INB_PHYSTOP;
4520         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4521         memset(&payload, 0, sizeof(payload));
4522         payload.tag = cpu_to_le32(tag);
4523         payload.phy_id = cpu_to_le32(phy_id);
4524         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4525         return ret;
4526 }
4527
4528 /**
4529  * see comments on pm8001_mpi_reg_resp.
4530  */
4531 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4532         struct pm8001_device *pm8001_dev, u32 flag)
4533 {
4534         struct reg_dev_req payload;
4535         u32     opc;
4536         u32 stp_sspsmp_sata = 0x4;
4537         struct inbound_queue_table *circularQ;
4538         u32 linkrate, phy_id;
4539         int rc, tag = 0xdeadbeef;
4540         struct pm8001_ccb_info *ccb;
4541         u8 retryFlag = 0x1;
4542         u16 firstBurstSize = 0;
4543         u16 ITNT = 2000;
4544         struct domain_device *dev = pm8001_dev->sas_device;
4545         struct domain_device *parent_dev = dev->parent;
4546         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4547
4548         memset(&payload, 0, sizeof(payload));
4549         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4550         if (rc)
4551                 return rc;
4552         ccb = &pm8001_ha->ccb_info[tag];
4553         ccb->device = pm8001_dev;
4554         ccb->ccb_tag = tag;
4555         payload.tag = cpu_to_le32(tag);
4556
4557         if (flag == 1) {
4558                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4559         } else {
4560                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4561                         stp_sspsmp_sata = 0x00; /* stp*/
4562                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4563                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4564                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4565                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4566         }
4567         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4568                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4569         else
4570                 phy_id = pm8001_dev->attached_phy;
4571
4572         opc = OPC_INB_REG_DEV;
4573
4574         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4575                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4576
4577         payload.phyid_portid =
4578                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4579                 ((phy_id & 0xFF) << 8));
4580
4581         payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4582                 ((linkrate & 0x0F) << 24) |
4583                 ((stp_sspsmp_sata & 0x03) << 28));
4584         payload.firstburstsize_ITNexustimeout =
4585                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4586
4587         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4588                 SAS_ADDR_SIZE);
4589
4590         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4591         if (rc)
4592                 pm8001_tag_free(pm8001_ha, tag);
4593
4594         return rc;
4595 }
4596
4597 /**
4598  * pm80xx_chip_phy_ctl_req - support the local phy operation
4599  * @pm8001_ha: our hba card information.
4600  * @num: the inbound queue number
4601  * @phy_id: the phy id which we wanted to operate
4602  * @phy_op:
4603  */
4604 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4605         u32 phyId, u32 phy_op)
4606 {
4607         u32 tag;
4608         int rc;
4609         struct local_phy_ctl_req payload;
4610         struct inbound_queue_table *circularQ;
4611         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4612         memset(&payload, 0, sizeof(payload));
4613         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4614         if (rc)
4615                 return rc;
4616         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4617         payload.tag = cpu_to_le32(tag);
4618         payload.phyop_phyid =
4619                 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4620         return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4621 }
4622
4623 static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4624 {
4625         u32 value;
4626 #ifdef PM8001_USE_MSIX
4627         return 1;
4628 #endif
4629         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4630         if (value)
4631                 return 1;
4632         return 0;
4633
4634 }
4635
4636 /**
4637  * pm8001_chip_isr - PM8001 isr handler.
4638  * @pm8001_ha: our hba card information.
4639  * @irq: irq number.
4640  * @stat: stat.
4641  */
4642 static irqreturn_t
4643 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4644 {
4645         pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4646         process_oq(pm8001_ha, vec);
4647         pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4648         return IRQ_HANDLED;
4649 }
4650
4651 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4652         u32 operation, u32 phyid, u32 length, u32 *buf)
4653 {
4654         u32 tag , i, j = 0;
4655         int rc;
4656         struct set_phy_profile_req payload;
4657         struct inbound_queue_table *circularQ;
4658         u32 opc = OPC_INB_SET_PHY_PROFILE;
4659
4660         memset(&payload, 0, sizeof(payload));
4661         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4662         if (rc)
4663                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
4664         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4665         payload.tag = cpu_to_le32(tag);
4666         payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid  & 0xFF));
4667         PM8001_INIT_DBG(pm8001_ha,
4668                 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
4669                         payload.ppc_phyid, length));
4670         for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4671                 payload.reserved[j] =  cpu_to_le32(*((u32 *)buf + i));
4672                 j++;
4673         }
4674         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4675         if (rc)
4676                 pm8001_tag_free(pm8001_ha, tag);
4677 }
4678
4679 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4680         u32 length, u8 *buf)
4681 {
4682         u32 page_code, i;
4683
4684         page_code = SAS_PHY_ANALOG_SETTINGS_PAGE;
4685         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4686                 mpi_set_phy_profile_req(pm8001_ha,
4687                         SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4688                 length = length + PHY_DWORD_LENGTH;
4689         }
4690         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
4691 }
4692
4693 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4694                 u32 phy, u32 length, u32 *buf)
4695 {
4696         u32 tag, opc;
4697         int rc, i;
4698         struct set_phy_profile_req payload;
4699         struct inbound_queue_table *circularQ;
4700
4701         memset(&payload, 0, sizeof(payload));
4702
4703         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4704         if (rc)
4705                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag"));
4706
4707         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4708         opc = OPC_INB_SET_PHY_PROFILE;
4709
4710         payload.tag = cpu_to_le32(tag);
4711         payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4712                                 | (phy & 0xFF));
4713
4714         for (i = 0; i < length; i++)
4715                 payload.reserved[i] = cpu_to_le32(*(buf + i));
4716
4717         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4718         if (rc)
4719                 pm8001_tag_free(pm8001_ha, tag);
4720
4721         PM8001_INIT_DBG(pm8001_ha,
4722                 pm8001_printk("PHY %d settings applied", phy));
4723 }
4724 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4725         .name                   = "pmc80xx",
4726         .chip_init              = pm80xx_chip_init,
4727         .chip_soft_rst          = pm80xx_chip_soft_rst,
4728         .chip_rst               = pm80xx_hw_chip_rst,
4729         .chip_iounmap           = pm8001_chip_iounmap,
4730         .isr                    = pm80xx_chip_isr,
4731         .is_our_interupt        = pm80xx_chip_is_our_interupt,
4732         .isr_process_oq         = process_oq,
4733         .interrupt_enable       = pm80xx_chip_interrupt_enable,
4734         .interrupt_disable      = pm80xx_chip_interrupt_disable,
4735         .make_prd               = pm8001_chip_make_sg,
4736         .smp_req                = pm80xx_chip_smp_req,
4737         .ssp_io_req             = pm80xx_chip_ssp_io_req,
4738         .sata_req               = pm80xx_chip_sata_req,
4739         .phy_start_req          = pm80xx_chip_phy_start_req,
4740         .phy_stop_req           = pm80xx_chip_phy_stop_req,
4741         .reg_dev_req            = pm80xx_chip_reg_dev_req,
4742         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
4743         .phy_ctl_req            = pm80xx_chip_phy_ctl_req,
4744         .task_abort             = pm8001_chip_abort_task,
4745         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
4746         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
4747         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
4748         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
4749         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
4750 };