2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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37 * POSSIBILITY OF SUCH DAMAGES.
41 #ifndef _PMC8001_REG_H_
42 #define _PMC8001_REG_H_
44 #include <linux/types.h>
45 #include <scsi/libsas.h>
47 /* for Request Opcode of IOMB */
48 #define OPC_INB_ECHO 1 /* 0x000 */
49 #define OPC_INB_PHYSTART 4 /* 0x004 */
50 #define OPC_INB_PHYSTOP 5 /* 0x005 */
51 #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
52 #define OPC_INB_SSPINITMSTART 7 /* 0x007 */
53 /* 0x8 RESV IN SPCv */
54 #define OPC_INB_RSVD 8 /* 0x008 */
55 #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
56 #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
57 #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
58 /* 0xC, 0xD, 0xE removed in SPCv */
59 #define OPC_INB_SSP_ABORT 15 /* 0x00F */
60 #define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */
61 #define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */
62 #define OPC_INB_SMP_REQUEST 18 /* 0x012 */
63 /* 0x13 SMP_RESPONSE is removed in SPCv */
64 #define OPC_INB_SMP_ABORT 20 /* 0x014 */
65 /* 0x16 RESV IN SPCv */
66 #define OPC_INB_RSVD1 22 /* 0x016 */
67 #define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */
68 #define OPC_INB_SATA_ABORT 24 /* 0x018 */
69 #define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */
70 /* 0x1A RESV IN SPCv */
71 #define OPC_INB_RSVD2 26 /* 0x01A */
72 #define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */
73 #define OPC_INB_GPIO 34 /* 0x022 */
74 #define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */
75 #define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */
76 /* 0x25 RESV IN SPCv */
77 #define OPC_INB_RSVD3 37 /* 0x025 */
78 #define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */
79 #define OPC_INB_PORT_CONTROL 39 /* 0x027 */
80 #define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */
81 #define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */
82 #define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */
83 #define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */
84 #define OPC_INB_SET_DEV_INFO 44 /* 0x02C */
85 /* 0x2D RESV IN SPCv */
86 #define OPC_INB_RSVD4 45 /* 0x02D */
87 #define OPC_INB_SGPIO_REGISTER 46 /* 0x02E */
88 #define OPC_INB_PCIE_DIAG_EXEC 47 /* 0x02F */
89 #define OPC_INB_SET_CONTROLLER_CONFIG 48 /* 0x030 */
90 #define OPC_INB_GET_CONTROLLER_CONFIG 49 /* 0x031 */
91 #define OPC_INB_REG_DEV 50 /* 0x032 */
92 #define OPC_INB_SAS_HW_EVENT_ACK 51 /* 0x033 */
93 #define OPC_INB_GET_DEVICE_INFO 52 /* 0x034 */
94 #define OPC_INB_GET_PHY_PROFILE 53 /* 0x035 */
95 #define OPC_INB_FLASH_OP_EXT 54 /* 0x036 */
96 #define OPC_INB_SET_PHY_PROFILE 55 /* 0x037 */
97 #define OPC_INB_KEK_MANAGEMENT 256 /* 0x100 */
98 #define OPC_INB_DEK_MANAGEMENT 257 /* 0x101 */
99 #define OPC_INB_SSP_INI_DIF_ENC_IO 258 /* 0x102 */
100 #define OPC_INB_SATA_DIF_ENC_IO 259 /* 0x103 */
102 /* for Response Opcode of IOMB */
103 #define OPC_OUB_ECHO 1 /* 0x001 */
104 #define OPC_OUB_RSVD 4 /* 0x004 */
105 #define OPC_OUB_SSP_COMP 5 /* 0x005 */
106 #define OPC_OUB_SMP_COMP 6 /* 0x006 */
107 #define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */
108 #define OPC_OUB_RSVD1 10 /* 0x00A */
109 #define OPC_OUB_DEREG_DEV 11 /* 0x00B */
110 #define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */
111 #define OPC_OUB_SATA_COMP 13 /* 0x00D */
112 #define OPC_OUB_SATA_EVENT 14 /* 0x00E */
113 #define OPC_OUB_SSP_EVENT 15 /* 0x00F */
114 #define OPC_OUB_RSVD2 16 /* 0x010 */
115 /* 0x11 - SMP_RECEIVED Notification removed in SPCv*/
116 #define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */
117 #define OPC_OUB_RSVD3 19 /* 0x013 */
118 #define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */
119 #define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */
120 #define OPC_OUB_GPIO_EVENT 23 /* 0x017 */
121 #define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */
122 #define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */
123 #define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */
124 #define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */
125 #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
126 #define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */
127 #define OPC_OUB_RSVD4 31 /* 0x01F */
128 #define OPC_OUB_PORT_CONTROL 32 /* 0x020 */
129 #define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */
130 #define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */
131 #define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */
132 #define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */
133 #define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */
134 #define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */
135 #define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */
136 #define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */
137 #define OPC_OUB_RSVD5 41 /* 0x029 */
138 #define OPC_OUB_HW_EVENT 1792 /* 0x700 */
139 #define OPC_OUB_DEV_HANDLE_ARRIV 1824 /* 0x720 */
140 #define OPC_OUB_THERM_HW_EVENT 1840 /* 0x730 */
141 #define OPC_OUB_SGPIO_RESP 2094 /* 0x82E */
142 #define OPC_OUB_PCIE_DIAG_EXECUTE 2095 /* 0x82F */
143 #define OPC_OUB_DEV_REGIST 2098 /* 0x832 */
144 #define OPC_OUB_SAS_HW_EVENT_ACK 2099 /* 0x833 */
145 #define OPC_OUB_GET_DEVICE_INFO 2100 /* 0x834 */
146 /* spcv specific commands */
147 #define OPC_OUB_PHY_START_RESP 2052 /* 0x804 */
148 #define OPC_OUB_PHY_STOP_RESP 2053 /* 0x805 */
149 #define OPC_OUB_SET_CONTROLLER_CONFIG 2096 /* 0x830 */
150 #define OPC_OUB_GET_CONTROLLER_CONFIG 2097 /* 0x831 */
151 #define OPC_OUB_GET_PHY_PROFILE 2101 /* 0x835 */
152 #define OPC_OUB_FLASH_OP_EXT 2102 /* 0x836 */
153 #define OPC_OUB_SET_PHY_PROFILE 2103 /* 0x837 */
154 #define OPC_OUB_KEK_MANAGEMENT_RESP 2304 /* 0x900 */
155 #define OPC_OUB_DEK_MANAGEMENT_RESP 2305 /* 0x901 */
156 #define OPC_OUB_SSP_COALESCED_COMP_RESP 2306 /* 0x902 */
159 #define SSC_DISABLE_15 (0x01 << 16)
160 #define SSC_DISABLE_30 (0x02 << 16)
161 #define SSC_DISABLE_60 (0x04 << 16)
162 #define SAS_ASE (0x01 << 15)
163 #define SPINHOLD_DISABLE (0x00 << 14)
164 #define SPINHOLD_ENABLE (0x01 << 14)
165 #define LINKMODE_SAS (0x01 << 12)
166 #define LINKMODE_DSATA (0x02 << 12)
167 #define LINKMODE_AUTO (0x03 << 12)
168 #define LINKRATE_15 (0x01 << 8)
169 #define LINKRATE_30 (0x02 << 8)
170 #define LINKRATE_60 (0x04 << 8)
171 #define LINKRATE_120 (0x08 << 8)
174 #define SAS_PHY_ANALOG_SETTINGS_PAGE 0x04
175 #define PHY_DWORD_LENGTH 0xC
177 /* Thermal related */
178 #define THERMAL_ENABLE 0x1
179 #define THERMAL_LOG_ENABLE 0x1
180 #define THERMAL_PAGE_CODE_7H 0x6
181 #define THERMAL_PAGE_CODE_8H 0x7
185 /* Encryption info */
186 #define SCRATCH_PAD3_ENC_DISABLED 0x00000000
187 #define SCRATCH_PAD3_ENC_DIS_ERR 0x00000001
188 #define SCRATCH_PAD3_ENC_ENA_ERR 0x00000002
189 #define SCRATCH_PAD3_ENC_READY 0x00000003
190 #define SCRATCH_PAD3_ENC_MASK SCRATCH_PAD3_ENC_READY
192 #define SCRATCH_PAD3_XTS_ENABLED (1 << 14)
193 #define SCRATCH_PAD3_SMA_ENABLED (1 << 4)
194 #define SCRATCH_PAD3_SMB_ENABLED (1 << 5)
195 #define SCRATCH_PAD3_SMF_ENABLED 0
196 #define SCRATCH_PAD3_SM_MASK 0x000000F0
197 #define SCRATCH_PAD3_ERR_CODE 0x00FF0000
199 #define SEC_MODE_SMF 0x0
200 #define SEC_MODE_SMA 0x100
201 #define SEC_MODE_SMB 0x200
202 #define CIPHER_MODE_ECB 0x00000001
203 #define CIPHER_MODE_XTS 0x00000002
204 #define KEK_MGMT_SUBOP_KEYCARDUPDATE 0x4
206 /* SAS protocol timer configuration page */
207 #define SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04
208 #define STP_MCT_TMO 32
209 #define SSP_MCT_TMO 32
210 #define SAS_MAX_OPEN_TIME 5
211 #define SMP_MAX_CONN_TIMER 0xFF
212 #define STP_FRM_TIMER 0
213 #define STP_IDLE_TIME 5 /* 5 us; controller default */
215 #define SAS_OPNRJT_RTRY_INTVL 2
216 #define SAS_DOPNRJT_RTRY_TMO 128
217 #define SAS_COPNRJT_RTRY_TMO 128
220 #define PHY_STATE_LINK_UP_SPCV 0x2
222 Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second.
223 Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128
226 #define SAS_DOPNRJT_RTRY_THR 23438
227 #define SAS_COPNRJT_RTRY_THR 23438
228 #define SAS_MAX_AIP 0x200000
229 #define IT_NEXUS_TIMEOUT 0x7D0
230 #define PORT_RECOVERY_TIMEOUT ((IT_NEXUS_TIMEOUT/100) + 30)
231 /* Port recovery timeout, 10000 ms for PM8006 controller */
232 #define CHIP_8006_PORT_RECOVERY_TIMEOUT 0x640000
234 #ifdef __LITTLE_ENDIAN_BITFIELD
235 struct sas_identify_frame_local {
272 u8 sas_addr[SAS_ADDR_SIZE];
281 #elif defined(__BIG_ENDIAN_BITFIELD)
282 struct sas_identify_frame_local {
319 u8 sas_addr[SAS_ADDR_SIZE];
327 #error "Bitfield order not defined!"
331 __le32 header; /* Bits [11:0] - Message operation code */
332 /* Bits [15:12] - Message Category */
333 /* Bits [21:16] - Outboundqueue ID for the
334 operation completion message */
335 /* Bits [23:22] - Reserved */
336 /* Bits [28:24] - Buffer Count, indicates how
337 many buffer are allocated for the massage */
338 /* Bits [30:29] - Reserved */
339 /* Bits [31] - Message Valid bit */
340 } __attribute__((packed, aligned(4)));
343 * brief the data structure of PHY Start Command
344 * use to describe enable the phy (128 bytes)
346 struct phy_start_req {
348 __le32 ase_sh_lm_slr_phyid;
349 struct sas_identify_frame_local sas_identify; /* 28 Bytes */
352 } __attribute__((packed, aligned(4)));
355 * brief the data structure of PHY Start Command
356 * use to disable the phy (128 bytes)
358 struct phy_stop_req {
362 } __attribute__((packed, aligned(4)));
364 /* set device bits fis - device to host */
365 struct set_dev_bits_fis {
366 u8 fis_type; /* 0xA1*/
368 /* b7 : n Bit. Notification bit. If set device needs attention. */
369 /* b6 : i Bit. Interrupt Bit */
370 /* b5-b4: reserved2 */
375 } __attribute__ ((packed));
376 /* PIO setup FIS - device to host */
377 struct pio_setup_fis {
378 u8 fis_type; /* 0x5f */
381 /* b6 : i bit. Interrupt bit */
382 /* b5 : d bit. data transfer direction. set to 1 for device to host
402 } __attribute__ ((packed));
405 * brief the data structure of SATA Completion Response
406 * use to describe the sata task response (64 bytes)
408 struct sata_completion_resp {
413 } __attribute__((packed, aligned(4)));
416 * brief the data structure of SAS HW Event Notification
417 * use to alert the host about the hardware event(64 bytes)
419 /* updated outbound struct for spcv */
421 struct hw_event_resp {
422 __le32 lr_status_evt_portid;
424 __le32 phyid_npip_portstate;
425 struct sas_identify_frame sas_identify;
426 struct dev_to_host_fis sata_fis;
427 } __attribute__((packed, aligned(4)));
430 * brief the data structure for thermal event notification
433 struct thermal_hw_event {
434 __le32 thermal_event;
436 } __attribute__((packed, aligned(4)));
439 * brief the data structure of REGISTER DEVICE Command
440 * use to describe MPI REGISTER DEVICE Command (64 bytes)
446 __le32 dtype_dlr_mcn_ir_retry;
447 __le32 firstburstsize_ITNexustimeout;
448 u8 sas_addr[SAS_ADDR_SIZE];
449 __le32 upper_device_id;
451 } __attribute__((packed, aligned(4)));
454 * brief the data structure of DEREGISTER DEVICE Command
455 * use to request spc to remove all internal resources associated
456 * with the device id (64 bytes)
459 struct dereg_dev_req {
463 } __attribute__((packed, aligned(4)));
466 * brief the data structure of DEVICE_REGISTRATION Response
467 * use to notify the completion of the device registration (64 bytes)
469 struct dev_reg_resp {
474 } __attribute__((packed, aligned(4)));
477 * brief the data structure of Local PHY Control Command
478 * use to issue PHY CONTROL to local phy (64 bytes)
480 struct local_phy_ctl_req {
484 } __attribute__((packed, aligned(4)));
487 * brief the data structure of Local Phy Control Response
488 * use to describe MPI Local Phy Control Response (64 bytes)
490 struct local_phy_ctl_resp {
495 } __attribute__((packed, aligned(4)));
497 #define OP_BITS 0x0000FF00
498 #define ID_BITS 0x000000FF
501 * brief the data structure of PORT Control Command
502 * use to control port properties (64 bytes)
505 struct port_ctl_req {
507 __le32 portop_portid;
511 } __attribute__((packed, aligned(4)));
514 * brief the data structure of HW Event Ack Command
515 * use to acknowledge receive HW event (64 bytes)
517 struct hw_event_ack_req {
519 __le32 phyid_sea_portid;
523 } __attribute__((packed, aligned(4)));
526 * brief the data structure of PHY_START Response Command
527 * indicates the completion of PHY_START command (64 bytes)
529 struct phy_start_resp {
534 } __attribute__((packed, aligned(4)));
537 * brief the data structure of PHY_STOP Response Command
538 * indicates the completion of PHY_STOP command (64 bytes)
540 struct phy_stop_resp {
545 } __attribute__((packed, aligned(4)));
548 * brief the data structure of SSP Completion Response
549 * use to indicate a SSP Completion (n bytes)
551 struct ssp_completion_resp {
555 __le32 ssptag_rescv_rescpad;
556 struct ssp_response_iu ssp_resp_iu;
557 __le32 residual_count;
558 } __attribute__((packed, aligned(4)));
560 #define SSP_RESCV_BIT 0x00010000
563 * brief the data structure of SATA EVNET response
564 * use to indicate a SATA Completion (64 bytes)
566 struct sata_event_resp {
574 __le32 sata_addr_h32;
575 __le32 sata_addr_l32;
576 __le32 e_udt1_udt0_crc;
577 __le32 e_udt5_udt4_udt3_udt2;
578 __le32 a_udt1_udt0_crc;
579 __le32 a_udt5_udt4_udt3_udt2;
580 __le32 hwdevid_diferr;
581 __le32 err_framelen_byteoffset;
582 __le32 err_dataframe;
583 } __attribute__((packed, aligned(4)));
586 * brief the data structure of SSP EVNET esponse
587 * use to indicate a SSP Completion (64 bytes)
589 struct ssp_event_resp {
599 __le32 e_udt1_udt0_crc;
600 __le32 e_udt5_udt4_udt3_udt2;
601 __le32 a_udt1_udt0_crc;
602 __le32 a_udt5_udt4_udt3_udt2;
603 __le32 hwdevid_diferr;
604 __le32 err_framelen_byteoffset;
605 __le32 err_dataframe;
606 } __attribute__((packed, aligned(4)));
609 * brief the data structure of General Event Notification Response
610 * use to describe MPI General Event Notification Response (64 bytes)
612 struct general_event_resp {
614 __le32 inb_IOMB_payload[14];
615 } __attribute__((packed, aligned(4)));
617 #define GENERAL_EVENT_PAYLOAD 14
618 #define OPCODE_BITS 0x00000fff
621 * brief the data structure of SMP Request Command
622 * use to describe MPI SMP REQUEST Command (64 bytes)
628 /* Bits [0] - Indirect response */
629 /* Bits [1] - Indirect Payload */
630 /* Bits [15:2] - Reserved */
631 /* Bits [23:16] - direct payload Len */
632 /* Bits [31:24] - Reserved */
637 __le64 long_req_addr;/* sg dma address, LE */
638 __le32 long_req_size;/* LE */
640 __le64 long_resp_addr;/* sg dma address, LE */
641 __le32 long_resp_size;/* LE */
643 } long_smp_req;/* sequencer extension */
646 } __attribute__((packed, aligned(4)));
648 * brief the data structure of SMP Completion Response
649 * use to describe MPI SMP Completion Response (64 bytes)
651 struct smp_completion_resp {
656 } __attribute__((packed, aligned(4)));
659 *brief the data structure of SSP SMP SATA Abort Command
660 * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
662 struct task_abort_req {
668 } __attribute__((packed, aligned(4)));
670 /* These flags used for SSP SMP & SATA Abort */
671 #define ABORT_MASK 0x3
672 #define ABORT_SINGLE 0x0
673 #define ABORT_ALL 0x1
676 * brief the data structure of SSP SATA SMP Abort Response
677 * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
679 struct task_abort_resp {
684 } __attribute__((packed, aligned(4)));
687 * brief the data structure of SAS Diagnostic Start/End Command
688 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
690 struct sas_diag_start_end_req {
692 __le32 operation_phyid;
694 } __attribute__((packed, aligned(4)));
697 * brief the data structure of SAS Diagnostic Execute Command
698 * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
700 struct sas_diag_execute_req {
702 __le32 cmdtype_cmddesc_phyid;
705 __le32 codepat_errmsk;
709 } __attribute__((packed, aligned(4)));
711 #define SAS_DIAG_PARAM_BYTES 24
714 * brief the data structure of Set Device State Command
715 * use to describe MPI Set Device State Command (64 bytes)
717 struct set_dev_state_req {
722 } __attribute__((packed, aligned(4)));
725 * brief the data structure of SATA Start Command
726 * use to describe MPI SATA IO Start Command (64 bytes)
727 * Note: This structure is common for normal / encryption I/O
730 struct sata_start_req {
734 __le32 ncqtag_atap_dir_m_dad;
735 struct host_to_dev_fis sata_fis;
737 u32 reserved2; /* dword 11. rsvd for normal I/O. */
738 /* EPLE Descl for enc I/O */
739 u32 addr_low; /* dword 12. rsvd for enc I/O */
740 u32 addr_high; /* dword 13. reserved for enc I/O */
741 __le32 len; /* dword 14: length for normal I/O. */
742 /* EPLE Desch for enc I/O */
743 __le32 esgl; /* dword 15. rsvd for enc I/O */
744 __le32 atapi_scsi_cdb[4]; /* dword 16-19. rsvd for enc I/O */
745 /* The below fields are reserved for normal I/O */
746 __le32 key_index_mode; /* dword 20 */
747 __le32 sector_cnt_enss;/* dword 21 */
748 __le32 keytagl; /* dword 22 */
749 __le32 keytagh; /* dword 23 */
750 __le32 twk_val0; /* dword 24 */
751 __le32 twk_val1; /* dword 25 */
752 __le32 twk_val2; /* dword 26 */
753 __le32 twk_val3; /* dword 27 */
754 __le32 enc_addr_low; /* dword 28. Encryption SGL address high */
755 __le32 enc_addr_high; /* dword 29. Encryption SGL address low */
756 __le32 enc_len; /* dword 30. Encryption length */
757 __le32 enc_esgl; /* dword 31. Encryption esgl bit */
758 } __attribute__((packed, aligned(4)));
761 * brief the data structure of SSP INI TM Start Command
762 * use to describe MPI SSP INI TM Start Command (64 bytes)
764 struct ssp_ini_tm_start_req {
772 } __attribute__((packed, aligned(4)));
774 struct ssp_info_unit {
775 u8 lun[8];/* SCSI Logical Unit Number */
776 u8 reserved1;/* reserved */
778 /* B7 : enabledFirstBurst */
779 /* B6-3 : taskPriority */
780 /* B2-0 : taskAttribute */
781 u8 reserved2; /* reserved */
782 u8 additional_cdb_len;
783 /* B7-2 : additional_cdb_len */
784 /* B1-0 : reserved */
785 u8 cdb[16];/* The SCSI CDB up to 16 bytes length */
786 } __attribute__((packed, aligned(4)));
789 * brief the data structure of SSP INI IO Start Command
790 * use to describe MPI SSP INI IO Start Command (64 bytes)
791 * Note: This structure is common for normal / encryption I/O
793 struct ssp_ini_io_start_req {
797 __le32 dad_dir_m_tlr;
798 struct ssp_info_unit ssp_iu;
799 __le32 addr_low; /* dword 12: sgl low for normal I/O. */
800 /* epl_descl for encryption I/O */
801 __le32 addr_high; /* dword 13: sgl hi for normal I/O */
802 /* dpl_descl for encryption I/O */
803 __le32 len; /* dword 14: len for normal I/O. */
804 /* edpl_desch for encryption I/O */
805 __le32 esgl; /* dword 15: ESGL bit for normal I/O. */
806 /* user defined tag mask for enc I/O */
807 /* The below fields are reserved for normal I/O */
808 u8 udt[12]; /* dword 16-18 */
809 __le32 sectcnt_ios; /* dword 19 */
810 __le32 key_cmode; /* dword 20 */
811 __le32 ks_enss; /* dword 21 */
812 __le32 keytagl; /* dword 22 */
813 __le32 keytagh; /* dword 23 */
814 __le32 twk_val0; /* dword 24 */
815 __le32 twk_val1; /* dword 25 */
816 __le32 twk_val2; /* dword 26 */
817 __le32 twk_val3; /* dword 27 */
818 __le32 enc_addr_low; /* dword 28: Encryption sgl addr low */
819 __le32 enc_addr_high; /* dword 29: Encryption sgl addr hi */
820 __le32 enc_len; /* dword 30: Encryption length */
821 __le32 enc_esgl; /* dword 31: ESGL bit for encryption */
822 } __attribute__((packed, aligned(4)));
825 * brief the data structure for SSP_INI_DIF_ENC_IO COMMAND
826 * use to initiate SSP I/O operation with optional DIF/ENC
828 struct ssp_dif_enc_io_req {
841 __le32 dpl_desl_ndplr;
843 __le32 uum_uuv_bss_difbits;
858 } __attribute__((packed, aligned(4)));
861 * brief the data structure of Firmware download
862 * use to describe MPI FW DOWNLOAD Command (64 bytes)
864 struct fw_flash_Update_req {
866 __le32 cur_image_offset;
867 __le32 cur_image_len;
868 __le32 total_image_len;
875 } __attribute__((packed, aligned(4)));
877 #define FWFLASH_IOMB_RESERVED_LEN 0x07
879 * brief the data structure of FW_FLASH_UPDATE Response
880 * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
883 struct fw_flash_Update_resp {
887 } __attribute__((packed, aligned(4)));
890 * brief the data structure of Get NVM Data Command
891 * use to get data from NVM in HBA(64 bytes)
893 struct get_nvm_data_req {
902 } __attribute__((packed, aligned(4)));
904 struct set_nvm_data_req {
913 } __attribute__((packed, aligned(4)));
916 * brief the data structure for SET CONTROLLER CONFIG COMMAND
917 * use to modify controller configuration
919 struct set_ctrl_cfg_req {
923 } __attribute__((packed, aligned(4)));
926 * brief the data structure for GET CONTROLLER CONFIG COMMAND
927 * use to get controller configuration page
929 struct get_ctrl_cfg_req {
934 } __attribute__((packed, aligned(4)));
937 * brief the data structure for KEK_MANAGEMENT COMMAND
938 * use for KEK management
940 struct kek_mgmt_req {
942 __le32 new_curidx_ksop;
946 } __attribute__((packed, aligned(4)));
949 * brief the data structure for DEK_MANAGEMENT COMMAND
950 * use for DEK management
952 struct dek_mgmt_req {
961 } __attribute__((packed, aligned(4)));
964 * brief the data structure for SET PHY PROFILE COMMAND
965 * use to retrive phy specific information
967 struct set_phy_profile_req {
971 } __attribute__((packed, aligned(4)));
974 * brief the data structure for GET PHY PROFILE COMMAND
975 * use to retrive phy specific information
977 struct get_phy_profile_req {
981 } __attribute__((packed, aligned(4)));
984 * brief the data structure for EXT FLASH PARTITION
985 * use to manage ext flash partition
987 struct ext_flash_partition_req {
998 } __attribute__((packed, aligned(4)));
1000 #define TWI_DEVICE 0x0
1001 #define C_SEEPROM 0x1
1002 #define VPD_FLASH 0x4
1003 #define AAP1_RDUMP 0x5
1004 #define IOP_RDUMP 0x6
1005 #define EXPAN_ROM 0x7
1007 #define IPMode 0x80000000
1008 #define NVMD_TYPE 0x0000000F
1009 #define NVMD_STAT 0x0000FFFF
1010 #define NVMD_LEN 0xFF000000
1012 * brief the data structure of Get NVMD Data Response
1013 * use to describe MPI Get NVMD Data Response (64 bytes)
1015 struct get_nvm_data_resp {
1017 __le32 ir_tda_bn_dps_das_nvm;
1019 __le32 nvm_data[12];
1020 } __attribute__((packed, aligned(4)));
1023 * brief the data structure of SAS Diagnostic Start/End Response
1024 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
1027 struct sas_diag_start_end_resp {
1031 } __attribute__((packed, aligned(4)));
1034 * brief the data structure of SAS Diagnostic Execute Response
1035 * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
1038 struct sas_diag_execute_resp {
1040 __le32 cmdtype_cmddesc_phyid;
1044 } __attribute__((packed, aligned(4)));
1047 * brief the data structure of Set Device State Response
1048 * use to describe MPI Set Device State Response (64 bytes)
1051 struct set_dev_state_resp {
1057 } __attribute__((packed, aligned(4)));
1059 /* new outbound structure for spcv - begins */
1061 * brief the data structure for SET CONTROLLER CONFIG COMMAND
1062 * use to modify controller configuration
1064 struct set_ctrl_cfg_resp {
1067 __le32 err_qlfr_pgcd;
1069 } __attribute__((packed, aligned(4)));
1071 struct get_ctrl_cfg_resp {
1075 __le32 confg_page[12];
1076 } __attribute__((packed, aligned(4)));
1078 struct kek_mgmt_resp {
1081 __le32 kidx_new_curr_ksop;
1084 } __attribute__((packed, aligned(4)));
1086 struct dek_mgmt_resp {
1089 __le32 kekidx_tbls_dsop;
1093 } __attribute__((packed, aligned(4)));
1095 struct get_phy_profile_resp {
1099 __le32 ppc_specific_rsp[12];
1100 } __attribute__((packed, aligned(4)));
1102 struct flash_op_ext_resp {
1107 __le32 epart_sect_size;
1109 } __attribute__((packed, aligned(4)));
1111 struct set_phy_profile_resp {
1115 __le32 ppc_specific_rsp[12];
1116 } __attribute__((packed, aligned(4)));
1118 struct ssp_coalesced_comp_resp {
1124 __le32 add_tag_ssp_tag[10];
1125 } __attribute__((packed, aligned(4)));
1127 /* new outbound structure for spcv - ends */
1129 /* brief data structure for SAS protocol timer configuration page.
1132 struct SASProtocolTimerConfig {
1133 __le32 pageCode; /* 0 */
1134 __le32 MST_MSI; /* 1 */
1135 __le32 STP_SSP_MCT_TMO; /* 2 */
1136 __le32 STP_FRM_TMO; /* 3 */
1137 __le32 STP_IDLE_TMO; /* 4 */
1138 __le32 OPNRJT_RTRY_INTVL; /* 5 */
1139 __le32 Data_Cmd_OPNRJT_RTRY_TMO; /* 6 */
1140 __le32 Data_Cmd_OPNRJT_RTRY_THR; /* 7 */
1141 __le32 MAX_AIP; /* 8 */
1142 } __attribute__((packed, aligned(4)));
1144 typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
1146 #define NDS_BITS 0x0F
1147 #define PDS_BITS 0xF0
1153 #define HW_EVENT_RESET_START 0x01
1154 #define HW_EVENT_CHIP_RESET_COMPLETE 0x02
1155 #define HW_EVENT_PHY_STOP_STATUS 0x03
1156 #define HW_EVENT_SAS_PHY_UP 0x04
1157 #define HW_EVENT_SATA_PHY_UP 0x05
1158 #define HW_EVENT_SATA_SPINUP_HOLD 0x06
1159 #define HW_EVENT_PHY_DOWN 0x07
1160 #define HW_EVENT_PORT_INVALID 0x08
1161 #define HW_EVENT_BROADCAST_CHANGE 0x09
1162 #define HW_EVENT_PHY_ERROR 0x0A
1163 #define HW_EVENT_BROADCAST_SES 0x0B
1164 #define HW_EVENT_INBOUND_CRC_ERROR 0x0C
1165 #define HW_EVENT_HARD_RESET_RECEIVED 0x0D
1166 #define HW_EVENT_MALFUNCTION 0x0E
1167 #define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
1168 #define HW_EVENT_BROADCAST_EXP 0x10
1169 #define HW_EVENT_PHY_START_STATUS 0x11
1170 #define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
1171 #define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
1172 #define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
1173 #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
1174 #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
1175 #define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
1176 #define HW_EVENT_PORT_RECOVER 0x18
1177 #define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
1178 #define HW_EVENT_PORT_RESET_COMPLETE 0x20
1179 #define EVENT_BROADCAST_ASYNCH_EVENT 0x21
1182 #define PORT_NOT_ESTABLISHED 0x00
1183 #define PORT_VALID 0x01
1184 #define PORT_LOSTCOMM 0x02
1185 #define PORT_IN_RESET 0x04
1186 #define PORT_3RD_PARTY_RESET 0x07
1187 #define PORT_INVALID 0x08
1190 * SSP/SMP/SATA IO Completion Status values
1193 #define IO_SUCCESS 0x00
1194 #define IO_ABORTED 0x01
1195 #define IO_OVERFLOW 0x02
1196 #define IO_UNDERFLOW 0x03
1197 #define IO_FAILED 0x04
1198 #define IO_ABORT_RESET 0x05
1199 #define IO_NOT_VALID 0x06
1200 #define IO_NO_DEVICE 0x07
1201 #define IO_ILLEGAL_PARAMETER 0x08
1202 #define IO_LINK_FAILURE 0x09
1203 #define IO_PROG_ERROR 0x0A
1205 #define IO_EDC_IN_ERROR 0x0B
1206 #define IO_EDC_OUT_ERROR 0x0C
1207 #define IO_ERROR_HW_TIMEOUT 0x0D
1208 #define IO_XFER_ERROR_BREAK 0x0E
1209 #define IO_XFER_ERROR_PHY_NOT_READY 0x0F
1210 #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
1211 #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
1212 #define IO_OPEN_CNX_ERROR_BREAK 0x12
1213 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
1214 #define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
1215 #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
1216 #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
1217 #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
1218 /* This error code 0x18 is not used on SPCv */
1219 #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
1220 #define IO_XFER_ERROR_NAK_RECEIVED 0x19
1221 #define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
1222 #define IO_XFER_ERROR_PEER_ABORTED 0x1B
1223 #define IO_XFER_ERROR_RX_FRAME 0x1C
1224 #define IO_XFER_ERROR_DMA 0x1D
1225 #define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
1226 #define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
1227 #define IO_XFER_ERROR_SATA 0x20
1229 /* This error code 0x22 is not used on SPCv */
1230 #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
1231 #define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
1232 #define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
1233 #define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
1234 /* This error code 0x25 is not used on SPCv */
1235 #define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
1236 #define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
1237 #define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
1238 #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
1239 #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
1241 /* The following error code 0x31 and 0x32 are not using (obsolete) */
1242 #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
1243 #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
1245 #define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
1246 #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
1247 #define IO_XFER_CMD_FRAME_ISSUED 0x36
1248 #define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
1249 #define IO_PORT_IN_RESET 0x38
1250 #define IO_DS_NON_OPERATIONAL 0x39
1251 #define IO_DS_IN_RECOVERY 0x3A
1252 #define IO_TM_TAG_NOT_FOUND 0x3B
1253 #define IO_XFER_PIO_SETUP_ERROR 0x3C
1254 #define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
1255 #define IO_DS_IN_ERROR 0x3E
1256 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
1257 #define IO_ABORT_IN_PROGRESS 0x40
1258 #define IO_ABORT_DELAYED 0x41
1259 #define IO_INVALID_LENGTH 0x42
1261 /********** additional response event values *****************/
1263 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT 0x43
1264 #define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED 0x44
1265 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO 0x45
1266 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST 0x46
1267 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE 0x47
1268 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48
1269 #define IO_DS_INVALID 0x49
1270 /* WARNING: the value is not contiguous from here */
1271 #define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR 0x52
1272 #define IO_XFER_DMA_ACTIVATE_TIMEOUT 0x53
1273 #define IO_XFER_ERROR_INTERNAL_CRC_ERROR 0x54
1274 #define MPI_IO_RQE_BUSY_FULL 0x55
1275 #define IO_XFER_ERR_EOB_DATA_OVERRUN 0x56
1276 #define IO_XFER_ERROR_INVALID_SSP_RSP_FRAME 0x57
1277 #define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED 0x58
1279 #define MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004
1280 #define MPI_ERR_ATAPI_DEVICE_BUSY 0x1024
1282 #define IO_XFR_ERROR_DEK_KEY_CACHE_MISS 0x2040
1284 * An encryption IO request failed due to DEK Key Tag mismatch.
1285 * The key tag supplied in the encryption IOMB does not match with
1286 * the Key Tag in the referenced DEK Entry.
1288 #define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH 0x2041
1289 #define IO_XFR_ERROR_CIPHER_MODE_INVALID 0x2042
1291 * An encryption I/O request failed because the initial value (IV)
1292 * in the unwrapped DEK blob didn't match the IV used to unwrap it.
1294 #define IO_XFR_ERROR_DEK_IV_MISMATCH 0x2043
1295 /* An encryption I/O request failed due to an internal RAM ECC or
1296 * interface error while unwrapping the DEK. */
1297 #define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR 0x2044
1298 /* An encryption I/O request failed due to an internal RAM ECC or
1299 * interface error while unwrapping the DEK. */
1300 #define IO_XFR_ERROR_INTERNAL_RAM 0x2045
1302 * An encryption I/O request failed
1303 * because the DEK index specified in the I/O was outside the bounds of
1304 * the total number of entries in the host DEK table.
1306 #define IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046
1308 /* define DIF IO response error status code */
1309 #define IO_XFR_ERROR_DIF_MISMATCH 0x3000
1310 #define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001
1311 #define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002
1312 #define IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003
1314 /* define operator management response status and error qualifier code */
1315 #define OPR_MGMT_OP_NOT_SUPPORTED 0x2060
1316 #define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061
1317 #define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062
1318 #define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063
1319 #define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064
1320 #define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL 0x2022
1321 #define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE 0x2023
1322 /***************** additional response event values ***************/
1324 /* WARNING: This error code must always be the last number.
1325 * If you add error code, modify this code also
1326 * It is used as an index
1328 #define IO_ERROR_UNKNOWN_GENERIC 0x2023
1330 /* MSGU CONFIGURATION TABLE*/
1332 #define SPCv_MSGU_CFG_TABLE_UPDATE 0x001
1333 #define SPCv_MSGU_CFG_TABLE_RESET 0x002
1334 #define SPCv_MSGU_CFG_TABLE_FREEZE 0x004
1335 #define SPCv_MSGU_CFG_TABLE_UNFREEZE 0x008
1336 #define MSGU_IBDB_SET 0x00
1337 #define MSGU_HOST_INT_STATUS 0x08
1338 #define MSGU_HOST_INT_MASK 0x0C
1339 #define MSGU_IOPIB_INT_STATUS 0x18
1340 #define MSGU_IOPIB_INT_MASK 0x1C
1341 #define MSGU_IBDB_CLEAR 0x20
1343 #define MSGU_MSGU_CONTROL 0x24
1344 #define MSGU_ODR 0x20
1345 #define MSGU_ODCR 0x28
1347 #define MSGU_ODMR 0x30
1348 #define MSGU_ODMR_U 0x34
1349 #define MSGU_ODMR_CLR 0x38
1350 #define MSGU_ODMR_CLR_U 0x3C
1351 #define MSGU_OD_RSVD 0x40
1353 #define MSGU_SCRATCH_PAD_0 0x44
1354 #define MSGU_SCRATCH_PAD_1 0x48
1355 #define MSGU_SCRATCH_PAD_2 0x4C
1356 #define MSGU_SCRATCH_PAD_3 0x50
1357 #define MSGU_HOST_SCRATCH_PAD_0 0x54
1358 #define MSGU_HOST_SCRATCH_PAD_1 0x58
1359 #define MSGU_HOST_SCRATCH_PAD_2 0x5C
1360 #define MSGU_HOST_SCRATCH_PAD_3 0x60
1361 #define MSGU_HOST_SCRATCH_PAD_4 0x64
1362 #define MSGU_HOST_SCRATCH_PAD_5 0x68
1363 #define MSGU_HOST_SCRATCH_PAD_6 0x6C
1364 #define MSGU_HOST_SCRATCH_PAD_7 0x70
1366 /* bit definition for ODMR register */
1367 #define ODMR_MASK_ALL 0xFFFFFFFF/* mask all
1369 #define ODMR_CLEAR_ALL 0 /* clear all
1371 /* bit definition for ODCR register */
1372 #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all
1374 /* MSIX Interupts */
1375 #define MSIX_TABLE_OFFSET 0x2000
1376 #define MSIX_TABLE_ELEMENT_SIZE 0x10
1377 #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
1378 #define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + \
1379 MSIX_INTERRUPT_CONTROL_OFFSET)
1380 #define MSIX_INTERRUPT_DISABLE 0x1
1381 #define MSIX_INTERRUPT_ENABLE 0x0
1383 /* state definition for Scratch Pad1 register */
1384 #define SCRATCH_PAD_RAAE_READY 0x3
1385 #define SCRATCH_PAD_ILA_READY 0xC
1386 #define SCRATCH_PAD_BOOT_LOAD_SUCCESS 0x0
1387 #define SCRATCH_PAD_IOP0_READY 0xC00
1388 #define SCRATCH_PAD_IOP1_READY 0x3000
1389 #define SCRATCH_PAD_MIPSALL_READY (SCRATCH_PAD_IOP1_READY | \
1390 SCRATCH_PAD_IOP0_READY | \
1391 SCRATCH_PAD_RAAE_READY)
1393 /* boot loader state */
1394 #define SCRATCH_PAD1_BOOTSTATE_MASK 0x70 /* Bit 4-6 */
1395 #define SCRATCH_PAD1_BOOTSTATE_SUCESS 0x0 /* Load successful */
1396 #define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM 0x10 /* HDA SEEPROM */
1397 #define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP 0x20 /* HDA BootStrap Pins */
1398 #define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET 0x30 /* HDA Soft Reset */
1399 #define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR 0x40 /* HDA critical error */
1400 #define SCRATCH_PAD1_BOOTSTATE_R1 0x50 /* Reserved */
1401 #define SCRATCH_PAD1_BOOTSTATE_R2 0x60 /* Reserved */
1402 #define SCRATCH_PAD1_BOOTSTATE_FATAL 0x70 /* Fatal Error */
1404 /* state definition for Scratch Pad2 register */
1405 #define SCRATCH_PAD2_POR 0x00 /* power on state */
1406 #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
1407 #define SCRATCH_PAD2_ERR 0x02 /* error state */
1408 #define SCRATCH_PAD2_RDY 0x03 /* ready state */
1409 #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW rdy for soft reset flag */
1410 #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
1411 #define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2
1412 Mask, bit1-0 State */
1413 #define SCRATCH_PAD2_RESERVED 0x000003FC/* Scratch Pad1
1414 Reserved bit 2 to 9 */
1416 #define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */
1417 #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */
1419 /* main configuration offset - byte offset */
1420 #define MAIN_SIGNATURE_OFFSET 0x00 /* DWORD 0x00 */
1421 #define MAIN_INTERFACE_REVISION 0x04 /* DWORD 0x01 */
1422 #define MAIN_FW_REVISION 0x08 /* DWORD 0x02 */
1423 #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C /* DWORD 0x03 */
1424 #define MAIN_MAX_SGL_OFFSET 0x10 /* DWORD 0x04 */
1425 #define MAIN_CNTRL_CAP_OFFSET 0x14 /* DWORD 0x05 */
1426 #define MAIN_GST_OFFSET 0x18 /* DWORD 0x06 */
1427 #define MAIN_IBQ_OFFSET 0x1C /* DWORD 0x07 */
1428 #define MAIN_OBQ_OFFSET 0x20 /* DWORD 0x08 */
1429 #define MAIN_IQNPPD_HPPD_OFFSET 0x24 /* DWORD 0x09 */
1431 /* 0x28 - 0x4C - RSVD */
1432 #define MAIN_EVENT_CRC_CHECK 0x48 /* DWORD 0x12 */
1433 #define MAIN_EVENT_LOG_ADDR_HI 0x50 /* DWORD 0x14 */
1434 #define MAIN_EVENT_LOG_ADDR_LO 0x54 /* DWORD 0x15 */
1435 #define MAIN_EVENT_LOG_BUFF_SIZE 0x58 /* DWORD 0x16 */
1436 #define MAIN_EVENT_LOG_OPTION 0x5C /* DWORD 0x17 */
1437 #define MAIN_PCS_EVENT_LOG_ADDR_HI 0x60 /* DWORD 0x18 */
1438 #define MAIN_PCS_EVENT_LOG_ADDR_LO 0x64 /* DWORD 0x19 */
1439 #define MAIN_PCS_EVENT_LOG_BUFF_SIZE 0x68 /* DWORD 0x1A */
1440 #define MAIN_PCS_EVENT_LOG_OPTION 0x6C /* DWORD 0x1B */
1441 #define MAIN_FATAL_ERROR_INTERRUPT 0x70 /* DWORD 0x1C */
1442 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74 /* DWORD 0x1D */
1443 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78 /* DWORD 0x1E */
1444 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C /* DWORD 0x1F */
1445 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80 /* DWORD 0x20 */
1446 #define MAIN_GPIO_LED_FLAGS_OFFSET 0x84 /* DWORD 0x21 */
1447 #define MAIN_ANALOG_SETUP_OFFSET 0x88 /* DWORD 0x22 */
1449 #define MAIN_INT_VECTOR_TABLE_OFFSET 0x8C /* DWORD 0x23 */
1450 #define MAIN_SAS_PHY_ATTR_TABLE_OFFSET 0x90 /* DWORD 0x24 */
1451 #define MAIN_PORT_RECOVERY_TIMER 0x94 /* DWORD 0x25 */
1452 #define MAIN_INT_REASSERTION_DELAY 0x98 /* DWORD 0x26 */
1453 #define MAIN_MPI_ILA_RELEASE_TYPE 0xA4 /* DWORD 0x29 */
1454 #define MAIN_MPI_INACTIVE_FW_VERSION 0XB0 /* DWORD 0x2C */
1456 /* Gereral Status Table offset - byte offset */
1457 #define GST_GSTLEN_MPIS_OFFSET 0x00
1458 #define GST_IQ_FREEZE_STATE0_OFFSET 0x04
1459 #define GST_IQ_FREEZE_STATE1_OFFSET 0x08
1460 #define GST_MSGUTCNT_OFFSET 0x0C
1461 #define GST_IOPTCNT_OFFSET 0x10
1462 /* 0x14 - 0x34 - RSVD */
1463 #define GST_GPIO_INPUT_VAL 0x38
1464 /* 0x3c - 0x40 - RSVD */
1465 #define GST_RERRINFO_OFFSET0 0x44
1466 #define GST_RERRINFO_OFFSET1 0x48
1467 #define GST_RERRINFO_OFFSET2 0x4c
1468 #define GST_RERRINFO_OFFSET3 0x50
1469 #define GST_RERRINFO_OFFSET4 0x54
1470 #define GST_RERRINFO_OFFSET5 0x58
1471 #define GST_RERRINFO_OFFSET6 0x5c
1472 #define GST_RERRINFO_OFFSET7 0x60
1474 /* General Status Table - MPI state */
1475 #define GST_MPI_STATE_UNINIT 0x00
1476 #define GST_MPI_STATE_INIT 0x01
1477 #define GST_MPI_STATE_TERMINATION 0x02
1478 #define GST_MPI_STATE_ERROR 0x03
1479 #define GST_MPI_STATE_MASK 0x07
1481 /* Per SAS PHY Attributes */
1483 #define PSPA_PHYSTATE0_OFFSET 0x00 /* Dword V */
1484 #define PSPA_OB_HW_EVENT_PID0_OFFSET 0x04 /* DWORD V+1 */
1485 #define PSPA_PHYSTATE1_OFFSET 0x08 /* Dword V+2 */
1486 #define PSPA_OB_HW_EVENT_PID1_OFFSET 0x0C /* DWORD V+3 */
1487 #define PSPA_PHYSTATE2_OFFSET 0x10 /* Dword V+4 */
1488 #define PSPA_OB_HW_EVENT_PID2_OFFSET 0x14 /* DWORD V+5 */
1489 #define PSPA_PHYSTATE3_OFFSET 0x18 /* Dword V+6 */
1490 #define PSPA_OB_HW_EVENT_PID3_OFFSET 0x1C /* DWORD V+7 */
1491 #define PSPA_PHYSTATE4_OFFSET 0x20 /* Dword V+8 */
1492 #define PSPA_OB_HW_EVENT_PID4_OFFSET 0x24 /* DWORD V+9 */
1493 #define PSPA_PHYSTATE5_OFFSET 0x28 /* Dword V+10 */
1494 #define PSPA_OB_HW_EVENT_PID5_OFFSET 0x2C /* DWORD V+11 */
1495 #define PSPA_PHYSTATE6_OFFSET 0x30 /* Dword V+12 */
1496 #define PSPA_OB_HW_EVENT_PID6_OFFSET 0x34 /* DWORD V+13 */
1497 #define PSPA_PHYSTATE7_OFFSET 0x38 /* Dword V+14 */
1498 #define PSPA_OB_HW_EVENT_PID7_OFFSET 0x3C /* DWORD V+15 */
1499 #define PSPA_PHYSTATE8_OFFSET 0x40 /* DWORD V+16 */
1500 #define PSPA_OB_HW_EVENT_PID8_OFFSET 0x44 /* DWORD V+17 */
1501 #define PSPA_PHYSTATE9_OFFSET 0x48 /* DWORD V+18 */
1502 #define PSPA_OB_HW_EVENT_PID9_OFFSET 0x4C /* DWORD V+19 */
1503 #define PSPA_PHYSTATE10_OFFSET 0x50 /* DWORD V+20 */
1504 #define PSPA_OB_HW_EVENT_PID10_OFFSET 0x54 /* DWORD V+21 */
1505 #define PSPA_PHYSTATE11_OFFSET 0x58 /* DWORD V+22 */
1506 #define PSPA_OB_HW_EVENT_PID11_OFFSET 0x5C /* DWORD V+23 */
1507 #define PSPA_PHYSTATE12_OFFSET 0x60 /* DWORD V+24 */
1508 #define PSPA_OB_HW_EVENT_PID12_OFFSET 0x64 /* DWORD V+25 */
1509 #define PSPA_PHYSTATE13_OFFSET 0x68 /* DWORD V+26 */
1510 #define PSPA_OB_HW_EVENT_PID13_OFFSET 0x6c /* DWORD V+27 */
1511 #define PSPA_PHYSTATE14_OFFSET 0x70 /* DWORD V+28 */
1512 #define PSPA_OB_HW_EVENT_PID14_OFFSET 0x74 /* DWORD V+29 */
1513 #define PSPA_PHYSTATE15_OFFSET 0x78 /* DWORD V+30 */
1514 #define PSPA_OB_HW_EVENT_PID15_OFFSET 0x7c /* DWORD V+31 */
1517 /* inbound queue configuration offset - byte offset */
1518 #define IB_PROPERITY_OFFSET 0x00
1519 #define IB_BASE_ADDR_HI_OFFSET 0x04
1520 #define IB_BASE_ADDR_LO_OFFSET 0x08
1521 #define IB_CI_BASE_ADDR_HI_OFFSET 0x0C
1522 #define IB_CI_BASE_ADDR_LO_OFFSET 0x10
1523 #define IB_PIPCI_BAR 0x14
1524 #define IB_PIPCI_BAR_OFFSET 0x18
1525 #define IB_RESERVED_OFFSET 0x1C
1527 /* outbound queue configuration offset - byte offset */
1528 #define OB_PROPERITY_OFFSET 0x00
1529 #define OB_BASE_ADDR_HI_OFFSET 0x04
1530 #define OB_BASE_ADDR_LO_OFFSET 0x08
1531 #define OB_PI_BASE_ADDR_HI_OFFSET 0x0C
1532 #define OB_PI_BASE_ADDR_LO_OFFSET 0x10
1533 #define OB_CIPCI_BAR 0x14
1534 #define OB_CIPCI_BAR_OFFSET 0x18
1535 #define OB_INTERRUPT_COALES_OFFSET 0x1C
1536 #define OB_DYNAMIC_COALES_OFFSET 0x20
1537 #define OB_PROPERTY_INT_ENABLE 0x40000000
1539 #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
1540 #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
1541 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
1542 #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
1543 #define PCIE_EVENT_INTERRUPT 0x003044
1544 #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
1545 #define PCIE_ERROR_INTERRUPT 0x00304C
1547 /* SPCV soft reset */
1548 #define SPC_REG_SOFT_RESET 0x00001000
1549 #define SPCv_NORMAL_RESET_VALUE 0x1
1551 #define SPCv_SOFT_RESET_READ_MASK 0xC0
1552 #define SPCv_SOFT_RESET_NO_RESET 0x0
1553 #define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED 0x40
1554 #define SPCv_SOFT_RESET_HDA_MODE_OCCURED 0x80
1555 #define SPCv_SOFT_RESET_CHIP_RESET_OCCURED 0xC0
1557 /* signature definition for host scratch pad0 register */
1558 #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
1559 /* Signature for Soft Reset */
1561 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
1562 #define SPC_REG_RESET 0x000000/* reset register */
1564 /* bit definition for SPC_RESET register */
1565 #define SPC_REG_RESET_OSSP 0x00000001
1566 #define SPC_REG_RESET_RAAE 0x00000002
1567 #define SPC_REG_RESET_PCS_SPBC 0x00000004
1568 #define SPC_REG_RESET_PCS_IOP_SS 0x00000008
1569 #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
1570 #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
1571 #define SPC_REG_RESET_PCS_LM 0x00000040
1572 #define SPC_REG_RESET_PCS 0x00000080
1573 #define SPC_REG_RESET_GSM 0x00000100
1574 #define SPC_REG_RESET_DDR2 0x00010000
1575 #define SPC_REG_RESET_BDMA_CORE 0x00020000
1576 #define SPC_REG_RESET_BDMA_SXCBI 0x00040000
1577 #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
1578 #define SPC_REG_RESET_PCIE_PWR 0x00100000
1579 #define SPC_REG_RESET_PCIE_SFT 0x00200000
1580 #define SPC_REG_RESET_PCS_SXCBI 0x00400000
1581 #define SPC_REG_RESET_LMS_SXCBI 0x00800000
1582 #define SPC_REG_RESET_PMIC_SXCBI 0x01000000
1583 #define SPC_REG_RESET_PMIC_CORE 0x02000000
1584 #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
1585 #define SPC_REG_RESET_DEVICE 0x80000000
1587 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
1588 #define SPCV_IBW_AXI_TRANSLATION_LOW 0x001010
1590 #define MBIC_AAP1_ADDR_BASE 0x060000
1591 #define MBIC_IOP_ADDR_BASE 0x070000
1592 #define GSM_ADDR_BASE 0x0700000
1593 /* Dynamic map through Bar4 - 0x00700000 */
1594 #define GSM_CONFIG_RESET 0x00000000
1595 #define RAM_ECC_DB_ERR 0x00000018
1596 #define GSM_READ_ADDR_PARITY_INDIC 0x00000058
1597 #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
1598 #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
1599 #define GSM_READ_ADDR_PARITY_CHECK 0x00000038
1600 #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
1601 #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
1603 #define RB6_ACCESS_REG 0x6A0000
1604 #define HDAC_EXEC_CMD 0x0002
1605 #define HDA_C_PA 0xcb
1606 #define HDA_SEQ_ID_BITS 0x00ff0000
1607 #define HDA_GSM_OFFSET_BITS 0x00FFFFFF
1608 #define HDA_GSM_CMD_OFFSET_BITS 0x42C0
1609 #define HDA_GSM_RSP_OFFSET_BITS 0x42E0
1611 #define MBIC_AAP1_ADDR_BASE 0x060000
1612 #define MBIC_IOP_ADDR_BASE 0x070000
1613 #define GSM_ADDR_BASE 0x0700000
1614 #define SPC_TOP_LEVEL_ADDR_BASE 0x000000
1615 #define GSM_CONFIG_RESET_VALUE 0x00003b00
1616 #define GPIO_ADDR_BASE 0x00090000
1617 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
1620 #define SPC_RB6_OFFSET 0x80C0
1621 /* Magic number of soft reset for RB6 */
1622 #define RB6_MAGIC_NUMBER_RST 0x1234
1624 /* Device Register status */
1625 #define DEVREG_SUCCESS 0x00
1626 #define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
1627 #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
1628 #define DEVREG_FAILURE_INVALID_PHY_ID 0x03
1629 #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
1630 #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
1631 #define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
1632 #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
1635 #define MEMBASE_II_SHIFT_REGISTER 0x1010