drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005-2015 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/slab.h>
  21 #include <linux/time.h>
  22 #include <linux/pci.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/ktime.h>
  29 #include <linux/reboot.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/byteorder.h>
  33 #include <scsi/scsi.h>
  34 #include <scsi/scsi_device.h>
  35 #include <scsi/scsi_cmnd.h>
  36 #include <scsi/scsi_host.h>
  37 #include <scsi/scsi_tcq.h>
  38 #include <scsi/scsi_dbg.h>
  39 #include <scsi/scsi_eh.h>
  40
  41 #define DRV_NAME "stex"
  42 #define ST_DRIVER_VERSION       "6.02.0000.01"
  43 #define ST_VER_MAJOR            6
  44 #define ST_VER_MINOR            02
  45 #define ST_OEM                          0000
  46 #define ST_BUILD_VER            01
  47
  48 enum {
  49         /* MU register offset */
  50         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  51         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  52         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  53         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  54         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  55         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  56         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  57         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  58         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  59         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  60
  61         YIOA_STATUS                             = 0x00,
  62         YH2I_INT                                = 0x20,
  63         YINT_EN                                 = 0x34,
  64         YI2H_INT                                = 0x9c,
  65         YI2H_INT_C                              = 0xa0,
  66         YH2I_REQ                                = 0xc0,
  67         YH2I_REQ_HI                             = 0xc4,
  68         PSCRATCH0                               = 0xb0,
  69         PSCRATCH1                               = 0xb4,
  70         PSCRATCH2                               = 0xb8,
  71         PSCRATCH3                               = 0xbc,
  72         PSCRATCH4                               = 0xc8,
  73         MAILBOX_BASE                    = 0x1000,
  74         MAILBOX_HNDSHK_STS              = 0x0,
  75
  76         /* MU register value */
  77         MU_INBOUND_DOORBELL_HANDSHAKE           = (1 << 0),
  78         MU_INBOUND_DOORBELL_REQHEADCHANGED      = (1 << 1),
  79         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = (1 << 2),
  80         MU_INBOUND_DOORBELL_HMUSTOPPED          = (1 << 3),
  81         MU_INBOUND_DOORBELL_RESET               = (1 << 4),
  82
  83         MU_OUTBOUND_DOORBELL_HANDSHAKE          = (1 << 0),
  84         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
  85         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = (1 << 2),
  86         MU_OUTBOUND_DOORBELL_BUSCHANGE          = (1 << 3),
  87         MU_OUTBOUND_DOORBELL_HASEVENT           = (1 << 4),
  88         MU_OUTBOUND_DOORBELL_REQUEST_RESET      = (1 << 27),
  89
  90         /* MU status code */
  91         MU_STATE_STARTING                       = 1,
  92         MU_STATE_STARTED                        = 2,
  93         MU_STATE_RESETTING                      = 3,
  94         MU_STATE_FAILED                         = 4,
  95         MU_STATE_STOP                           = 5,
  96         MU_STATE_NOCONNECT                      = 6,
  97
  98         MU_MAX_DELAY                            = 50,
  99         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
 100         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
 101         MU_HARD_RESET_WAIT                      = 30000,
 102         HMU_PARTNER_TYPE                        = 2,
 103
 104         /* firmware returned values */
 105         SRB_STATUS_SUCCESS                      = 0x01,
 106         SRB_STATUS_ERROR                        = 0x04,
 107         SRB_STATUS_BUSY                         = 0x05,
 108         SRB_STATUS_INVALID_REQUEST              = 0x06,
 109         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
 110         SRB_SEE_SENSE                           = 0x80,
 111
 112         /* task attribute */
 113         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
 114         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
 115         TASK_ATTRIBUTE_ORDERED                  = 0x2,
 116         TASK_ATTRIBUTE_ACA                      = 0x4,
 117 };
 118
 119 enum {
 120         SS_STS_NORMAL                           = 0x80000000,
 121         SS_STS_DONE                             = 0x40000000,
 122         SS_STS_HANDSHAKE                        = 0x20000000,
 123
 124         SS_HEAD_HANDSHAKE                       = 0x80,
 125
 126         SS_H2I_INT_RESET                        = 0x100,
 127
 128         SS_I2H_REQUEST_RESET                    = 0x2000,
 129
 130         SS_MU_OPERATIONAL                       = 0x80000000,
 131 };
 132
 133 enum {
 134         STEX_CDB_LENGTH                         = 16,
 135         STATUS_VAR_LEN                          = 128,
 136
 137         /* sg flags */
 138         SG_CF_EOT                               = 0x80, /* end of table */
 139         SG_CF_64B                               = 0x40, /* 64 bit item */
 140         SG_CF_HOST                              = 0x20, /* sg in host memory */
 141         MSG_DATA_DIR_ND                         = 0,
 142         MSG_DATA_DIR_IN                         = 1,
 143         MSG_DATA_DIR_OUT                        = 2,
 144
 145         st_shasta                               = 0,
 146         st_vsc                                  = 1,
 147         st_yosemite                             = 2,
 148         st_seq                                  = 3,
 149         st_yel                                  = 4,
 150         st_P3                                   = 5,
 151
 152         PASSTHRU_REQ_TYPE                       = 0x00000001,
 153         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 154         ST_INTERNAL_TIMEOUT                     = 180,
 155
 156         ST_TO_CMD                               = 0,
 157         ST_FROM_CMD                             = 1,
 158
 159         /* vendor specific commands of Promise */
 160         MGT_CMD                                 = 0xd8,
 161         SINBAND_MGT_CMD                         = 0xd9,
 162         ARRAY_CMD                               = 0xe0,
 163         CONTROLLER_CMD                          = 0xe1,
 164         DEBUGGING_CMD                           = 0xe2,
 165         PASSTHRU_CMD                            = 0xe3,
 166
 167         PASSTHRU_GET_ADAPTER                    = 0x05,
 168         PASSTHRU_GET_DRVVER                     = 0x10,
 169
 170         CTLR_CONFIG_CMD                         = 0x03,
 171         CTLR_SHUTDOWN                           = 0x0d,
 172
 173         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 174         CTLR_POWER_SAVING                       = 0x01,
 175
 176         PASSTHRU_SIGNATURE                      = 0x4e415041,
 177         MGT_CMD_SIGNATURE                       = 0xba,
 178
 179         INQUIRY_EVPD                            = 0x01,
 180
 181         ST_ADDITIONAL_MEM                       = 0x200000,
 182         ST_ADDITIONAL_MEM_MIN                   = 0x80000,
 183         PMIC_SHUTDOWN                           = 0x0D,
 184         PMIC_REUMSE                                     = 0x10,
 185         ST_IGNORED                                      = -1,
 186         ST_NOTHANDLED                           = 7,
 187         ST_S3                                           = 3,
 188         ST_S4                                           = 4,
 189         ST_S5                                           = 5,
 190         ST_S6                                           = 6,
 191 };
 192
 193 struct st_sgitem {
 194         u8 ctrl;        /* SG_CF_xxx */
 195         u8 reserved[3];
 196         __le32 count;
 197         __le64 addr;
 198 };
 199
 200 struct st_ss_sgitem {
 201         __le32 addr;
 202         __le32 addr_hi;
 203         __le32 count;
 204 };
 205
 206 struct st_sgtable {
 207         __le16 sg_count;
 208         __le16 max_sg_count;
 209         __le32 sz_in_byte;
 210 };
 211
 212 struct st_msg_header {
 213         __le64 handle;
 214         u8 flag;
 215         u8 channel;
 216         __le16 timeout;
 217         u32 reserved;
 218 };
 219
 220 struct handshake_frame {
 221         __le64 rb_phy;          /* request payload queue physical address */
 222         __le16 req_sz;          /* size of each request payload */
 223         __le16 req_cnt;         /* count of reqs the buffer can hold */
 224         __le16 status_sz;       /* size of each status payload */
 225         __le16 status_cnt;      /* count of status the buffer can hold */
 226         __le64 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 227         u8 partner_type;        /* who sends this frame */
 228         u8 reserved0[7];
 229         __le32 partner_ver_major;
 230         __le32 partner_ver_minor;
 231         __le32 partner_ver_oem;
 232         __le32 partner_ver_build;
 233         __le32 extra_offset;    /* NEW */
 234         __le32 extra_size;      /* NEW */
 235         __le32 scratch_size;
 236         u32 reserved1;
 237 };
 238
 239 struct req_msg {
 240         __le16 tag;
 241         u8 lun;
 242         u8 target;
 243         u8 task_attr;
 244         u8 task_manage;
 245         u8 data_dir;
 246         u8 payload_sz;          /* payload size in 4-byte, not used */
 247         u8 cdb[STEX_CDB_LENGTH];
 248         u32 variable[0];
 249 };
 250
 251 struct status_msg {
 252         __le16 tag;
 253         u8 lun;
 254         u8 target;
 255         u8 srb_status;
 256         u8 scsi_status;
 257         u8 reserved;
 258         u8 payload_sz;          /* payload size in 4-byte */
 259         u8 variable[STATUS_VAR_LEN];
 260 };
 261
 262 struct ver_info {
 263         u32 major;
 264         u32 minor;
 265         u32 oem;
 266         u32 build;
 267         u32 reserved[2];
 268 };
 269
 270 struct st_frame {
 271         u32 base[6];
 272         u32 rom_addr;
 273
 274         struct ver_info drv_ver;
 275         struct ver_info bios_ver;
 276
 277         u32 bus;
 278         u32 slot;
 279         u32 irq_level;
 280         u32 irq_vec;
 281         u32 id;
 282         u32 subid;
 283
 284         u32 dimm_size;
 285         u8 dimm_type;
 286         u8 reserved[3];
 287
 288         u32 channel;
 289         u32 reserved1;
 290 };
 291
 292 struct st_drvver {
 293         u32 major;
 294         u32 minor;
 295         u32 oem;
 296         u32 build;
 297         u32 signature[2];
 298         u8 console_id;
 299         u8 host_no;
 300         u8 reserved0[2];
 301         u32 reserved[3];
 302 };
 303
 304 struct st_ccb {
 305         struct req_msg *req;
 306         struct scsi_cmnd *cmd;
 307
 308         void *sense_buffer;
 309         unsigned int sense_bufflen;
 310         int sg_count;
 311
 312         u32 req_type;
 313         u8 srb_status;
 314         u8 scsi_status;
 315         u8 reserved[2];
 316 };
 317
 318 struct st_hba {
 319         void __iomem *mmio_base;        /* iomapped PCI memory space */
 320         void *dma_mem;
 321         dma_addr_t dma_handle;
 322         size_t dma_size;
 323
 324         struct Scsi_Host *host;
 325         struct pci_dev *pdev;
 326
 327         struct req_msg * (*alloc_rq) (struct st_hba *);
 328         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 329         void (*send) (struct st_hba *, struct req_msg *, u16);
 330
 331         u32 req_head;
 332         u32 req_tail;
 333         u32 status_head;
 334         u32 status_tail;
 335
 336         struct status_msg *status_buffer;
 337         void *copy_buffer; /* temp buffer for driver-handled commands */
 338         struct st_ccb *ccb;
 339         struct st_ccb *wait_ccb;
 340         __le32 *scratch;
 341
 342         char work_q_name[20];
 343         struct workqueue_struct *work_q;
 344         struct work_struct reset_work;
 345         wait_queue_head_t reset_waitq;
 346         unsigned int mu_status;
 347         unsigned int cardtype;
 348         int msi_enabled;
 349         int out_req_cnt;
 350         u32 extra_offset;
 351         u16 rq_count;
 352         u16 rq_size;
 353         u16 sts_count;
 354         u8  supports_pm;
 355         int msi_lock;
 356 };
 357
 358 struct st_card_info {
 359         struct req_msg * (*alloc_rq) (struct st_hba *);
 360         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 361         void (*send) (struct st_hba *, struct req_msg *, u16);
 362         unsigned int max_id;
 363         unsigned int max_lun;
 364         unsigned int max_channel;
 365         u16 rq_count;
 366         u16 rq_size;
 367         u16 sts_count;
 368 };
 369
 370 static int S6flag;
 371 static int stex_halt(struct notifier_block *nb, ulong event, void *buf);
 372 static struct notifier_block stex_notifier = {
 373         stex_halt, NULL, 0
 374 };
 375
 376 static int msi;
 377 module_param(msi, int, 0);
 378 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
 379
 380 static const char console_inq_page[] =
 381 {
 382         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 383         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 384         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 385         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 386         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 387         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 388         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 389         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 390 };
 391
 392 MODULE_AUTHOR("Ed Lin");
 393 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 394 MODULE_LICENSE("GPL");
 395 MODULE_VERSION(ST_DRIVER_VERSION);
 396
 397 static struct status_msg *stex_get_status(struct st_hba *hba)
 398 {
 399         struct status_msg *status = hba->status_buffer + hba->status_tail;
 400
 401         ++hba->status_tail;
 402         hba->status_tail %= hba->sts_count+1;
 403
 404         return status;
 405 }
 406
 407 static void stex_invalid_field(struct scsi_cmnd *cmd,
 408                                void (*done)(struct scsi_cmnd *))
 409 {
 410         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 411
 412         /* "Invalid field in cdb" */
 413         scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
 414                                 0x0);
 415         done(cmd);
 416 }
 417
 418 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 419 {
 420         struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
 421
 422         ++hba->req_head;
 423         hba->req_head %= hba->rq_count+1;
 424
 425         return req;
 426 }
 427
 428 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
 429 {
 430         return (struct req_msg *)(hba->dma_mem +
 431                 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
 432 }
 433
 434 static int stex_map_sg(struct st_hba *hba,
 435         struct req_msg *req, struct st_ccb *ccb)
 436 {
 437         struct scsi_cmnd *cmd;
 438         struct scatterlist *sg;
 439         struct st_sgtable *dst;
 440         struct st_sgitem *table;
 441         int i, nseg;
 442
 443         cmd = ccb->cmd;
 444         nseg = scsi_dma_map(cmd);
 445         BUG_ON(nseg < 0);
 446         if (nseg) {
 447                 dst = (struct st_sgtable *)req->variable;
 448
 449                 ccb->sg_count = nseg;
 450                 dst->sg_count = cpu_to_le16((u16)nseg);
 451                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 452                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 453
 454                 table = (struct st_sgitem *)(dst + 1);
 455                 scsi_for_each_sg(cmd, sg, nseg, i) {
 456                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 457                         table[i].addr = cpu_to_le64(sg_dma_address(sg));
 458                         table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 459                 }
 460                 table[--i].ctrl |= SG_CF_EOT;
 461         }
 462
 463         return nseg;
 464 }
 465
 466 static int stex_ss_map_sg(struct st_hba *hba,
 467         struct req_msg *req, struct st_ccb *ccb)
 468 {
 469         struct scsi_cmnd *cmd;
 470         struct scatterlist *sg;
 471         struct st_sgtable *dst;
 472         struct st_ss_sgitem *table;
 473         int i, nseg;
 474
 475         cmd = ccb->cmd;
 476         nseg = scsi_dma_map(cmd);
 477         BUG_ON(nseg < 0);
 478         if (nseg) {
 479                 dst = (struct st_sgtable *)req->variable;
 480
 481                 ccb->sg_count = nseg;
 482                 dst->sg_count = cpu_to_le16((u16)nseg);
 483                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 484                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 485
 486                 table = (struct st_ss_sgitem *)(dst + 1);
 487                 scsi_for_each_sg(cmd, sg, nseg, i) {
 488                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 489                         table[i].addr =
 490                                 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
 491                         table[i].addr_hi =
 492                                 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
 493                 }
 494         }
 495
 496         return nseg;
 497 }
 498
 499 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 500 {
 501         struct st_frame *p;
 502         size_t count = sizeof(struct st_frame);
 503
 504         p = hba->copy_buffer;
 505         scsi_sg_copy_to_buffer(ccb->cmd, p, count);
 506         memset(p->base, 0, sizeof(u32)*6);
 507         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 508         p->rom_addr = 0;
 509
 510         p->drv_ver.major = ST_VER_MAJOR;
 511         p->drv_ver.minor = ST_VER_MINOR;
 512         p->drv_ver.oem = ST_OEM;
 513         p->drv_ver.build = ST_BUILD_VER;
 514
 515         p->bus = hba->pdev->bus->number;
 516         p->slot = hba->pdev->devfn;
 517         p->irq_level = 0;
 518         p->irq_vec = hba->pdev->irq;
 519         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 520         p->subid =
 521                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 522
 523         scsi_sg_copy_from_buffer(ccb->cmd, p, count);
 524 }
 525
 526 static void
 527 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 528 {
 529         req->tag = cpu_to_le16(tag);
 530
 531         hba->ccb[tag].req = req;
 532         hba->out_req_cnt++;
 533
 534         writel(hba->req_head, hba->mmio_base + IMR0);
 535         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 536         readl(hba->mmio_base + IDBL); /* flush */
 537 }
 538
 539 static void
 540 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 541 {
 542         struct scsi_cmnd *cmd;
 543         struct st_msg_header *msg_h;
 544         dma_addr_t addr;
 545
 546         req->tag = cpu_to_le16(tag);
 547
 548         hba->ccb[tag].req = req;
 549         hba->out_req_cnt++;
 550
 551         cmd = hba->ccb[tag].cmd;
 552         msg_h = (struct st_msg_header *)req - 1;
 553         if (likely(cmd)) {
 554                 msg_h->channel = (u8)cmd->device->channel;
 555                 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
 556         }
 557         addr = hba->dma_handle + hba->req_head * hba->rq_size;
 558         addr += (hba->ccb[tag].sg_count+4)/11;
 559         msg_h->handle = cpu_to_le64(addr);
 560
 561         ++hba->req_head;
 562         hba->req_head %= hba->rq_count+1;
 563         if (hba->cardtype == st_P3) {
 564                 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 565                 writel(addr, hba->mmio_base + YH2I_REQ);
 566         } else {
 567                 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 568                 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
 569                 writel(addr, hba->mmio_base + YH2I_REQ);
 570                 readl(hba->mmio_base + YH2I_REQ); /* flush */
 571         }
 572 }
 573
 574 static void return_abnormal_state(struct st_hba *hba, int status)
 575 {
 576         struct st_ccb *ccb;
 577         unsigned long flags;
 578         u16 tag;
 579
 580         spin_lock_irqsave(hba->host->host_lock, flags);
 581         for (tag = 0; tag < hba->host->can_queue; tag++) {
 582                 ccb = &hba->ccb[tag];
 583                 if (ccb->req == NULL)
 584                         continue;
 585                 ccb->req = NULL;
 586                 if (ccb->cmd) {
 587                         scsi_dma_unmap(ccb->cmd);
 588                         ccb->cmd->result = status << 16;
 589                         ccb->cmd->scsi_done(ccb->cmd);
 590                         ccb->cmd = NULL;
 591                 }
 592         }
 593         spin_unlock_irqrestore(hba->host->host_lock, flags);
 594 }
 595 static int
 596 stex_slave_config(struct scsi_device *sdev)
 597 {
 598         sdev->use_10_for_rw = 1;
 599         sdev->use_10_for_ms = 1;
 600         blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
 601
 602         return 0;
 603 }
 604
 605 static int
 606 stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
 607 {
 608         struct st_hba *hba;
 609         struct Scsi_Host *host;
 610         unsigned int id, lun;
 611         struct req_msg *req;
 612         u16 tag;
 613
 614         host = cmd->device->host;
 615         id = cmd->device->id;
 616         lun = cmd->device->lun;
 617         hba = (struct st_hba *) &host->hostdata[0];
 618         if (hba->mu_status == MU_STATE_NOCONNECT) {
 619                 cmd->result = DID_NO_CONNECT;
 620                 done(cmd);
 621                 return 0;
 622         }
 623         if (unlikely(hba->mu_status != MU_STATE_STARTED))
 624                 return SCSI_MLQUEUE_HOST_BUSY;
 625
 626         switch (cmd->cmnd[0]) {
 627         case MODE_SENSE_10:
 628         {
 629                 static char ms10_caching_page[12] =
 630                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 631                 unsigned char page;
 632
 633                 page = cmd->cmnd[2] & 0x3f;
 634                 if (page == 0x8 || page == 0x3f) {
 635                         scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
 636                                                  sizeof(ms10_caching_page));
 637                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 638                         done(cmd);
 639                 } else
 640                         stex_invalid_field(cmd, done);
 641                 return 0;
 642         }
 643         case REPORT_LUNS:
 644                 /*
 645                  * The shasta firmware does not report actual luns in the
 646                  * target, so fail the command to force sequential lun scan.
 647                  * Also, the console device does not support this command.
 648                  */
 649                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 650                         stex_invalid_field(cmd, done);
 651                         return 0;
 652                 }
 653                 break;
 654         case TEST_UNIT_READY:
 655                 if (id == host->max_id - 1) {
 656                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 657                         done(cmd);
 658                         return 0;
 659                 }
 660                 break;
 661         case INQUIRY:
 662                 if (lun >= host->max_lun) {
 663                         cmd->result = DID_NO_CONNECT << 16;
 664                         done(cmd);
 665                         return 0;
 666                 }
 667                 if (id != host->max_id - 1)
 668                         break;
 669                 if (!lun && !cmd->device->channel &&
 670                         (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 671                         scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
 672                                                  sizeof(console_inq_page));
 673                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 674                         done(cmd);
 675                 } else
 676                         stex_invalid_field(cmd, done);
 677                 return 0;
 678         case PASSTHRU_CMD:
 679                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 680                         const struct st_drvver ver = {
 681                                 .major = ST_VER_MAJOR,
 682                                 .minor = ST_VER_MINOR,
 683                                 .oem = ST_OEM,
 684                                 .build = ST_BUILD_VER,
 685                                 .signature[0] = PASSTHRU_SIGNATURE,
 686                                 .console_id = host->max_id - 1,
 687                                 .host_no = hba->host->host_no,
 688                         };
 689                         size_t cp_len = sizeof(ver);
 690
 691                         cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
 692                         cmd->result = sizeof(ver) == cp_len ?
 693                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 694                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 695                         done(cmd);
 696                         return 0;
 697                 }
 698         default:
 699                 break;
 700         }
 701
 702         cmd->scsi_done = done;
 703
 704         tag = cmd->request->tag;
 705
 706         if (unlikely(tag >= host->can_queue))
 707                 return SCSI_MLQUEUE_HOST_BUSY;
 708
 709         req = hba->alloc_rq(hba);
 710
 711         req->lun = lun;
 712         req->target = id;
 713
 714         /* cdb */
 715         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 716
 717         if (cmd->sc_data_direction == DMA_FROM_DEVICE)
 718                 req->data_dir = MSG_DATA_DIR_IN;
 719         else if (cmd->sc_data_direction == DMA_TO_DEVICE)
 720                 req->data_dir = MSG_DATA_DIR_OUT;
 721         else
 722                 req->data_dir = MSG_DATA_DIR_ND;
 723
 724         hba->ccb[tag].cmd = cmd;
 725         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 726         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 727
 728         if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
 729                 hba->ccb[tag].sg_count = 0;
 730                 memset(&req->variable[0], 0, 8);
 731         }
 732
 733         hba->send(hba, req, tag);
 734         return 0;
 735 }
 736
 737 static DEF_SCSI_QCMD(stex_queuecommand)
 738
 739 static void stex_scsi_done(struct st_ccb *ccb)
 740 {
 741         struct scsi_cmnd *cmd = ccb->cmd;
 742         int result;
 743
 744         if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
 745                 result = ccb->scsi_status;
 746                 switch (ccb->scsi_status) {
 747                 case SAM_STAT_GOOD:
 748                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 749                         break;
 750                 case SAM_STAT_CHECK_CONDITION:
 751                         result |= DRIVER_SENSE << 24;
 752                         break;
 753                 case SAM_STAT_BUSY:
 754                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 755                         break;
 756                 default:
 757                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 758                         break;
 759                 }
 760         }
 761         else if (ccb->srb_status & SRB_SEE_SENSE)
 762                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 763         else switch (ccb->srb_status) {
 764                 case SRB_STATUS_SELECTION_TIMEOUT:
 765                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 766                         break;
 767                 case SRB_STATUS_BUSY:
 768                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 769                         break;
 770                 case SRB_STATUS_INVALID_REQUEST:
 771                 case SRB_STATUS_ERROR:
 772                 default:
 773                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 774                         break;
 775         }
 776
 777         cmd->result = result;
 778         cmd->scsi_done(cmd);
 779 }
 780
 781 static void stex_copy_data(struct st_ccb *ccb,
 782         struct status_msg *resp, unsigned int variable)
 783 {
 784         if (resp->scsi_status != SAM_STAT_GOOD) {
 785                 if (ccb->sense_buffer != NULL)
 786                         memcpy(ccb->sense_buffer, resp->variable,
 787                                 min(variable, ccb->sense_bufflen));
 788                 return;
 789         }
 790
 791         if (ccb->cmd == NULL)
 792                 return;
 793         scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
 794 }
 795
 796 static void stex_check_cmd(struct st_hba *hba,
 797         struct st_ccb *ccb, struct status_msg *resp)
 798 {
 799         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 800                 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
 801                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
 802                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
 803 }
 804
 805 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 806 {
 807         void __iomem *base = hba->mmio_base;
 808         struct status_msg *resp;
 809         struct st_ccb *ccb;
 810         unsigned int size;
 811         u16 tag;
 812
 813         if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
 814                 return;
 815
 816         /* status payloads */
 817         hba->status_head = readl(base + OMR1);
 818         if (unlikely(hba->status_head > hba->sts_count)) {
 819                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 820                         pci_name(hba->pdev));
 821                 return;
 822         }
 823
 824         /*
 825          * it's not a valid status payload if:
 826          * 1. there are no pending requests(e.g. during init stage)
 827          * 2. there are some pending requests, but the controller is in
 828          *     reset status, and its type is not st_yosemite
 829          * firmware of st_yosemite in reset status will return pending requests
 830          * to driver, so we allow it to pass
 831          */
 832         if (unlikely(hba->out_req_cnt <= 0 ||
 833                         (hba->mu_status == MU_STATE_RESETTING &&
 834                          hba->cardtype != st_yosemite))) {
 835                 hba->status_tail = hba->status_head;
 836                 goto update_status;
 837         }
 838
 839         while (hba->status_tail != hba->status_head) {
 840                 resp = stex_get_status(hba);
 841                 tag = le16_to_cpu(resp->tag);
 842                 if (unlikely(tag >= hba->host->can_queue)) {
 843                         printk(KERN_WARNING DRV_NAME
 844                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 845                         continue;
 846                 }
 847
 848                 hba->out_req_cnt--;
 849                 ccb = &hba->ccb[tag];
 850                 if (unlikely(hba->wait_ccb == ccb))
 851                         hba->wait_ccb = NULL;
 852                 if (unlikely(ccb->req == NULL)) {
 853                         printk(KERN_WARNING DRV_NAME
 854                                 "(%s): lagging req\n", pci_name(hba->pdev));
 855                         continue;
 856                 }
 857
 858                 size = resp->payload_sz * sizeof(u32); /* payload size */
 859                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 860                         size > sizeof(*resp))) {
 861                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 862                                 pci_name(hba->pdev));
 863                 } else {
 864                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 865                         if (size)
 866                                 stex_copy_data(ccb, resp, size);
 867                 }
 868
 869                 ccb->req = NULL;
 870                 ccb->srb_status = resp->srb_status;
 871                 ccb->scsi_status = resp->scsi_status;
 872
 873                 if (likely(ccb->cmd != NULL)) {
 874                         if (hba->cardtype == st_yosemite)
 875                                 stex_check_cmd(hba, ccb, resp);
 876
 877                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 878                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 879                                 stex_controller_info(hba, ccb);
 880
 881                         scsi_dma_unmap(ccb->cmd);
 882                         stex_scsi_done(ccb);
 883                 } else
 884                         ccb->req_type = 0;
 885         }
 886
 887 update_status:
 888         writel(hba->status_head, base + IMR1);
 889         readl(base + IMR1); /* flush */
 890 }
 891
 892 static irqreturn_t stex_intr(int irq, void *__hba)
 893 {
 894         struct st_hba *hba = __hba;
 895         void __iomem *base = hba->mmio_base;
 896         u32 data;
 897         unsigned long flags;
 898
 899         spin_lock_irqsave(hba->host->host_lock, flags);
 900
 901         data = readl(base + ODBL);
 902
 903         if (data && data != 0xffffffff) {
 904                 /* clear the interrupt */
 905                 writel(data, base + ODBL);
 906                 readl(base + ODBL); /* flush */
 907                 stex_mu_intr(hba, data);
 908                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 909                 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
 910                         hba->cardtype == st_shasta))
 911                         queue_work(hba->work_q, &hba->reset_work);
 912                 return IRQ_HANDLED;
 913         }
 914
 915         spin_unlock_irqrestore(hba->host->host_lock, flags);
 916
 917         return IRQ_NONE;
 918 }
 919
 920 static void stex_ss_mu_intr(struct st_hba *hba)
 921 {
 922         struct status_msg *resp;
 923         struct st_ccb *ccb;
 924         __le32 *scratch;
 925         unsigned int size;
 926         int count = 0;
 927         u32 value;
 928         u16 tag;
 929
 930         if (unlikely(hba->out_req_cnt <= 0 ||
 931                         hba->mu_status == MU_STATE_RESETTING))
 932                 return;
 933
 934         while (count < hba->sts_count) {
 935                 scratch = hba->scratch + hba->status_tail;
 936                 value = le32_to_cpu(*scratch);
 937                 if (unlikely(!(value & SS_STS_NORMAL)))
 938                         return;
 939
 940                 resp = hba->status_buffer + hba->status_tail;
 941                 *scratch = 0;
 942                 ++count;
 943                 ++hba->status_tail;
 944                 hba->status_tail %= hba->sts_count+1;
 945
 946                 tag = (u16)value;
 947                 if (unlikely(tag >= hba->host->can_queue)) {
 948                         printk(KERN_WARNING DRV_NAME
 949                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 950                         continue;
 951                 }
 952
 953                 hba->out_req_cnt--;
 954                 ccb = &hba->ccb[tag];
 955                 if (unlikely(hba->wait_ccb == ccb))
 956                         hba->wait_ccb = NULL;
 957                 if (unlikely(ccb->req == NULL)) {
 958                         printk(KERN_WARNING DRV_NAME
 959                                 "(%s): lagging req\n", pci_name(hba->pdev));
 960                         continue;
 961                 }
 962
 963                 ccb->req = NULL;
 964                 if (likely(value & SS_STS_DONE)) { /* normal case */
 965                         ccb->srb_status = SRB_STATUS_SUCCESS;
 966                         ccb->scsi_status = SAM_STAT_GOOD;
 967                 } else {
 968                         ccb->srb_status = resp->srb_status;
 969                         ccb->scsi_status = resp->scsi_status;
 970                         size = resp->payload_sz * sizeof(u32);
 971                         if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 972                                 size > sizeof(*resp))) {
 973                                 printk(KERN_WARNING DRV_NAME
 974                                         "(%s): bad status size\n",
 975                                         pci_name(hba->pdev));
 976                         } else {
 977                                 size -= sizeof(*resp) - STATUS_VAR_LEN;
 978                                 if (size)
 979                                         stex_copy_data(ccb, resp, size);
 980                         }
 981                         if (likely(ccb->cmd != NULL))
 982                                 stex_check_cmd(hba, ccb, resp);
 983                 }
 984
 985                 if (likely(ccb->cmd != NULL)) {
 986                         scsi_dma_unmap(ccb->cmd);
 987                         stex_scsi_done(ccb);
 988                 } else
 989                         ccb->req_type = 0;
 990         }
 991 }
 992
 993 static irqreturn_t stex_ss_intr(int irq, void *__hba)
 994 {
 995         struct st_hba *hba = __hba;
 996         void __iomem *base = hba->mmio_base;
 997         u32 data;
 998         unsigned long flags;
 999
1000         spin_lock_irqsave(hba->host->host_lock, flags);
1001
1002         if (hba->cardtype == st_yel) {
1003                 data = readl(base + YI2H_INT);
1004                 if (data && data != 0xffffffff) {
1005                         /* clear the interrupt */
1006                         writel(data, base + YI2H_INT_C);
1007                         stex_ss_mu_intr(hba);
1008                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1009                         if (unlikely(data & SS_I2H_REQUEST_RESET))
1010                                 queue_work(hba->work_q, &hba->reset_work);
1011                         return IRQ_HANDLED;
1012                 }
1013         } else {
1014                 data = readl(base + PSCRATCH4);
1015                 if (data != 0xffffffff) {
1016                         if (data != 0) {
1017                                 /* clear the interrupt */
1018                                 writel(data, base + PSCRATCH1);
1019                                 writel((1 << 22), base + YH2I_INT);
1020                         }
1021                         stex_ss_mu_intr(hba);
1022                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1023                         if (unlikely(data & SS_I2H_REQUEST_RESET))
1024                                 queue_work(hba->work_q, &hba->reset_work);
1025                         return IRQ_HANDLED;
1026                 }
1027         }
1028
1029         spin_unlock_irqrestore(hba->host->host_lock, flags);
1030
1031         return IRQ_NONE;
1032 }
1033
1034 static int stex_common_handshake(struct st_hba *hba)
1035 {
1036         void __iomem *base = hba->mmio_base;
1037         struct handshake_frame *h;
1038         dma_addr_t status_phys;
1039         u32 data;
1040         unsigned long before;
1041
1042         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1043                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1044                 readl(base + IDBL);
1045                 before = jiffies;
1046                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1047                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1048                                 printk(KERN_ERR DRV_NAME
1049                                         "(%s): no handshake signature\n",
1050                                         pci_name(hba->pdev));
1051                                 return -1;
1052                         }
1053                         rmb();
1054                         msleep(1);
1055                 }
1056         }
1057
1058         udelay(10);
1059
1060         data = readl(base + OMR1);
1061         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1062                 data &= 0x0000ffff;
1063                 if (hba->host->can_queue > data) {
1064                         hba->host->can_queue = data;
1065                         hba->host->cmd_per_lun = data;
1066                 }
1067         }
1068
1069         h = (struct handshake_frame *)hba->status_buffer;
1070         h->rb_phy = cpu_to_le64(hba->dma_handle);
1071         h->req_sz = cpu_to_le16(hba->rq_size);
1072         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1073         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1074         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1075         h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1076         h->partner_type = HMU_PARTNER_TYPE;
1077         if (hba->extra_offset) {
1078                 h->extra_offset = cpu_to_le32(hba->extra_offset);
1079                 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1080         } else
1081                 h->extra_offset = h->extra_size = 0;
1082
1083         status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1084         writel(status_phys, base + IMR0);
1085         readl(base + IMR0);
1086         writel((status_phys >> 16) >> 16, base + IMR1);
1087         readl(base + IMR1);
1088
1089         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1090         readl(base + OMR0);
1091         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1092         readl(base + IDBL); /* flush */
1093
1094         udelay(10);
1095         before = jiffies;
1096         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1097                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1098                         printk(KERN_ERR DRV_NAME
1099                                 "(%s): no signature after handshake frame\n",
1100                                 pci_name(hba->pdev));
1101                         return -1;
1102                 }
1103                 rmb();
1104                 msleep(1);
1105         }
1106
1107         writel(0, base + IMR0);
1108         readl(base + IMR0);
1109         writel(0, base + OMR0);
1110         readl(base + OMR0);
1111         writel(0, base + IMR1);
1112         readl(base + IMR1);
1113         writel(0, base + OMR1);
1114         readl(base + OMR1); /* flush */
1115         return 0;
1116 }
1117
1118 static int stex_ss_handshake(struct st_hba *hba)
1119 {
1120         void __iomem *base = hba->mmio_base;
1121         struct st_msg_header *msg_h;
1122         struct handshake_frame *h;
1123         __le32 *scratch;
1124         u32 data, scratch_size, mailboxdata, operationaldata;
1125         unsigned long before;
1126         int ret = 0;
1127
1128         before = jiffies;
1129
1130         if (hba->cardtype == st_yel) {
1131                 operationaldata = readl(base + YIOA_STATUS);
1132                 while (operationaldata != SS_MU_OPERATIONAL) {
1133                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1134                                 printk(KERN_ERR DRV_NAME
1135                                         "(%s): firmware not operational\n",
1136                                         pci_name(hba->pdev));
1137                                 return -1;
1138                         }
1139                         msleep(1);
1140                         operationaldata = readl(base + YIOA_STATUS);
1141                 }
1142         } else {
1143                 operationaldata = readl(base + PSCRATCH3);
1144                 while (operationaldata != SS_MU_OPERATIONAL) {
1145                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1146                                 printk(KERN_ERR DRV_NAME
1147                                         "(%s): firmware not operational\n",
1148                                         pci_name(hba->pdev));
1149                                 return -1;
1150                         }
1151                         msleep(1);
1152                         operationaldata = readl(base + PSCRATCH3);
1153                 }
1154         }
1155
1156         msg_h = (struct st_msg_header *)hba->dma_mem;
1157         msg_h->handle = cpu_to_le64(hba->dma_handle);
1158         msg_h->flag = SS_HEAD_HANDSHAKE;
1159
1160         h = (struct handshake_frame *)(msg_h + 1);
1161         h->rb_phy = cpu_to_le64(hba->dma_handle);
1162         h->req_sz = cpu_to_le16(hba->rq_size);
1163         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1164         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1165         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1166         h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1167         h->partner_type = HMU_PARTNER_TYPE;
1168         h->extra_offset = h->extra_size = 0;
1169         scratch_size = (hba->sts_count+1)*sizeof(u32);
1170         h->scratch_size = cpu_to_le32(scratch_size);
1171
1172         if (hba->cardtype == st_yel) {
1173                 data = readl(base + YINT_EN);
1174                 data &= ~4;
1175                 writel(data, base + YINT_EN);
1176                 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1177                 readl(base + YH2I_REQ_HI);
1178                 writel(hba->dma_handle, base + YH2I_REQ);
1179                 readl(base + YH2I_REQ); /* flush */
1180         } else {
1181                 data = readl(base + YINT_EN);
1182                 data &= ~(1 << 0);
1183                 data &= ~(1 << 2);
1184                 writel(data, base + YINT_EN);
1185                 if (hba->msi_lock == 0) {
1186                         /* P3 MSI Register cannot access twice */
1187                         writel((1 << 6), base + YH2I_INT);
1188                         hba->msi_lock  = 1;
1189                 }
1190                 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1191                 writel(hba->dma_handle, base + YH2I_REQ);
1192         }
1193
1194         before = jiffies;
1195         scratch = hba->scratch;
1196         if (hba->cardtype == st_yel) {
1197                 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1198                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1199                                 printk(KERN_ERR DRV_NAME
1200                                         "(%s): no signature after handshake frame\n",
1201                                         pci_name(hba->pdev));
1202                                 ret = -1;
1203                                 break;
1204                         }
1205                         rmb();
1206                         msleep(1);
1207                 }
1208         } else {
1209                 mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1210                 while (mailboxdata != SS_STS_HANDSHAKE) {
1211                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1212                                 printk(KERN_ERR DRV_NAME
1213                                         "(%s): no signature after handshake frame\n",
1214                                         pci_name(hba->pdev));
1215                                 ret = -1;
1216                                 break;
1217                         }
1218                         rmb();
1219                         msleep(1);
1220                         mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1221                 }
1222         }
1223         memset(scratch, 0, scratch_size);
1224         msg_h->flag = 0;
1225
1226         return ret;
1227 }
1228
1229 static int stex_handshake(struct st_hba *hba)
1230 {
1231         int err;
1232         unsigned long flags;
1233         unsigned int mu_status;
1234
1235         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1236                 err = stex_ss_handshake(hba);
1237         else
1238                 err = stex_common_handshake(hba);
1239         spin_lock_irqsave(hba->host->host_lock, flags);
1240         mu_status = hba->mu_status;
1241         if (err == 0) {
1242                 hba->req_head = 0;
1243                 hba->req_tail = 0;
1244                 hba->status_head = 0;
1245                 hba->status_tail = 0;
1246                 hba->out_req_cnt = 0;
1247                 hba->mu_status = MU_STATE_STARTED;
1248         } else
1249                 hba->mu_status = MU_STATE_FAILED;
1250         if (mu_status == MU_STATE_RESETTING)
1251                 wake_up_all(&hba->reset_waitq);
1252         spin_unlock_irqrestore(hba->host->host_lock, flags);
1253         return err;
1254 }
1255
1256 static int stex_abort(struct scsi_cmnd *cmd)
1257 {
1258         struct Scsi_Host *host = cmd->device->host;
1259         struct st_hba *hba = (struct st_hba *)host->hostdata;
1260         u16 tag = cmd->request->tag;
1261         void __iomem *base;
1262         u32 data;
1263         int result = SUCCESS;
1264         unsigned long flags;
1265
1266         scmd_printk(KERN_INFO, cmd, "aborting command\n");
1267
1268         base = hba->mmio_base;
1269         spin_lock_irqsave(host->host_lock, flags);
1270         if (tag < host->can_queue &&
1271                 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1272                 hba->wait_ccb = &hba->ccb[tag];
1273         else
1274                 goto out;
1275
1276         if (hba->cardtype == st_yel) {
1277                 data = readl(base + YI2H_INT);
1278                 if (data == 0 || data == 0xffffffff)
1279                         goto fail_out;
1280
1281                 writel(data, base + YI2H_INT_C);
1282                 stex_ss_mu_intr(hba);
1283         } else if (hba->cardtype == st_P3) {
1284                 data = readl(base + PSCRATCH4);
1285                 if (data == 0xffffffff)
1286                         goto fail_out;
1287                 if (data != 0) {
1288                         writel(data, base + PSCRATCH1);
1289                         writel((1 << 22), base + YH2I_INT);
1290                 }
1291                 stex_ss_mu_intr(hba);
1292         } else {
1293                 data = readl(base + ODBL);
1294                 if (data == 0 || data == 0xffffffff)
1295                         goto fail_out;
1296
1297                 writel(data, base + ODBL);
1298                 readl(base + ODBL); /* flush */
1299                 stex_mu_intr(hba, data);
1300         }
1301         if (hba->wait_ccb == NULL) {
1302                 printk(KERN_WARNING DRV_NAME
1303                         "(%s): lost interrupt\n", pci_name(hba->pdev));
1304                 goto out;
1305         }
1306
1307 fail_out:
1308         scsi_dma_unmap(cmd);
1309         hba->wait_ccb->req = NULL; /* nullify the req's future return */
1310         hba->wait_ccb = NULL;
1311         result = FAILED;
1312 out:
1313         spin_unlock_irqrestore(host->host_lock, flags);
1314         return result;
1315 }
1316
1317 static void stex_hard_reset(struct st_hba *hba)
1318 {
1319         struct pci_bus *bus;
1320         int i;
1321         u16 pci_cmd;
1322         u8 pci_bctl;
1323
1324         for (i = 0; i < 16; i++)
1325                 pci_read_config_dword(hba->pdev, i * 4,
1326                         &hba->pdev->saved_config_space[i]);
1327
1328         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1329            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1330         bus = hba->pdev->bus;
1331         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1332         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1333         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1334
1335         /*
1336          * 1 ms may be enough for 8-port controllers. But 16-port controllers
1337          * require more time to finish bus reset. Use 100 ms here for safety
1338          */
1339         msleep(100);
1340         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1341         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1342
1343         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1344                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1345                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1346                         break;
1347                 msleep(1);
1348         }
1349
1350         ssleep(5);
1351         for (i = 0; i < 16; i++)
1352                 pci_write_config_dword(hba->pdev, i * 4,
1353                         hba->pdev->saved_config_space[i]);
1354 }
1355
1356 static int stex_yos_reset(struct st_hba *hba)
1357 {
1358         void __iomem *base;
1359         unsigned long flags, before;
1360         int ret = 0;
1361
1362         base = hba->mmio_base;
1363         writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1364         readl(base + IDBL); /* flush */
1365         before = jiffies;
1366         while (hba->out_req_cnt > 0) {
1367                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1368                         printk(KERN_WARNING DRV_NAME
1369                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1370                         ret = -1;
1371                         break;
1372                 }
1373                 msleep(1);
1374         }
1375
1376         spin_lock_irqsave(hba->host->host_lock, flags);
1377         if (ret == -1)
1378                 hba->mu_status = MU_STATE_FAILED;
1379         else
1380                 hba->mu_status = MU_STATE_STARTED;
1381         wake_up_all(&hba->reset_waitq);
1382         spin_unlock_irqrestore(hba->host->host_lock, flags);
1383
1384         return ret;
1385 }
1386
1387 static void stex_ss_reset(struct st_hba *hba)
1388 {
1389         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1390         readl(hba->mmio_base + YH2I_INT);
1391         ssleep(5);
1392 }
1393
1394 static void stex_p3_reset(struct st_hba *hba)
1395 {
1396         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1397         ssleep(5);
1398 }
1399
1400 static int stex_do_reset(struct st_hba *hba)
1401 {
1402         unsigned long flags;
1403         unsigned int mu_status = MU_STATE_RESETTING;
1404
1405         spin_lock_irqsave(hba->host->host_lock, flags);
1406         if (hba->mu_status == MU_STATE_STARTING) {
1407                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1408                 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1409                         pci_name(hba->pdev));
1410                 return 0;
1411         }
1412         while (hba->mu_status == MU_STATE_RESETTING) {
1413                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1414                 wait_event_timeout(hba->reset_waitq,
1415                                    hba->mu_status != MU_STATE_RESETTING,
1416                                    MU_MAX_DELAY * HZ);
1417                 spin_lock_irqsave(hba->host->host_lock, flags);
1418                 mu_status = hba->mu_status;
1419         }
1420
1421         if (mu_status != MU_STATE_RESETTING) {
1422                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1423                 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1424         }
1425
1426         hba->mu_status = MU_STATE_RESETTING;
1427         spin_unlock_irqrestore(hba->host->host_lock, flags);
1428
1429         if (hba->cardtype == st_yosemite)
1430                 return stex_yos_reset(hba);
1431
1432         if (hba->cardtype == st_shasta)
1433                 stex_hard_reset(hba);
1434         else if (hba->cardtype == st_yel)
1435                 stex_ss_reset(hba);
1436         else if (hba->cardtype == st_P3)
1437                 stex_p3_reset(hba);
1438
1439         return_abnormal_state(hba, DID_RESET);
1440
1441         if (stex_handshake(hba) == 0)
1442                 return 0;
1443
1444         printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1445                 pci_name(hba->pdev));
1446         return -1;
1447 }
1448
1449 static int stex_reset(struct scsi_cmnd *cmd)
1450 {
1451         struct st_hba *hba;
1452
1453         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1454
1455         shost_printk(KERN_INFO, cmd->device->host,
1456                      "resetting host\n");
1457
1458         return stex_do_reset(hba) ? FAILED : SUCCESS;
1459 }
1460
1461 static void stex_reset_work(struct work_struct *work)
1462 {
1463         struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1464
1465         stex_do_reset(hba);
1466 }
1467
1468 static int stex_biosparam(struct scsi_device *sdev,
1469         struct block_device *bdev, sector_t capacity, int geom[])
1470 {
1471         int heads = 255, sectors = 63;
1472
1473         if (capacity < 0x200000) {
1474                 heads = 64;
1475                 sectors = 32;
1476         }
1477
1478         sector_div(capacity, heads * sectors);
1479
1480         geom[0] = heads;
1481         geom[1] = sectors;
1482         geom[2] = capacity;
1483
1484         return 0;
1485 }
1486
1487 static struct scsi_host_template driver_template = {
1488         .module                         = THIS_MODULE,
1489         .name                           = DRV_NAME,
1490         .proc_name                      = DRV_NAME,
1491         .bios_param                     = stex_biosparam,
1492         .queuecommand                   = stex_queuecommand,
1493         .slave_configure                = stex_slave_config,
1494         .eh_abort_handler               = stex_abort,
1495         .eh_host_reset_handler          = stex_reset,
1496         .this_id                        = -1,
1497 };
1498
1499 static struct pci_device_id stex_pci_tbl[] = {
1500         /* st_shasta */
1501         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1502                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1503         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1504                 st_shasta }, /* SuperTrak EX12350 */
1505         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1506                 st_shasta }, /* SuperTrak EX4350 */
1507         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1508                 st_shasta }, /* SuperTrak EX24350 */
1509
1510         /* st_vsc */
1511         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1512
1513         /* st_yosemite */
1514         { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1515
1516         /* st_seq */
1517         { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1518
1519         /* st_yel */
1520         { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1521         { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1522
1523         /* st_P3, pluto */
1524         { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1525                 0x8870, 0, 0, st_P3 },
1526         /* st_P3, p3 */
1527         { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1528                 0x4300, 0, 0, st_P3 },
1529
1530         /* st_P3, SymplyStor4E */
1531         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1532                 0x4311, 0, 0, st_P3 },
1533         /* st_P3, SymplyStor8E */
1534         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1535                 0x4312, 0, 0, st_P3 },
1536         /* st_P3, SymplyStor4 */
1537         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1538                 0x4321, 0, 0, st_P3 },
1539         /* st_P3, SymplyStor8 */
1540         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1541                 0x4322, 0, 0, st_P3 },
1542         { }     /* terminate list */
1543 };
1544
1545 static struct st_card_info stex_card_info[] = {
1546         /* st_shasta */
1547         {
1548                 .max_id         = 17,
1549                 .max_lun        = 8,
1550                 .max_channel    = 0,
1551                 .rq_count       = 32,
1552                 .rq_size        = 1048,
1553                 .sts_count      = 32,
1554                 .alloc_rq       = stex_alloc_req,
1555                 .map_sg         = stex_map_sg,
1556                 .send           = stex_send_cmd,
1557         },
1558
1559         /* st_vsc */
1560         {
1561                 .max_id         = 129,
1562                 .max_lun        = 1,
1563                 .max_channel    = 0,
1564                 .rq_count       = 32,
1565                 .rq_size        = 1048,
1566                 .sts_count      = 32,
1567                 .alloc_rq       = stex_alloc_req,
1568                 .map_sg         = stex_map_sg,
1569                 .send           = stex_send_cmd,
1570         },
1571
1572         /* st_yosemite */
1573         {
1574                 .max_id         = 2,
1575                 .max_lun        = 256,
1576                 .max_channel    = 0,
1577                 .rq_count       = 256,
1578                 .rq_size        = 1048,
1579                 .sts_count      = 256,
1580                 .alloc_rq       = stex_alloc_req,
1581                 .map_sg         = stex_map_sg,
1582                 .send           = stex_send_cmd,
1583         },
1584
1585         /* st_seq */
1586         {
1587                 .max_id         = 129,
1588                 .max_lun        = 1,
1589                 .max_channel    = 0,
1590                 .rq_count       = 32,
1591                 .rq_size        = 1048,
1592                 .sts_count      = 32,
1593                 .alloc_rq       = stex_alloc_req,
1594                 .map_sg         = stex_map_sg,
1595                 .send           = stex_send_cmd,
1596         },
1597
1598         /* st_yel */
1599         {
1600                 .max_id         = 129,
1601                 .max_lun        = 256,
1602                 .max_channel    = 3,
1603                 .rq_count       = 801,
1604                 .rq_size        = 512,
1605                 .sts_count      = 801,
1606                 .alloc_rq       = stex_ss_alloc_req,
1607                 .map_sg         = stex_ss_map_sg,
1608                 .send           = stex_ss_send_cmd,
1609         },
1610
1611         /* st_P3 */
1612         {
1613                 .max_id         = 129,
1614                 .max_lun        = 256,
1615                 .max_channel    = 0,
1616                 .rq_count       = 801,
1617                 .rq_size        = 512,
1618                 .sts_count      = 801,
1619                 .alloc_rq       = stex_ss_alloc_req,
1620                 .map_sg         = stex_ss_map_sg,
1621                 .send           = stex_ss_send_cmd,
1622         },
1623 };
1624
1625 static int stex_set_dma_mask(struct pci_dev * pdev)
1626 {
1627         int ret;
1628
1629         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1630                 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
1631                 return 0;
1632         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1633         if (!ret)
1634                 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1635         return ret;
1636 }
1637
1638 static int stex_request_irq(struct st_hba *hba)
1639 {
1640         struct pci_dev *pdev = hba->pdev;
1641         int status;
1642
1643         if (msi || hba->cardtype == st_P3) {
1644                 status = pci_enable_msi(pdev);
1645                 if (status != 0)
1646                         printk(KERN_ERR DRV_NAME
1647                                 "(%s): error %d setting up MSI\n",
1648                                 pci_name(pdev), status);
1649                 else
1650                         hba->msi_enabled = 1;
1651         } else
1652                 hba->msi_enabled = 0;
1653
1654         status = request_irq(pdev->irq,
1655                 (hba->cardtype == st_yel || hba->cardtype == st_P3) ?
1656                 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1657
1658         if (status != 0) {
1659                 if (hba->msi_enabled)
1660                         pci_disable_msi(pdev);
1661         }
1662         return status;
1663 }
1664
1665 static void stex_free_irq(struct st_hba *hba)
1666 {
1667         struct pci_dev *pdev = hba->pdev;
1668
1669         free_irq(pdev->irq, hba);
1670         if (hba->msi_enabled)
1671                 pci_disable_msi(pdev);
1672 }
1673
1674 static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1675 {
1676         struct st_hba *hba;
1677         struct Scsi_Host *host;
1678         const struct st_card_info *ci = NULL;
1679         u32 sts_offset, cp_offset, scratch_offset;
1680         int err;
1681
1682         err = pci_enable_device(pdev);
1683         if (err)
1684                 return err;
1685
1686         pci_set_master(pdev);
1687
1688         S6flag = 0;
1689         register_reboot_notifier(&stex_notifier);
1690
1691         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1692
1693         if (!host) {
1694                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1695                         pci_name(pdev));
1696                 err = -ENOMEM;
1697                 goto out_disable;
1698         }
1699
1700         hba = (struct st_hba *)host->hostdata;
1701         memset(hba, 0, sizeof(struct st_hba));
1702
1703         err = pci_request_regions(pdev, DRV_NAME);
1704         if (err < 0) {
1705                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1706                         pci_name(pdev));
1707                 goto out_scsi_host_put;
1708         }
1709
1710         hba->mmio_base = pci_ioremap_bar(pdev, 0);
1711         if ( !hba->mmio_base) {
1712                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1713                         pci_name(pdev));
1714                 err = -ENOMEM;
1715                 goto out_release_regions;
1716         }
1717
1718         err = stex_set_dma_mask(pdev);
1719         if (err) {
1720                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1721                         pci_name(pdev));
1722                 goto out_iounmap;
1723         }
1724
1725         hba->cardtype = (unsigned int) id->driver_data;
1726         ci = &stex_card_info[hba->cardtype];
1727         switch (id->subdevice) {
1728         case 0x4221:
1729         case 0x4222:
1730         case 0x4223:
1731         case 0x4224:
1732         case 0x4225:
1733         case 0x4226:
1734         case 0x4227:
1735         case 0x4261:
1736         case 0x4262:
1737         case 0x4263:
1738         case 0x4264:
1739         case 0x4265:
1740                 break;
1741         default:
1742                 if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1743                         hba->supports_pm = 1;
1744         }
1745
1746         sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1747         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1748                 sts_offset += (ci->sts_count+1) * sizeof(u32);
1749         cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1750         hba->dma_size = cp_offset + sizeof(struct st_frame);
1751         if (hba->cardtype == st_seq ||
1752                 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1753                 hba->extra_offset = hba->dma_size;
1754                 hba->dma_size += ST_ADDITIONAL_MEM;
1755         }
1756         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1757                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1758         if (!hba->dma_mem) {
1759                 /* Retry minimum coherent mapping for st_seq and st_vsc */
1760                 if (hba->cardtype == st_seq ||
1761                     (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1762                         printk(KERN_WARNING DRV_NAME
1763                                 "(%s): allocating min buffer for controller\n",
1764                                 pci_name(pdev));
1765                         hba->dma_size = hba->extra_offset
1766                                 + ST_ADDITIONAL_MEM_MIN;
1767                         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1768                                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1769                 }
1770
1771                 if (!hba->dma_mem) {
1772                         err = -ENOMEM;
1773                         printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1774                                 pci_name(pdev));
1775                         goto out_iounmap;
1776                 }
1777         }
1778
1779         hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1780         if (!hba->ccb) {
1781                 err = -ENOMEM;
1782                 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1783                         pci_name(pdev));
1784                 goto out_pci_free;
1785         }
1786
1787         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1788                 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1789         hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1790         hba->copy_buffer = hba->dma_mem + cp_offset;
1791         hba->rq_count = ci->rq_count;
1792         hba->rq_size = ci->rq_size;
1793         hba->sts_count = ci->sts_count;
1794         hba->alloc_rq = ci->alloc_rq;
1795         hba->map_sg = ci->map_sg;
1796         hba->send = ci->send;
1797         hba->mu_status = MU_STATE_STARTING;
1798         hba->msi_lock = 0;
1799
1800         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1801                 host->sg_tablesize = 38;
1802         else
1803                 host->sg_tablesize = 32;
1804         host->can_queue = ci->rq_count;
1805         host->cmd_per_lun = ci->rq_count;
1806         host->max_id = ci->max_id;
1807         host->max_lun = ci->max_lun;
1808         host->max_channel = ci->max_channel;
1809         host->unique_id = host->host_no;
1810         host->max_cmd_len = STEX_CDB_LENGTH;
1811
1812         hba->host = host;
1813         hba->pdev = pdev;
1814         init_waitqueue_head(&hba->reset_waitq);
1815
1816         snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1817                  "stex_wq_%d", host->host_no);
1818         hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1819         if (!hba->work_q) {
1820                 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1821                         pci_name(pdev));
1822                 err = -ENOMEM;
1823                 goto out_ccb_free;
1824         }
1825         INIT_WORK(&hba->reset_work, stex_reset_work);
1826
1827         err = stex_request_irq(hba);
1828         if (err) {
1829                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1830                         pci_name(pdev));
1831                 goto out_free_wq;
1832         }
1833
1834         err = stex_handshake(hba);
1835         if (err)
1836                 goto out_free_irq;
1837
1838         pci_set_drvdata(pdev, hba);
1839
1840         err = scsi_add_host(host, &pdev->dev);
1841         if (err) {
1842                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1843                         pci_name(pdev));
1844                 goto out_free_irq;
1845         }
1846
1847         scsi_scan_host(host);
1848
1849         return 0;
1850
1851 out_free_irq:
1852         stex_free_irq(hba);
1853 out_free_wq:
1854         destroy_workqueue(hba->work_q);
1855 out_ccb_free:
1856         kfree(hba->ccb);
1857 out_pci_free:
1858         dma_free_coherent(&pdev->dev, hba->dma_size,
1859                           hba->dma_mem, hba->dma_handle);
1860 out_iounmap:
1861         iounmap(hba->mmio_base);
1862 out_release_regions:
1863         pci_release_regions(pdev);
1864 out_scsi_host_put:
1865         scsi_host_put(host);
1866 out_disable:
1867         pci_disable_device(pdev);
1868
1869         return err;
1870 }
1871
1872 static void stex_hba_stop(struct st_hba *hba, int st_sleep_mic)
1873 {
1874         struct req_msg *req;
1875         struct st_msg_header *msg_h;
1876         unsigned long flags;
1877         unsigned long before;
1878         u16 tag = 0;
1879
1880         spin_lock_irqsave(hba->host->host_lock, flags);
1881
1882         if ((hba->cardtype == st_yel || hba->cardtype == st_P3) &&
1883                 hba->supports_pm == 1) {
1884                 if (st_sleep_mic == ST_NOTHANDLED) {
1885                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1886                         return;
1887                 }
1888         }
1889         req = hba->alloc_rq(hba);
1890         if (hba->cardtype == st_yel || hba->cardtype == st_P3) {
1891                 msg_h = (struct st_msg_header *)req - 1;
1892                 memset(msg_h, 0, hba->rq_size);
1893         } else
1894                 memset(req, 0, hba->rq_size);
1895
1896         if ((hba->cardtype == st_yosemite || hba->cardtype == st_yel
1897                 || hba->cardtype == st_P3)
1898                 && st_sleep_mic == ST_IGNORED) {
1899                 req->cdb[0] = MGT_CMD;
1900                 req->cdb[1] = MGT_CMD_SIGNATURE;
1901                 req->cdb[2] = CTLR_CONFIG_CMD;
1902                 req->cdb[3] = CTLR_SHUTDOWN;
1903         } else if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
1904                 && st_sleep_mic != ST_IGNORED) {
1905                 req->cdb[0] = MGT_CMD;
1906                 req->cdb[1] = MGT_CMD_SIGNATURE;
1907                 req->cdb[2] = CTLR_CONFIG_CMD;
1908                 req->cdb[3] = PMIC_SHUTDOWN;
1909                 req->cdb[4] = st_sleep_mic;
1910         } else {
1911                 req->cdb[0] = CONTROLLER_CMD;
1912                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1913                 req->cdb[2] = CTLR_POWER_SAVING;
1914         }
1915         hba->ccb[tag].cmd = NULL;
1916         hba->ccb[tag].sg_count = 0;
1917         hba->ccb[tag].sense_bufflen = 0;
1918         hba->ccb[tag].sense_buffer = NULL;
1919         hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1920         hba->send(hba, req, tag);
1921         spin_unlock_irqrestore(hba->host->host_lock, flags);
1922         before = jiffies;
1923         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1924                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1925                         hba->ccb[tag].req_type = 0;
1926                         hba->mu_status = MU_STATE_STOP;
1927                         return;
1928                 }
1929                 msleep(1);
1930         }
1931         hba->mu_status = MU_STATE_STOP;
1932 }
1933
1934 static void stex_hba_free(struct st_hba *hba)
1935 {
1936         stex_free_irq(hba);
1937
1938         destroy_workqueue(hba->work_q);
1939
1940         iounmap(hba->mmio_base);
1941
1942         pci_release_regions(hba->pdev);
1943
1944         kfree(hba->ccb);
1945
1946         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1947                           hba->dma_mem, hba->dma_handle);
1948 }
1949
1950 static void stex_remove(struct pci_dev *pdev)
1951 {
1952         struct st_hba *hba = pci_get_drvdata(pdev);
1953
1954         hba->mu_status = MU_STATE_NOCONNECT;
1955         return_abnormal_state(hba, DID_NO_CONNECT);
1956         scsi_remove_host(hba->host);
1957
1958         scsi_block_requests(hba->host);
1959
1960         stex_hba_free(hba);
1961
1962         scsi_host_put(hba->host);
1963
1964         pci_disable_device(pdev);
1965
1966         unregister_reboot_notifier(&stex_notifier);
1967 }
1968
1969 static void stex_shutdown(struct pci_dev *pdev)
1970 {
1971         struct st_hba *hba = pci_get_drvdata(pdev);
1972
1973         if (hba->supports_pm == 0) {
1974                 stex_hba_stop(hba, ST_IGNORED);
1975         } else if (hba->supports_pm == 1 && S6flag) {
1976                 unregister_reboot_notifier(&stex_notifier);
1977                 stex_hba_stop(hba, ST_S6);
1978         } else
1979                 stex_hba_stop(hba, ST_S5);
1980 }
1981
1982 static int stex_choice_sleep_mic(struct st_hba *hba, pm_message_t state)
1983 {
1984         switch (state.event) {
1985         case PM_EVENT_SUSPEND:
1986                 return ST_S3;
1987         case PM_EVENT_HIBERNATE:
1988                 hba->msi_lock = 0;
1989                 return ST_S4;
1990         default:
1991                 return ST_NOTHANDLED;
1992         }
1993 }
1994
1995 static int stex_suspend(struct pci_dev *pdev, pm_message_t state)
1996 {
1997         struct st_hba *hba = pci_get_drvdata(pdev);
1998
1999         if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
2000                 && hba->supports_pm == 1)
2001                 stex_hba_stop(hba, stex_choice_sleep_mic(hba, state));
2002         else
2003                 stex_hba_stop(hba, ST_IGNORED);
2004         return 0;
2005 }
2006
2007 static int stex_resume(struct pci_dev *pdev)
2008 {
2009         struct st_hba *hba = pci_get_drvdata(pdev);
2010
2011         hba->mu_status = MU_STATE_STARTING;
2012         stex_handshake(hba);
2013         return 0;
2014 }
2015
2016 static int stex_halt(struct notifier_block *nb, unsigned long event, void *buf)
2017 {
2018         S6flag = 1;
2019         return NOTIFY_OK;
2020 }
2021 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
2022
2023 static struct pci_driver stex_pci_driver = {
2024         .name           = DRV_NAME,
2025         .id_table       = stex_pci_tbl,
2026         .probe          = stex_probe,
2027         .remove         = stex_remove,
2028         .shutdown       = stex_shutdown,
2029         .suspend        = stex_suspend,
2030         .resume         = stex_resume,
2031 };
2032
2033 static int __init stex_init(void)
2034 {
2035         printk(KERN_INFO DRV_NAME
2036                 ": Promise SuperTrak EX Driver version: %s\n",
2037                  ST_DRIVER_VERSION);
2038
2039         return pci_register_driver(&stex_pci_driver);
2040 }
2041
2042 static void __exit stex_exit(void)
2043 {
2044         pci_unregister_driver(&stex_pci_driver);
2045 }
2046
2047 module_init(stex_init);
2048 module_exit(stex_exit);