drivers/soc/bcm/brcmstb/pm/pm-mips.c

   1 /*
   2  * MIPS-specific support for Broadcom STB S2/S3/S5 power management
   3  *
   4  * Copyright (C) 2016-2017 Broadcom
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/printk.h>
  18 #include <linux/io.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/delay.h>
  22 #include <linux/suspend.h>
  23 #include <asm/bmips.h>
  24 #include <asm/tlbflush.h>
  25
  26 #include "pm.h"
  27
  28 #define S2_NUM_PARAMS           6
  29 #define MAX_NUM_MEMC            3
  30
  31 /* S3 constants */
  32 #define MAX_GP_REGS             16
  33 #define MAX_CP0_REGS            32
  34 #define NUM_MEMC_CLIENTS        128
  35 #define AON_CTRL_RAM_SIZE       128
  36 #define BRCMSTB_S3_MAGIC        0x5AFEB007
  37
  38 #define CLEAR_RESET_MASK        0x01
  39
  40 /* Index each CP0 register that needs to be saved */
  41 #define CONTEXT         0
  42 #define USER_LOCAL      1
  43 #define PGMK            2
  44 #define HWRENA          3
  45 #define COMPARE         4
  46 #define STATUS          5
  47 #define CONFIG          6
  48 #define MODE            7
  49 #define EDSP            8
  50 #define BOOT_VEC        9
  51 #define EBASE           10
  52
  53 struct brcmstb_memc {
  54         void __iomem *ddr_phy_base;
  55         void __iomem *arb_base;
  56 };
  57
  58 struct brcmstb_pm_control {
  59         void __iomem *aon_ctrl_base;
  60         void __iomem *aon_sram_base;
  61         void __iomem *timers_base;
  62         struct brcmstb_memc memcs[MAX_NUM_MEMC];
  63         int num_memc;
  64 };
  65
  66 struct brcm_pm_s3_context {
  67         u32                     cp0_regs[MAX_CP0_REGS];
  68         u32                     memc0_rts[NUM_MEMC_CLIENTS];
  69         u32                     sc_boot_vec;
  70 };
  71
  72 struct brcmstb_mem_transfer;
  73
  74 struct brcmstb_mem_transfer {
  75         struct brcmstb_mem_transfer     *next;
  76         void                            *src;
  77         void                            *dst;
  78         dma_addr_t                      pa_src;
  79         dma_addr_t                      pa_dst;
  80         u32                             len;
  81         u8                              key;
  82         u8                              mode;
  83         u8                              src_remapped;
  84         u8                              dst_remapped;
  85         u8                              src_dst_remapped;
  86 };
  87
  88 #define AON_SAVE_SRAM(base, idx, val) \
  89         __raw_writel(val, base + (idx << 2))
  90
  91 /* Used for saving registers in asm */
  92 u32 gp_regs[MAX_GP_REGS];
  93
  94 #define BSP_CLOCK_STOP          0x00
  95 #define PM_INITIATE             0x01
  96
  97 static struct brcmstb_pm_control ctrl;
  98
  99 static void brcm_pm_save_cp0_context(struct brcm_pm_s3_context *ctx)
 100 {
 101         /* Generic MIPS */
 102         ctx->cp0_regs[CONTEXT] = read_c0_context();
 103         ctx->cp0_regs[USER_LOCAL] = read_c0_userlocal();
 104         ctx->cp0_regs[PGMK] = read_c0_pagemask();
 105         ctx->cp0_regs[HWRENA] = read_c0_cache();
 106         ctx->cp0_regs[COMPARE] = read_c0_compare();
 107         ctx->cp0_regs[STATUS] = read_c0_status();
 108
 109         /* Broadcom specific */
 110         ctx->cp0_regs[CONFIG] = read_c0_brcm_config();
 111         ctx->cp0_regs[MODE] = read_c0_brcm_mode();
 112         ctx->cp0_regs[EDSP] = read_c0_brcm_edsp();
 113         ctx->cp0_regs[BOOT_VEC] = read_c0_brcm_bootvec();
 114         ctx->cp0_regs[EBASE] = read_c0_ebase();
 115
 116         ctx->sc_boot_vec = bmips_read_zscm_reg(0xa0);
 117 }
 118
 119 static void brcm_pm_restore_cp0_context(struct brcm_pm_s3_context *ctx)
 120 {
 121         /* Restore cp0 state */
 122         bmips_write_zscm_reg(0xa0, ctx->sc_boot_vec);
 123
 124         /* Generic MIPS */
 125         write_c0_context(ctx->cp0_regs[CONTEXT]);
 126         write_c0_userlocal(ctx->cp0_regs[USER_LOCAL]);
 127         write_c0_pagemask(ctx->cp0_regs[PGMK]);
 128         write_c0_cache(ctx->cp0_regs[HWRENA]);
 129         write_c0_compare(ctx->cp0_regs[COMPARE]);
 130         write_c0_status(ctx->cp0_regs[STATUS]);
 131
 132         /* Broadcom specific */
 133         write_c0_brcm_config(ctx->cp0_regs[CONFIG]);
 134         write_c0_brcm_mode(ctx->cp0_regs[MODE]);
 135         write_c0_brcm_edsp(ctx->cp0_regs[EDSP]);
 136         write_c0_brcm_bootvec(ctx->cp0_regs[BOOT_VEC]);
 137         write_c0_ebase(ctx->cp0_regs[EBASE]);
 138 }
 139
 140 static void  brcmstb_pm_handshake(void)
 141 {
 142         void __iomem *base = ctrl.aon_ctrl_base;
 143         u32 tmp;
 144
 145         /* BSP power handshake, v1 */
 146         tmp = __raw_readl(base + AON_CTRL_HOST_MISC_CMDS);
 147         tmp &= ~1UL;
 148         __raw_writel(tmp, base + AON_CTRL_HOST_MISC_CMDS);
 149         (void)__raw_readl(base + AON_CTRL_HOST_MISC_CMDS);
 150
 151         __raw_writel(0, base + AON_CTRL_PM_INITIATE);
 152         (void)__raw_readl(base + AON_CTRL_PM_INITIATE);
 153         __raw_writel(BSP_CLOCK_STOP | PM_INITIATE,
 154                      base + AON_CTRL_PM_INITIATE);
 155         /*
 156          * HACK: BSP may have internal race on the CLOCK_STOP command.
 157          * Avoid touching the BSP for a few milliseconds.
 158          */
 159         mdelay(3);
 160 }
 161
 162 static void brcmstb_pm_s5(void)
 163 {
 164         void __iomem *base = ctrl.aon_ctrl_base;
 165
 166         brcmstb_pm_handshake();
 167
 168         /* Clear magic s3 warm-boot value */
 169         AON_SAVE_SRAM(ctrl.aon_sram_base, 0, 0);
 170
 171         /* Set the countdown */
 172         __raw_writel(0x10, base + AON_CTRL_PM_CPU_WAIT_COUNT);
 173         (void)__raw_readl(base + AON_CTRL_PM_CPU_WAIT_COUNT);
 174
 175         /* Prepare to S5 cold boot */
 176         __raw_writel(PM_COLD_CONFIG, base + AON_CTRL_PM_CTRL);
 177         (void)__raw_readl(base + AON_CTRL_PM_CTRL);
 178
 179         __raw_writel((PM_COLD_CONFIG | PM_PWR_DOWN), base +
 180                       AON_CTRL_PM_CTRL);
 181         (void)__raw_readl(base + AON_CTRL_PM_CTRL);
 182
 183         __asm__ __volatile__(
 184         "       wait\n"
 185         : : : "memory");
 186 }
 187
 188 static int brcmstb_pm_s3(void)
 189 {
 190         struct brcm_pm_s3_context s3_context;
 191         void __iomem *memc_arb_base;
 192         unsigned long flags;
 193         u32 tmp;
 194         int i;
 195
 196         /* Prepare for s3 */
 197         AON_SAVE_SRAM(ctrl.aon_sram_base, 0, BRCMSTB_S3_MAGIC);
 198         AON_SAVE_SRAM(ctrl.aon_sram_base, 1, (u32)&s3_reentry);
 199         AON_SAVE_SRAM(ctrl.aon_sram_base, 2, 0);
 200
 201         /* Clear RESET_HISTORY */
 202         tmp = __raw_readl(ctrl.aon_ctrl_base + AON_CTRL_RESET_CTRL);
 203         tmp &= ~CLEAR_RESET_MASK;
 204         __raw_writel(tmp, ctrl.aon_ctrl_base + AON_CTRL_RESET_CTRL);
 205
 206         local_irq_save(flags);
 207
 208         /* Inhibit DDR_RSTb pulse for both MMCs*/
 209         for (i = 0; i < ctrl.num_memc; i++) {
 210                 tmp = __raw_readl(ctrl.memcs[i].ddr_phy_base +
 211                         DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL);
 212
 213                 tmp &= ~0x0f;
 214                 __raw_writel(tmp, ctrl.memcs[i].ddr_phy_base +
 215                         DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL);
 216                 tmp |= (0x05 | BIT(5));
 217                 __raw_writel(tmp, ctrl.memcs[i].ddr_phy_base +
 218                         DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL);
 219         }
 220
 221         /* Save CP0 context */
 222         brcm_pm_save_cp0_context(&s3_context);
 223
 224         /* Save RTS(skip debug register) */
 225         memc_arb_base = ctrl.memcs[0].arb_base + 4;
 226         for (i = 0; i < NUM_MEMC_CLIENTS; i++) {
 227                 s3_context.memc0_rts[i] = __raw_readl(memc_arb_base);
 228                 memc_arb_base += 4;
 229         }
 230
 231         /* Save I/O context */
 232         local_flush_tlb_all();
 233         _dma_cache_wback_inv(0, ~0);
 234
 235         brcm_pm_do_s3(ctrl.aon_ctrl_base, current_cpu_data.dcache.linesz);
 236
 237         /* CPU reconfiguration */
 238         local_flush_tlb_all();
 239         bmips_cpu_setup();
 240         cpumask_clear(&bmips_booted_mask);
 241
 242         /* Restore RTS (skip debug register) */
 243         memc_arb_base = ctrl.memcs[0].arb_base + 4;
 244         for (i = 0; i < NUM_MEMC_CLIENTS; i++) {
 245                 __raw_writel(s3_context.memc0_rts[i], memc_arb_base);
 246                 memc_arb_base += 4;
 247         }
 248
 249         /* restore CP0 context */
 250         brcm_pm_restore_cp0_context(&s3_context);
 251
 252         local_irq_restore(flags);
 253
 254         return 0;
 255 }
 256
 257 static int brcmstb_pm_s2(void)
 258 {
 259         /*
 260          * We need to pass 6 arguments to an assembly function. Lets avoid the
 261          * stack and pass arguments in a explicit 4 byte array. The assembly
 262          * code assumes all arguments are 4 bytes and arguments are ordered
 263          * like so:
 264          *
 265          * 0: AON_CTRl base register
 266          * 1: DDR_PHY base register
 267          * 2: TIMERS base resgister
 268          * 3: I-Cache line size
 269          * 4: Restart vector address
 270          * 5: Restart vector size
 271          */
 272         u32 s2_params[6];
 273
 274         /* Prepare s2 parameters */
 275         s2_params[0] = (u32)ctrl.aon_ctrl_base;
 276         s2_params[1] = (u32)ctrl.memcs[0].ddr_phy_base;
 277         s2_params[2] = (u32)ctrl.timers_base;
 278         s2_params[3] = (u32)current_cpu_data.icache.linesz;
 279         s2_params[4] = (u32)BMIPS_WARM_RESTART_VEC;
 280         s2_params[5] = (u32)(bmips_smp_int_vec_end -
 281                 bmips_smp_int_vec);
 282
 283         /* Drop to standby */
 284         brcm_pm_do_s2(s2_params);
 285
 286         return 0;
 287 }
 288
 289 static int brcmstb_pm_standby(bool deep_standby)
 290 {
 291         brcmstb_pm_handshake();
 292
 293         /* Send IRQs to BMIPS_WARM_RESTART_VEC */
 294         clear_c0_cause(CAUSEF_IV);
 295         irq_disable_hazard();
 296         set_c0_status(ST0_BEV);
 297         irq_disable_hazard();
 298
 299         if (deep_standby)
 300                 brcmstb_pm_s3();
 301         else
 302                 brcmstb_pm_s2();
 303
 304         /* Send IRQs to normal runtime vectors */
 305         clear_c0_status(ST0_BEV);
 306         irq_disable_hazard();
 307         set_c0_cause(CAUSEF_IV);
 308         irq_disable_hazard();
 309
 310         return 0;
 311 }
 312
 313 static int brcmstb_pm_enter(suspend_state_t state)
 314 {
 315         int ret = -EINVAL;
 316
 317         switch (state) {
 318         case PM_SUSPEND_STANDBY:
 319                 ret = brcmstb_pm_standby(false);
 320                 break;
 321         case PM_SUSPEND_MEM:
 322                 ret = brcmstb_pm_standby(true);
 323                 break;
 324         }
 325
 326         return ret;
 327 }
 328
 329 static int brcmstb_pm_valid(suspend_state_t state)
 330 {
 331         switch (state) {
 332         case PM_SUSPEND_STANDBY:
 333                 return true;
 334         case PM_SUSPEND_MEM:
 335                 return true;
 336         default:
 337                 return false;
 338         }
 339 }
 340
 341 static const struct platform_suspend_ops brcmstb_pm_ops = {
 342         .enter          = brcmstb_pm_enter,
 343         .valid          = brcmstb_pm_valid,
 344 };
 345
 346 static const struct of_device_id aon_ctrl_dt_ids[] = {
 347         { .compatible = "brcm,brcmstb-aon-ctrl" },
 348         { /* sentinel */ }
 349 };
 350
 351 static const struct of_device_id ddr_phy_dt_ids[] = {
 352         { .compatible = "brcm,brcmstb-ddr-phy" },
 353         { /* sentinel */ }
 354 };
 355
 356 static const struct of_device_id arb_dt_ids[] = {
 357         { .compatible = "brcm,brcmstb-memc-arb" },
 358         { /* sentinel */ }
 359 };
 360
 361 static const struct of_device_id timers_ids[] = {
 362         { .compatible = "brcm,brcmstb-timers" },
 363         { /* sentinel */ }
 364 };
 365
 366 static inline void __iomem *brcmstb_ioremap_node(struct device_node *dn,
 367                                                  int index)
 368 {
 369         return of_io_request_and_map(dn, index, dn->full_name);
 370 }
 371
 372 static void __iomem *brcmstb_ioremap_match(const struct of_device_id *matches,
 373                                            int index, const void **ofdata)
 374 {
 375         struct device_node *dn;
 376         const struct of_device_id *match;
 377
 378         dn = of_find_matching_node_and_match(NULL, matches, &match);
 379         if (!dn)
 380                 return ERR_PTR(-EINVAL);
 381
 382         if (ofdata)
 383                 *ofdata = match->data;
 384
 385         return brcmstb_ioremap_node(dn, index);
 386 }
 387
 388 static int brcmstb_pm_init(void)
 389 {
 390         struct device_node *dn;
 391         void __iomem *base;
 392         int i;
 393
 394         /* AON ctrl registers */
 395         base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 0, NULL);
 396         if (IS_ERR(base)) {
 397                 pr_err("error mapping AON_CTRL\n");
 398                 goto aon_err;
 399         }
 400         ctrl.aon_ctrl_base = base;
 401
 402         /* AON SRAM registers */
 403         base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 1, NULL);
 404         if (IS_ERR(base)) {
 405                 pr_err("error mapping AON_SRAM\n");
 406                 goto sram_err;
 407         }
 408         ctrl.aon_sram_base = base;
 409
 410         ctrl.num_memc = 0;
 411         /* Map MEMC DDR PHY registers */
 412         for_each_matching_node(dn, ddr_phy_dt_ids) {
 413                 i = ctrl.num_memc;
 414                 if (i >= MAX_NUM_MEMC) {
 415                         pr_warn("Too many MEMCs (max %d)\n", MAX_NUM_MEMC);
 416                         break;
 417                 }
 418                 base = brcmstb_ioremap_node(dn, 0);
 419                 if (IS_ERR(base))
 420                         goto ddr_err;
 421
 422                 ctrl.memcs[i].ddr_phy_base = base;
 423                 ctrl.num_memc++;
 424         }
 425
 426         /* MEMC ARB registers */
 427         base = brcmstb_ioremap_match(arb_dt_ids, 0, NULL);
 428         if (IS_ERR(base)) {
 429                 pr_err("error mapping MEMC ARB\n");
 430                 goto ddr_err;
 431         }
 432         ctrl.memcs[0].arb_base = base;
 433
 434         /* Timer registers */
 435         base = brcmstb_ioremap_match(timers_ids, 0, NULL);
 436         if (IS_ERR(base)) {
 437                 pr_err("error mapping timers\n");
 438                 goto tmr_err;
 439         }
 440         ctrl.timers_base = base;
 441
 442         /* s3 cold boot aka s5 */
 443         pm_power_off = brcmstb_pm_s5;
 444
 445         suspend_set_ops(&brcmstb_pm_ops);
 446
 447         return 0;
 448
 449 tmr_err:
 450         iounmap(ctrl.memcs[0].arb_base);
 451 ddr_err:
 452         for (i = 0; i < ctrl.num_memc; i++)
 453                 iounmap(ctrl.memcs[i].ddr_phy_base);
 454
 455         iounmap(ctrl.aon_sram_base);
 456 sram_err:
 457         iounmap(ctrl.aon_ctrl_base);
 458 aon_err:
 459         return PTR_ERR(base);
 460 }
 461 arch_initcall(brcmstb_pm_init);