drivers/soc/imx/gpc.c

   1 /*
   2  * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/io.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_domain.h>
  19 #include <linux/regmap.h>
  20 #include <linux/regulator/consumer.h>
  21
  22 #define GPC_CNTR                0x000
  23
  24 #define GPC_PGC_CTRL_OFFS       0x0
  25 #define GPC_PGC_PUPSCR_OFFS     0x4
  26 #define GPC_PGC_PDNSCR_OFFS     0x8
  27 #define GPC_PGC_SW2ISO_SHIFT    0x8
  28 #define GPC_PGC_SW_SHIFT        0x0
  29
  30 #define GPC_PGC_PCI_PDN         0x200
  31 #define GPC_PGC_PCI_SR          0x20c
  32
  33 #define GPC_PGC_GPU_PDN         0x260
  34 #define GPC_PGC_GPU_PUPSCR      0x264
  35 #define GPC_PGC_GPU_PDNSCR      0x268
  36 #define GPC_PGC_GPU_SR          0x26c
  37
  38 #define GPC_PGC_DISP_PDN        0x240
  39 #define GPC_PGC_DISP_SR         0x24c
  40
  41 #define GPU_VPU_PUP_REQ         BIT(1)
  42 #define GPU_VPU_PDN_REQ         BIT(0)
  43
  44 #define GPC_CLK_MAX             6
  45
  46 #define PGC_DOMAIN_FLAG_NO_PD           BIT(0)
  47
  48 struct imx_pm_domain {
  49         struct generic_pm_domain base;
  50         struct regmap *regmap;
  51         struct regulator *supply;
  52         struct clk *clk[GPC_CLK_MAX];
  53         int num_clks;
  54         unsigned int reg_offs;
  55         signed char cntr_pdn_bit;
  56         unsigned int ipg_rate_mhz;
  57         unsigned int flags;
  58 };
  59
  60 static inline struct imx_pm_domain *
  61 to_imx_pm_domain(struct generic_pm_domain *genpd)
  62 {
  63         return container_of(genpd, struct imx_pm_domain, base);
  64 }
  65
  66 static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd)
  67 {
  68         struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
  69         int iso, iso2sw;
  70         u32 val;
  71
  72         if (pd->flags & PGC_DOMAIN_FLAG_NO_PD)
  73                 return -EBUSY;
  74
  75         /* Read ISO and ISO2SW power down delays */
  76         regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PDNSCR_OFFS, &val);
  77         iso = val & 0x3f;
  78         iso2sw = (val >> 8) & 0x3f;
  79
  80         /* Gate off domain when powered down */
  81         regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
  82                            0x1, 0x1);
  83
  84         /* Request GPC to power down domain */
  85         val = BIT(pd->cntr_pdn_bit);
  86         regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
  87
  88         /* Wait ISO + ISO2SW IPG clock cycles */
  89         udelay(DIV_ROUND_UP(iso + iso2sw, pd->ipg_rate_mhz));
  90
  91         if (pd->supply)
  92                 regulator_disable(pd->supply);
  93
  94         return 0;
  95 }
  96
  97 static int imx6_pm_domain_power_on(struct generic_pm_domain *genpd)
  98 {
  99         struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
 100         int i, ret;
 101         u32 val, req;
 102
 103         if (pd->supply) {
 104                 ret = regulator_enable(pd->supply);
 105                 if (ret) {
 106                         pr_err("%s: failed to enable regulator: %d\n",
 107                                __func__, ret);
 108                         return ret;
 109                 }
 110         }
 111
 112         /* Enable reset clocks for all devices in the domain */
 113         for (i = 0; i < pd->num_clks; i++)
 114                 clk_prepare_enable(pd->clk[i]);
 115
 116         /* Gate off domain when powered down */
 117         regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
 118                            0x1, 0x1);
 119
 120         /* Request GPC to power up domain */
 121         req = BIT(pd->cntr_pdn_bit + 1);
 122         regmap_update_bits(pd->regmap, GPC_CNTR, req, req);
 123
 124         /* Wait for the PGC to handle the request */
 125         ret = regmap_read_poll_timeout(pd->regmap, GPC_CNTR, val, !(val & req),
 126                                        1, 50);
 127         if (ret)
 128                 pr_err("powerup request on domain %s timed out\n", genpd->name);
 129
 130         /* Wait for reset to propagate through peripherals */
 131         usleep_range(5, 10);
 132
 133         /* Disable reset clocks for all devices in the domain */
 134         for (i = 0; i < pd->num_clks; i++)
 135                 clk_disable_unprepare(pd->clk[i]);
 136
 137         return 0;
 138 }
 139
 140 static int imx_pgc_get_clocks(struct device *dev, struct imx_pm_domain *domain)
 141 {
 142         int i, ret;
 143
 144         for (i = 0; ; i++) {
 145                 struct clk *clk = of_clk_get(dev->of_node, i);
 146                 if (IS_ERR(clk))
 147                         break;
 148                 if (i >= GPC_CLK_MAX) {
 149                         dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
 150                         ret = -EINVAL;
 151                         goto clk_err;
 152                 }
 153                 domain->clk[i] = clk;
 154         }
 155         domain->num_clks = i;
 156
 157         return 0;
 158
 159 clk_err:
 160         while (i--)
 161                 clk_put(domain->clk[i]);
 162
 163         return ret;
 164 }
 165
 166 static void imx_pgc_put_clocks(struct imx_pm_domain *domain)
 167 {
 168         int i;
 169
 170         for (i = domain->num_clks - 1; i >= 0; i--)
 171                 clk_put(domain->clk[i]);
 172 }
 173
 174 static int imx_pgc_parse_dt(struct device *dev, struct imx_pm_domain *domain)
 175 {
 176         /* try to get the domain supply regulator */
 177         domain->supply = devm_regulator_get_optional(dev, "power");
 178         if (IS_ERR(domain->supply)) {
 179                 if (PTR_ERR(domain->supply) == -ENODEV)
 180                         domain->supply = NULL;
 181                 else
 182                         return PTR_ERR(domain->supply);
 183         }
 184
 185         /* try to get all clocks needed for reset propagation */
 186         return imx_pgc_get_clocks(dev, domain);
 187 }
 188
 189 static int imx_pgc_power_domain_probe(struct platform_device *pdev)
 190 {
 191         struct imx_pm_domain *domain = pdev->dev.platform_data;
 192         struct device *dev = &pdev->dev;
 193         int ret;
 194
 195         /* if this PD is associated with a DT node try to parse it */
 196         if (dev->of_node) {
 197                 ret = imx_pgc_parse_dt(dev, domain);
 198                 if (ret)
 199                         return ret;
 200         }
 201
 202         /* initially power on the domain */
 203         if (domain->base.power_on)
 204                 domain->base.power_on(&domain->base);
 205
 206         if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
 207                 pm_genpd_init(&domain->base, NULL, false);
 208                 ret = of_genpd_add_provider_simple(dev->of_node, &domain->base);
 209                 if (ret)
 210                         goto genpd_err;
 211         }
 212
 213         device_link_add(dev, dev->parent, DL_FLAG_AUTOREMOVE);
 214
 215         return 0;
 216
 217 genpd_err:
 218         pm_genpd_remove(&domain->base);
 219         imx_pgc_put_clocks(domain);
 220
 221         return ret;
 222 }
 223
 224 static int imx_pgc_power_domain_remove(struct platform_device *pdev)
 225 {
 226         struct imx_pm_domain *domain = pdev->dev.platform_data;
 227
 228         if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
 229                 of_genpd_del_provider(pdev->dev.of_node);
 230                 pm_genpd_remove(&domain->base);
 231                 imx_pgc_put_clocks(domain);
 232         }
 233
 234         return 0;
 235 }
 236
 237 static const struct platform_device_id imx_pgc_power_domain_id[] = {
 238         { "imx-pgc-power-domain"},
 239         { },
 240 };
 241
 242 static struct platform_driver imx_pgc_power_domain_driver = {
 243         .driver = {
 244                 .name = "imx-pgc-pd",
 245         },
 246         .probe = imx_pgc_power_domain_probe,
 247         .remove = imx_pgc_power_domain_remove,
 248         .id_table = imx_pgc_power_domain_id,
 249 };
 250 builtin_platform_driver(imx_pgc_power_domain_driver)
 251
 252 #define GPC_PGC_DOMAIN_ARM      0
 253 #define GPC_PGC_DOMAIN_PU       1
 254 #define GPC_PGC_DOMAIN_DISPLAY  2
 255
 256 static struct genpd_power_state imx6_pm_domain_pu_state = {
 257         .power_off_latency_ns = 25000,
 258         .power_on_latency_ns = 2000000,
 259 };
 260
 261 static struct imx_pm_domain imx_gpc_domains[] = {
 262         {
 263                 .base = {
 264                         .name = "ARM",
 265                 },
 266         }, {
 267                 .base = {
 268                         .name = "PU",
 269                         .power_off = imx6_pm_domain_power_off,
 270                         .power_on = imx6_pm_domain_power_on,
 271                         .states = &imx6_pm_domain_pu_state,
 272                         .state_count = 1,
 273                 },
 274                 .reg_offs = 0x260,
 275                 .cntr_pdn_bit = 0,
 276         }, {
 277                 .base = {
 278                         .name = "DISPLAY",
 279                         .power_off = imx6_pm_domain_power_off,
 280                         .power_on = imx6_pm_domain_power_on,
 281                 },
 282                 .reg_offs = 0x240,
 283                 .cntr_pdn_bit = 4,
 284         }
 285 };
 286
 287 struct imx_gpc_dt_data {
 288         int num_domains;
 289         bool err009619_present;
 290 };
 291
 292 static const struct imx_gpc_dt_data imx6q_dt_data = {
 293         .num_domains = 2,
 294         .err009619_present = false,
 295 };
 296
 297 static const struct imx_gpc_dt_data imx6qp_dt_data = {
 298         .num_domains = 2,
 299         .err009619_present = true,
 300 };
 301
 302 static const struct imx_gpc_dt_data imx6sl_dt_data = {
 303         .num_domains = 3,
 304         .err009619_present = false,
 305 };
 306
 307 static const struct of_device_id imx_gpc_dt_ids[] = {
 308         { .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
 309         { .compatible = "fsl,imx6qp-gpc", .data = &imx6qp_dt_data },
 310         { .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
 311         { }
 312 };
 313
 314 static const struct regmap_range yes_ranges[] = {
 315         regmap_reg_range(GPC_CNTR, GPC_CNTR),
 316         regmap_reg_range(GPC_PGC_PCI_PDN, GPC_PGC_PCI_SR),
 317         regmap_reg_range(GPC_PGC_GPU_PDN, GPC_PGC_GPU_SR),
 318         regmap_reg_range(GPC_PGC_DISP_PDN, GPC_PGC_DISP_SR),
 319 };
 320
 321 static const struct regmap_access_table access_table = {
 322         .yes_ranges     = yes_ranges,
 323         .n_yes_ranges   = ARRAY_SIZE(yes_ranges),
 324 };
 325
 326 static const struct regmap_config imx_gpc_regmap_config = {
 327         .reg_bits = 32,
 328         .val_bits = 32,
 329         .reg_stride = 4,
 330         .rd_table = &access_table,
 331         .wr_table = &access_table,
 332         .max_register = 0x2ac,
 333         .fast_io = true,
 334 };
 335
 336 static struct generic_pm_domain *imx_gpc_onecell_domains[] = {
 337         &imx_gpc_domains[0].base,
 338         &imx_gpc_domains[1].base,
 339 };
 340
 341 static struct genpd_onecell_data imx_gpc_onecell_data = {
 342         .domains = imx_gpc_onecell_domains,
 343         .num_domains = 2,
 344 };
 345
 346 static int imx_gpc_old_dt_init(struct device *dev, struct regmap *regmap,
 347                                unsigned int num_domains)
 348 {
 349         struct imx_pm_domain *domain;
 350         int i, ret;
 351
 352         for (i = 0; i < num_domains; i++) {
 353                 domain = &imx_gpc_domains[i];
 354                 domain->regmap = regmap;
 355                 domain->ipg_rate_mhz = 66;
 356
 357                 if (i == 1) {
 358                         domain->supply = devm_regulator_get(dev, "pu");
 359                         if (IS_ERR(domain->supply))
 360                                 return PTR_ERR(domain->supply);;
 361
 362                         ret = imx_pgc_get_clocks(dev, domain);
 363                         if (ret)
 364                                 goto clk_err;
 365
 366                         domain->base.power_on(&domain->base);
 367                 }
 368         }
 369
 370         for (i = 0; i < num_domains; i++)
 371                 pm_genpd_init(&imx_gpc_domains[i].base, NULL, false);
 372
 373         if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
 374                 ret = of_genpd_add_provider_onecell(dev->of_node,
 375                                                     &imx_gpc_onecell_data);
 376                 if (ret)
 377                         goto genpd_err;
 378         }
 379
 380         return 0;
 381
 382 genpd_err:
 383         for (i = 0; i < num_domains; i++)
 384                 pm_genpd_remove(&imx_gpc_domains[i].base);
 385         imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
 386 clk_err:
 387         return ret;
 388 }
 389
 390 static int imx_gpc_probe(struct platform_device *pdev)
 391 {
 392         const struct of_device_id *of_id =
 393                         of_match_device(imx_gpc_dt_ids, &pdev->dev);
 394         const struct imx_gpc_dt_data *of_id_data = of_id->data;
 395         struct device_node *pgc_node;
 396         struct regmap *regmap;
 397         struct resource *res;
 398         void __iomem *base;
 399         int ret;
 400
 401         pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
 402
 403         /* bail out if DT too old and doesn't provide the necessary info */
 404         if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
 405             !pgc_node)
 406                 return 0;
 407
 408         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 409         base = devm_ioremap_resource(&pdev->dev, res);
 410         if (IS_ERR(base))
 411                 return PTR_ERR(base);
 412
 413         regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
 414                                            &imx_gpc_regmap_config);
 415         if (IS_ERR(regmap)) {
 416                 ret = PTR_ERR(regmap);
 417                 dev_err(&pdev->dev, "failed to init regmap: %d\n",
 418                         ret);
 419                 return ret;
 420         }
 421
 422         /* Disable PU power down in normal operation if ERR009619 is present */
 423         if (of_id_data->err009619_present)
 424                 imx_gpc_domains[GPC_PGC_DOMAIN_PU].flags |=
 425                                 PGC_DOMAIN_FLAG_NO_PD;
 426
 427         if (!pgc_node) {
 428                 ret = imx_gpc_old_dt_init(&pdev->dev, regmap,
 429                                           of_id_data->num_domains);
 430                 if (ret)
 431                         return ret;
 432         } else {
 433                 struct imx_pm_domain *domain;
 434                 struct platform_device *pd_pdev;
 435                 struct device_node *np;
 436                 struct clk *ipg_clk;
 437                 unsigned int ipg_rate_mhz;
 438                 int domain_index;
 439
 440                 ipg_clk = devm_clk_get(&pdev->dev, "ipg");
 441                 if (IS_ERR(ipg_clk))
 442                         return PTR_ERR(ipg_clk);
 443                 ipg_rate_mhz = clk_get_rate(ipg_clk) / 1000000;
 444
 445                 for_each_child_of_node(pgc_node, np) {
 446                         ret = of_property_read_u32(np, "reg", &domain_index);
 447                         if (ret) {
 448                                 of_node_put(np);
 449                                 return ret;
 450                         }
 451                         if (domain_index >= of_id_data->num_domains)
 452                                 continue;
 453
 454                         domain = &imx_gpc_domains[domain_index];
 455                         domain->regmap = regmap;
 456                         domain->ipg_rate_mhz = ipg_rate_mhz;
 457
 458                         pd_pdev = platform_device_alloc("imx-pgc-power-domain",
 459                                                         domain_index);
 460                         if (!pd_pdev) {
 461                                 of_node_put(np);
 462                                 return -ENOMEM;
 463                         }
 464                         pd_pdev->dev.platform_data = domain;
 465                         pd_pdev->dev.parent = &pdev->dev;
 466                         pd_pdev->dev.of_node = np;
 467
 468                         ret = platform_device_add(pd_pdev);
 469                         if (ret) {
 470                                 platform_device_put(pd_pdev);
 471                                 of_node_put(np);
 472                                 return ret;
 473                         }
 474                 }
 475         }
 476
 477         return 0;
 478 }
 479
 480 static int imx_gpc_remove(struct platform_device *pdev)
 481 {
 482         struct device_node *pgc_node;
 483         int ret;
 484
 485         pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
 486
 487         /* bail out if DT too old and doesn't provide the necessary info */
 488         if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
 489             !pgc_node)
 490                 return 0;
 491
 492         /*
 493          * If the old DT binding is used the toplevel driver needs to
 494          * de-register the power domains
 495          */
 496         if (!pgc_node) {
 497                 of_genpd_del_provider(pdev->dev.of_node);
 498
 499                 ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base);
 500                 if (ret)
 501                         return ret;
 502                 imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
 503
 504                 ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base);
 505                 if (ret)
 506                         return ret;
 507         }
 508
 509         return 0;
 510 }
 511
 512 static struct platform_driver imx_gpc_driver = {
 513         .driver = {
 514                 .name = "imx-gpc",
 515                 .of_match_table = imx_gpc_dt_ids,
 516         },
 517         .probe = imx_gpc_probe,
 518         .remove = imx_gpc_remove,
 519 };
 520 builtin_platform_driver(imx_gpc_driver)