drivers/soc/tegra/fuse/fuse-tegra.c

   1 /*
   2  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  *
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/device.h>
  20 #include <linux/kobject.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/io.h>
  26
  27 #include <soc/tegra/common.h>
  28 #include <soc/tegra/fuse.h>
  29
  30 #include "fuse.h"
  31
  32 struct tegra_sku_info tegra_sku_info;
  33 EXPORT_SYMBOL(tegra_sku_info);
  34
  35 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
  36         [TEGRA_REVISION_UNKNOWN] = "unknown",
  37         [TEGRA_REVISION_A01]     = "A01",
  38         [TEGRA_REVISION_A02]     = "A02",
  39         [TEGRA_REVISION_A03]     = "A03",
  40         [TEGRA_REVISION_A03p]    = "A03 prime",
  41         [TEGRA_REVISION_A04]     = "A04",
  42 };
  43
  44 static u8 fuse_readb(struct tegra_fuse *fuse, unsigned int offset)
  45 {
  46         u32 val;
  47
  48         val = fuse->read(fuse, round_down(offset, 4));
  49         val >>= (offset % 4) * 8;
  50         val &= 0xff;
  51
  52         return val;
  53 }
  54
  55 static ssize_t fuse_read(struct file *fd, struct kobject *kobj,
  56                          struct bin_attribute *attr, char *buf,
  57                          loff_t pos, size_t size)
  58 {
  59         struct device *dev = kobj_to_dev(kobj);
  60         struct tegra_fuse *fuse = dev_get_drvdata(dev);
  61         int i;
  62
  63         if (pos < 0 || pos >= attr->size)
  64                 return 0;
  65
  66         if (size > attr->size - pos)
  67                 size = attr->size - pos;
  68
  69         for (i = 0; i < size; i++)
  70                 buf[i] = fuse_readb(fuse, pos + i);
  71
  72         return i;
  73 }
  74
  75 static struct bin_attribute fuse_bin_attr = {
  76         .attr = { .name = "fuse", .mode = S_IRUGO, },
  77         .read = fuse_read,
  78 };
  79
  80 static int tegra_fuse_create_sysfs(struct device *dev, unsigned int size,
  81                                    const struct tegra_fuse_info *info)
  82 {
  83         fuse_bin_attr.size = size;
  84
  85         return device_create_bin_file(dev, &fuse_bin_attr);
  86 }
  87
  88 static const struct of_device_id car_match[] __initconst = {
  89         { .compatible = "nvidia,tegra20-car", },
  90         { .compatible = "nvidia,tegra30-car", },
  91         { .compatible = "nvidia,tegra114-car", },
  92         { .compatible = "nvidia,tegra124-car", },
  93         { .compatible = "nvidia,tegra132-car", },
  94         { .compatible = "nvidia,tegra210-car", },
  95         {},
  96 };
  97
  98 static struct tegra_fuse *fuse = &(struct tegra_fuse) {
  99         .base = NULL,
 100         .soc = NULL,
 101 };
 102
 103 static const struct of_device_id tegra_fuse_match[] = {
 104 #ifdef CONFIG_ARCH_TEGRA_210_SOC
 105         { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
 106 #endif
 107 #ifdef CONFIG_ARCH_TEGRA_132_SOC
 108         { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
 109 #endif
 110 #ifdef CONFIG_ARCH_TEGRA_124_SOC
 111         { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
 112 #endif
 113 #ifdef CONFIG_ARCH_TEGRA_114_SOC
 114         { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
 115 #endif
 116 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 117         { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
 118 #endif
 119 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 120         { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
 121 #endif
 122         { /* sentinel */ }
 123 };
 124
 125 static int tegra_fuse_probe(struct platform_device *pdev)
 126 {
 127         void __iomem *base = fuse->base;
 128         struct resource *res;
 129         int err;
 130
 131         /* take over the memory region from the early initialization */
 132         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 133         fuse->base = devm_ioremap_resource(&pdev->dev, res);
 134         if (IS_ERR(fuse->base)) {
 135                 err = PTR_ERR(fuse->base);
 136                 fuse->base = base;
 137                 return err;
 138         }
 139
 140         fuse->clk = devm_clk_get(&pdev->dev, "fuse");
 141         if (IS_ERR(fuse->clk)) {
 142                 dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
 143                         PTR_ERR(fuse->clk));
 144                 fuse->base = base;
 145                 return PTR_ERR(fuse->clk);
 146         }
 147
 148         platform_set_drvdata(pdev, fuse);
 149         fuse->dev = &pdev->dev;
 150
 151         if (fuse->soc->probe) {
 152                 err = fuse->soc->probe(fuse);
 153                 if (err < 0) {
 154                         fuse->base = base;
 155                         return err;
 156                 }
 157         }
 158
 159         if (tegra_fuse_create_sysfs(&pdev->dev, fuse->soc->info->size,
 160                                     fuse->soc->info))
 161                 return -ENODEV;
 162
 163         /* release the early I/O memory mapping */
 164         iounmap(base);
 165
 166         return 0;
 167 }
 168
 169 static struct platform_driver tegra_fuse_driver = {
 170         .driver = {
 171                 .name = "tegra-fuse",
 172                 .of_match_table = tegra_fuse_match,
 173                 .suppress_bind_attrs = true,
 174         },
 175         .probe = tegra_fuse_probe,
 176 };
 177 module_platform_driver(tegra_fuse_driver);
 178
 179 bool __init tegra_fuse_read_spare(unsigned int spare)
 180 {
 181         unsigned int offset = fuse->soc->info->spare + spare * 4;
 182
 183         return fuse->read_early(fuse, offset) & 1;
 184 }
 185
 186 u32 __init tegra_fuse_read_early(unsigned int offset)
 187 {
 188         return fuse->read_early(fuse, offset);
 189 }
 190
 191 int tegra_fuse_readl(unsigned long offset, u32 *value)
 192 {
 193         if (!fuse->read)
 194                 return -EPROBE_DEFER;
 195
 196         *value = fuse->read(fuse, offset);
 197
 198         return 0;
 199 }
 200 EXPORT_SYMBOL(tegra_fuse_readl);
 201
 202 static void tegra_enable_fuse_clk(void __iomem *base)
 203 {
 204         u32 reg;
 205
 206         reg = readl_relaxed(base + 0x48);
 207         reg |= 1 << 28;
 208         writel(reg, base + 0x48);
 209
 210         /*
 211          * Enable FUSE clock. This needs to be hardcoded because the clock
 212          * subsystem is not active during early boot.
 213          */
 214         reg = readl(base + 0x14);
 215         reg |= 1 << 7;
 216         writel(reg, base + 0x14);
 217 }
 218
 219 static int __init tegra_init_fuse(void)
 220 {
 221         const struct of_device_id *match;
 222         struct device_node *np;
 223         struct resource regs;
 224
 225         tegra_init_apbmisc();
 226
 227         np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
 228         if (!np) {
 229                 /*
 230                  * Fall back to legacy initialization for 32-bit ARM only. All
 231                  * 64-bit ARM device tree files for Tegra are required to have
 232                  * a FUSE node.
 233                  *
 234                  * This is for backwards-compatibility with old device trees
 235                  * that didn't contain a FUSE node.
 236                  */
 237                 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
 238                         u8 chip = tegra_get_chip_id();
 239
 240                         regs.start = 0x7000f800;
 241                         regs.end = 0x7000fbff;
 242                         regs.flags = IORESOURCE_MEM;
 243
 244                         switch (chip) {
 245 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 246                         case TEGRA20:
 247                                 fuse->soc = &tegra20_fuse_soc;
 248                                 break;
 249 #endif
 250
 251 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 252                         case TEGRA30:
 253                                 fuse->soc = &tegra30_fuse_soc;
 254                                 break;
 255 #endif
 256
 257 #ifdef CONFIG_ARCH_TEGRA_114_SOC
 258                         case TEGRA114:
 259                                 fuse->soc = &tegra114_fuse_soc;
 260                                 break;
 261 #endif
 262
 263 #ifdef CONFIG_ARCH_TEGRA_124_SOC
 264                         case TEGRA124:
 265                                 fuse->soc = &tegra124_fuse_soc;
 266                                 break;
 267 #endif
 268
 269                         default:
 270                                 pr_warn("Unsupported SoC: %02x\n", chip);
 271                                 break;
 272                         }
 273                 } else {
 274                         /*
 275                          * At this point we're not running on Tegra, so play
 276                          * nice with multi-platform kernels.
 277                          */
 278                         return 0;
 279                 }
 280         } else {
 281                 /*
 282                  * Extract information from the device tree if we've found a
 283                  * matching node.
 284                  */
 285                 if (of_address_to_resource(np, 0, &regs) < 0) {
 286                         pr_err("failed to get FUSE register\n");
 287                         return -ENXIO;
 288                 }
 289
 290                 fuse->soc = match->data;
 291         }
 292
 293         np = of_find_matching_node(NULL, car_match);
 294         if (np) {
 295                 void __iomem *base = of_iomap(np, 0);
 296                 if (base) {
 297                         tegra_enable_fuse_clk(base);
 298                         iounmap(base);
 299                 } else {
 300                         pr_err("failed to map clock registers\n");
 301                         return -ENXIO;
 302                 }
 303         }
 304
 305         fuse->base = ioremap_nocache(regs.start, resource_size(&regs));
 306         if (!fuse->base) {
 307                 pr_err("failed to map FUSE registers\n");
 308                 return -ENXIO;
 309         }
 310
 311         fuse->soc->init(fuse);
 312
 313         pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
 314                 tegra_revision_name[tegra_sku_info.revision],
 315                 tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
 316                 tegra_sku_info.soc_process_id);
 317         pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
 318                  tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
 319
 320         return 0;
 321 }
 322 early_initcall(tegra_init_fuse);