drivers/spi/spi-atmel.c

   1 /*
   2  * Driver for Atmel AT32 and AT91 SPI Controllers
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/clk.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/delay.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_data/dma-atmel.h>
  23 #include <linux/of.h>
  24
  25 #include <linux/io.h>
  26 #include <linux/gpio.h>
  27 #include <linux/of_gpio.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/pm_runtime.h>
  30
  31 /* SPI register offsets */
  32 #define SPI_CR                                  0x0000
  33 #define SPI_MR                                  0x0004
  34 #define SPI_RDR                                 0x0008
  35 #define SPI_TDR                                 0x000c
  36 #define SPI_SR                                  0x0010
  37 #define SPI_IER                                 0x0014
  38 #define SPI_IDR                                 0x0018
  39 #define SPI_IMR                                 0x001c
  40 #define SPI_CSR0                                0x0030
  41 #define SPI_CSR1                                0x0034
  42 #define SPI_CSR2                                0x0038
  43 #define SPI_CSR3                                0x003c
  44 #define SPI_FMR                                 0x0040
  45 #define SPI_FLR                                 0x0044
  46 #define SPI_VERSION                             0x00fc
  47 #define SPI_RPR                                 0x0100
  48 #define SPI_RCR                                 0x0104
  49 #define SPI_TPR                                 0x0108
  50 #define SPI_TCR                                 0x010c
  51 #define SPI_RNPR                                0x0110
  52 #define SPI_RNCR                                0x0114
  53 #define SPI_TNPR                                0x0118
  54 #define SPI_TNCR                                0x011c
  55 #define SPI_PTCR                                0x0120
  56 #define SPI_PTSR                                0x0124
  57
  58 /* Bitfields in CR */
  59 #define SPI_SPIEN_OFFSET                        0
  60 #define SPI_SPIEN_SIZE                          1
  61 #define SPI_SPIDIS_OFFSET                       1
  62 #define SPI_SPIDIS_SIZE                         1
  63 #define SPI_SWRST_OFFSET                        7
  64 #define SPI_SWRST_SIZE                          1
  65 #define SPI_LASTXFER_OFFSET                     24
  66 #define SPI_LASTXFER_SIZE                       1
  67 #define SPI_TXFCLR_OFFSET                       16
  68 #define SPI_TXFCLR_SIZE                         1
  69 #define SPI_RXFCLR_OFFSET                       17
  70 #define SPI_RXFCLR_SIZE                         1
  71 #define SPI_FIFOEN_OFFSET                       30
  72 #define SPI_FIFOEN_SIZE                         1
  73 #define SPI_FIFODIS_OFFSET                      31
  74 #define SPI_FIFODIS_SIZE                        1
  75
  76 /* Bitfields in MR */
  77 #define SPI_MSTR_OFFSET                         0
  78 #define SPI_MSTR_SIZE                           1
  79 #define SPI_PS_OFFSET                           1
  80 #define SPI_PS_SIZE                             1
  81 #define SPI_PCSDEC_OFFSET                       2
  82 #define SPI_PCSDEC_SIZE                         1
  83 #define SPI_FDIV_OFFSET                         3
  84 #define SPI_FDIV_SIZE                           1
  85 #define SPI_MODFDIS_OFFSET                      4
  86 #define SPI_MODFDIS_SIZE                        1
  87 #define SPI_WDRBT_OFFSET                        5
  88 #define SPI_WDRBT_SIZE                          1
  89 #define SPI_LLB_OFFSET                          7
  90 #define SPI_LLB_SIZE                            1
  91 #define SPI_PCS_OFFSET                          16
  92 #define SPI_PCS_SIZE                            4
  93 #define SPI_DLYBCS_OFFSET                       24
  94 #define SPI_DLYBCS_SIZE                         8
  95
  96 /* Bitfields in RDR */
  97 #define SPI_RD_OFFSET                           0
  98 #define SPI_RD_SIZE                             16
  99
 100 /* Bitfields in TDR */
 101 #define SPI_TD_OFFSET                           0
 102 #define SPI_TD_SIZE                             16
 103
 104 /* Bitfields in SR */
 105 #define SPI_RDRF_OFFSET                         0
 106 #define SPI_RDRF_SIZE                           1
 107 #define SPI_TDRE_OFFSET                         1
 108 #define SPI_TDRE_SIZE                           1
 109 #define SPI_MODF_OFFSET                         2
 110 #define SPI_MODF_SIZE                           1
 111 #define SPI_OVRES_OFFSET                        3
 112 #define SPI_OVRES_SIZE                          1
 113 #define SPI_ENDRX_OFFSET                        4
 114 #define SPI_ENDRX_SIZE                          1
 115 #define SPI_ENDTX_OFFSET                        5
 116 #define SPI_ENDTX_SIZE                          1
 117 #define SPI_RXBUFF_OFFSET                       6
 118 #define SPI_RXBUFF_SIZE                         1
 119 #define SPI_TXBUFE_OFFSET                       7
 120 #define SPI_TXBUFE_SIZE                         1
 121 #define SPI_NSSR_OFFSET                         8
 122 #define SPI_NSSR_SIZE                           1
 123 #define SPI_TXEMPTY_OFFSET                      9
 124 #define SPI_TXEMPTY_SIZE                        1
 125 #define SPI_SPIENS_OFFSET                       16
 126 #define SPI_SPIENS_SIZE                         1
 127 #define SPI_TXFEF_OFFSET                        24
 128 #define SPI_TXFEF_SIZE                          1
 129 #define SPI_TXFFF_OFFSET                        25
 130 #define SPI_TXFFF_SIZE                          1
 131 #define SPI_TXFTHF_OFFSET                       26
 132 #define SPI_TXFTHF_SIZE                         1
 133 #define SPI_RXFEF_OFFSET                        27
 134 #define SPI_RXFEF_SIZE                          1
 135 #define SPI_RXFFF_OFFSET                        28
 136 #define SPI_RXFFF_SIZE                          1
 137 #define SPI_RXFTHF_OFFSET                       29
 138 #define SPI_RXFTHF_SIZE                         1
 139 #define SPI_TXFPTEF_OFFSET                      30
 140 #define SPI_TXFPTEF_SIZE                        1
 141 #define SPI_RXFPTEF_OFFSET                      31
 142 #define SPI_RXFPTEF_SIZE                        1
 143
 144 /* Bitfields in CSR0 */
 145 #define SPI_CPOL_OFFSET                         0
 146 #define SPI_CPOL_SIZE                           1
 147 #define SPI_NCPHA_OFFSET                        1
 148 #define SPI_NCPHA_SIZE                          1
 149 #define SPI_CSAAT_OFFSET                        3
 150 #define SPI_CSAAT_SIZE                          1
 151 #define SPI_BITS_OFFSET                         4
 152 #define SPI_BITS_SIZE                           4
 153 #define SPI_SCBR_OFFSET                         8
 154 #define SPI_SCBR_SIZE                           8
 155 #define SPI_DLYBS_OFFSET                        16
 156 #define SPI_DLYBS_SIZE                          8
 157 #define SPI_DLYBCT_OFFSET                       24
 158 #define SPI_DLYBCT_SIZE                         8
 159
 160 /* Bitfields in RCR */
 161 #define SPI_RXCTR_OFFSET                        0
 162 #define SPI_RXCTR_SIZE                          16
 163
 164 /* Bitfields in TCR */
 165 #define SPI_TXCTR_OFFSET                        0
 166 #define SPI_TXCTR_SIZE                          16
 167
 168 /* Bitfields in RNCR */
 169 #define SPI_RXNCR_OFFSET                        0
 170 #define SPI_RXNCR_SIZE                          16
 171
 172 /* Bitfields in TNCR */
 173 #define SPI_TXNCR_OFFSET                        0
 174 #define SPI_TXNCR_SIZE                          16
 175
 176 /* Bitfields in PTCR */
 177 #define SPI_RXTEN_OFFSET                        0
 178 #define SPI_RXTEN_SIZE                          1
 179 #define SPI_RXTDIS_OFFSET                       1
 180 #define SPI_RXTDIS_SIZE                         1
 181 #define SPI_TXTEN_OFFSET                        8
 182 #define SPI_TXTEN_SIZE                          1
 183 #define SPI_TXTDIS_OFFSET                       9
 184 #define SPI_TXTDIS_SIZE                         1
 185
 186 /* Bitfields in FMR */
 187 #define SPI_TXRDYM_OFFSET                       0
 188 #define SPI_TXRDYM_SIZE                         2
 189 #define SPI_RXRDYM_OFFSET                       4
 190 #define SPI_RXRDYM_SIZE                         2
 191 #define SPI_TXFTHRES_OFFSET                     16
 192 #define SPI_TXFTHRES_SIZE                       6
 193 #define SPI_RXFTHRES_OFFSET                     24
 194 #define SPI_RXFTHRES_SIZE                       6
 195
 196 /* Bitfields in FLR */
 197 #define SPI_TXFL_OFFSET                         0
 198 #define SPI_TXFL_SIZE                           6
 199 #define SPI_RXFL_OFFSET                         16
 200 #define SPI_RXFL_SIZE                           6
 201
 202 /* Constants for BITS */
 203 #define SPI_BITS_8_BPT                          0
 204 #define SPI_BITS_9_BPT                          1
 205 #define SPI_BITS_10_BPT                         2
 206 #define SPI_BITS_11_BPT                         3
 207 #define SPI_BITS_12_BPT                         4
 208 #define SPI_BITS_13_BPT                         5
 209 #define SPI_BITS_14_BPT                         6
 210 #define SPI_BITS_15_BPT                         7
 211 #define SPI_BITS_16_BPT                         8
 212 #define SPI_ONE_DATA                            0
 213 #define SPI_TWO_DATA                            1
 214 #define SPI_FOUR_DATA                           2
 215
 216 /* Bit manipulation macros */
 217 #define SPI_BIT(name) \
 218         (1 << SPI_##name##_OFFSET)
 219 #define SPI_BF(name, value) \
 220         (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
 221 #define SPI_BFEXT(name, value) \
 222         (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
 223 #define SPI_BFINS(name, value, old) \
 224         (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
 225           | SPI_BF(name, value))
 226
 227 /* Register access macros */
 228 #ifdef CONFIG_AVR32
 229 #define spi_readl(port, reg) \
 230         __raw_readl((port)->regs + SPI_##reg)
 231 #define spi_writel(port, reg, value) \
 232         __raw_writel((value), (port)->regs + SPI_##reg)
 233
 234 #define spi_readw(port, reg) \
 235         __raw_readw((port)->regs + SPI_##reg)
 236 #define spi_writew(port, reg, value) \
 237         __raw_writew((value), (port)->regs + SPI_##reg)
 238
 239 #define spi_readb(port, reg) \
 240         __raw_readb((port)->regs + SPI_##reg)
 241 #define spi_writeb(port, reg, value) \
 242         __raw_writeb((value), (port)->regs + SPI_##reg)
 243 #else
 244 #define spi_readl(port, reg) \
 245         readl_relaxed((port)->regs + SPI_##reg)
 246 #define spi_writel(port, reg, value) \
 247         writel_relaxed((value), (port)->regs + SPI_##reg)
 248
 249 #define spi_readw(port, reg) \
 250         readw_relaxed((port)->regs + SPI_##reg)
 251 #define spi_writew(port, reg, value) \
 252         writew_relaxed((value), (port)->regs + SPI_##reg)
 253
 254 #define spi_readb(port, reg) \
 255         readb_relaxed((port)->regs + SPI_##reg)
 256 #define spi_writeb(port, reg, value) \
 257         writeb_relaxed((value), (port)->regs + SPI_##reg)
 258 #endif
 259 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 260  * cache operations; better heuristics consider wordsize and bitrate.
 261  */
 262 #define DMA_MIN_BYTES   16
 263
 264 #define SPI_DMA_TIMEOUT         (msecs_to_jiffies(1000))
 265
 266 #define AUTOSUSPEND_TIMEOUT     2000
 267
 268 struct atmel_spi_caps {
 269         bool    is_spi2;
 270         bool    has_wdrbt;
 271         bool    has_dma_support;
 272         bool    has_pdc_support;
 273 };
 274
 275 /*
 276  * The core SPI transfer engine just talks to a register bank to set up
 277  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
 278  * framework provides the base clock, subdivided for each spi_device.
 279  */
 280 struct atmel_spi {
 281         spinlock_t              lock;
 282         unsigned long           flags;
 283
 284         phys_addr_t             phybase;
 285         void __iomem            *regs;
 286         int                     irq;
 287         struct clk              *clk;
 288         struct platform_device  *pdev;
 289         unsigned long           spi_clk;
 290
 291         struct spi_transfer     *current_transfer;
 292         int                     current_remaining_bytes;
 293         int                     done_status;
 294         dma_addr_t              dma_addr_rx_bbuf;
 295         dma_addr_t              dma_addr_tx_bbuf;
 296         void                    *addr_rx_bbuf;
 297         void                    *addr_tx_bbuf;
 298
 299         struct completion       xfer_completion;
 300
 301         struct atmel_spi_caps   caps;
 302
 303         bool                    use_dma;
 304         bool                    use_pdc;
 305         bool                    use_cs_gpios;
 306
 307         bool                    keep_cs;
 308
 309         u32                     fifo_size;
 310 };
 311
 312 /* Controller-specific per-slave state */
 313 struct atmel_spi_device {
 314         unsigned int            npcs_pin;
 315         u32                     csr;
 316 };
 317
 318 #define SPI_MAX_DMA_XFER        65535 /* true for both PDC and DMA */
 319 #define INVALID_DMA_ADDRESS     0xffffffff
 320
 321 /*
 322  * Version 2 of the SPI controller has
 323  *  - CR.LASTXFER
 324  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
 325  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
 326  *  - SPI_CSRx.CSAAT
 327  *  - SPI_CSRx.SBCR allows faster clocking
 328  */
 329 static bool atmel_spi_is_v2(struct atmel_spi *as)
 330 {
 331         return as->caps.is_spi2;
 332 }
 333
 334 /*
 335  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
 336  * they assume that spi slave device state will not change on deselect, so
 337  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
 338  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
 339  * controllers have CSAAT and friends.
 340  *
 341  * Since the CSAAT functionality is a bit weird on newer controllers as
 342  * well, we use GPIO to control nCSx pins on all controllers, updating
 343  * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
 344  * support active-high chipselects despite the controller's belief that
 345  * only active-low devices/systems exists.
 346  *
 347  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
 348  * right when driven with GPIO.  ("Mode Fault does not allow more than one
 349  * Master on Chip Select 0.")  No workaround exists for that ... so for
 350  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
 351  * and (c) will trigger that first erratum in some cases.
 352  */
 353
 354 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 355 {
 356         struct atmel_spi_device *asd = spi->controller_state;
 357         unsigned active = spi->mode & SPI_CS_HIGH;
 358         u32 mr;
 359
 360         if (atmel_spi_is_v2(as)) {
 361                 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
 362                 /* For the low SPI version, there is a issue that PDC transfer
 363                  * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
 364                  */
 365                 spi_writel(as, CSR0, asd->csr);
 366                 if (as->caps.has_wdrbt) {
 367                         spi_writel(as, MR,
 368                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 369                                         | SPI_BIT(WDRBT)
 370                                         | SPI_BIT(MODFDIS)
 371                                         | SPI_BIT(MSTR));
 372                 } else {
 373                         spi_writel(as, MR,
 374                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 375                                         | SPI_BIT(MODFDIS)
 376                                         | SPI_BIT(MSTR));
 377                 }
 378
 379                 mr = spi_readl(as, MR);
 380                 if (as->use_cs_gpios)
 381                         gpio_set_value(asd->npcs_pin, active);
 382         } else {
 383                 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
 384                 int i;
 385                 u32 csr;
 386
 387                 /* Make sure clock polarity is correct */
 388                 for (i = 0; i < spi->master->num_chipselect; i++) {
 389                         csr = spi_readl(as, CSR0 + 4 * i);
 390                         if ((csr ^ cpol) & SPI_BIT(CPOL))
 391                                 spi_writel(as, CSR0 + 4 * i,
 392                                                 csr ^ SPI_BIT(CPOL));
 393                 }
 394
 395                 mr = spi_readl(as, MR);
 396                 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
 397                 if (as->use_cs_gpios && spi->chip_select != 0)
 398                         gpio_set_value(asd->npcs_pin, active);
 399                 spi_writel(as, MR, mr);
 400         }
 401
 402         dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
 403                         asd->npcs_pin, active ? " (high)" : "",
 404                         mr);
 405 }
 406
 407 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 408 {
 409         struct atmel_spi_device *asd = spi->controller_state;
 410         unsigned active = spi->mode & SPI_CS_HIGH;
 411         u32 mr;
 412
 413         /* only deactivate *this* device; sometimes transfers to
 414          * another device may be active when this routine is called.
 415          */
 416         mr = spi_readl(as, MR);
 417         if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
 418                 mr = SPI_BFINS(PCS, 0xf, mr);
 419                 spi_writel(as, MR, mr);
 420         }
 421
 422         dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
 423                         asd->npcs_pin, active ? " (low)" : "",
 424                         mr);
 425
 426         if (!as->use_cs_gpios)
 427                 spi_writel(as, CR, SPI_BIT(LASTXFER));
 428         else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
 429                 gpio_set_value(asd->npcs_pin, !active);
 430 }
 431
 432 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
 433 {
 434         spin_lock_irqsave(&as->lock, as->flags);
 435 }
 436
 437 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
 438 {
 439         spin_unlock_irqrestore(&as->lock, as->flags);
 440 }
 441
 442 static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer)
 443 {
 444         return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf);
 445 }
 446
 447 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
 448                                 struct spi_transfer *xfer)
 449 {
 450         return as->use_dma && xfer->len >= DMA_MIN_BYTES;
 451 }
 452
 453 static bool atmel_spi_can_dma(struct spi_master *master,
 454                               struct spi_device *spi,
 455                               struct spi_transfer *xfer)
 456 {
 457         struct atmel_spi *as = spi_master_get_devdata(master);
 458
 459         if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5))
 460                 return atmel_spi_use_dma(as, xfer) &&
 461                         !atmel_spi_is_vmalloc_xfer(xfer);
 462         else
 463                 return atmel_spi_use_dma(as, xfer);
 464
 465 }
 466
 467 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
 468                                 struct dma_slave_config *slave_config,
 469                                 u8 bits_per_word)
 470 {
 471         struct spi_master *master = platform_get_drvdata(as->pdev);
 472         int err = 0;
 473
 474         if (bits_per_word > 8) {
 475                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 476                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 477         } else {
 478                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 479                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 480         }
 481
 482         slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
 483         slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
 484         slave_config->src_maxburst = 1;
 485         slave_config->dst_maxburst = 1;
 486         slave_config->device_fc = false;
 487
 488         /*
 489          * This driver uses fixed peripheral select mode (PS bit set to '0' in
 490          * the Mode Register).
 491          * So according to the datasheet, when FIFOs are available (and
 492          * enabled), the Transmit FIFO operates in Multiple Data Mode.
 493          * In this mode, up to 2 data, not 4, can be written into the Transmit
 494          * Data Register in a single access.
 495          * However, the first data has to be written into the lowest 16 bits and
 496          * the second data into the highest 16 bits of the Transmit
 497          * Data Register. For 8bit data (the most frequent case), it would
 498          * require to rework tx_buf so each data would actualy fit 16 bits.
 499          * So we'd rather write only one data at the time. Hence the transmit
 500          * path works the same whether FIFOs are available (and enabled) or not.
 501          */
 502         slave_config->direction = DMA_MEM_TO_DEV;
 503         if (dmaengine_slave_config(master->dma_tx, slave_config)) {
 504                 dev_err(&as->pdev->dev,
 505                         "failed to configure tx dma channel\n");
 506                 err = -EINVAL;
 507         }
 508
 509         /*
 510          * This driver configures the spi controller for master mode (MSTR bit
 511          * set to '1' in the Mode Register).
 512          * So according to the datasheet, when FIFOs are available (and
 513          * enabled), the Receive FIFO operates in Single Data Mode.
 514          * So the receive path works the same whether FIFOs are available (and
 515          * enabled) or not.
 516          */
 517         slave_config->direction = DMA_DEV_TO_MEM;
 518         if (dmaengine_slave_config(master->dma_rx, slave_config)) {
 519                 dev_err(&as->pdev->dev,
 520                         "failed to configure rx dma channel\n");
 521                 err = -EINVAL;
 522         }
 523
 524         return err;
 525 }
 526
 527 static int atmel_spi_configure_dma(struct spi_master *master,
 528                                    struct atmel_spi *as)
 529 {
 530         struct dma_slave_config slave_config;
 531         struct device *dev = &as->pdev->dev;
 532         int err;
 533
 534         dma_cap_mask_t mask;
 535         dma_cap_zero(mask);
 536         dma_cap_set(DMA_SLAVE, mask);
 537
 538         master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
 539         if (IS_ERR(master->dma_tx)) {
 540                 err = PTR_ERR(master->dma_tx);
 541                 if (err == -EPROBE_DEFER) {
 542                         dev_warn(dev, "no DMA channel available at the moment\n");
 543                         goto error_clear;
 544                 }
 545                 dev_err(dev,
 546                         "DMA TX channel not available, SPI unable to use DMA\n");
 547                 err = -EBUSY;
 548                 goto error_clear;
 549         }
 550
 551         /*
 552          * No reason to check EPROBE_DEFER here since we have already requested
 553          * tx channel. If it fails here, it's for another reason.
 554          */
 555         master->dma_rx = dma_request_slave_channel(dev, "rx");
 556
 557         if (!master->dma_rx) {
 558                 dev_err(dev,
 559                         "DMA RX channel not available, SPI unable to use DMA\n");
 560                 err = -EBUSY;
 561                 goto error;
 562         }
 563
 564         err = atmel_spi_dma_slave_config(as, &slave_config, 8);
 565         if (err)
 566                 goto error;
 567
 568         dev_info(&as->pdev->dev,
 569                         "Using %s (tx) and %s (rx) for DMA transfers\n",
 570                         dma_chan_name(master->dma_tx),
 571                         dma_chan_name(master->dma_rx));
 572
 573         return 0;
 574 error:
 575         if (master->dma_rx)
 576                 dma_release_channel(master->dma_rx);
 577         if (!IS_ERR(master->dma_tx))
 578                 dma_release_channel(master->dma_tx);
 579 error_clear:
 580         master->dma_tx = master->dma_rx = NULL;
 581         return err;
 582 }
 583
 584 static void atmel_spi_stop_dma(struct spi_master *master)
 585 {
 586         if (master->dma_rx)
 587                 dmaengine_terminate_all(master->dma_rx);
 588         if (master->dma_tx)
 589                 dmaengine_terminate_all(master->dma_tx);
 590 }
 591
 592 static void atmel_spi_release_dma(struct spi_master *master)
 593 {
 594         if (master->dma_rx) {
 595                 dma_release_channel(master->dma_rx);
 596                 master->dma_rx = NULL;
 597         }
 598         if (master->dma_tx) {
 599                 dma_release_channel(master->dma_tx);
 600                 master->dma_tx = NULL;
 601         }
 602 }
 603
 604 /* This function is called by the DMA driver from tasklet context */
 605 static void dma_callback(void *data)
 606 {
 607         struct spi_master       *master = data;
 608         struct atmel_spi        *as = spi_master_get_devdata(master);
 609
 610         if (is_vmalloc_addr(as->current_transfer->rx_buf) &&
 611             IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
 612                 memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf,
 613                        as->current_transfer->len);
 614         }
 615         complete(&as->xfer_completion);
 616 }
 617
 618 /*
 619  * Next transfer using PIO without FIFO.
 620  */
 621 static void atmel_spi_next_xfer_single(struct spi_master *master,
 622                                        struct spi_transfer *xfer)
 623 {
 624         struct atmel_spi        *as = spi_master_get_devdata(master);
 625         unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
 626
 627         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
 628
 629         /* Make sure data is not remaining in RDR */
 630         spi_readl(as, RDR);
 631         while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
 632                 spi_readl(as, RDR);
 633                 cpu_relax();
 634         }
 635
 636         if (xfer->bits_per_word > 8)
 637                 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
 638         else
 639                 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
 640
 641         dev_dbg(master->dev.parent,
 642                 "  start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
 643                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 644                 xfer->bits_per_word);
 645
 646         /* Enable relevant interrupts */
 647         spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
 648 }
 649
 650 /*
 651  * Next transfer using PIO with FIFO.
 652  */
 653 static void atmel_spi_next_xfer_fifo(struct spi_master *master,
 654                                      struct spi_transfer *xfer)
 655 {
 656         struct atmel_spi *as = spi_master_get_devdata(master);
 657         u32 current_remaining_data, num_data;
 658         u32 offset = xfer->len - as->current_remaining_bytes;
 659         const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
 660         const u8  *bytes = (const u8  *)((u8 *)xfer->tx_buf + offset);
 661         u16 td0, td1;
 662         u32 fifomr;
 663
 664         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
 665
 666         /* Compute the number of data to transfer in the current iteration */
 667         current_remaining_data = ((xfer->bits_per_word > 8) ?
 668                                   ((u32)as->current_remaining_bytes >> 1) :
 669                                   (u32)as->current_remaining_bytes);
 670         num_data = min(current_remaining_data, as->fifo_size);
 671
 672         /* Flush RX and TX FIFOs */
 673         spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
 674         while (spi_readl(as, FLR))
 675                 cpu_relax();
 676
 677         /* Set RX FIFO Threshold to the number of data to transfer */
 678         fifomr = spi_readl(as, FMR);
 679         spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
 680
 681         /* Clear FIFO flags in the Status Register, especially RXFTHF */
 682         (void)spi_readl(as, SR);
 683
 684         /* Fill TX FIFO */
 685         while (num_data >= 2) {
 686                 if (xfer->bits_per_word > 8) {
 687                         td0 = *words++;
 688                         td1 = *words++;
 689                 } else {
 690                         td0 = *bytes++;
 691                         td1 = *bytes++;
 692                 }
 693
 694                 spi_writel(as, TDR, (td1 << 16) | td0);
 695                 num_data -= 2;
 696         }
 697
 698         if (num_data) {
 699                 if (xfer->bits_per_word > 8)
 700                         td0 = *words++;
 701                 else
 702                         td0 = *bytes++;
 703
 704                 spi_writew(as, TDR, td0);
 705                 num_data--;
 706         }
 707
 708         dev_dbg(master->dev.parent,
 709                 "  start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
 710                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 711                 xfer->bits_per_word);
 712
 713         /*
 714          * Enable RX FIFO Threshold Flag interrupt to be notified about
 715          * transfer completion.
 716          */
 717         spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
 718 }
 719
 720 /*
 721  * Next transfer using PIO.
 722  */
 723 static void atmel_spi_next_xfer_pio(struct spi_master *master,
 724                                     struct spi_transfer *xfer)
 725 {
 726         struct atmel_spi *as = spi_master_get_devdata(master);
 727
 728         if (as->fifo_size)
 729                 atmel_spi_next_xfer_fifo(master, xfer);
 730         else
 731                 atmel_spi_next_xfer_single(master, xfer);
 732 }
 733
 734 /*
 735  * Submit next transfer for DMA.
 736  */
 737 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
 738                                 struct spi_transfer *xfer,
 739                                 u32 *plen)
 740 {
 741         struct atmel_spi        *as = spi_master_get_devdata(master);
 742         struct dma_chan         *rxchan = master->dma_rx;
 743         struct dma_chan         *txchan = master->dma_tx;
 744         struct dma_async_tx_descriptor *rxdesc;
 745         struct dma_async_tx_descriptor *txdesc;
 746         struct dma_slave_config slave_config;
 747         dma_cookie_t            cookie;
 748
 749         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
 750
 751         /* Check that the channels are available */
 752         if (!rxchan || !txchan)
 753                 return -ENODEV;
 754
 755         /* release lock for DMA operations */
 756         atmel_spi_unlock(as);
 757
 758         *plen = xfer->len;
 759
 760         if (atmel_spi_dma_slave_config(as, &slave_config,
 761                                        xfer->bits_per_word))
 762                 goto err_exit;
 763
 764         /* Send both scatterlists */
 765         if (atmel_spi_is_vmalloc_xfer(xfer) &&
 766             IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
 767                 rxdesc = dmaengine_prep_slave_single(rxchan,
 768                                                      as->dma_addr_rx_bbuf,
 769                                                      xfer->len,
 770                                                      DMA_DEV_TO_MEM,
 771                                                      DMA_PREP_INTERRUPT |
 772                                                      DMA_CTRL_ACK);
 773         } else {
 774                 rxdesc = dmaengine_prep_slave_sg(rxchan,
 775                                                  xfer->rx_sg.sgl,
 776                                                  xfer->rx_sg.nents,
 777                                                  DMA_DEV_TO_MEM,
 778                                                  DMA_PREP_INTERRUPT |
 779                                                  DMA_CTRL_ACK);
 780         }
 781         if (!rxdesc)
 782                 goto err_dma;
 783
 784         if (atmel_spi_is_vmalloc_xfer(xfer) &&
 785             IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
 786                 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len);
 787                 txdesc = dmaengine_prep_slave_single(txchan,
 788                                                      as->dma_addr_tx_bbuf,
 789                                                      xfer->len, DMA_MEM_TO_DEV,
 790                                                      DMA_PREP_INTERRUPT |
 791                                                      DMA_CTRL_ACK);
 792         } else {
 793                 txdesc = dmaengine_prep_slave_sg(txchan,
 794                                                  xfer->tx_sg.sgl,
 795                                                  xfer->tx_sg.nents,
 796                                                  DMA_MEM_TO_DEV,
 797                                                  DMA_PREP_INTERRUPT |
 798                                                  DMA_CTRL_ACK);
 799         }
 800         if (!txdesc)
 801                 goto err_dma;
 802
 803         dev_dbg(master->dev.parent,
 804                 "  start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 805                 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
 806                 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
 807
 808         /* Enable relevant interrupts */
 809         spi_writel(as, IER, SPI_BIT(OVRES));
 810
 811         /* Put the callback on the RX transfer only, that should finish last */
 812         rxdesc->callback = dma_callback;
 813         rxdesc->callback_param = master;
 814
 815         /* Submit and fire RX and TX with TX last so we're ready to read! */
 816         cookie = rxdesc->tx_submit(rxdesc);
 817         if (dma_submit_error(cookie))
 818                 goto err_dma;
 819         cookie = txdesc->tx_submit(txdesc);
 820         if (dma_submit_error(cookie))
 821                 goto err_dma;
 822         rxchan->device->device_issue_pending(rxchan);
 823         txchan->device->device_issue_pending(txchan);
 824
 825         /* take back lock */
 826         atmel_spi_lock(as);
 827         return 0;
 828
 829 err_dma:
 830         spi_writel(as, IDR, SPI_BIT(OVRES));
 831         atmel_spi_stop_dma(master);
 832 err_exit:
 833         atmel_spi_lock(as);
 834         return -ENOMEM;
 835 }
 836
 837 static void atmel_spi_next_xfer_data(struct spi_master *master,
 838                                 struct spi_transfer *xfer,
 839                                 dma_addr_t *tx_dma,
 840                                 dma_addr_t *rx_dma,
 841                                 u32 *plen)
 842 {
 843         *rx_dma = xfer->rx_dma + xfer->len - *plen;
 844         *tx_dma = xfer->tx_dma + xfer->len - *plen;
 845         if (*plen > master->max_dma_len)
 846                 *plen = master->max_dma_len;
 847 }
 848
 849 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
 850                                     struct spi_device *spi,
 851                                     struct spi_transfer *xfer)
 852 {
 853         u32                     scbr, csr;
 854         unsigned long           bus_hz;
 855
 856         /* v1 chips start out at half the peripheral bus speed. */
 857         bus_hz = as->spi_clk;
 858         if (!atmel_spi_is_v2(as))
 859                 bus_hz /= 2;
 860
 861         /*
 862          * Calculate the lowest divider that satisfies the
 863          * constraint, assuming div32/fdiv/mbz == 0.
 864          */
 865         scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
 866
 867         /*
 868          * If the resulting divider doesn't fit into the
 869          * register bitfield, we can't satisfy the constraint.
 870          */
 871         if (scbr >= (1 << SPI_SCBR_SIZE)) {
 872                 dev_err(&spi->dev,
 873                         "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
 874                         xfer->speed_hz, scbr, bus_hz/255);
 875                 return -EINVAL;
 876         }
 877         if (scbr == 0) {
 878                 dev_err(&spi->dev,
 879                         "setup: %d Hz too high, scbr %u; max %ld Hz\n",
 880                         xfer->speed_hz, scbr, bus_hz);
 881                 return -EINVAL;
 882         }
 883         csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
 884         csr = SPI_BFINS(SCBR, scbr, csr);
 885         spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
 886
 887         return 0;
 888 }
 889
 890 /*
 891  * Submit next transfer for PDC.
 892  * lock is held, spi irq is blocked
 893  */
 894 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
 895                                         struct spi_message *msg,
 896                                         struct spi_transfer *xfer)
 897 {
 898         struct atmel_spi        *as = spi_master_get_devdata(master);
 899         u32                     len;
 900         dma_addr_t              tx_dma, rx_dma;
 901
 902         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 903
 904         len = as->current_remaining_bytes;
 905         atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 906         as->current_remaining_bytes -= len;
 907
 908         spi_writel(as, RPR, rx_dma);
 909         spi_writel(as, TPR, tx_dma);
 910
 911         if (msg->spi->bits_per_word > 8)
 912                 len >>= 1;
 913         spi_writel(as, RCR, len);
 914         spi_writel(as, TCR, len);
 915
 916         dev_dbg(&msg->spi->dev,
 917                 "  start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 918                 xfer, xfer->len, xfer->tx_buf,
 919                 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 920                 (unsigned long long)xfer->rx_dma);
 921
 922         if (as->current_remaining_bytes) {
 923                 len = as->current_remaining_bytes;
 924                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 925                 as->current_remaining_bytes -= len;
 926
 927                 spi_writel(as, RNPR, rx_dma);
 928                 spi_writel(as, TNPR, tx_dma);
 929
 930                 if (msg->spi->bits_per_word > 8)
 931                         len >>= 1;
 932                 spi_writel(as, RNCR, len);
 933                 spi_writel(as, TNCR, len);
 934
 935                 dev_dbg(&msg->spi->dev,
 936                         "  next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 937                         xfer, xfer->len, xfer->tx_buf,
 938                         (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 939                         (unsigned long long)xfer->rx_dma);
 940         }
 941
 942         /* REVISIT: We're waiting for RXBUFF before we start the next
 943          * transfer because we need to handle some difficult timing
 944          * issues otherwise. If we wait for TXBUFE in one transfer and
 945          * then starts waiting for RXBUFF in the next, it's difficult
 946          * to tell the difference between the RXBUFF interrupt we're
 947          * actually waiting for and the RXBUFF interrupt of the
 948          * previous transfer.
 949          *
 950          * It should be doable, though. Just not now...
 951          */
 952         spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
 953         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 954 }
 955
 956 /*
 957  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 958  *  - The buffer is either valid for CPU access, else NULL
 959  *  - If the buffer is valid, so is its DMA address
 960  *
 961  * This driver manages the dma address unless message->is_dma_mapped.
 962  */
 963 static int
 964 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 965 {
 966         struct device   *dev = &as->pdev->dev;
 967
 968         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 969         if (xfer->tx_buf) {
 970                 /* tx_buf is a const void* where we need a void * for the dma
 971                  * mapping */
 972                 void *nonconst_tx = (void *)xfer->tx_buf;
 973
 974                 xfer->tx_dma = dma_map_single(dev,
 975                                 nonconst_tx, xfer->len,
 976                                 DMA_TO_DEVICE);
 977                 if (dma_mapping_error(dev, xfer->tx_dma))
 978                         return -ENOMEM;
 979         }
 980         if (xfer->rx_buf) {
 981                 xfer->rx_dma = dma_map_single(dev,
 982                                 xfer->rx_buf, xfer->len,
 983                                 DMA_FROM_DEVICE);
 984                 if (dma_mapping_error(dev, xfer->rx_dma)) {
 985                         if (xfer->tx_buf)
 986                                 dma_unmap_single(dev,
 987                                                 xfer->tx_dma, xfer->len,
 988                                                 DMA_TO_DEVICE);
 989                         return -ENOMEM;
 990                 }
 991         }
 992         return 0;
 993 }
 994
 995 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 996                                      struct spi_transfer *xfer)
 997 {
 998         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
 999                 dma_unmap_single(master->dev.parent, xfer->tx_dma,
1000                                  xfer->len, DMA_TO_DEVICE);
1001         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
1002                 dma_unmap_single(master->dev.parent, xfer->rx_dma,
1003                                  xfer->len, DMA_FROM_DEVICE);
1004 }
1005
1006 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
1007 {
1008         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1009 }
1010
1011 static void
1012 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
1013 {
1014         u8              *rxp;
1015         u16             *rxp16;
1016         unsigned long   xfer_pos = xfer->len - as->current_remaining_bytes;
1017
1018         if (xfer->bits_per_word > 8) {
1019                 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
1020                 *rxp16 = spi_readl(as, RDR);
1021         } else {
1022                 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
1023                 *rxp = spi_readl(as, RDR);
1024         }
1025         if (xfer->bits_per_word > 8) {
1026                 if (as->current_remaining_bytes > 2)
1027                         as->current_remaining_bytes -= 2;
1028                 else
1029                         as->current_remaining_bytes = 0;
1030         } else {
1031                 as->current_remaining_bytes--;
1032         }
1033 }
1034
1035 static void
1036 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
1037 {
1038         u32 fifolr = spi_readl(as, FLR);
1039         u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
1040         u32 offset = xfer->len - as->current_remaining_bytes;
1041         u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
1042         u8  *bytes = (u8  *)((u8 *)xfer->rx_buf + offset);
1043         u16 rd; /* RD field is the lowest 16 bits of RDR */
1044
1045         /* Update the number of remaining bytes to transfer */
1046         num_bytes = ((xfer->bits_per_word > 8) ?
1047                      (num_data << 1) :
1048                      num_data);
1049
1050         if (as->current_remaining_bytes > num_bytes)
1051                 as->current_remaining_bytes -= num_bytes;
1052         else
1053                 as->current_remaining_bytes = 0;
1054
1055         /* Handle odd number of bytes when data are more than 8bit width */
1056         if (xfer->bits_per_word > 8)
1057                 as->current_remaining_bytes &= ~0x1;
1058
1059         /* Read data */
1060         while (num_data) {
1061                 rd = spi_readl(as, RDR);
1062                 if (xfer->bits_per_word > 8)
1063                         *words++ = rd;
1064                 else
1065                         *bytes++ = rd;
1066                 num_data--;
1067         }
1068 }
1069
1070 /* Called from IRQ
1071  *
1072  * Must update "current_remaining_bytes" to keep track of data
1073  * to transfer.
1074  */
1075 static void
1076 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1077 {
1078         if (as->fifo_size)
1079                 atmel_spi_pump_fifo_data(as, xfer);
1080         else
1081                 atmel_spi_pump_single_data(as, xfer);
1082 }
1083
1084 /* Interrupt
1085  *
1086  * No need for locking in this Interrupt handler: done_status is the
1087  * only information modified.
1088  */
1089 static irqreturn_t
1090 atmel_spi_pio_interrupt(int irq, void *dev_id)
1091 {
1092         struct spi_master       *master = dev_id;
1093         struct atmel_spi        *as = spi_master_get_devdata(master);
1094         u32                     status, pending, imr;
1095         struct spi_transfer     *xfer;
1096         int                     ret = IRQ_NONE;
1097
1098         imr = spi_readl(as, IMR);
1099         status = spi_readl(as, SR);
1100         pending = status & imr;
1101
1102         if (pending & SPI_BIT(OVRES)) {
1103                 ret = IRQ_HANDLED;
1104                 spi_writel(as, IDR, SPI_BIT(OVRES));
1105                 dev_warn(master->dev.parent, "overrun\n");
1106
1107                 /*
1108                  * When we get an overrun, we disregard the current
1109                  * transfer. Data will not be copied back from any
1110                  * bounce buffer and msg->actual_len will not be
1111                  * updated with the last xfer.
1112                  *
1113                  * We will also not process any remaning transfers in
1114                  * the message.
1115                  */
1116                 as->done_status = -EIO;
1117                 smp_wmb();
1118
1119                 /* Clear any overrun happening while cleaning up */
1120                 spi_readl(as, SR);
1121
1122                 complete(&as->xfer_completion);
1123
1124         } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1125                 atmel_spi_lock(as);
1126
1127                 if (as->current_remaining_bytes) {
1128                         ret = IRQ_HANDLED;
1129                         xfer = as->current_transfer;
1130                         atmel_spi_pump_pio_data(as, xfer);
1131                         if (!as->current_remaining_bytes)
1132                                 spi_writel(as, IDR, pending);
1133
1134                         complete(&as->xfer_completion);
1135                 }
1136
1137                 atmel_spi_unlock(as);
1138         } else {
1139                 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1140                 ret = IRQ_HANDLED;
1141                 spi_writel(as, IDR, pending);
1142         }
1143
1144         return ret;
1145 }
1146
1147 static irqreturn_t
1148 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1149 {
1150         struct spi_master       *master = dev_id;
1151         struct atmel_spi        *as = spi_master_get_devdata(master);
1152         u32                     status, pending, imr;
1153         int                     ret = IRQ_NONE;
1154
1155         imr = spi_readl(as, IMR);
1156         status = spi_readl(as, SR);
1157         pending = status & imr;
1158
1159         if (pending & SPI_BIT(OVRES)) {
1160
1161                 ret = IRQ_HANDLED;
1162
1163                 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1164                                      | SPI_BIT(OVRES)));
1165
1166                 /* Clear any overrun happening while cleaning up */
1167                 spi_readl(as, SR);
1168
1169                 as->done_status = -EIO;
1170
1171                 complete(&as->xfer_completion);
1172
1173         } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1174                 ret = IRQ_HANDLED;
1175
1176                 spi_writel(as, IDR, pending);
1177
1178                 complete(&as->xfer_completion);
1179         }
1180
1181         return ret;
1182 }
1183
1184 static int atmel_spi_setup(struct spi_device *spi)
1185 {
1186         struct atmel_spi        *as;
1187         struct atmel_spi_device *asd;
1188         u32                     csr;
1189         unsigned int            bits = spi->bits_per_word;
1190         unsigned int            npcs_pin;
1191
1192         as = spi_master_get_devdata(spi->master);
1193
1194         /* see notes above re chipselect */
1195         if (!as->use_cs_gpios && (spi->mode & SPI_CS_HIGH)) {
1196                 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
1197                 return -EINVAL;
1198         }
1199
1200         csr = SPI_BF(BITS, bits - 8);
1201         if (spi->mode & SPI_CPOL)
1202                 csr |= SPI_BIT(CPOL);
1203         if (!(spi->mode & SPI_CPHA))
1204                 csr |= SPI_BIT(NCPHA);
1205         if (!as->use_cs_gpios)
1206                 csr |= SPI_BIT(CSAAT);
1207
1208         /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1209          *
1210          * DLYBCT would add delays between words, slowing down transfers.
1211          * It could potentially be useful to cope with DMA bottlenecks, but
1212          * in those cases it's probably best to just use a lower bitrate.
1213          */
1214         csr |= SPI_BF(DLYBS, 0);
1215         csr |= SPI_BF(DLYBCT, 0);
1216
1217         /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1218         npcs_pin = (unsigned long)spi->controller_data;
1219
1220         if (!as->use_cs_gpios)
1221                 npcs_pin = spi->chip_select;
1222         else if (gpio_is_valid(spi->cs_gpio))
1223                 npcs_pin = spi->cs_gpio;
1224
1225         asd = spi->controller_state;
1226         if (!asd) {
1227                 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1228                 if (!asd)
1229                         return -ENOMEM;
1230
1231                 if (as->use_cs_gpios)
1232                         gpio_direction_output(npcs_pin,
1233                                               !(spi->mode & SPI_CS_HIGH));
1234
1235                 asd->npcs_pin = npcs_pin;
1236                 spi->controller_state = asd;
1237         }
1238
1239         asd->csr = csr;
1240
1241         dev_dbg(&spi->dev,
1242                 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1243                 bits, spi->mode, spi->chip_select, csr);
1244
1245         if (!atmel_spi_is_v2(as))
1246                 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1247
1248         return 0;
1249 }
1250
1251 static int atmel_spi_one_transfer(struct spi_master *master,
1252                                         struct spi_message *msg,
1253                                         struct spi_transfer *xfer)
1254 {
1255         struct atmel_spi        *as;
1256         struct spi_device       *spi = msg->spi;
1257         u8                      bits;
1258         u32                     len;
1259         struct atmel_spi_device *asd;
1260         int                     timeout;
1261         int                     ret;
1262         unsigned long           dma_timeout;
1263
1264         as = spi_master_get_devdata(master);
1265
1266         if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1267                 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1268                 return -EINVAL;
1269         }
1270
1271         asd = spi->controller_state;
1272         bits = (asd->csr >> 4) & 0xf;
1273         if (bits != xfer->bits_per_word - 8) {
1274                 dev_dbg(&spi->dev,
1275                         "you can't yet change bits_per_word in transfers\n");
1276                 return -ENOPROTOOPT;
1277         }
1278
1279         /*
1280          * DMA map early, for performance (empties dcache ASAP) and
1281          * better fault reporting.
1282          */
1283         if ((!msg->is_dma_mapped)
1284                 && as->use_pdc) {
1285                 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1286                         return -ENOMEM;
1287         }
1288
1289         atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1290
1291         as->done_status = 0;
1292         as->current_transfer = xfer;
1293         as->current_remaining_bytes = xfer->len;
1294         while (as->current_remaining_bytes) {
1295                 reinit_completion(&as->xfer_completion);
1296
1297                 if (as->use_pdc) {
1298                         atmel_spi_pdc_next_xfer(master, msg, xfer);
1299                 } else if (atmel_spi_use_dma(as, xfer)) {
1300                         len = as->current_remaining_bytes;
1301                         ret = atmel_spi_next_xfer_dma_submit(master,
1302                                                                 xfer, &len);
1303                         if (ret) {
1304                                 dev_err(&spi->dev,
1305                                         "unable to use DMA, fallback to PIO\n");
1306                                 atmel_spi_next_xfer_pio(master, xfer);
1307                         } else {
1308                                 as->current_remaining_bytes -= len;
1309                                 if (as->current_remaining_bytes < 0)
1310                                         as->current_remaining_bytes = 0;
1311                         }
1312                 } else {
1313                         atmel_spi_next_xfer_pio(master, xfer);
1314                 }
1315
1316                 /* interrupts are disabled, so free the lock for schedule */
1317                 atmel_spi_unlock(as);
1318                 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1319                                                           SPI_DMA_TIMEOUT);
1320                 atmel_spi_lock(as);
1321                 if (WARN_ON(dma_timeout == 0)) {
1322                         dev_err(&spi->dev, "spi transfer timeout\n");
1323                         as->done_status = -EIO;
1324                 }
1325
1326                 if (as->done_status)
1327                         break;
1328         }
1329
1330         if (as->done_status) {
1331                 if (as->use_pdc) {
1332                         dev_warn(master->dev.parent,
1333                                 "overrun (%u/%u remaining)\n",
1334                                 spi_readl(as, TCR), spi_readl(as, RCR));
1335
1336                         /*
1337                          * Clean up DMA registers and make sure the data
1338                          * registers are empty.
1339                          */
1340                         spi_writel(as, RNCR, 0);
1341                         spi_writel(as, TNCR, 0);
1342                         spi_writel(as, RCR, 0);
1343                         spi_writel(as, TCR, 0);
1344                         for (timeout = 1000; timeout; timeout--)
1345                                 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1346                                         break;
1347                         if (!timeout)
1348                                 dev_warn(master->dev.parent,
1349                                          "timeout waiting for TXEMPTY");
1350                         while (spi_readl(as, SR) & SPI_BIT(RDRF))
1351                                 spi_readl(as, RDR);
1352
1353                         /* Clear any overrun happening while cleaning up */
1354                         spi_readl(as, SR);
1355
1356                 } else if (atmel_spi_use_dma(as, xfer)) {
1357                         atmel_spi_stop_dma(master);
1358                 }
1359
1360                 if (!msg->is_dma_mapped
1361                         && as->use_pdc)
1362                         atmel_spi_dma_unmap_xfer(master, xfer);
1363
1364                 return 0;
1365
1366         } else {
1367                 /* only update length if no error */
1368                 msg->actual_length += xfer->len;
1369         }
1370
1371         if (!msg->is_dma_mapped
1372                 && as->use_pdc)
1373                 atmel_spi_dma_unmap_xfer(master, xfer);
1374
1375         if (xfer->delay_usecs)
1376                 udelay(xfer->delay_usecs);
1377
1378         if (xfer->cs_change) {
1379                 if (list_is_last(&xfer->transfer_list,
1380                                  &msg->transfers)) {
1381                         as->keep_cs = true;
1382                 } else {
1383                         cs_deactivate(as, msg->spi);
1384                         udelay(10);
1385                         cs_activate(as, msg->spi);
1386                 }
1387         }
1388
1389         return 0;
1390 }
1391
1392 static int atmel_spi_transfer_one_message(struct spi_master *master,
1393                                                 struct spi_message *msg)
1394 {
1395         struct atmel_spi *as;
1396         struct spi_transfer *xfer;
1397         struct spi_device *spi = msg->spi;
1398         int ret = 0;
1399
1400         as = spi_master_get_devdata(master);
1401
1402         dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1403                                         msg, dev_name(&spi->dev));
1404
1405         atmel_spi_lock(as);
1406         cs_activate(as, spi);
1407
1408         as->keep_cs = false;
1409
1410         msg->status = 0;
1411         msg->actual_length = 0;
1412
1413         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1414                 ret = atmel_spi_one_transfer(master, msg, xfer);
1415                 if (ret)
1416                         goto msg_done;
1417         }
1418
1419         if (as->use_pdc)
1420                 atmel_spi_disable_pdc_transfer(as);
1421
1422         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1423                 dev_dbg(&spi->dev,
1424                         "  xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1425                         xfer, xfer->len,
1426                         xfer->tx_buf, &xfer->tx_dma,
1427                         xfer->rx_buf, &xfer->rx_dma);
1428         }
1429
1430 msg_done:
1431         if (!as->keep_cs)
1432                 cs_deactivate(as, msg->spi);
1433
1434         atmel_spi_unlock(as);
1435
1436         msg->status = as->done_status;
1437         spi_finalize_current_message(spi->master);
1438
1439         return ret;
1440 }
1441
1442 static void atmel_spi_cleanup(struct spi_device *spi)
1443 {
1444         struct atmel_spi_device *asd = spi->controller_state;
1445
1446         if (!asd)
1447                 return;
1448
1449         spi->controller_state = NULL;
1450         kfree(asd);
1451 }
1452
1453 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1454 {
1455         return spi_readl(as, VERSION) & 0x00000fff;
1456 }
1457
1458 static void atmel_get_caps(struct atmel_spi *as)
1459 {
1460         unsigned int version;
1461
1462         version = atmel_get_version(as);
1463
1464         as->caps.is_spi2 = version > 0x121;
1465         as->caps.has_wdrbt = version >= 0x210;
1466         as->caps.has_dma_support = version >= 0x212;
1467         as->caps.has_pdc_support = version < 0x212;
1468 }
1469
1470 /*-------------------------------------------------------------------------*/
1471 static int atmel_spi_gpio_cs(struct platform_device *pdev)
1472 {
1473         struct spi_master       *master = platform_get_drvdata(pdev);
1474         struct atmel_spi        *as = spi_master_get_devdata(master);
1475         struct device_node      *np = master->dev.of_node;
1476         int                     i;
1477         int                     ret = 0;
1478         int                     nb = 0;
1479
1480         if (!as->use_cs_gpios)
1481                 return 0;
1482
1483         if (!np)
1484                 return 0;
1485
1486         nb = of_gpio_named_count(np, "cs-gpios");
1487         for (i = 0; i < nb; i++) {
1488                 int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
1489                                                 "cs-gpios", i);
1490
1491                 if (cs_gpio == -EPROBE_DEFER)
1492                         return cs_gpio;
1493
1494                 if (gpio_is_valid(cs_gpio)) {
1495                         ret = devm_gpio_request(&pdev->dev, cs_gpio,
1496                                                 dev_name(&pdev->dev));
1497                         if (ret)
1498                                 return ret;
1499                 }
1500         }
1501
1502         return 0;
1503 }
1504
1505 static void atmel_spi_init(struct atmel_spi *as)
1506 {
1507         spi_writel(as, CR, SPI_BIT(SWRST));
1508         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1509
1510         /* It is recommended to enable FIFOs first thing after reset */
1511         if (as->fifo_size)
1512                 spi_writel(as, CR, SPI_BIT(FIFOEN));
1513
1514         if (as->caps.has_wdrbt) {
1515                 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1516                                 | SPI_BIT(MSTR));
1517         } else {
1518                 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1519         }
1520
1521         if (as->use_pdc)
1522                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1523         spi_writel(as, CR, SPI_BIT(SPIEN));
1524 }
1525
1526 static int atmel_spi_probe(struct platform_device *pdev)
1527 {
1528         struct resource         *regs;
1529         int                     irq;
1530         struct clk              *clk;
1531         int                     ret;
1532         struct spi_master       *master;
1533         struct atmel_spi        *as;
1534
1535         /* Select default pin state */
1536         pinctrl_pm_select_default_state(&pdev->dev);
1537
1538         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1539         if (!regs)
1540                 return -ENXIO;
1541
1542         irq = platform_get_irq(pdev, 0);
1543         if (irq < 0)
1544                 return irq;
1545
1546         clk = devm_clk_get(&pdev->dev, "spi_clk");
1547         if (IS_ERR(clk))
1548                 return PTR_ERR(clk);
1549
1550         /* setup spi core then atmel-specific driver state */
1551         ret = -ENOMEM;
1552         master = spi_alloc_master(&pdev->dev, sizeof(*as));
1553         if (!master)
1554                 goto out_free;
1555
1556         /* the spi->mode bits understood by this driver: */
1557         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1558         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1559         master->dev.of_node = pdev->dev.of_node;
1560         master->bus_num = pdev->id;
1561         master->num_chipselect = master->dev.of_node ? 0 : 4;
1562         master->setup = atmel_spi_setup;
1563         master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
1564         master->transfer_one_message = atmel_spi_transfer_one_message;
1565         master->cleanup = atmel_spi_cleanup;
1566         master->auto_runtime_pm = true;
1567         master->max_dma_len = SPI_MAX_DMA_XFER;
1568         master->can_dma = atmel_spi_can_dma;
1569         platform_set_drvdata(pdev, master);
1570
1571         as = spi_master_get_devdata(master);
1572
1573         spin_lock_init(&as->lock);
1574
1575         as->pdev = pdev;
1576         as->regs = devm_ioremap_resource(&pdev->dev, regs);
1577         if (IS_ERR(as->regs)) {
1578                 ret = PTR_ERR(as->regs);
1579                 goto out_unmap_regs;
1580         }
1581         as->phybase = regs->start;
1582         as->irq = irq;
1583         as->clk = clk;
1584
1585         init_completion(&as->xfer_completion);
1586
1587         atmel_get_caps(as);
1588
1589         as->use_cs_gpios = true;
1590         if (atmel_spi_is_v2(as) &&
1591             pdev->dev.of_node &&
1592             !of_get_property(pdev->dev.of_node, "cs-gpios", NULL)) {
1593                 as->use_cs_gpios = false;
1594                 master->num_chipselect = 4;
1595         }
1596
1597         ret = atmel_spi_gpio_cs(pdev);
1598         if (ret)
1599                 goto out_unmap_regs;
1600
1601         as->use_dma = false;
1602         as->use_pdc = false;
1603         if (as->caps.has_dma_support) {
1604                 ret = atmel_spi_configure_dma(master, as);
1605                 if (ret == 0) {
1606                         as->use_dma = true;
1607                 } else if (ret == -EPROBE_DEFER) {
1608                         goto out_unmap_regs;
1609                 }
1610         } else if (as->caps.has_pdc_support) {
1611                 as->use_pdc = true;
1612         }
1613
1614         if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1615                 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev,
1616                                                       SPI_MAX_DMA_XFER,
1617                                                       &as->dma_addr_rx_bbuf,
1618                                                       GFP_KERNEL | GFP_DMA);
1619                 if (!as->addr_rx_bbuf) {
1620                         as->use_dma = false;
1621                 } else {
1622                         as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev,
1623                                         SPI_MAX_DMA_XFER,
1624                                         &as->dma_addr_tx_bbuf,
1625                                         GFP_KERNEL | GFP_DMA);
1626                         if (!as->addr_tx_bbuf) {
1627                                 as->use_dma = false;
1628                                 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1629                                                   as->addr_rx_bbuf,
1630                                                   as->dma_addr_rx_bbuf);
1631                         }
1632                 }
1633                 if (!as->use_dma)
1634                         dev_info(master->dev.parent,
1635                                  "  can not allocate dma coherent memory\n");
1636         }
1637
1638         if (as->caps.has_dma_support && !as->use_dma)
1639                 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1640
1641         if (as->use_pdc) {
1642                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1643                                         0, dev_name(&pdev->dev), master);
1644         } else {
1645                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1646                                         0, dev_name(&pdev->dev), master);
1647         }
1648         if (ret)
1649                 goto out_unmap_regs;
1650
1651         /* Initialize the hardware */
1652         ret = clk_prepare_enable(clk);
1653         if (ret)
1654                 goto out_free_irq;
1655
1656         as->spi_clk = clk_get_rate(clk);
1657
1658         as->fifo_size = 0;
1659         if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1660                                   &as->fifo_size)) {
1661                 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1662         }
1663
1664         atmel_spi_init(as);
1665
1666         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1667         pm_runtime_use_autosuspend(&pdev->dev);
1668         pm_runtime_set_active(&pdev->dev);
1669         pm_runtime_enable(&pdev->dev);
1670
1671         ret = devm_spi_register_master(&pdev->dev, master);
1672         if (ret)
1673                 goto out_free_dma;
1674
1675         /* go! */
1676         dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
1677                         atmel_get_version(as), (unsigned long)regs->start,
1678                         irq);
1679
1680         return 0;
1681
1682 out_free_dma:
1683         pm_runtime_disable(&pdev->dev);
1684         pm_runtime_set_suspended(&pdev->dev);
1685
1686         if (as->use_dma)
1687                 atmel_spi_release_dma(master);
1688
1689         spi_writel(as, CR, SPI_BIT(SWRST));
1690         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1691         clk_disable_unprepare(clk);
1692 out_free_irq:
1693 out_unmap_regs:
1694 out_free:
1695         spi_master_put(master);
1696         return ret;
1697 }
1698
1699 static int atmel_spi_remove(struct platform_device *pdev)
1700 {
1701         struct spi_master       *master = platform_get_drvdata(pdev);
1702         struct atmel_spi        *as = spi_master_get_devdata(master);
1703
1704         pm_runtime_get_sync(&pdev->dev);
1705
1706         /* reset the hardware and block queue progress */
1707         if (as->use_dma) {
1708                 atmel_spi_stop_dma(master);
1709                 atmel_spi_release_dma(master);
1710                 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1711                         dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1712                                           as->addr_tx_bbuf,
1713                                           as->dma_addr_tx_bbuf);
1714                         dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1715                                           as->addr_rx_bbuf,
1716                                           as->dma_addr_rx_bbuf);
1717                 }
1718         }
1719
1720         spin_lock_irq(&as->lock);
1721         spi_writel(as, CR, SPI_BIT(SWRST));
1722         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1723         spi_readl(as, SR);
1724         spin_unlock_irq(&as->lock);
1725
1726         clk_disable_unprepare(as->clk);
1727
1728         pm_runtime_put_noidle(&pdev->dev);
1729         pm_runtime_disable(&pdev->dev);
1730
1731         return 0;
1732 }
1733
1734 #ifdef CONFIG_PM
1735 static int atmel_spi_runtime_suspend(struct device *dev)
1736 {
1737         struct spi_master *master = dev_get_drvdata(dev);
1738         struct atmel_spi *as = spi_master_get_devdata(master);
1739
1740         clk_disable_unprepare(as->clk);
1741         pinctrl_pm_select_sleep_state(dev);
1742
1743         return 0;
1744 }
1745
1746 static int atmel_spi_runtime_resume(struct device *dev)
1747 {
1748         struct spi_master *master = dev_get_drvdata(dev);
1749         struct atmel_spi *as = spi_master_get_devdata(master);
1750
1751         pinctrl_pm_select_default_state(dev);
1752
1753         return clk_prepare_enable(as->clk);
1754 }
1755
1756 #ifdef CONFIG_PM_SLEEP
1757 static int atmel_spi_suspend(struct device *dev)
1758 {
1759         struct spi_master *master = dev_get_drvdata(dev);
1760         int ret;
1761
1762         /* Stop the queue running */
1763         ret = spi_master_suspend(master);
1764         if (ret) {
1765                 dev_warn(dev, "cannot suspend master\n");
1766                 return ret;
1767         }
1768
1769         if (!pm_runtime_suspended(dev))
1770                 atmel_spi_runtime_suspend(dev);
1771
1772         return 0;
1773 }
1774
1775 static int atmel_spi_resume(struct device *dev)
1776 {
1777         struct spi_master *master = dev_get_drvdata(dev);
1778         struct atmel_spi *as = spi_master_get_devdata(master);
1779         int ret;
1780
1781         ret = clk_prepare_enable(as->clk);
1782         if (ret)
1783                 return ret;
1784
1785         atmel_spi_init(as);
1786
1787         clk_disable_unprepare(as->clk);
1788
1789         if (!pm_runtime_suspended(dev)) {
1790                 ret = atmel_spi_runtime_resume(dev);
1791                 if (ret)
1792                         return ret;
1793         }
1794
1795         /* Start the queue running */
1796         ret = spi_master_resume(master);
1797         if (ret)
1798                 dev_err(dev, "problem starting queue (%d)\n", ret);
1799
1800         return ret;
1801 }
1802 #endif
1803
1804 static const struct dev_pm_ops atmel_spi_pm_ops = {
1805         SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1806         SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1807                            atmel_spi_runtime_resume, NULL)
1808 };
1809 #define ATMEL_SPI_PM_OPS        (&atmel_spi_pm_ops)
1810 #else
1811 #define ATMEL_SPI_PM_OPS        NULL
1812 #endif
1813
1814 #if defined(CONFIG_OF)
1815 static const struct of_device_id atmel_spi_dt_ids[] = {
1816         { .compatible = "atmel,at91rm9200-spi" },
1817         { /* sentinel */ }
1818 };
1819
1820 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1821 #endif
1822
1823 static struct platform_driver atmel_spi_driver = {
1824         .driver         = {
1825                 .name   = "atmel_spi",
1826                 .pm     = ATMEL_SPI_PM_OPS,
1827                 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1828         },
1829         .probe          = atmel_spi_probe,
1830         .remove         = atmel_spi_remove,
1831 };
1832 module_platform_driver(atmel_spi_driver);
1833
1834 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1835 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1836 MODULE_LICENSE("GPL");
1837 MODULE_ALIAS("platform:atmel_spi");