drivers/spi/spi-cadence.c

   1 /*
   2  * Cadence SPI controller driver (master mode only)
   3  *
   4  * Copyright (C) 2008 - 2014 Xilinx, Inc.
   5  *
   6  * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
   7  *
   8  * This program is free software; you can redistribute it and/or modify it under
   9  * the terms of the GNU General Public License version 2 as published by the
  10  * Free Software Foundation; either version 2 of the License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_address.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/spi/spi.h>
  25
  26 /* Name of this driver */
  27 #define CDNS_SPI_NAME           "cdns-spi"
  28
  29 /* Register offset definitions */
  30 #define CDNS_SPI_CR     0x00 /* Configuration  Register, RW */
  31 #define CDNS_SPI_ISR    0x04 /* Interrupt Status Register, RO */
  32 #define CDNS_SPI_IER    0x08 /* Interrupt Enable Register, WO */
  33 #define CDNS_SPI_IDR    0x0c /* Interrupt Disable Register, WO */
  34 #define CDNS_SPI_IMR    0x10 /* Interrupt Enabled Mask Register, RO */
  35 #define CDNS_SPI_ER     0x14 /* Enable/Disable Register, RW */
  36 #define CDNS_SPI_DR     0x18 /* Delay Register, RW */
  37 #define CDNS_SPI_TXD    0x1C /* Data Transmit Register, WO */
  38 #define CDNS_SPI_RXD    0x20 /* Data Receive Register, RO */
  39 #define CDNS_SPI_SICR   0x24 /* Slave Idle Count Register, RW */
  40 #define CDNS_SPI_THLD   0x28 /* Transmit FIFO Watermark Register,RW */
  41
  42 #define SPI_AUTOSUSPEND_TIMEOUT         3000
  43 /*
  44  * SPI Configuration Register bit Masks
  45  *
  46  * This register contains various control bits that affect the operation
  47  * of the SPI controller
  48  */
  49 #define CDNS_SPI_CR_MANSTRT     0x00010000 /* Manual TX Start */
  50 #define CDNS_SPI_CR_CPHA                0x00000004 /* Clock Phase Control */
  51 #define CDNS_SPI_CR_CPOL                0x00000002 /* Clock Polarity Control */
  52 #define CDNS_SPI_CR_SSCTRL              0x00003C00 /* Slave Select Mask */
  53 #define CDNS_SPI_CR_PERI_SEL    0x00000200 /* Peripheral Select Decode */
  54 #define CDNS_SPI_CR_BAUD_DIV    0x00000038 /* Baud Rate Divisor Mask */
  55 #define CDNS_SPI_CR_MSTREN              0x00000001 /* Master Enable Mask */
  56 #define CDNS_SPI_CR_MANSTRTEN   0x00008000 /* Manual TX Enable Mask */
  57 #define CDNS_SPI_CR_SSFORCE     0x00004000 /* Manual SS Enable Mask */
  58 #define CDNS_SPI_CR_BAUD_DIV_4  0x00000008 /* Default Baud Div Mask */
  59 #define CDNS_SPI_CR_DEFAULT     (CDNS_SPI_CR_MSTREN | \
  60                                         CDNS_SPI_CR_SSCTRL | \
  61                                         CDNS_SPI_CR_SSFORCE | \
  62                                         CDNS_SPI_CR_BAUD_DIV_4)
  63
  64 /*
  65  * SPI Configuration Register - Baud rate and slave select
  66  *
  67  * These are the values used in the calculation of baud rate divisor and
  68  * setting the slave select.
  69  */
  70
  71 #define CDNS_SPI_BAUD_DIV_MAX           7 /* Baud rate divisor maximum */
  72 #define CDNS_SPI_BAUD_DIV_MIN           1 /* Baud rate divisor minimum */
  73 #define CDNS_SPI_BAUD_DIV_SHIFT         3 /* Baud rate divisor shift in CR */
  74 #define CDNS_SPI_SS_SHIFT               10 /* Slave Select field shift in CR */
  75 #define CDNS_SPI_SS0                    0x1 /* Slave Select zero */
  76
  77 /*
  78  * SPI Interrupt Registers bit Masks
  79  *
  80  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  81  * bit definitions.
  82  */
  83 #define CDNS_SPI_IXR_TXOW       0x00000004 /* SPI TX FIFO Overwater */
  84 #define CDNS_SPI_IXR_MODF       0x00000002 /* SPI Mode Fault */
  85 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
  86 #define CDNS_SPI_IXR_DEFAULT    (CDNS_SPI_IXR_TXOW | \
  87                                         CDNS_SPI_IXR_MODF)
  88 #define CDNS_SPI_IXR_TXFULL     0x00000008 /* SPI TX Full */
  89 #define CDNS_SPI_IXR_ALL        0x0000007F /* SPI all interrupts */
  90
  91 /*
  92  * SPI Enable Register bit Masks
  93  *
  94  * This register is used to enable or disable the SPI controller
  95  */
  96 #define CDNS_SPI_ER_ENABLE      0x00000001 /* SPI Enable Bit Mask */
  97 #define CDNS_SPI_ER_DISABLE     0x0 /* SPI Disable Bit Mask */
  98
  99 /* SPI FIFO depth in bytes */
 100 #define CDNS_SPI_FIFO_DEPTH     128
 101
 102 /* Default number of chip select lines */
 103 #define CDNS_SPI_DEFAULT_NUM_CS         4
 104
 105 /**
 106  * struct cdns_spi - This definition defines spi driver instance
 107  * @regs:               Virtual address of the SPI controller registers
 108  * @ref_clk:            Pointer to the peripheral clock
 109  * @pclk:               Pointer to the APB clock
 110  * @speed_hz:           Current SPI bus clock speed in Hz
 111  * @txbuf:              Pointer to the TX buffer
 112  * @rxbuf:              Pointer to the RX buffer
 113  * @tx_bytes:           Number of bytes left to transfer
 114  * @rx_bytes:           Number of bytes requested
 115  * @dev_busy:           Device busy flag
 116  * @is_decoded_cs:      Flag for decoder property set or not
 117  */
 118 struct cdns_spi {
 119         void __iomem *regs;
 120         struct clk *ref_clk;
 121         struct clk *pclk;
 122         unsigned int clk_rate;
 123         u32 speed_hz;
 124         const u8 *txbuf;
 125         u8 *rxbuf;
 126         int tx_bytes;
 127         int rx_bytes;
 128         u8 dev_busy;
 129         u32 is_decoded_cs;
 130 };
 131
 132 struct cdns_spi_device_data {
 133         bool gpio_requested;
 134 };
 135
 136 /* Macros for the SPI controller read/write */
 137 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
 138 {
 139         return readl_relaxed(xspi->regs + offset);
 140 }
 141
 142 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
 143 {
 144         writel_relaxed(val, xspi->regs + offset);
 145 }
 146
 147 /**
 148  * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
 149  * @xspi:       Pointer to the cdns_spi structure
 150  *
 151  * On reset the SPI controller is configured to be in master mode, baud rate
 152  * divisor is set to 4, threshold value for TX FIFO not full interrupt is set
 153  * to 1 and size of the word to be transferred as 8 bit.
 154  * This function initializes the SPI controller to disable and clear all the
 155  * interrupts, enable manual slave select and manual start, deselect all the
 156  * chip select lines, and enable the SPI controller.
 157  */
 158 static void cdns_spi_init_hw(struct cdns_spi *xspi)
 159 {
 160         u32 ctrl_reg = CDNS_SPI_CR_DEFAULT;
 161
 162         if (xspi->is_decoded_cs)
 163                 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
 164
 165         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 166         cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
 167
 168         /* Clear the RX FIFO */
 169         while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
 170                 cdns_spi_read(xspi, CDNS_SPI_RXD);
 171
 172         cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
 173         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 174         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 175 }
 176
 177 /**
 178  * cdns_spi_chipselect - Select or deselect the chip select line
 179  * @spi:        Pointer to the spi_device structure
 180  * @is_high:    Select(0) or deselect (1) the chip select line
 181  */
 182 static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
 183 {
 184         struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
 185         u32 ctrl_reg;
 186
 187         ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 188
 189         if (is_high) {
 190                 /* Deselect the slave */
 191                 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
 192         } else {
 193                 /* Select the slave */
 194                 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
 195                 if (!(xspi->is_decoded_cs))
 196                         ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
 197                                      CDNS_SPI_SS_SHIFT) &
 198                                      CDNS_SPI_CR_SSCTRL;
 199                 else
 200                         ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
 201                                      CDNS_SPI_CR_SSCTRL;
 202         }
 203
 204         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 205 }
 206
 207 /**
 208  * cdns_spi_config_clock_mode - Sets clock polarity and phase
 209  * @spi:        Pointer to the spi_device structure
 210  *
 211  * Sets the requested clock polarity and phase.
 212  */
 213 static void cdns_spi_config_clock_mode(struct spi_device *spi)
 214 {
 215         struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
 216         u32 ctrl_reg, new_ctrl_reg;
 217
 218         new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 219         ctrl_reg = new_ctrl_reg;
 220
 221         /* Set the SPI clock phase and clock polarity */
 222         new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
 223         if (spi->mode & SPI_CPHA)
 224                 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
 225         if (spi->mode & SPI_CPOL)
 226                 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
 227
 228         if (new_ctrl_reg != ctrl_reg) {
 229                 /*
 230                  * Just writing the CR register does not seem to apply the clock
 231                  * setting changes. This is problematic when changing the clock
 232                  * polarity as it will cause the SPI slave to see spurious clock
 233                  * transitions. To workaround the issue toggle the ER register.
 234                  */
 235                 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 236                 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
 237                 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 238         }
 239 }
 240
 241 /**
 242  * cdns_spi_config_clock_freq - Sets clock frequency
 243  * @spi:        Pointer to the spi_device structure
 244  * @transfer:   Pointer to the spi_transfer structure which provides
 245  *              information about next transfer setup parameters
 246  *
 247  * Sets the requested clock frequency.
 248  * Note: If the requested frequency is not an exact match with what can be
 249  * obtained using the prescalar value the driver sets the clock frequency which
 250  * is lower than the requested frequency (maximum lower) for the transfer. If
 251  * the requested frequency is higher or lower than that is supported by the SPI
 252  * controller the driver will set the highest or lowest frequency supported by
 253  * controller.
 254  */
 255 static void cdns_spi_config_clock_freq(struct spi_device *spi,
 256                                        struct spi_transfer *transfer)
 257 {
 258         struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
 259         u32 ctrl_reg, baud_rate_val;
 260         unsigned long frequency;
 261
 262         frequency = xspi->clk_rate;
 263
 264         ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 265
 266         /* Set the clock frequency */
 267         if (xspi->speed_hz != transfer->speed_hz) {
 268                 /* first valid value is 1 */
 269                 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
 270                 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
 271                        (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
 272                         baud_rate_val++;
 273
 274                 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
 275                 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
 276
 277                 xspi->speed_hz = frequency / (2 << baud_rate_val);
 278         }
 279         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 280 }
 281
 282 /**
 283  * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
 284  * @spi:        Pointer to the spi_device structure
 285  * @transfer:   Pointer to the spi_transfer structure which provides
 286  *              information about next transfer setup parameters
 287  *
 288  * Sets the operational mode of SPI controller for the next SPI transfer and
 289  * sets the requested clock frequency.
 290  *
 291  * Return:      Always 0
 292  */
 293 static int cdns_spi_setup_transfer(struct spi_device *spi,
 294                                    struct spi_transfer *transfer)
 295 {
 296         struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
 297
 298         cdns_spi_config_clock_freq(spi, transfer);
 299
 300         dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
 301                 __func__, spi->mode, spi->bits_per_word,
 302                 xspi->speed_hz);
 303
 304         return 0;
 305 }
 306
 307 /**
 308  * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
 309  * @xspi:       Pointer to the cdns_spi structure
 310  */
 311 static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
 312 {
 313         unsigned long trans_cnt = 0;
 314
 315         while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
 316                (xspi->tx_bytes > 0)) {
 317
 318                 /* When xspi in busy condition, bytes may send failed,
 319                  * then spi control did't work thoroughly, add one byte delay
 320                  */
 321                 if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
 322                     CDNS_SPI_IXR_TXFULL)
 323                         udelay(10);
 324
 325                 if (xspi->txbuf)
 326                         cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
 327                 else
 328                         cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
 329
 330                 xspi->tx_bytes--;
 331                 trans_cnt++;
 332         }
 333 }
 334
 335 /**
 336  * cdns_spi_irq - Interrupt service routine of the SPI controller
 337  * @irq:        IRQ number
 338  * @dev_id:     Pointer to the xspi structure
 339  *
 340  * This function handles TX empty and Mode Fault interrupts only.
 341  * On TX empty interrupt this function reads the received data from RX FIFO and
 342  * fills the TX FIFO if there is any data remaining to be transferred.
 343  * On Mode Fault interrupt this function indicates that transfer is completed,
 344  * the SPI subsystem will identify the error as the remaining bytes to be
 345  * transferred is non-zero.
 346  *
 347  * Return:      IRQ_HANDLED when handled; IRQ_NONE otherwise.
 348  */
 349 static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
 350 {
 351         struct spi_master *master = dev_id;
 352         struct cdns_spi *xspi = spi_master_get_devdata(master);
 353         u32 intr_status, status;
 354
 355         status = IRQ_NONE;
 356         intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
 357         cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
 358
 359         if (intr_status & CDNS_SPI_IXR_MODF) {
 360                 /* Indicate that transfer is completed, the SPI subsystem will
 361                  * identify the error as the remaining bytes to be
 362                  * transferred is non-zero
 363                  */
 364                 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
 365                 spi_finalize_current_transfer(master);
 366                 status = IRQ_HANDLED;
 367         } else if (intr_status & CDNS_SPI_IXR_TXOW) {
 368                 unsigned long trans_cnt;
 369
 370                 trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
 371
 372                 /* Read out the data from the RX FIFO */
 373                 while (trans_cnt) {
 374                         u8 data;
 375
 376                         data = cdns_spi_read(xspi, CDNS_SPI_RXD);
 377                         if (xspi->rxbuf)
 378                                 *xspi->rxbuf++ = data;
 379
 380                         xspi->rx_bytes--;
 381                         trans_cnt--;
 382                 }
 383
 384                 if (xspi->tx_bytes) {
 385                         /* There is more data to send */
 386                         cdns_spi_fill_tx_fifo(xspi);
 387                 } else {
 388                         /* Transfer is completed */
 389                         cdns_spi_write(xspi, CDNS_SPI_IDR,
 390                                        CDNS_SPI_IXR_DEFAULT);
 391                         spi_finalize_current_transfer(master);
 392                 }
 393                 status = IRQ_HANDLED;
 394         }
 395
 396         return status;
 397 }
 398
 399 static int cdns_prepare_message(struct spi_master *master,
 400                                 struct spi_message *msg)
 401 {
 402         cdns_spi_config_clock_mode(msg->spi);
 403         return 0;
 404 }
 405
 406 /**
 407  * cdns_transfer_one - Initiates the SPI transfer
 408  * @master:     Pointer to spi_master structure
 409  * @spi:        Pointer to the spi_device structure
 410  * @transfer:   Pointer to the spi_transfer structure which provides
 411  *              information about next transfer parameters
 412  *
 413  * This function fills the TX FIFO, starts the SPI transfer and
 414  * returns a positive transfer count so that core will wait for completion.
 415  *
 416  * Return:      Number of bytes transferred in the last transfer
 417  */
 418 static int cdns_transfer_one(struct spi_master *master,
 419                              struct spi_device *spi,
 420                              struct spi_transfer *transfer)
 421 {
 422         struct cdns_spi *xspi = spi_master_get_devdata(master);
 423
 424         xspi->txbuf = transfer->tx_buf;
 425         xspi->rxbuf = transfer->rx_buf;
 426         xspi->tx_bytes = transfer->len;
 427         xspi->rx_bytes = transfer->len;
 428
 429         cdns_spi_setup_transfer(spi, transfer);
 430
 431         cdns_spi_fill_tx_fifo(xspi);
 432
 433         cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
 434         return transfer->len;
 435 }
 436
 437 /**
 438  * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
 439  * @master:     Pointer to the spi_master structure which provides
 440  *              information about the controller.
 441  *
 442  * This function enables SPI master controller.
 443  *
 444  * Return:      0 always
 445  */
 446 static int cdns_prepare_transfer_hardware(struct spi_master *master)
 447 {
 448         struct cdns_spi *xspi = spi_master_get_devdata(master);
 449
 450         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 451
 452         return 0;
 453 }
 454
 455 /**
 456  * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
 457  * @master:     Pointer to the spi_master structure which provides
 458  *              information about the controller.
 459  *
 460  * This function disables the SPI master controller.
 461  *
 462  * Return:      0 always
 463  */
 464 static int cdns_unprepare_transfer_hardware(struct spi_master *master)
 465 {
 466         struct cdns_spi *xspi = spi_master_get_devdata(master);
 467
 468         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 469
 470         return 0;
 471 }
 472
 473 static int cdns_spi_setup(struct spi_device *spi)
 474 {
 475
 476         int ret = -EINVAL;
 477         struct cdns_spi_device_data *cdns_spi_data = spi_get_ctldata(spi);
 478
 479         /* this is a pin managed by the controller, leave it alone */
 480         if (spi->cs_gpio == -ENOENT)
 481                 return 0;
 482
 483         /* this seems to be the first time we're here */
 484         if (!cdns_spi_data) {
 485                 cdns_spi_data = kzalloc(sizeof(*cdns_spi_data), GFP_KERNEL);
 486                 if (!cdns_spi_data)
 487                         return -ENOMEM;
 488                 cdns_spi_data->gpio_requested = false;
 489                 spi_set_ctldata(spi, cdns_spi_data);
 490         }
 491
 492         /* if we haven't done so, grab the gpio */
 493         if (!cdns_spi_data->gpio_requested && gpio_is_valid(spi->cs_gpio)) {
 494                 ret = gpio_request_one(spi->cs_gpio,
 495                                        (spi->mode & SPI_CS_HIGH) ?
 496                                        GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,
 497                                        dev_name(&spi->dev));
 498                 if (ret)
 499                         dev_err(&spi->dev, "can't request chipselect gpio %d\n",
 500                                 spi->cs_gpio);
 501                 else
 502                         cdns_spi_data->gpio_requested = true;
 503         } else {
 504                 if (gpio_is_valid(spi->cs_gpio)) {
 505                         int mode = ((spi->mode & SPI_CS_HIGH) ?
 506                                     GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH);
 507
 508                         ret = gpio_direction_output(spi->cs_gpio, mode);
 509                         if (ret)
 510                                 dev_err(&spi->dev, "chipselect gpio %d setup failed (%d)\n",
 511                                         spi->cs_gpio, ret);
 512                 }
 513         }
 514
 515         return ret;
 516 }
 517
 518 static void cdns_spi_cleanup(struct spi_device *spi)
 519 {
 520         struct cdns_spi_device_data *cdns_spi_data = spi_get_ctldata(spi);
 521
 522         if (cdns_spi_data) {
 523                 if (cdns_spi_data->gpio_requested)
 524                         gpio_free(spi->cs_gpio);
 525                 kfree(cdns_spi_data);
 526                 spi_set_ctldata(spi, NULL);
 527         }
 528
 529 }
 530
 531 /**
 532  * cdns_spi_probe - Probe method for the SPI driver
 533  * @pdev:       Pointer to the platform_device structure
 534  *
 535  * This function initializes the driver data structures and the hardware.
 536  *
 537  * Return:      0 on success and error value on error
 538  */
 539 static int cdns_spi_probe(struct platform_device *pdev)
 540 {
 541         int ret = 0, irq;
 542         struct spi_master *master;
 543         struct cdns_spi *xspi;
 544         struct resource *res;
 545         u32 num_cs;
 546
 547         master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
 548         if (!master)
 549                 return -ENOMEM;
 550
 551         xspi = spi_master_get_devdata(master);
 552         master->dev.of_node = pdev->dev.of_node;
 553         platform_set_drvdata(pdev, master);
 554
 555         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 556         xspi->regs = devm_ioremap_resource(&pdev->dev, res);
 557         if (IS_ERR(xspi->regs)) {
 558                 ret = PTR_ERR(xspi->regs);
 559                 goto remove_master;
 560         }
 561
 562         xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
 563         if (IS_ERR(xspi->pclk)) {
 564                 dev_err(&pdev->dev, "pclk clock not found.\n");
 565                 ret = PTR_ERR(xspi->pclk);
 566                 goto remove_master;
 567         }
 568
 569         xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
 570         if (IS_ERR(xspi->ref_clk)) {
 571                 dev_err(&pdev->dev, "ref_clk clock not found.\n");
 572                 ret = PTR_ERR(xspi->ref_clk);
 573                 goto remove_master;
 574         }
 575
 576         ret = clk_prepare_enable(xspi->pclk);
 577         if (ret) {
 578                 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
 579                 goto remove_master;
 580         }
 581
 582         ret = clk_prepare_enable(xspi->ref_clk);
 583         if (ret) {
 584                 dev_err(&pdev->dev, "Unable to enable device clock.\n");
 585                 goto clk_dis_apb;
 586         }
 587
 588         pm_runtime_use_autosuspend(&pdev->dev);
 589         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
 590         pm_runtime_get_noresume(&pdev->dev);
 591         pm_runtime_set_active(&pdev->dev);
 592         pm_runtime_enable(&pdev->dev);
 593
 594         ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
 595         if (ret < 0)
 596                 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
 597         else
 598                 master->num_chipselect = num_cs;
 599
 600         ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
 601                                    &xspi->is_decoded_cs);
 602         if (ret < 0)
 603                 xspi->is_decoded_cs = 0;
 604
 605         /* SPI controller initializations */
 606         cdns_spi_init_hw(xspi);
 607
 608         irq = platform_get_irq(pdev, 0);
 609         if (irq <= 0) {
 610                 ret = -ENXIO;
 611                 dev_err(&pdev->dev, "irq number is invalid\n");
 612                 goto clk_dis_all;
 613         }
 614
 615         ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
 616                                0, pdev->name, master);
 617         if (ret != 0) {
 618                 ret = -ENXIO;
 619                 dev_err(&pdev->dev, "request_irq failed\n");
 620                 goto clk_dis_all;
 621         }
 622
 623         master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
 624         master->prepare_message = cdns_prepare_message;
 625         master->transfer_one = cdns_transfer_one;
 626         master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
 627         master->set_cs = cdns_spi_chipselect;
 628         master->setup = cdns_spi_setup;
 629         master->cleanup = cdns_spi_cleanup;
 630         master->auto_runtime_pm = true;
 631         master->mode_bits = SPI_CPOL | SPI_CPHA;
 632
 633         xspi->clk_rate = clk_get_rate(xspi->ref_clk);
 634         /* Set to default valid value */
 635         master->max_speed_hz = xspi->clk_rate / 4;
 636         xspi->speed_hz = master->max_speed_hz;
 637
 638         master->bits_per_word_mask = SPI_BPW_MASK(8);
 639
 640         pm_runtime_mark_last_busy(&pdev->dev);
 641         pm_runtime_put_autosuspend(&pdev->dev);
 642
 643         ret = spi_register_master(master);
 644         if (ret) {
 645                 dev_err(&pdev->dev, "spi_register_master failed\n");
 646                 goto clk_dis_all;
 647         }
 648
 649         return ret;
 650
 651 clk_dis_all:
 652         pm_runtime_set_suspended(&pdev->dev);
 653         pm_runtime_disable(&pdev->dev);
 654         clk_disable_unprepare(xspi->ref_clk);
 655 clk_dis_apb:
 656         clk_disable_unprepare(xspi->pclk);
 657 remove_master:
 658         spi_master_put(master);
 659         return ret;
 660 }
 661
 662 /**
 663  * cdns_spi_remove - Remove method for the SPI driver
 664  * @pdev:       Pointer to the platform_device structure
 665  *
 666  * This function is called if a device is physically removed from the system or
 667  * if the driver module is being unloaded. It frees all resources allocated to
 668  * the device.
 669  *
 670  * Return:      0 on success and error value on error
 671  */
 672 static int cdns_spi_remove(struct platform_device *pdev)
 673 {
 674         struct spi_master *master = platform_get_drvdata(pdev);
 675         struct cdns_spi *xspi = spi_master_get_devdata(master);
 676
 677         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 678
 679         clk_disable_unprepare(xspi->ref_clk);
 680         clk_disable_unprepare(xspi->pclk);
 681         pm_runtime_set_suspended(&pdev->dev);
 682         pm_runtime_disable(&pdev->dev);
 683
 684         spi_unregister_master(master);
 685
 686         return 0;
 687 }
 688
 689 /**
 690  * cdns_spi_suspend - Suspend method for the SPI driver
 691  * @dev:        Address of the platform_device structure
 692  *
 693  * This function disables the SPI controller and
 694  * changes the driver state to "suspend"
 695  *
 696  * Return:      0 on success and error value on error
 697  */
 698 static int __maybe_unused cdns_spi_suspend(struct device *dev)
 699 {
 700         struct spi_master *master = dev_get_drvdata(dev);
 701
 702         return spi_master_suspend(master);
 703 }
 704
 705 /**
 706  * cdns_spi_resume - Resume method for the SPI driver
 707  * @dev:        Address of the platform_device structure
 708  *
 709  * This function changes the driver state to "ready"
 710  *
 711  * Return:      0 on success and error value on error
 712  */
 713 static int __maybe_unused cdns_spi_resume(struct device *dev)
 714 {
 715         struct spi_master *master = dev_get_drvdata(dev);
 716         struct cdns_spi *xspi = spi_master_get_devdata(master);
 717
 718         cdns_spi_init_hw(xspi);
 719         return spi_master_resume(master);
 720 }
 721
 722 /**
 723  * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
 724  * @dev:        Address of the platform_device structure
 725  *
 726  * This function enables the clocks
 727  *
 728  * Return:      0 on success and error value on error
 729  */
 730 static int __maybe_unused cnds_runtime_resume(struct device *dev)
 731 {
 732         struct spi_master *master = dev_get_drvdata(dev);
 733         struct cdns_spi *xspi = spi_master_get_devdata(master);
 734         int ret;
 735
 736         ret = clk_prepare_enable(xspi->pclk);
 737         if (ret) {
 738                 dev_err(dev, "Cannot enable APB clock.\n");
 739                 return ret;
 740         }
 741
 742         ret = clk_prepare_enable(xspi->ref_clk);
 743         if (ret) {
 744                 dev_err(dev, "Cannot enable device clock.\n");
 745                 clk_disable_unprepare(xspi->pclk);
 746                 return ret;
 747         }
 748         return 0;
 749 }
 750
 751 /**
 752  * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
 753  * @dev:        Address of the platform_device structure
 754  *
 755  * This function disables the clocks
 756  *
 757  * Return:      Always 0
 758  */
 759 static int __maybe_unused cnds_runtime_suspend(struct device *dev)
 760 {
 761         struct spi_master *master = dev_get_drvdata(dev);
 762         struct cdns_spi *xspi = spi_master_get_devdata(master);
 763
 764         clk_disable_unprepare(xspi->ref_clk);
 765         clk_disable_unprepare(xspi->pclk);
 766
 767         return 0;
 768 }
 769
 770 static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
 771         SET_RUNTIME_PM_OPS(cnds_runtime_suspend,
 772                            cnds_runtime_resume, NULL)
 773         SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
 774 };
 775
 776 static const struct of_device_id cdns_spi_of_match[] = {
 777         { .compatible = "xlnx,zynq-spi-r1p6" },
 778         { .compatible = "cdns,spi-r1p6" },
 779         { /* end of table */ }
 780 };
 781 MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
 782
 783 /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
 784 static struct platform_driver cdns_spi_driver = {
 785         .probe  = cdns_spi_probe,
 786         .remove = cdns_spi_remove,
 787         .driver = {
 788                 .name = CDNS_SPI_NAME,
 789                 .of_match_table = cdns_spi_of_match,
 790                 .pm = &cdns_spi_dev_pm_ops,
 791         },
 792 };
 793
 794 module_platform_driver(cdns_spi_driver);
 795
 796 MODULE_AUTHOR("Xilinx, Inc.");
 797 MODULE_DESCRIPTION("Cadence SPI driver");
 798 MODULE_LICENSE("GPL");