drivers/spi/spi-lantiq-ssc.c

   1 /*
   2  * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
   3  * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
   4  *
   5  * This program is free software; you can distribute it and/or modify it
   6  * under the terms of the GNU General Public License (Version 2) as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk.h>
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/sched.h>
  18 #include <linux/completion.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/err.h>
  21 #include <linux/gpio.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/spi/spi.h>
  24
  25 #ifdef CONFIG_LANTIQ
  26 #include <lantiq_soc.h>
  27 #endif
  28
  29 #define LTQ_SPI_RX_IRQ_NAME     "spi_rx"
  30 #define LTQ_SPI_TX_IRQ_NAME     "spi_tx"
  31 #define LTQ_SPI_ERR_IRQ_NAME    "spi_err"
  32 #define LTQ_SPI_FRM_IRQ_NAME    "spi_frm"
  33
  34 #define LTQ_SPI_CLC             0x00
  35 #define LTQ_SPI_PISEL           0x04
  36 #define LTQ_SPI_ID              0x08
  37 #define LTQ_SPI_CON             0x10
  38 #define LTQ_SPI_STAT            0x14
  39 #define LTQ_SPI_WHBSTATE        0x18
  40 #define LTQ_SPI_TB              0x20
  41 #define LTQ_SPI_RB              0x24
  42 #define LTQ_SPI_RXFCON          0x30
  43 #define LTQ_SPI_TXFCON          0x34
  44 #define LTQ_SPI_FSTAT           0x38
  45 #define LTQ_SPI_BRT             0x40
  46 #define LTQ_SPI_BRSTAT          0x44
  47 #define LTQ_SPI_SFCON           0x60
  48 #define LTQ_SPI_SFSTAT          0x64
  49 #define LTQ_SPI_GPOCON          0x70
  50 #define LTQ_SPI_GPOSTAT         0x74
  51 #define LTQ_SPI_FPGO            0x78
  52 #define LTQ_SPI_RXREQ           0x80
  53 #define LTQ_SPI_RXCNT           0x84
  54 #define LTQ_SPI_DMACON          0xec
  55 #define LTQ_SPI_IRNEN           0xf4
  56 #define LTQ_SPI_IRNICR          0xf8
  57 #define LTQ_SPI_IRNCR           0xfc
  58
  59 #define LTQ_SPI_CLC_SMC_S       16      /* Clock divider for sleep mode */
  60 #define LTQ_SPI_CLC_SMC_M       (0xFF << LTQ_SPI_CLC_SMC_S)
  61 #define LTQ_SPI_CLC_RMC_S       8       /* Clock divider for normal run mode */
  62 #define LTQ_SPI_CLC_RMC_M       (0xFF << LTQ_SPI_CLC_RMC_S)
  63 #define LTQ_SPI_CLC_DISS        BIT(1)  /* Disable status bit */
  64 #define LTQ_SPI_CLC_DISR        BIT(0)  /* Disable request bit */
  65
  66 #define LTQ_SPI_ID_TXFS_S       24      /* Implemented TX FIFO size */
  67 #define LTQ_SPI_ID_TXFS_M       (0x3F << LTQ_SPI_ID_TXFS_S)
  68 #define LTQ_SPI_ID_RXFS_S       16      /* Implemented RX FIFO size */
  69 #define LTQ_SPI_ID_RXFS_M       (0x3F << LTQ_SPI_ID_RXFS_S)
  70 #define LTQ_SPI_ID_MOD_S        8       /* Module ID */
  71 #define LTQ_SPI_ID_MOD_M        (0xff << LTQ_SPI_ID_MOD_S)
  72 #define LTQ_SPI_ID_CFG_S        5       /* DMA interface support */
  73 #define LTQ_SPI_ID_CFG_M        (1 << LTQ_SPI_ID_CFG_S)
  74 #define LTQ_SPI_ID_REV_M        0x1F    /* Hardware revision number */
  75
  76 #define LTQ_SPI_CON_BM_S        16      /* Data width selection */
  77 #define LTQ_SPI_CON_BM_M        (0x1F << LTQ_SPI_CON_BM_S)
  78 #define LTQ_SPI_CON_EM          BIT(24) /* Echo mode */
  79 #define LTQ_SPI_CON_IDLE        BIT(23) /* Idle bit value */
  80 #define LTQ_SPI_CON_ENBV        BIT(22) /* Enable byte valid control */
  81 #define LTQ_SPI_CON_RUEN        BIT(12) /* Receive underflow error enable */
  82 #define LTQ_SPI_CON_TUEN        BIT(11) /* Transmit underflow error enable */
  83 #define LTQ_SPI_CON_AEN         BIT(10) /* Abort error enable */
  84 #define LTQ_SPI_CON_REN         BIT(9)  /* Receive overflow error enable */
  85 #define LTQ_SPI_CON_TEN         BIT(8)  /* Transmit overflow error enable */
  86 #define LTQ_SPI_CON_LB          BIT(7)  /* Loopback control */
  87 #define LTQ_SPI_CON_PO          BIT(6)  /* Clock polarity control */
  88 #define LTQ_SPI_CON_PH          BIT(5)  /* Clock phase control */
  89 #define LTQ_SPI_CON_HB          BIT(4)  /* Heading control */
  90 #define LTQ_SPI_CON_RXOFF       BIT(1)  /* Switch receiver off */
  91 #define LTQ_SPI_CON_TXOFF       BIT(0)  /* Switch transmitter off */
  92
  93 #define LTQ_SPI_STAT_RXBV_S     28
  94 #define LTQ_SPI_STAT_RXBV_M     (0x7 << LTQ_SPI_STAT_RXBV_S)
  95 #define LTQ_SPI_STAT_BSY        BIT(13) /* Busy flag */
  96 #define LTQ_SPI_STAT_RUE        BIT(12) /* Receive underflow error flag */
  97 #define LTQ_SPI_STAT_TUE        BIT(11) /* Transmit underflow error flag */
  98 #define LTQ_SPI_STAT_AE         BIT(10) /* Abort error flag */
  99 #define LTQ_SPI_STAT_RE         BIT(9)  /* Receive error flag */
 100 #define LTQ_SPI_STAT_TE         BIT(8)  /* Transmit error flag */
 101 #define LTQ_SPI_STAT_ME         BIT(7)  /* Mode error flag */
 102 #define LTQ_SPI_STAT_MS         BIT(1)  /* Master/slave select bit */
 103 #define LTQ_SPI_STAT_EN         BIT(0)  /* Enable bit */
 104 #define LTQ_SPI_STAT_ERRORS     (LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \
 105                                  LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \
 106                                  LTQ_SPI_STAT_TUE | LTQ_SPI_STAT_RUE)
 107
 108 #define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
 109 #define LTQ_SPI_WHBSTATE_SETAE  BIT(14) /* Set abort error flag */
 110 #define LTQ_SPI_WHBSTATE_SETRE  BIT(13) /* Set receive error flag */
 111 #define LTQ_SPI_WHBSTATE_SETTE  BIT(12) /* Set transmit error flag */
 112 #define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */
 113 #define LTQ_SPI_WHBSTATE_CLRAE  BIT(10) /* Clear abort error flag */
 114 #define LTQ_SPI_WHBSTATE_CLRRE  BIT(9)  /* Clear receive error flag */
 115 #define LTQ_SPI_WHBSTATE_CLRTE  BIT(8)  /* Clear transmit error flag */
 116 #define LTQ_SPI_WHBSTATE_SETME  BIT(7)  /* Set mode error flag */
 117 #define LTQ_SPI_WHBSTATE_CLRME  BIT(6)  /* Clear mode error flag */
 118 #define LTQ_SPI_WHBSTATE_SETRUE BIT(5)  /* Set receive underflow error flag */
 119 #define LTQ_SPI_WHBSTATE_CLRRUE BIT(4)  /* Clear receive underflow error flag */
 120 #define LTQ_SPI_WHBSTATE_SETMS  BIT(3)  /* Set master select bit */
 121 #define LTQ_SPI_WHBSTATE_CLRMS  BIT(2)  /* Clear master select bit */
 122 #define LTQ_SPI_WHBSTATE_SETEN  BIT(1)  /* Set enable bit (operational mode) */
 123 #define LTQ_SPI_WHBSTATE_CLREN  BIT(0)  /* Clear enable bit (config mode */
 124 #define LTQ_SPI_WHBSTATE_CLR_ERRORS     (LTQ_SPI_WHBSTATE_CLRRUE | \
 125                                          LTQ_SPI_WHBSTATE_CLRME | \
 126                                          LTQ_SPI_WHBSTATE_CLRTE | \
 127                                          LTQ_SPI_WHBSTATE_CLRRE | \
 128                                          LTQ_SPI_WHBSTATE_CLRAE | \
 129                                          LTQ_SPI_WHBSTATE_CLRTUE)
 130
 131 #define LTQ_SPI_RXFCON_RXFITL_S 8       /* FIFO interrupt trigger level */
 132 #define LTQ_SPI_RXFCON_RXFITL_M (0x3F << LTQ_SPI_RXFCON_RXFITL_S)
 133 #define LTQ_SPI_RXFCON_RXFLU    BIT(1)  /* FIFO flush */
 134 #define LTQ_SPI_RXFCON_RXFEN    BIT(0)  /* FIFO enable */
 135
 136 #define LTQ_SPI_TXFCON_TXFITL_S 8       /* FIFO interrupt trigger level */
 137 #define LTQ_SPI_TXFCON_TXFITL_M (0x3F << LTQ_SPI_TXFCON_TXFITL_S)
 138 #define LTQ_SPI_TXFCON_TXFLU    BIT(1)  /* FIFO flush */
 139 #define LTQ_SPI_TXFCON_TXFEN    BIT(0)  /* FIFO enable */
 140
 141 #define LTQ_SPI_FSTAT_RXFFL_S   0
 142 #define LTQ_SPI_FSTAT_RXFFL_M   (0x3f << LTQ_SPI_FSTAT_RXFFL_S)
 143 #define LTQ_SPI_FSTAT_TXFFL_S   8
 144 #define LTQ_SPI_FSTAT_TXFFL_M   (0x3f << LTQ_SPI_FSTAT_TXFFL_S)
 145
 146 #define LTQ_SPI_GPOCON_ISCSBN_S 8
 147 #define LTQ_SPI_GPOCON_INVOUTN_S        0
 148
 149 #define LTQ_SPI_FGPO_SETOUTN_S  8
 150 #define LTQ_SPI_FGPO_CLROUTN_S  0
 151
 152 #define LTQ_SPI_RXREQ_RXCNT_M   0xFFFF  /* Receive count value */
 153 #define LTQ_SPI_RXCNT_TODO_M    0xFFFF  /* Recevie to-do value */
 154
 155 #define LTQ_SPI_IRNEN_TFI       BIT(4)  /* TX finished interrupt */
 156 #define LTQ_SPI_IRNEN_F         BIT(3)  /* Frame end interrupt request */
 157 #define LTQ_SPI_IRNEN_E         BIT(2)  /* Error end interrupt request */
 158 #define LTQ_SPI_IRNEN_T_XWAY    BIT(1)  /* Transmit end interrupt request */
 159 #define LTQ_SPI_IRNEN_R_XWAY    BIT(0)  /* Receive end interrupt request */
 160 #define LTQ_SPI_IRNEN_R_XRX     BIT(1)  /* Transmit end interrupt request */
 161 #define LTQ_SPI_IRNEN_T_XRX     BIT(0)  /* Receive end interrupt request */
 162 #define LTQ_SPI_IRNEN_ALL       0x1F
 163
 164 struct lantiq_ssc_hwcfg {
 165         unsigned int irnen_r;
 166         unsigned int irnen_t;
 167 };
 168
 169 struct lantiq_ssc_spi {
 170         struct spi_master               *master;
 171         struct device                   *dev;
 172         void __iomem                    *regbase;
 173         struct clk                      *spi_clk;
 174         struct clk                      *fpi_clk;
 175         const struct lantiq_ssc_hwcfg   *hwcfg;
 176
 177         spinlock_t                      lock;
 178         struct workqueue_struct         *wq;
 179         struct work_struct              work;
 180
 181         const u8                        *tx;
 182         u8                              *rx;
 183         unsigned int                    tx_todo;
 184         unsigned int                    rx_todo;
 185         unsigned int                    bits_per_word;
 186         unsigned int                    speed_hz;
 187         unsigned int                    tx_fifo_size;
 188         unsigned int                    rx_fifo_size;
 189         unsigned int                    base_cs;
 190         unsigned int                    fdx_tx_level;
 191 };
 192
 193 static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
 194 {
 195         return __raw_readl(spi->regbase + reg);
 196 }
 197
 198 static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,
 199                               u32 reg)
 200 {
 201         __raw_writel(val, spi->regbase + reg);
 202 }
 203
 204 static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
 205                              u32 set, u32 reg)
 206 {
 207         u32 val = __raw_readl(spi->regbase + reg);
 208
 209         val &= ~clr;
 210         val |= set;
 211         __raw_writel(val, spi->regbase + reg);
 212 }
 213
 214 static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
 215 {
 216         u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
 217
 218         return (fstat & LTQ_SPI_FSTAT_TXFFL_M) >> LTQ_SPI_FSTAT_TXFFL_S;
 219 }
 220
 221 static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
 222 {
 223         u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
 224
 225         return fstat & LTQ_SPI_FSTAT_RXFFL_M;
 226 }
 227
 228 static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
 229 {
 230         return spi->tx_fifo_size - tx_fifo_level(spi);
 231 }
 232
 233 static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)
 234 {
 235         u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S;
 236
 237         val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
 238         lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON);
 239 }
 240
 241 static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)
 242 {
 243         u32 val = 1 << LTQ_SPI_TXFCON_TXFITL_S;
 244
 245         val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
 246         lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON);
 247 }
 248
 249 static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)
 250 {
 251         lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
 252 }
 253
 254 static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)
 255 {
 256         lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
 257 }
 258
 259 static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)
 260 {
 261         lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
 262 }
 263
 264 static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)
 265 {
 266         lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
 267 }
 268
 269 static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,
 270                               unsigned int max_speed_hz)
 271 {
 272         u32 spi_clk, brt;
 273
 274         /*
 275          * SPI module clock is derived from FPI bus clock dependent on
 276          * divider value in CLC.RMS which is always set to 1.
 277          *
 278          *                 f_SPI
 279          * baudrate = --------------
 280          *             2 * (BR + 1)
 281          */
 282         spi_clk = clk_get_rate(spi->fpi_clk) / 2;
 283
 284         if (max_speed_hz > spi_clk)
 285                 brt = 0;
 286         else
 287                 brt = spi_clk / max_speed_hz - 1;
 288
 289         if (brt > 0xFFFF)
 290                 brt = 0xFFFF;
 291
 292         dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",
 293                 spi_clk, max_speed_hz, brt);
 294
 295         lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT);
 296 }
 297
 298 static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,
 299                                    unsigned int bits_per_word)
 300 {
 301         u32 bm;
 302
 303         /* CON.BM value = bits_per_word - 1 */
 304         bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_S;
 305
 306         lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON);
 307 }
 308
 309 static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,
 310                                 unsigned int mode)
 311 {
 312         u32 con_set = 0, con_clr = 0;
 313
 314         /*
 315          * SPI mode mapping in CON register:
 316          * Mode CPOL CPHA CON.PO CON.PH
 317          *  0    0    0      0      1
 318          *  1    0    1      0      0
 319          *  2    1    0      1      1
 320          *  3    1    1      1      0
 321          */
 322         if (mode & SPI_CPHA)
 323                 con_clr |= LTQ_SPI_CON_PH;
 324         else
 325                 con_set |= LTQ_SPI_CON_PH;
 326
 327         if (mode & SPI_CPOL)
 328                 con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
 329         else
 330                 con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
 331
 332         /* Set heading control */
 333         if (mode & SPI_LSB_FIRST)
 334                 con_clr |= LTQ_SPI_CON_HB;
 335         else
 336                 con_set |= LTQ_SPI_CON_HB;
 337
 338         /* Set loopback mode */
 339         if (mode & SPI_LOOP)
 340                 con_set |= LTQ_SPI_CON_LB;
 341         else
 342                 con_clr |= LTQ_SPI_CON_LB;
 343
 344         lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON);
 345 }
 346
 347 static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
 348 {
 349         const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
 350
 351         /*
 352          * Set clock divider for run mode to 1 to
 353          * run at same frequency as FPI bus
 354          */
 355         lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC);
 356
 357         /* Put controller into config mode */
 358         hw_enter_config_mode(spi);
 359
 360         /* Clear error flags */
 361         lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
 362
 363         /* Enable error checking, disable TX/RX */
 364         lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
 365                 LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF |
 366                 LTQ_SPI_CON_RXOFF, LTQ_SPI_CON);
 367
 368         /* Setup default SPI mode */
 369         hw_setup_bits_per_word(spi, spi->bits_per_word);
 370         hw_setup_clock_mode(spi, SPI_MODE_0);
 371
 372         /* Enable master mode and clear error flags */
 373         lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS |
 374                                LTQ_SPI_WHBSTATE_CLR_ERRORS,
 375                                LTQ_SPI_WHBSTATE);
 376
 377         /* Reset GPIO/CS registers */
 378         lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON);
 379         lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO);
 380
 381         /* Enable and flush FIFOs */
 382         rx_fifo_reset(spi);
 383         tx_fifo_reset(spi);
 384
 385         /* Enable interrupts */
 386         lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r |
 387                           LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
 388 }
 389
 390 static int lantiq_ssc_setup(struct spi_device *spidev)
 391 {
 392         struct spi_master *master = spidev->master;
 393         struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 394         unsigned int cs = spidev->chip_select;
 395         u32 gpocon;
 396
 397         /* GPIOs are used for CS */
 398         if (gpio_is_valid(spidev->cs_gpio))
 399                 return 0;
 400
 401         dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
 402
 403         if (cs < spi->base_cs) {
 404                 dev_err(spi->dev,
 405                         "chipselect %i too small (min %i)\n", cs, spi->base_cs);
 406                 return -EINVAL;
 407         }
 408
 409         /* set GPO pin to CS mode */
 410         gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S);
 411
 412         /* invert GPO pin */
 413         if (spidev->mode & SPI_CS_HIGH)
 414                 gpocon |= 1 << (cs - spi->base_cs);
 415
 416         lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON);
 417
 418         return 0;
 419 }
 420
 421 static int lantiq_ssc_prepare_message(struct spi_master *master,
 422                                       struct spi_message *message)
 423 {
 424         struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 425
 426         hw_enter_config_mode(spi);
 427         hw_setup_clock_mode(spi, message->spi->mode);
 428         hw_enter_active_mode(spi);
 429
 430         return 0;
 431 }
 432
 433 static void hw_setup_transfer(struct lantiq_ssc_spi *spi,
 434                               struct spi_device *spidev, struct spi_transfer *t)
 435 {
 436         unsigned int speed_hz = t->speed_hz;
 437         unsigned int bits_per_word = t->bits_per_word;
 438         u32 con;
 439
 440         if (bits_per_word != spi->bits_per_word ||
 441                 speed_hz != spi->speed_hz) {
 442                 hw_enter_config_mode(spi);
 443                 hw_setup_speed_hz(spi, speed_hz);
 444                 hw_setup_bits_per_word(spi, bits_per_word);
 445                 hw_enter_active_mode(spi);
 446
 447                 spi->speed_hz = speed_hz;
 448                 spi->bits_per_word = bits_per_word;
 449         }
 450
 451         /* Configure transmitter and receiver */
 452         con = lantiq_ssc_readl(spi, LTQ_SPI_CON);
 453         if (t->tx_buf)
 454                 con &= ~LTQ_SPI_CON_TXOFF;
 455         else
 456                 con |= LTQ_SPI_CON_TXOFF;
 457
 458         if (t->rx_buf)
 459                 con &= ~LTQ_SPI_CON_RXOFF;
 460         else
 461                 con |= LTQ_SPI_CON_RXOFF;
 462
 463         lantiq_ssc_writel(spi, con, LTQ_SPI_CON);
 464 }
 465
 466 static int lantiq_ssc_unprepare_message(struct spi_master *master,
 467                                         struct spi_message *message)
 468 {
 469         struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 470
 471         flush_workqueue(spi->wq);
 472
 473         /* Disable transmitter and receiver while idle */
 474         lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF,
 475                          LTQ_SPI_CON);
 476
 477         return 0;
 478 }
 479
 480 static void tx_fifo_write(struct lantiq_ssc_spi *spi)
 481 {
 482         const u8 *tx8;
 483         const u16 *tx16;
 484         const u32 *tx32;
 485         u32 data;
 486         unsigned int tx_free = tx_fifo_free(spi);
 487
 488         spi->fdx_tx_level = 0;
 489         while (spi->tx_todo && tx_free) {
 490                 switch (spi->bits_per_word) {
 491                 case 2 ... 8:
 492                         tx8 = spi->tx;
 493                         data = *tx8;
 494                         spi->tx_todo--;
 495                         spi->tx++;
 496                         break;
 497                 case 16:
 498                         tx16 = (u16 *) spi->tx;
 499                         data = *tx16;
 500                         spi->tx_todo -= 2;
 501                         spi->tx += 2;
 502                         break;
 503                 case 32:
 504                         tx32 = (u32 *) spi->tx;
 505                         data = *tx32;
 506                         spi->tx_todo -= 4;
 507                         spi->tx += 4;
 508                         break;
 509                 default:
 510                         WARN_ON(1);
 511                         data = 0;
 512                         break;
 513                 }
 514
 515                 lantiq_ssc_writel(spi, data, LTQ_SPI_TB);
 516                 tx_free--;
 517                 spi->fdx_tx_level++;
 518         }
 519 }
 520
 521 static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)
 522 {
 523         u8 *rx8;
 524         u16 *rx16;
 525         u32 *rx32;
 526         u32 data;
 527         unsigned int rx_fill = rx_fifo_level(spi);
 528
 529         /*
 530          * Wait until all expected data to be shifted in.
 531          * Otherwise, rx overrun may occur.
 532          */
 533         while (rx_fill != spi->fdx_tx_level)
 534                 rx_fill = rx_fifo_level(spi);
 535
 536         while (rx_fill) {
 537                 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
 538
 539                 switch (spi->bits_per_word) {
 540                 case 2 ... 8:
 541                         rx8 = spi->rx;
 542                         *rx8 = data;
 543                         spi->rx_todo--;
 544                         spi->rx++;
 545                         break;
 546                 case 16:
 547                         rx16 = (u16 *) spi->rx;
 548                         *rx16 = data;
 549                         spi->rx_todo -= 2;
 550                         spi->rx += 2;
 551                         break;
 552                 case 32:
 553                         rx32 = (u32 *) spi->rx;
 554                         *rx32 = data;
 555                         spi->rx_todo -= 4;
 556                         spi->rx += 4;
 557                         break;
 558                 default:
 559                         WARN_ON(1);
 560                         break;
 561                 }
 562
 563                 rx_fill--;
 564         }
 565 }
 566
 567 static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)
 568 {
 569         u32 data, *rx32;
 570         u8 *rx8;
 571         unsigned int rxbv, shift;
 572         unsigned int rx_fill = rx_fifo_level(spi);
 573
 574         /*
 575          * In RX-only mode the bits per word value is ignored by HW. A value
 576          * of 32 is used instead. Thus all 4 bytes per FIFO must be read.
 577          * If remaining RX bytes are less than 4, the FIFO must be read
 578          * differently. The amount of received and valid bytes is indicated
 579          * by STAT.RXBV register value.
 580          */
 581         while (rx_fill) {
 582                 if (spi->rx_todo < 4)  {
 583                         rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) &
 584                                 LTQ_SPI_STAT_RXBV_M) >> LTQ_SPI_STAT_RXBV_S;
 585                         data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
 586
 587                         shift = (rxbv - 1) * 8;
 588                         rx8 = spi->rx;
 589
 590                         while (rxbv) {
 591                                 *rx8++ = (data >> shift) & 0xFF;
 592                                 rxbv--;
 593                                 shift -= 8;
 594                                 spi->rx_todo--;
 595                                 spi->rx++;
 596                         }
 597                 } else {
 598                         data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
 599                         rx32 = (u32 *) spi->rx;
 600
 601                         *rx32++ = data;
 602                         spi->rx_todo -= 4;
 603                         spi->rx += 4;
 604                 }
 605                 rx_fill--;
 606         }
 607 }
 608
 609 static void rx_request(struct lantiq_ssc_spi *spi)
 610 {
 611         unsigned int rxreq, rxreq_max;
 612
 613         /*
 614          * To avoid receive overflows at high clocks it is better to request
 615          * only the amount of bytes that fits into all FIFOs. This value
 616          * depends on the FIFO size implemented in hardware.
 617          */
 618         rxreq = spi->rx_todo;
 619         rxreq_max = spi->rx_fifo_size * 4;
 620         if (rxreq > rxreq_max)
 621                 rxreq = rxreq_max;
 622
 623         lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ);
 624 }
 625
 626 static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
 627 {
 628         struct lantiq_ssc_spi *spi = data;
 629
 630         if (spi->tx) {
 631                 if (spi->rx && spi->rx_todo)
 632                         rx_fifo_read_full_duplex(spi);
 633
 634                 if (spi->tx_todo)
 635                         tx_fifo_write(spi);
 636                 else if (!tx_fifo_level(spi))
 637                         goto completed;
 638         } else if (spi->rx) {
 639                 if (spi->rx_todo) {
 640                         rx_fifo_read_half_duplex(spi);
 641
 642                         if (spi->rx_todo)
 643                                 rx_request(spi);
 644                         else
 645                                 goto completed;
 646                 } else {
 647                         goto completed;
 648                 }
 649         }
 650
 651         return IRQ_HANDLED;
 652
 653 completed:
 654         queue_work(spi->wq, &spi->work);
 655
 656         return IRQ_HANDLED;
 657 }
 658
 659 static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
 660 {
 661         struct lantiq_ssc_spi *spi = data;
 662         u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
 663
 664         if (!(stat & LTQ_SPI_STAT_ERRORS))
 665                 return IRQ_NONE;
 666
 667         if (stat & LTQ_SPI_STAT_RUE)
 668                 dev_err(spi->dev, "receive underflow error\n");
 669         if (stat & LTQ_SPI_STAT_TUE)
 670                 dev_err(spi->dev, "transmit underflow error\n");
 671         if (stat & LTQ_SPI_STAT_AE)
 672                 dev_err(spi->dev, "abort error\n");
 673         if (stat & LTQ_SPI_STAT_RE)
 674                 dev_err(spi->dev, "receive overflow error\n");
 675         if (stat & LTQ_SPI_STAT_TE)
 676                 dev_err(spi->dev, "transmit overflow error\n");
 677         if (stat & LTQ_SPI_STAT_ME)
 678                 dev_err(spi->dev, "mode error\n");
 679
 680         /* Clear error flags */
 681         lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
 682
 683         /* set bad status so it can be retried */
 684         if (spi->master->cur_msg)
 685                 spi->master->cur_msg->status = -EIO;
 686         queue_work(spi->wq, &spi->work);
 687
 688         return IRQ_HANDLED;
 689 }
 690
 691 static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,
 692                           struct spi_transfer *t)
 693 {
 694         unsigned long flags;
 695
 696         spin_lock_irqsave(&spi->lock, flags);
 697
 698         spi->tx = t->tx_buf;
 699         spi->rx = t->rx_buf;
 700
 701         if (t->tx_buf) {
 702                 spi->tx_todo = t->len;
 703
 704                 /* initially fill TX FIFO */
 705                 tx_fifo_write(spi);
 706         }
 707
 708         if (spi->rx) {
 709                 spi->rx_todo = t->len;
 710
 711                 /* start shift clock in RX-only mode */
 712                 if (!spi->tx)
 713                         rx_request(spi);
 714         }
 715
 716         spin_unlock_irqrestore(&spi->lock, flags);
 717
 718         return t->len;
 719 }
 720
 721 /*
 722  * The driver only gets an interrupt when the FIFO is empty, but there
 723  * is an additional shift register from which the data is written to
 724  * the wire. We get the last interrupt when the controller starts to
 725  * write the last word to the wire, not when it is finished. Do busy
 726  * waiting till it finishes.
 727  */
 728 static void lantiq_ssc_bussy_work(struct work_struct *work)
 729 {
 730         struct lantiq_ssc_spi *spi;
 731         unsigned long long timeout = 8LL * 1000LL;
 732         unsigned long end;
 733
 734         spi = container_of(work, typeof(*spi), work);
 735
 736         do_div(timeout, spi->speed_hz);
 737         timeout += timeout + 100; /* some tolerance */
 738
 739         end = jiffies + msecs_to_jiffies(timeout);
 740         do {
 741                 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
 742
 743                 if (!(stat & LTQ_SPI_STAT_BSY)) {
 744                         spi_finalize_current_transfer(spi->master);
 745                         return;
 746                 }
 747
 748                 cond_resched();
 749         } while (!time_after_eq(jiffies, end));
 750
 751         if (spi->master->cur_msg)
 752                 spi->master->cur_msg->status = -EIO;
 753         spi_finalize_current_transfer(spi->master);
 754 }
 755
 756 static void lantiq_ssc_handle_err(struct spi_master *master,
 757                                   struct spi_message *message)
 758 {
 759         struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 760
 761         /* flush FIFOs on timeout */
 762         rx_fifo_flush(spi);
 763         tx_fifo_flush(spi);
 764 }
 765
 766 static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable)
 767 {
 768         struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);
 769         unsigned int cs = spidev->chip_select;
 770         u32 fgpo;
 771
 772         if (!!(spidev->mode & SPI_CS_HIGH) == enable)
 773                 fgpo = (1 << (cs - spi->base_cs));
 774         else
 775                 fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S));
 776
 777         lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO);
 778 }
 779
 780 static int lantiq_ssc_transfer_one(struct spi_master *master,
 781                                    struct spi_device *spidev,
 782                                    struct spi_transfer *t)
 783 {
 784         struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 785
 786         hw_setup_transfer(spi, spidev, t);
 787
 788         return transfer_start(spi, spidev, t);
 789 }
 790
 791 static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
 792         .irnen_r = LTQ_SPI_IRNEN_R_XWAY,
 793         .irnen_t = LTQ_SPI_IRNEN_T_XWAY,
 794 };
 795
 796 static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
 797         .irnen_r = LTQ_SPI_IRNEN_R_XRX,
 798         .irnen_t = LTQ_SPI_IRNEN_T_XRX,
 799 };
 800
 801 static const struct of_device_id lantiq_ssc_match[] = {
 802         { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
 803         { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
 804         { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
 805         {},
 806 };
 807 MODULE_DEVICE_TABLE(of, lantiq_ssc_match);
 808
 809 static int lantiq_ssc_probe(struct platform_device *pdev)
 810 {
 811         struct device *dev = &pdev->dev;
 812         struct spi_master *master;
 813         struct resource *res;
 814         struct lantiq_ssc_spi *spi;
 815         const struct lantiq_ssc_hwcfg *hwcfg;
 816         const struct of_device_id *match;
 817         int err, rx_irq, tx_irq, err_irq;
 818         u32 id, supports_dma, revision;
 819         unsigned int num_cs;
 820
 821         match = of_match_device(lantiq_ssc_match, dev);
 822         if (!match) {
 823                 dev_err(dev, "no device match\n");
 824                 return -EINVAL;
 825         }
 826         hwcfg = match->data;
 827
 828         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 829         if (!res) {
 830                 dev_err(dev, "failed to get resources\n");
 831                 return -ENXIO;
 832         }
 833
 834         rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME);
 835         if (rx_irq < 0) {
 836                 dev_err(dev, "failed to get %s\n", LTQ_SPI_RX_IRQ_NAME);
 837                 return -ENXIO;
 838         }
 839
 840         tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME);
 841         if (tx_irq < 0) {
 842                 dev_err(dev, "failed to get %s\n", LTQ_SPI_TX_IRQ_NAME);
 843                 return -ENXIO;
 844         }
 845
 846         err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME);
 847         if (err_irq < 0) {
 848                 dev_err(dev, "failed to get %s\n", LTQ_SPI_ERR_IRQ_NAME);
 849                 return -ENXIO;
 850         }
 851
 852         master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi));
 853         if (!master)
 854                 return -ENOMEM;
 855
 856         spi = spi_master_get_devdata(master);
 857         spi->master = master;
 858         spi->dev = dev;
 859         spi->hwcfg = hwcfg;
 860         platform_set_drvdata(pdev, spi);
 861
 862         spi->regbase = devm_ioremap_resource(dev, res);
 863         if (IS_ERR(spi->regbase)) {
 864                 err = PTR_ERR(spi->regbase);
 865                 goto err_master_put;
 866         }
 867
 868         err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt,
 869                                0, LTQ_SPI_RX_IRQ_NAME, spi);
 870         if (err)
 871                 goto err_master_put;
 872
 873         err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt,
 874                                0, LTQ_SPI_TX_IRQ_NAME, spi);
 875         if (err)
 876                 goto err_master_put;
 877
 878         err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt,
 879                                0, LTQ_SPI_ERR_IRQ_NAME, spi);
 880         if (err)
 881                 goto err_master_put;
 882
 883         spi->spi_clk = devm_clk_get(dev, "gate");
 884         if (IS_ERR(spi->spi_clk)) {
 885                 err = PTR_ERR(spi->spi_clk);
 886                 goto err_master_put;
 887         }
 888         err = clk_prepare_enable(spi->spi_clk);
 889         if (err)
 890                 goto err_master_put;
 891
 892         /*
 893          * Use the old clk_get_fpi() function on Lantiq platform, till it
 894          * supports common clk.
 895          */
 896 #if defined(CONFIG_LANTIQ) && !defined(CONFIG_COMMON_CLK)
 897         spi->fpi_clk = clk_get_fpi();
 898 #else
 899         spi->fpi_clk = clk_get(dev, "freq");
 900 #endif
 901         if (IS_ERR(spi->fpi_clk)) {
 902                 err = PTR_ERR(spi->fpi_clk);
 903                 goto err_clk_disable;
 904         }
 905
 906         num_cs = 8;
 907         of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
 908
 909         spi->base_cs = 1;
 910         of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs);
 911
 912         spin_lock_init(&spi->lock);
 913         spi->bits_per_word = 8;
 914         spi->speed_hz = 0;
 915
 916         master->dev.of_node = pdev->dev.of_node;
 917         master->num_chipselect = num_cs;
 918         master->setup = lantiq_ssc_setup;
 919         master->set_cs = lantiq_ssc_set_cs;
 920         master->handle_err = lantiq_ssc_handle_err;
 921         master->prepare_message = lantiq_ssc_prepare_message;
 922         master->unprepare_message = lantiq_ssc_unprepare_message;
 923         master->transfer_one = lantiq_ssc_transfer_one;
 924         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH |
 925                                 SPI_LOOP;
 926         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) |
 927                                      SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
 928
 929         spi->wq = alloc_ordered_workqueue(dev_name(dev), 0);
 930         if (!spi->wq) {
 931                 err = -ENOMEM;
 932                 goto err_clk_put;
 933         }
 934         INIT_WORK(&spi->work, lantiq_ssc_bussy_work);
 935
 936         id = lantiq_ssc_readl(spi, LTQ_SPI_ID);
 937         spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S;
 938         spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S;
 939         supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S;
 940         revision = id & LTQ_SPI_ID_REV_M;
 941
 942         lantiq_ssc_hw_init(spi);
 943
 944         dev_info(dev,
 945                 "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n",
 946                 revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);
 947
 948         err = devm_spi_register_master(dev, master);
 949         if (err) {
 950                 dev_err(dev, "failed to register spi_master\n");
 951                 goto err_wq_destroy;
 952         }
 953
 954         return 0;
 955
 956 err_wq_destroy:
 957         destroy_workqueue(spi->wq);
 958 err_clk_put:
 959         clk_put(spi->fpi_clk);
 960 err_clk_disable:
 961         clk_disable_unprepare(spi->spi_clk);
 962 err_master_put:
 963         spi_master_put(master);
 964
 965         return err;
 966 }
 967
 968 static int lantiq_ssc_remove(struct platform_device *pdev)
 969 {
 970         struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);
 971
 972         lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN);
 973         lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC);
 974         rx_fifo_flush(spi);
 975         tx_fifo_flush(spi);
 976         hw_enter_config_mode(spi);
 977
 978         destroy_workqueue(spi->wq);
 979         clk_disable_unprepare(spi->spi_clk);
 980         clk_put(spi->fpi_clk);
 981
 982         return 0;
 983 }
 984
 985 static struct platform_driver lantiq_ssc_driver = {
 986         .probe = lantiq_ssc_probe,
 987         .remove = lantiq_ssc_remove,
 988         .driver = {
 989                 .name = "spi-lantiq-ssc",
 990                 .of_match_table = lantiq_ssc_match,
 991         },
 992 };
 993 module_platform_driver(lantiq_ssc_driver);
 994
 995 MODULE_DESCRIPTION("Lantiq SSC SPI controller driver");
 996 MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@gmail.com>");
 997 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
 998 MODULE_LICENSE("GPL");
 999 MODULE_ALIAS("platform:spi-lantiq-ssc");