drivers/spi/spi-omap2-mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/device.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/dmaengine.h>
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/err.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/slab.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/gcd.h>
  36
  37 #include <linux/spi/spi.h>
  38 #include <linux/gpio.h>
  39
  40 #include <linux/platform_data/spi-omap2-mcspi.h>
  41
  42 #define OMAP2_MCSPI_MAX_FREQ            48000000
  43 #define OMAP2_MCSPI_MAX_DIVIDER         4096
  44 #define OMAP2_MCSPI_MAX_FIFODEPTH       64
  45 #define OMAP2_MCSPI_MAX_FIFOWCNT        0xFFFF
  46 #define SPI_AUTOSUSPEND_TIMEOUT         2000
  47
  48 #define OMAP2_MCSPI_REVISION            0x00
  49 #define OMAP2_MCSPI_SYSSTATUS           0x14
  50 #define OMAP2_MCSPI_IRQSTATUS           0x18
  51 #define OMAP2_MCSPI_IRQENABLE           0x1c
  52 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  53 #define OMAP2_MCSPI_SYST                0x24
  54 #define OMAP2_MCSPI_MODULCTRL           0x28
  55 #define OMAP2_MCSPI_XFERLEVEL           0x7c
  56
  57 /* per-channel banks, 0x14 bytes each, first is: */
  58 #define OMAP2_MCSPI_CHCONF0             0x2c
  59 #define OMAP2_MCSPI_CHSTAT0             0x30
  60 #define OMAP2_MCSPI_CHCTRL0             0x34
  61 #define OMAP2_MCSPI_TX0                 0x38
  62 #define OMAP2_MCSPI_RX0                 0x3c
  63
  64 /* per-register bitmasks: */
  65 #define OMAP2_MCSPI_IRQSTATUS_EOW       BIT(17)
  66
  67 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  68 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  69 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  70
  71 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  72 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  74 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  75 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  78 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  79 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  80 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  81 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  82 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  83 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  84 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  85 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  86 #define OMAP2_MCSPI_CHCONF_FFET         BIT(27)
  87 #define OMAP2_MCSPI_CHCONF_FFER         BIT(28)
  88 #define OMAP2_MCSPI_CHCONF_CLKG         BIT(29)
  89
  90 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  91 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  92 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  93 #define OMAP2_MCSPI_CHSTAT_TXFFE        BIT(3)
  94
  95 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  96 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK  (0xff << 8)
  97
  98 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
  99
 100 /* We have 2 DMA channels per CS, one for RX and one for TX */
 101 struct omap2_mcspi_dma {
 102         struct dma_chan *dma_tx;
 103         struct dma_chan *dma_rx;
 104
 105         int dma_tx_sync_dev;
 106         int dma_rx_sync_dev;
 107
 108         struct completion dma_tx_completion;
 109         struct completion dma_rx_completion;
 110
 111         char dma_rx_ch_name[14];
 112         char dma_tx_ch_name[14];
 113 };
 114
 115 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 116  * cache operations; better heuristics consider wordsize and bitrate.
 117  */
 118 #define DMA_MIN_BYTES                   160
 119
 120
 121 /*
 122  * Used for context save and restore, structure members to be updated whenever
 123  * corresponding registers are modified.
 124  */
 125 struct omap2_mcspi_regs {
 126         u32 modulctrl;
 127         u32 wakeupenable;
 128         struct list_head cs;
 129 };
 130
 131 struct omap2_mcspi {
 132         struct spi_master       *master;
 133         /* Virtual base address of the controller */
 134         void __iomem            *base;
 135         unsigned long           phys;
 136         /* SPI1 has 4 channels, while SPI2 has 2 */
 137         struct omap2_mcspi_dma  *dma_channels;
 138         struct device           *dev;
 139         struct omap2_mcspi_regs ctx;
 140         int                     fifo_depth;
 141         unsigned int            pin_dir:1;
 142 };
 143
 144 struct omap2_mcspi_cs {
 145         void __iomem            *base;
 146         unsigned long           phys;
 147         int                     word_len;
 148         u16                     mode;
 149         struct list_head        node;
 150         /* Context save and restore shadow register */
 151         u32                     chconf0, chctrl0;
 152 };
 153
 154 static inline void mcspi_write_reg(struct spi_master *master,
 155                 int idx, u32 val)
 156 {
 157         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 158
 159         writel_relaxed(val, mcspi->base + idx);
 160 }
 161
 162 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 163 {
 164         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 165
 166         return readl_relaxed(mcspi->base + idx);
 167 }
 168
 169 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 170                 int idx, u32 val)
 171 {
 172         struct omap2_mcspi_cs   *cs = spi->controller_state;
 173
 174         writel_relaxed(val, cs->base +  idx);
 175 }
 176
 177 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 178 {
 179         struct omap2_mcspi_cs   *cs = spi->controller_state;
 180
 181         return readl_relaxed(cs->base + idx);
 182 }
 183
 184 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 185 {
 186         struct omap2_mcspi_cs *cs = spi->controller_state;
 187
 188         return cs->chconf0;
 189 }
 190
 191 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 192 {
 193         struct omap2_mcspi_cs *cs = spi->controller_state;
 194
 195         cs->chconf0 = val;
 196         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 197         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 198 }
 199
 200 static inline int mcspi_bytes_per_word(int word_len)
 201 {
 202         if (word_len <= 8)
 203                 return 1;
 204         else if (word_len <= 16)
 205                 return 2;
 206         else /* word_len <= 32 */
 207                 return 4;
 208 }
 209
 210 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 211                 int is_read, int enable)
 212 {
 213         u32 l, rw;
 214
 215         l = mcspi_cached_chconf0(spi);
 216
 217         if (is_read) /* 1 is read, 0 write */
 218                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 219         else
 220                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 221
 222         if (enable)
 223                 l |= rw;
 224         else
 225                 l &= ~rw;
 226
 227         mcspi_write_chconf0(spi, l);
 228 }
 229
 230 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 231 {
 232         struct omap2_mcspi_cs *cs = spi->controller_state;
 233         u32 l;
 234
 235         l = cs->chctrl0;
 236         if (enable)
 237                 l |= OMAP2_MCSPI_CHCTRL_EN;
 238         else
 239                 l &= ~OMAP2_MCSPI_CHCTRL_EN;
 240         cs->chctrl0 = l;
 241         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
 242         /* Flash post-writes */
 243         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 244 }
 245
 246 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
 247 {
 248         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 249         u32 l;
 250
 251         /* The controller handles the inverted chip selects
 252          * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
 253          * the inversion from the core spi_set_cs function.
 254          */
 255         if (spi->mode & SPI_CS_HIGH)
 256                 enable = !enable;
 257
 258         if (spi->controller_state) {
 259                 int err = pm_runtime_get_sync(mcspi->dev);
 260                 if (err < 0) {
 261                         dev_err(mcspi->dev, "failed to get sync: %d\n", err);
 262                         return;
 263                 }
 264
 265                 l = mcspi_cached_chconf0(spi);
 266
 267                 if (enable)
 268                         l &= ~OMAP2_MCSPI_CHCONF_FORCE;
 269                 else
 270                         l |= OMAP2_MCSPI_CHCONF_FORCE;
 271
 272                 mcspi_write_chconf0(spi, l);
 273
 274                 pm_runtime_mark_last_busy(mcspi->dev);
 275                 pm_runtime_put_autosuspend(mcspi->dev);
 276         }
 277 }
 278
 279 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 280 {
 281         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
 282         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 283         u32 l;
 284
 285         /*
 286          * Setup when switching from (reset default) slave mode
 287          * to single-channel master mode
 288          */
 289         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 290         l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
 291         l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
 292         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 293
 294         ctx->modulctrl = l;
 295 }
 296
 297 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
 298                                 struct spi_transfer *t, int enable)
 299 {
 300         struct spi_master *master = spi->master;
 301         struct omap2_mcspi_cs *cs = spi->controller_state;
 302         struct omap2_mcspi *mcspi;
 303         unsigned int wcnt;
 304         int max_fifo_depth, bytes_per_word;
 305         u32 chconf, xferlevel;
 306
 307         mcspi = spi_master_get_devdata(master);
 308
 309         chconf = mcspi_cached_chconf0(spi);
 310         if (enable) {
 311                 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
 312                 if (t->len % bytes_per_word != 0)
 313                         goto disable_fifo;
 314
 315                 if (t->rx_buf != NULL && t->tx_buf != NULL)
 316                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
 317                 else
 318                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
 319
 320                 wcnt = t->len / bytes_per_word;
 321                 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
 322                         goto disable_fifo;
 323
 324                 xferlevel = wcnt << 16;
 325                 if (t->rx_buf != NULL) {
 326                         chconf |= OMAP2_MCSPI_CHCONF_FFER;
 327                         xferlevel |= (bytes_per_word - 1) << 8;
 328                 }
 329
 330                 if (t->tx_buf != NULL) {
 331                         chconf |= OMAP2_MCSPI_CHCONF_FFET;
 332                         xferlevel |= bytes_per_word - 1;
 333                 }
 334
 335                 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
 336                 mcspi_write_chconf0(spi, chconf);
 337                 mcspi->fifo_depth = max_fifo_depth;
 338
 339                 return;
 340         }
 341
 342 disable_fifo:
 343         if (t->rx_buf != NULL)
 344                 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
 345
 346         if (t->tx_buf != NULL)
 347                 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
 348
 349         mcspi_write_chconf0(spi, chconf);
 350         mcspi->fifo_depth = 0;
 351 }
 352
 353 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 354 {
 355         struct spi_master       *spi_cntrl = mcspi->master;
 356         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 357         struct omap2_mcspi_cs   *cs;
 358
 359         /* McSPI: context restore */
 360         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
 361         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
 362
 363         list_for_each_entry(cs, &ctx->cs, node)
 364                 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 365 }
 366
 367 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 368 {
 369         unsigned long timeout;
 370
 371         timeout = jiffies + msecs_to_jiffies(1000);
 372         while (!(readl_relaxed(reg) & bit)) {
 373                 if (time_after(jiffies, timeout)) {
 374                         if (!(readl_relaxed(reg) & bit))
 375                                 return -ETIMEDOUT;
 376                         else
 377                                 return 0;
 378                 }
 379                 cpu_relax();
 380         }
 381         return 0;
 382 }
 383
 384 static void omap2_mcspi_rx_callback(void *data)
 385 {
 386         struct spi_device *spi = data;
 387         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 388         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 389
 390         /* We must disable the DMA RX request */
 391         omap2_mcspi_set_dma_req(spi, 1, 0);
 392
 393         complete(&mcspi_dma->dma_rx_completion);
 394 }
 395
 396 static void omap2_mcspi_tx_callback(void *data)
 397 {
 398         struct spi_device *spi = data;
 399         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 400         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 401
 402         /* We must disable the DMA TX request */
 403         omap2_mcspi_set_dma_req(spi, 0, 0);
 404
 405         complete(&mcspi_dma->dma_tx_completion);
 406 }
 407
 408 static void omap2_mcspi_tx_dma(struct spi_device *spi,
 409                                 struct spi_transfer *xfer,
 410                                 struct dma_slave_config cfg)
 411 {
 412         struct omap2_mcspi      *mcspi;
 413         struct omap2_mcspi_dma  *mcspi_dma;
 414         unsigned int            count;
 415
 416         mcspi = spi_master_get_devdata(spi->master);
 417         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 418         count = xfer->len;
 419
 420         if (mcspi_dma->dma_tx) {
 421                 struct dma_async_tx_descriptor *tx;
 422                 struct scatterlist sg;
 423
 424                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
 425
 426                 sg_init_table(&sg, 1);
 427                 sg_dma_address(&sg) = xfer->tx_dma;
 428                 sg_dma_len(&sg) = xfer->len;
 429
 430                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
 431                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 432                 if (tx) {
 433                         tx->callback = omap2_mcspi_tx_callback;
 434                         tx->callback_param = spi;
 435                         dmaengine_submit(tx);
 436                 } else {
 437                         /* FIXME: fall back to PIO? */
 438                 }
 439         }
 440         dma_async_issue_pending(mcspi_dma->dma_tx);
 441         omap2_mcspi_set_dma_req(spi, 0, 1);
 442
 443 }
 444
 445 static unsigned
 446 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
 447                                 struct dma_slave_config cfg,
 448                                 unsigned es)
 449 {
 450         struct omap2_mcspi      *mcspi;
 451         struct omap2_mcspi_dma  *mcspi_dma;
 452         unsigned int            count, dma_count;
 453         u32                     l;
 454         int                     elements = 0;
 455         int                     word_len, element_count;
 456         struct omap2_mcspi_cs   *cs = spi->controller_state;
 457         void __iomem            *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 458
 459         mcspi = spi_master_get_devdata(spi->master);
 460         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 461         count = xfer->len;
 462         dma_count = xfer->len;
 463
 464         if (mcspi->fifo_depth == 0)
 465                 dma_count -= es;
 466
 467         word_len = cs->word_len;
 468         l = mcspi_cached_chconf0(spi);
 469
 470         if (word_len <= 8)
 471                 element_count = count;
 472         else if (word_len <= 16)
 473                 element_count = count >> 1;
 474         else /* word_len <= 32 */
 475                 element_count = count >> 2;
 476
 477         if (mcspi_dma->dma_rx) {
 478                 struct dma_async_tx_descriptor *tx;
 479                 struct scatterlist sg;
 480
 481                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
 482
 483                 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
 484                         dma_count -= es;
 485
 486                 sg_init_table(&sg, 1);
 487                 sg_dma_address(&sg) = xfer->rx_dma;
 488                 sg_dma_len(&sg) = dma_count;
 489
 490                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
 491                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
 492                                 DMA_CTRL_ACK);
 493                 if (tx) {
 494                         tx->callback = omap2_mcspi_rx_callback;
 495                         tx->callback_param = spi;
 496                         dmaengine_submit(tx);
 497                 } else {
 498                                 /* FIXME: fall back to PIO? */
 499                 }
 500         }
 501
 502         dma_async_issue_pending(mcspi_dma->dma_rx);
 503         omap2_mcspi_set_dma_req(spi, 1, 1);
 504
 505         wait_for_completion(&mcspi_dma->dma_rx_completion);
 506         dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
 507                          DMA_FROM_DEVICE);
 508
 509         if (mcspi->fifo_depth > 0)
 510                 return count;
 511
 512         omap2_mcspi_set_enable(spi, 0);
 513
 514         elements = element_count - 1;
 515
 516         if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 517                 elements--;
 518
 519                 if (!mcspi_wait_for_reg_bit(chstat_reg,
 520                                             OMAP2_MCSPI_CHSTAT_RXS)) {
 521                         u32 w;
 522
 523                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 524                         if (word_len <= 8)
 525                                 ((u8 *)xfer->rx_buf)[elements++] = w;
 526                         else if (word_len <= 16)
 527                                 ((u16 *)xfer->rx_buf)[elements++] = w;
 528                         else /* word_len <= 32 */
 529                                 ((u32 *)xfer->rx_buf)[elements++] = w;
 530                 } else {
 531                         int bytes_per_word = mcspi_bytes_per_word(word_len);
 532                         dev_err(&spi->dev, "DMA RX penultimate word empty\n");
 533                         count -= (bytes_per_word << 1);
 534                         omap2_mcspi_set_enable(spi, 1);
 535                         return count;
 536                 }
 537         }
 538         if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
 539                 u32 w;
 540
 541                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 542                 if (word_len <= 8)
 543                         ((u8 *)xfer->rx_buf)[elements] = w;
 544                 else if (word_len <= 16)
 545                         ((u16 *)xfer->rx_buf)[elements] = w;
 546                 else /* word_len <= 32 */
 547                         ((u32 *)xfer->rx_buf)[elements] = w;
 548         } else {
 549                 dev_err(&spi->dev, "DMA RX last word empty\n");
 550                 count -= mcspi_bytes_per_word(word_len);
 551         }
 552         omap2_mcspi_set_enable(spi, 1);
 553         return count;
 554 }
 555
 556 static unsigned
 557 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 558 {
 559         struct omap2_mcspi      *mcspi;
 560         struct omap2_mcspi_cs   *cs = spi->controller_state;
 561         struct omap2_mcspi_dma  *mcspi_dma;
 562         unsigned int            count;
 563         u32                     l;
 564         u8                      *rx;
 565         const u8                *tx;
 566         struct dma_slave_config cfg;
 567         enum dma_slave_buswidth width;
 568         unsigned es;
 569         void __iomem            *chstat_reg;
 570         void __iomem            *irqstat_reg;
 571         int                     wait_res;
 572
 573         mcspi = spi_master_get_devdata(spi->master);
 574         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 575         l = mcspi_cached_chconf0(spi);
 576
 577
 578         if (cs->word_len <= 8) {
 579                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 580                 es = 1;
 581         } else if (cs->word_len <= 16) {
 582                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 583                 es = 2;
 584         } else {
 585                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 586                 es = 4;
 587         }
 588
 589         count = xfer->len;
 590
 591         memset(&cfg, 0, sizeof(cfg));
 592         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
 593         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
 594         cfg.src_addr_width = width;
 595         cfg.dst_addr_width = width;
 596         cfg.src_maxburst = 1;
 597         cfg.dst_maxburst = 1;
 598
 599         rx = xfer->rx_buf;
 600         tx = xfer->tx_buf;
 601
 602         if (tx != NULL)
 603                 omap2_mcspi_tx_dma(spi, xfer, cfg);
 604
 605         if (rx != NULL)
 606                 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 607
 608         if (tx != NULL) {
 609                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 610                 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
 611                                  DMA_TO_DEVICE);
 612
 613                 if (mcspi->fifo_depth > 0) {
 614                         irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
 615
 616                         if (mcspi_wait_for_reg_bit(irqstat_reg,
 617                                                 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
 618                                 dev_err(&spi->dev, "EOW timed out\n");
 619
 620                         mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
 621                                         OMAP2_MCSPI_IRQSTATUS_EOW);
 622                 }
 623
 624                 /* for TX_ONLY mode, be sure all words have shifted out */
 625                 if (rx == NULL) {
 626                         chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 627                         if (mcspi->fifo_depth > 0) {
 628                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 629                                                 OMAP2_MCSPI_CHSTAT_TXFFE);
 630                                 if (wait_res < 0)
 631                                         dev_err(&spi->dev, "TXFFE timed out\n");
 632                         } else {
 633                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 634                                                 OMAP2_MCSPI_CHSTAT_TXS);
 635                                 if (wait_res < 0)
 636                                         dev_err(&spi->dev, "TXS timed out\n");
 637                         }
 638                         if (wait_res >= 0 &&
 639                                 (mcspi_wait_for_reg_bit(chstat_reg,
 640                                         OMAP2_MCSPI_CHSTAT_EOT) < 0))
 641                                 dev_err(&spi->dev, "EOT timed out\n");
 642                 }
 643         }
 644         return count;
 645 }
 646
 647 static unsigned
 648 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 649 {
 650         struct omap2_mcspi      *mcspi;
 651         struct omap2_mcspi_cs   *cs = spi->controller_state;
 652         unsigned int            count, c;
 653         u32                     l;
 654         void __iomem            *base = cs->base;
 655         void __iomem            *tx_reg;
 656         void __iomem            *rx_reg;
 657         void __iomem            *chstat_reg;
 658         int                     word_len;
 659
 660         mcspi = spi_master_get_devdata(spi->master);
 661         count = xfer->len;
 662         c = count;
 663         word_len = cs->word_len;
 664
 665         l = mcspi_cached_chconf0(spi);
 666
 667         /* We store the pre-calculated register addresses on stack to speed
 668          * up the transfer loop. */
 669         tx_reg          = base + OMAP2_MCSPI_TX0;
 670         rx_reg          = base + OMAP2_MCSPI_RX0;
 671         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 672
 673         if (c < (word_len>>3))
 674                 return 0;
 675
 676         if (word_len <= 8) {
 677                 u8              *rx;
 678                 const u8        *tx;
 679
 680                 rx = xfer->rx_buf;
 681                 tx = xfer->tx_buf;
 682
 683                 do {
 684                         c -= 1;
 685                         if (tx != NULL) {
 686                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 687                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 688                                         dev_err(&spi->dev, "TXS timed out\n");
 689                                         goto out;
 690                                 }
 691                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
 692                                                 word_len, *tx);
 693                                 writel_relaxed(*tx++, tx_reg);
 694                         }
 695                         if (rx != NULL) {
 696                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 697                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 698                                         dev_err(&spi->dev, "RXS timed out\n");
 699                                         goto out;
 700                                 }
 701
 702                                 if (c == 1 && tx == NULL &&
 703                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 704                                         omap2_mcspi_set_enable(spi, 0);
 705                                         *rx++ = readl_relaxed(rx_reg);
 706                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
 707                                                     word_len, *(rx - 1));
 708                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 709                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 710                                                 dev_err(&spi->dev,
 711                                                         "RXS timed out\n");
 712                                                 goto out;
 713                                         }
 714                                         c = 0;
 715                                 } else if (c == 0 && tx == NULL) {
 716                                         omap2_mcspi_set_enable(spi, 0);
 717                                 }
 718
 719                                 *rx++ = readl_relaxed(rx_reg);
 720                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
 721                                                 word_len, *(rx - 1));
 722                         }
 723                 } while (c);
 724         } else if (word_len <= 16) {
 725                 u16             *rx;
 726                 const u16       *tx;
 727
 728                 rx = xfer->rx_buf;
 729                 tx = xfer->tx_buf;
 730                 do {
 731                         c -= 2;
 732                         if (tx != NULL) {
 733                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 734                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 735                                         dev_err(&spi->dev, "TXS timed out\n");
 736                                         goto out;
 737                                 }
 738                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
 739                                                 word_len, *tx);
 740                                 writel_relaxed(*tx++, tx_reg);
 741                         }
 742                         if (rx != NULL) {
 743                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 744                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 745                                         dev_err(&spi->dev, "RXS timed out\n");
 746                                         goto out;
 747                                 }
 748
 749                                 if (c == 2 && tx == NULL &&
 750                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 751                                         omap2_mcspi_set_enable(spi, 0);
 752                                         *rx++ = readl_relaxed(rx_reg);
 753                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
 754                                                     word_len, *(rx - 1));
 755                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 756                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 757                                                 dev_err(&spi->dev,
 758                                                         "RXS timed out\n");
 759                                                 goto out;
 760                                         }
 761                                         c = 0;
 762                                 } else if (c == 0 && tx == NULL) {
 763                                         omap2_mcspi_set_enable(spi, 0);
 764                                 }
 765
 766                                 *rx++ = readl_relaxed(rx_reg);
 767                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
 768                                                 word_len, *(rx - 1));
 769                         }
 770                 } while (c >= 2);
 771         } else if (word_len <= 32) {
 772                 u32             *rx;
 773                 const u32       *tx;
 774
 775                 rx = xfer->rx_buf;
 776                 tx = xfer->tx_buf;
 777                 do {
 778                         c -= 4;
 779                         if (tx != NULL) {
 780                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 781                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 782                                         dev_err(&spi->dev, "TXS timed out\n");
 783                                         goto out;
 784                                 }
 785                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
 786                                                 word_len, *tx);
 787                                 writel_relaxed(*tx++, tx_reg);
 788                         }
 789                         if (rx != NULL) {
 790                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 791                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 792                                         dev_err(&spi->dev, "RXS timed out\n");
 793                                         goto out;
 794                                 }
 795
 796                                 if (c == 4 && tx == NULL &&
 797                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 798                                         omap2_mcspi_set_enable(spi, 0);
 799                                         *rx++ = readl_relaxed(rx_reg);
 800                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
 801                                                     word_len, *(rx - 1));
 802                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 803                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 804                                                 dev_err(&spi->dev,
 805                                                         "RXS timed out\n");
 806                                                 goto out;
 807                                         }
 808                                         c = 0;
 809                                 } else if (c == 0 && tx == NULL) {
 810                                         omap2_mcspi_set_enable(spi, 0);
 811                                 }
 812
 813                                 *rx++ = readl_relaxed(rx_reg);
 814                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
 815                                                 word_len, *(rx - 1));
 816                         }
 817                 } while (c >= 4);
 818         }
 819
 820         /* for TX_ONLY mode, be sure all words have shifted out */
 821         if (xfer->rx_buf == NULL) {
 822                 if (mcspi_wait_for_reg_bit(chstat_reg,
 823                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 824                         dev_err(&spi->dev, "TXS timed out\n");
 825                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 826                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 827                         dev_err(&spi->dev, "EOT timed out\n");
 828
 829                 /* disable chan to purge rx datas received in TX_ONLY transfer,
 830                  * otherwise these rx datas will affect the direct following
 831                  * RX_ONLY transfer.
 832                  */
 833                 omap2_mcspi_set_enable(spi, 0);
 834         }
 835 out:
 836         omap2_mcspi_set_enable(spi, 1);
 837         return count - c;
 838 }
 839
 840 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
 841 {
 842         u32 div;
 843
 844         for (div = 0; div < 15; div++)
 845                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
 846                         return div;
 847
 848         return 15;
 849 }
 850
 851 /* called only when no transfer is active to this device */
 852 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 853                 struct spi_transfer *t)
 854 {
 855         struct omap2_mcspi_cs *cs = spi->controller_state;
 856         struct omap2_mcspi *mcspi;
 857         struct spi_master *spi_cntrl;
 858         u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
 859         u8 word_len = spi->bits_per_word;
 860         u32 speed_hz = spi->max_speed_hz;
 861
 862         mcspi = spi_master_get_devdata(spi->master);
 863         spi_cntrl = mcspi->master;
 864
 865         if (t != NULL && t->bits_per_word)
 866                 word_len = t->bits_per_word;
 867
 868         cs->word_len = word_len;
 869
 870         if (t && t->speed_hz)
 871                 speed_hz = t->speed_hz;
 872
 873         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
 874         if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
 875                 clkd = omap2_mcspi_calc_divisor(speed_hz);
 876                 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
 877                 clkg = 0;
 878         } else {
 879                 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
 880                 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
 881                 clkd = (div - 1) & 0xf;
 882                 extclk = (div - 1) >> 4;
 883                 clkg = OMAP2_MCSPI_CHCONF_CLKG;
 884         }
 885
 886         l = mcspi_cached_chconf0(spi);
 887
 888         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 889          * REVISIT: this controller could support SPI_3WIRE mode.
 890          */
 891         if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
 892                 l &= ~OMAP2_MCSPI_CHCONF_IS;
 893                 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
 894                 l |= OMAP2_MCSPI_CHCONF_DPE0;
 895         } else {
 896                 l |= OMAP2_MCSPI_CHCONF_IS;
 897                 l |= OMAP2_MCSPI_CHCONF_DPE1;
 898                 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
 899         }
 900
 901         /* wordlength */
 902         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 903         l |= (word_len - 1) << 7;
 904
 905         /* set chipselect polarity; manage with FORCE */
 906         if (!(spi->mode & SPI_CS_HIGH))
 907                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 908         else
 909                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 910
 911         /* set clock divisor */
 912         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 913         l |= clkd << 2;
 914
 915         /* set clock granularity */
 916         l &= ~OMAP2_MCSPI_CHCONF_CLKG;
 917         l |= clkg;
 918         if (clkg) {
 919                 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
 920                 cs->chctrl0 |= extclk << 8;
 921                 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
 922         }
 923
 924         /* set SPI mode 0..3 */
 925         if (spi->mode & SPI_CPOL)
 926                 l |= OMAP2_MCSPI_CHCONF_POL;
 927         else
 928                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 929         if (spi->mode & SPI_CPHA)
 930                 l |= OMAP2_MCSPI_CHCONF_PHA;
 931         else
 932                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 933
 934         mcspi_write_chconf0(spi, l);
 935
 936         cs->mode = spi->mode;
 937
 938         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 939                         speed_hz,
 940                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 941                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 942
 943         return 0;
 944 }
 945
 946 /*
 947  * Note that we currently allow DMA only if we get a channel
 948  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
 949  */
 950 static int omap2_mcspi_request_dma(struct spi_device *spi)
 951 {
 952         struct spi_master       *master = spi->master;
 953         struct omap2_mcspi      *mcspi;
 954         struct omap2_mcspi_dma  *mcspi_dma;
 955         dma_cap_mask_t mask;
 956         unsigned sig;
 957
 958         mcspi = spi_master_get_devdata(master);
 959         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 960
 961         init_completion(&mcspi_dma->dma_rx_completion);
 962         init_completion(&mcspi_dma->dma_tx_completion);
 963
 964         dma_cap_zero(mask);
 965         dma_cap_set(DMA_SLAVE, mask);
 966         sig = mcspi_dma->dma_rx_sync_dev;
 967
 968         mcspi_dma->dma_rx =
 969                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
 970                                                  &sig, &master->dev,
 971                                                  mcspi_dma->dma_rx_ch_name);
 972         if (!mcspi_dma->dma_rx)
 973                 goto no_dma;
 974
 975         sig = mcspi_dma->dma_tx_sync_dev;
 976         mcspi_dma->dma_tx =
 977                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
 978                                                  &sig, &master->dev,
 979                                                  mcspi_dma->dma_tx_ch_name);
 980
 981         if (!mcspi_dma->dma_tx) {
 982                 dma_release_channel(mcspi_dma->dma_rx);
 983                 mcspi_dma->dma_rx = NULL;
 984                 goto no_dma;
 985         }
 986
 987         return 0;
 988
 989 no_dma:
 990         dev_warn(&spi->dev, "not using DMA for McSPI\n");
 991         return -EAGAIN;
 992 }
 993
 994 static int omap2_mcspi_setup(struct spi_device *spi)
 995 {
 996         int                     ret;
 997         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
 998         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 999         struct omap2_mcspi_dma  *mcspi_dma;
1000         struct omap2_mcspi_cs   *cs = spi->controller_state;
1001
1002         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1003
1004         if (!cs) {
1005                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1006                 if (!cs)
1007                         return -ENOMEM;
1008                 cs->base = mcspi->base + spi->chip_select * 0x14;
1009                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1010                 cs->mode = 0;
1011                 cs->chconf0 = 0;
1012                 cs->chctrl0 = 0;
1013                 spi->controller_state = cs;
1014                 /* Link this to context save list */
1015                 list_add_tail(&cs->node, &ctx->cs);
1016
1017                 if (gpio_is_valid(spi->cs_gpio)) {
1018                         ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1019                         if (ret) {
1020                                 dev_err(&spi->dev, "failed to request gpio\n");
1021                                 return ret;
1022                         }
1023                         gpio_direction_output(spi->cs_gpio,
1024                                          !(spi->mode & SPI_CS_HIGH));
1025                 }
1026         }
1027
1028         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1029                 ret = omap2_mcspi_request_dma(spi);
1030                 if (ret < 0 && ret != -EAGAIN)
1031                         return ret;
1032         }
1033
1034         ret = pm_runtime_get_sync(mcspi->dev);
1035         if (ret < 0)
1036                 return ret;
1037
1038         ret = omap2_mcspi_setup_transfer(spi, NULL);
1039         pm_runtime_mark_last_busy(mcspi->dev);
1040         pm_runtime_put_autosuspend(mcspi->dev);
1041
1042         return ret;
1043 }
1044
1045 static void omap2_mcspi_cleanup(struct spi_device *spi)
1046 {
1047         struct omap2_mcspi      *mcspi;
1048         struct omap2_mcspi_dma  *mcspi_dma;
1049         struct omap2_mcspi_cs   *cs;
1050
1051         mcspi = spi_master_get_devdata(spi->master);
1052
1053         if (spi->controller_state) {
1054                 /* Unlink controller state from context save list */
1055                 cs = spi->controller_state;
1056                 list_del(&cs->node);
1057
1058                 kfree(cs);
1059         }
1060
1061         if (spi->chip_select < spi->master->num_chipselect) {
1062                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1063
1064                 if (mcspi_dma->dma_rx) {
1065                         dma_release_channel(mcspi_dma->dma_rx);
1066                         mcspi_dma->dma_rx = NULL;
1067                 }
1068                 if (mcspi_dma->dma_tx) {
1069                         dma_release_channel(mcspi_dma->dma_tx);
1070                         mcspi_dma->dma_tx = NULL;
1071                 }
1072         }
1073
1074         if (gpio_is_valid(spi->cs_gpio))
1075                 gpio_free(spi->cs_gpio);
1076 }
1077
1078 static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi,
1079                 struct spi_device *spi, struct spi_transfer *t)
1080 {
1081
1082         /* We only enable one channel at a time -- the one whose message is
1083          * -- although this controller would gladly
1084          * arbitrate among multiple channels.  This corresponds to "single
1085          * channel" master mode.  As a side effect, we need to manage the
1086          * chipselect with the FORCE bit ... CS != channel enable.
1087          */
1088
1089         struct spi_master               *master;
1090         struct omap2_mcspi_dma          *mcspi_dma;
1091         struct omap2_mcspi_cs           *cs;
1092         struct omap2_mcspi_device_config *cd;
1093         int                             par_override = 0;
1094         int                             status = 0;
1095         u32                             chconf;
1096
1097         master = spi->master;
1098         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1099         cs = spi->controller_state;
1100         cd = spi->controller_data;
1101
1102         /*
1103          * The slave driver could have changed spi->mode in which case
1104          * it will be different from cs->mode (the current hardware setup).
1105          * If so, set par_override (even though its not a parity issue) so
1106          * omap2_mcspi_setup_transfer will be called to configure the hardware
1107          * with the correct mode on the first iteration of the loop below.
1108          */
1109         if (spi->mode != cs->mode)
1110                 par_override = 1;
1111
1112         omap2_mcspi_set_enable(spi, 0);
1113
1114         if (gpio_is_valid(spi->cs_gpio))
1115                 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1116
1117         if (par_override ||
1118             (t->speed_hz != spi->max_speed_hz) ||
1119             (t->bits_per_word != spi->bits_per_word)) {
1120                 par_override = 1;
1121                 status = omap2_mcspi_setup_transfer(spi, t);
1122                 if (status < 0)
1123                         goto out;
1124                 if (t->speed_hz == spi->max_speed_hz &&
1125                     t->bits_per_word == spi->bits_per_word)
1126                         par_override = 0;
1127         }
1128         if (cd && cd->cs_per_word) {
1129                 chconf = mcspi->ctx.modulctrl;
1130                 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1131                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1132                 mcspi->ctx.modulctrl =
1133                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1134         }
1135
1136         chconf = mcspi_cached_chconf0(spi);
1137         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1138         chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1139
1140         if (t->tx_buf == NULL)
1141                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1142         else if (t->rx_buf == NULL)
1143                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1144
1145         if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1146                 /* Turbo mode is for more than one word */
1147                 if (t->len > ((cs->word_len + 7) >> 3))
1148                         chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1149         }
1150
1151         mcspi_write_chconf0(spi, chconf);
1152
1153         if (t->len) {
1154                 unsigned        count;
1155
1156                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1157                     (t->len >= DMA_MIN_BYTES))
1158                         omap2_mcspi_set_fifo(spi, t, 1);
1159
1160                 omap2_mcspi_set_enable(spi, 1);
1161
1162                 /* RX_ONLY mode needs dummy data in TX reg */
1163                 if (t->tx_buf == NULL)
1164                         writel_relaxed(0, cs->base
1165                                         + OMAP2_MCSPI_TX0);
1166
1167                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1168                     (t->len >= DMA_MIN_BYTES))
1169                         count = omap2_mcspi_txrx_dma(spi, t);
1170                 else
1171                         count = omap2_mcspi_txrx_pio(spi, t);
1172
1173                 if (count != t->len) {
1174                         status = -EIO;
1175                         goto out;
1176                 }
1177         }
1178
1179         omap2_mcspi_set_enable(spi, 0);
1180
1181         if (mcspi->fifo_depth > 0)
1182                 omap2_mcspi_set_fifo(spi, t, 0);
1183
1184 out:
1185         /* Restore defaults if they were overriden */
1186         if (par_override) {
1187                 par_override = 0;
1188                 status = omap2_mcspi_setup_transfer(spi, NULL);
1189         }
1190
1191         if (cd && cd->cs_per_word) {
1192                 chconf = mcspi->ctx.modulctrl;
1193                 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1194                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1195                 mcspi->ctx.modulctrl =
1196                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1197         }
1198
1199         omap2_mcspi_set_enable(spi, 0);
1200
1201         if (gpio_is_valid(spi->cs_gpio))
1202                 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1203
1204         if (mcspi->fifo_depth > 0 && t)
1205                 omap2_mcspi_set_fifo(spi, t, 0);
1206
1207         return status;
1208 }
1209
1210 static int omap2_mcspi_prepare_message(struct spi_master *master,
1211                                        struct spi_message *msg)
1212 {
1213         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1214         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1215         struct omap2_mcspi_cs   *cs;
1216
1217         /* Only a single channel can have the FORCE bit enabled
1218          * in its chconf0 register.
1219          * Scan all channels and disable them except the current one.
1220          * A FORCE can remain from a last transfer having cs_change enabled
1221          */
1222         list_for_each_entry(cs, &ctx->cs, node) {
1223                 if (msg->spi->controller_state == cs)
1224                         continue;
1225
1226                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1227                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1228                         writel_relaxed(cs->chconf0,
1229                                         cs->base + OMAP2_MCSPI_CHCONF0);
1230                         readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1231                 }
1232         }
1233
1234         return 0;
1235 }
1236
1237 static int omap2_mcspi_transfer_one(struct spi_master *master,
1238                 struct spi_device *spi, struct spi_transfer *t)
1239 {
1240         struct omap2_mcspi      *mcspi;
1241         struct omap2_mcspi_dma  *mcspi_dma;
1242         const void      *tx_buf = t->tx_buf;
1243         void            *rx_buf = t->rx_buf;
1244         unsigned        len = t->len;
1245
1246         mcspi = spi_master_get_devdata(master);
1247         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1248
1249         if ((len && !(rx_buf || tx_buf))) {
1250                 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1251                                 t->speed_hz,
1252                                 len,
1253                                 tx_buf ? "tx" : "",
1254                                 rx_buf ? "rx" : "",
1255                                 t->bits_per_word);
1256                 return -EINVAL;
1257         }
1258
1259         if (len < DMA_MIN_BYTES)
1260                 goto skip_dma_map;
1261
1262         if (mcspi_dma->dma_tx && tx_buf != NULL) {
1263                 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1264                                 len, DMA_TO_DEVICE);
1265                 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1266                         dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1267                                         'T', len);
1268                         return -EINVAL;
1269                 }
1270         }
1271         if (mcspi_dma->dma_rx && rx_buf != NULL) {
1272                 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1273                                 DMA_FROM_DEVICE);
1274                 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1275                         dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1276                                         'R', len);
1277                         if (tx_buf != NULL)
1278                                 dma_unmap_single(mcspi->dev, t->tx_dma,
1279                                                 len, DMA_TO_DEVICE);
1280                         return -EINVAL;
1281                 }
1282         }
1283
1284 skip_dma_map:
1285         return omap2_mcspi_work_one(mcspi, spi, t);
1286 }
1287
1288 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1289 {
1290         struct spi_master       *master = mcspi->master;
1291         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1292         int                     ret = 0;
1293
1294         ret = pm_runtime_get_sync(mcspi->dev);
1295         if (ret < 0)
1296                 return ret;
1297
1298         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1299                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1300         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1301
1302         omap2_mcspi_set_master_mode(master);
1303         pm_runtime_mark_last_busy(mcspi->dev);
1304         pm_runtime_put_autosuspend(mcspi->dev);
1305         return 0;
1306 }
1307
1308 static int omap_mcspi_runtime_resume(struct device *dev)
1309 {
1310         struct omap2_mcspi      *mcspi;
1311         struct spi_master       *master;
1312
1313         master = dev_get_drvdata(dev);
1314         mcspi = spi_master_get_devdata(master);
1315         omap2_mcspi_restore_ctx(mcspi);
1316
1317         return 0;
1318 }
1319
1320 static struct omap2_mcspi_platform_config omap2_pdata = {
1321         .regs_offset = 0,
1322 };
1323
1324 static struct omap2_mcspi_platform_config omap4_pdata = {
1325         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1326 };
1327
1328 static const struct of_device_id omap_mcspi_of_match[] = {
1329         {
1330                 .compatible = "ti,omap2-mcspi",
1331                 .data = &omap2_pdata,
1332         },
1333         {
1334                 .compatible = "ti,omap4-mcspi",
1335                 .data = &omap4_pdata,
1336         },
1337         { },
1338 };
1339 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1340
1341 static int omap2_mcspi_probe(struct platform_device *pdev)
1342 {
1343         struct spi_master       *master;
1344         const struct omap2_mcspi_platform_config *pdata;
1345         struct omap2_mcspi      *mcspi;
1346         struct resource         *r;
1347         int                     status = 0, i;
1348         u32                     regs_offset = 0;
1349         static int              bus_num = 1;
1350         struct device_node      *node = pdev->dev.of_node;
1351         const struct of_device_id *match;
1352
1353         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1354         if (master == NULL) {
1355                 dev_dbg(&pdev->dev, "master allocation failed\n");
1356                 return -ENOMEM;
1357         }
1358
1359         /* the spi->mode bits understood by this driver: */
1360         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1361         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1362         master->setup = omap2_mcspi_setup;
1363         master->auto_runtime_pm = true;
1364         master->prepare_message = omap2_mcspi_prepare_message;
1365         master->transfer_one = omap2_mcspi_transfer_one;
1366         master->set_cs = omap2_mcspi_set_cs;
1367         master->cleanup = omap2_mcspi_cleanup;
1368         master->dev.of_node = node;
1369         master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1370         master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1371
1372         platform_set_drvdata(pdev, master);
1373
1374         mcspi = spi_master_get_devdata(master);
1375         mcspi->master = master;
1376
1377         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1378         if (match) {
1379                 u32 num_cs = 1; /* default number of chipselect */
1380                 pdata = match->data;
1381
1382                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1383                 master->num_chipselect = num_cs;
1384                 master->bus_num = bus_num++;
1385                 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1386                         mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1387         } else {
1388                 pdata = dev_get_platdata(&pdev->dev);
1389                 master->num_chipselect = pdata->num_cs;
1390                 if (pdev->id != -1)
1391                         master->bus_num = pdev->id;
1392                 mcspi->pin_dir = pdata->pin_dir;
1393         }
1394         regs_offset = pdata->regs_offset;
1395
1396         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1397         if (r == NULL) {
1398                 status = -ENODEV;
1399                 goto free_master;
1400         }
1401
1402         r->start += regs_offset;
1403         r->end += regs_offset;
1404         mcspi->phys = r->start;
1405
1406         mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1407         if (IS_ERR(mcspi->base)) {
1408                 status = PTR_ERR(mcspi->base);
1409                 goto free_master;
1410         }
1411
1412         mcspi->dev = &pdev->dev;
1413
1414         INIT_LIST_HEAD(&mcspi->ctx.cs);
1415
1416         mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1417                                            sizeof(struct omap2_mcspi_dma),
1418                                            GFP_KERNEL);
1419         if (mcspi->dma_channels == NULL) {
1420                 status = -ENOMEM;
1421                 goto free_master;
1422         }
1423
1424         for (i = 0; i < master->num_chipselect; i++) {
1425                 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
1426                 char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
1427                 struct resource *dma_res;
1428
1429                 sprintf(dma_rx_ch_name, "rx%d", i);
1430                 if (!pdev->dev.of_node) {
1431                         dma_res =
1432                                 platform_get_resource_byname(pdev,
1433                                                              IORESOURCE_DMA,
1434                                                              dma_rx_ch_name);
1435                         if (!dma_res) {
1436                                 dev_dbg(&pdev->dev,
1437                                         "cannot get DMA RX channel\n");
1438                                 status = -ENODEV;
1439                                 break;
1440                         }
1441
1442                         mcspi->dma_channels[i].dma_rx_sync_dev =
1443                                 dma_res->start;
1444                 }
1445                 sprintf(dma_tx_ch_name, "tx%d", i);
1446                 if (!pdev->dev.of_node) {
1447                         dma_res =
1448                                 platform_get_resource_byname(pdev,
1449                                                              IORESOURCE_DMA,
1450                                                              dma_tx_ch_name);
1451                         if (!dma_res) {
1452                                 dev_dbg(&pdev->dev,
1453                                         "cannot get DMA TX channel\n");
1454                                 status = -ENODEV;
1455                                 break;
1456                         }
1457
1458                         mcspi->dma_channels[i].dma_tx_sync_dev =
1459                                 dma_res->start;
1460                 }
1461         }
1462
1463         if (status < 0)
1464                 goto free_master;
1465
1466         pm_runtime_use_autosuspend(&pdev->dev);
1467         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1468         pm_runtime_enable(&pdev->dev);
1469
1470         status = omap2_mcspi_master_setup(mcspi);
1471         if (status < 0)
1472                 goto disable_pm;
1473
1474         status = devm_spi_register_master(&pdev->dev, master);
1475         if (status < 0)
1476                 goto disable_pm;
1477
1478         return status;
1479
1480 disable_pm:
1481         pm_runtime_disable(&pdev->dev);
1482 free_master:
1483         spi_master_put(master);
1484         return status;
1485 }
1486
1487 static int omap2_mcspi_remove(struct platform_device *pdev)
1488 {
1489         struct spi_master *master = platform_get_drvdata(pdev);
1490         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1491
1492         pm_runtime_put_sync(mcspi->dev);
1493         pm_runtime_disable(&pdev->dev);
1494
1495         return 0;
1496 }
1497
1498 /* work with hotplug and coldplug */
1499 MODULE_ALIAS("platform:omap2_mcspi");
1500
1501 #ifdef  CONFIG_SUSPEND
1502 /*
1503  * When SPI wake up from off-mode, CS is in activate state. If it was in
1504  * unactive state when driver was suspend, then force it to unactive state at
1505  * wake up.
1506  */
1507 static int omap2_mcspi_resume(struct device *dev)
1508 {
1509         struct spi_master       *master = dev_get_drvdata(dev);
1510         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1511         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1512         struct omap2_mcspi_cs   *cs;
1513
1514         pm_runtime_get_sync(mcspi->dev);
1515         list_for_each_entry(cs, &ctx->cs, node) {
1516                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1517                         /*
1518                          * We need to toggle CS state for OMAP take this
1519                          * change in account.
1520                          */
1521                         cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1522                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1523                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1524                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1525                 }
1526         }
1527         pm_runtime_mark_last_busy(mcspi->dev);
1528         pm_runtime_put_autosuspend(mcspi->dev);
1529         return 0;
1530 }
1531 #else
1532 #define omap2_mcspi_resume      NULL
1533 #endif
1534
1535 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1536         .resume = omap2_mcspi_resume,
1537         .runtime_resume = omap_mcspi_runtime_resume,
1538 };
1539
1540 static struct platform_driver omap2_mcspi_driver = {
1541         .driver = {
1542                 .name =         "omap2_mcspi",
1543                 .pm =           &omap2_mcspi_pm_ops,
1544                 .of_match_table = omap_mcspi_of_match,
1545         },
1546         .probe =        omap2_mcspi_probe,
1547         .remove =       omap2_mcspi_remove,
1548 };
1549
1550 module_platform_driver(omap2_mcspi_driver);
1551 MODULE_LICENSE("GPL");