drivers/spi/spi-orion.c

   1 /*
   2  * Marvell Orion SPI controller driver
   3  *
   4  * Author: Shadi Ammouri <shadi@marvell.com>
   5  * Copyright (C) 2007-2008 Marvell Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/interrupt.h>
  13 #include <linux/delay.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/module.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_device.h>
  23 #include <linux/clk.h>
  24 #include <linux/sizes.h>
  25 #include <asm/unaligned.h>
  26
  27 #define DRIVER_NAME                     "orion_spi"
  28
  29 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
  30 #define SPI_AUTOSUSPEND_TIMEOUT         200
  31
  32 /* Some SoCs using this driver support up to 8 chip selects.
  33  * It is up to the implementer to only use the chip selects
  34  * that are available.
  35  */
  36 #define ORION_NUM_CHIPSELECTS           8
  37
  38 #define ORION_SPI_WAIT_RDY_MAX_LOOP     2000 /* in usec */
  39
  40 #define ORION_SPI_IF_CTRL_REG           0x00
  41 #define ORION_SPI_IF_CONFIG_REG         0x04
  42 #define ORION_SPI_DATA_OUT_REG          0x08
  43 #define ORION_SPI_DATA_IN_REG           0x0c
  44 #define ORION_SPI_INT_CAUSE_REG         0x10
  45 #define ORION_SPI_TIMING_PARAMS_REG     0x18
  46
  47 /* Register for the "Direct Mode" */
  48 #define SPI_DIRECT_WRITE_CONFIG_REG     0x20
  49
  50 #define ORION_SPI_TMISO_SAMPLE_MASK     (0x3 << 6)
  51 #define ORION_SPI_TMISO_SAMPLE_1        (1 << 6)
  52 #define ORION_SPI_TMISO_SAMPLE_2        (2 << 6)
  53
  54 #define ORION_SPI_MODE_CPOL             (1 << 11)
  55 #define ORION_SPI_MODE_CPHA             (1 << 12)
  56 #define ORION_SPI_IF_8_16_BIT_MODE      (1 << 5)
  57 #define ORION_SPI_CLK_PRESCALE_MASK     0x1F
  58 #define ARMADA_SPI_CLK_PRESCALE_MASK    0xDF
  59 #define ORION_SPI_MODE_MASK             (ORION_SPI_MODE_CPOL | \
  60                                          ORION_SPI_MODE_CPHA)
  61 #define ORION_SPI_CS_MASK       0x1C
  62 #define ORION_SPI_CS_SHIFT      2
  63 #define ORION_SPI_CS(cs)        ((cs << ORION_SPI_CS_SHIFT) & \
  64                                         ORION_SPI_CS_MASK)
  65
  66 enum orion_spi_type {
  67         ORION_SPI,
  68         ARMADA_SPI,
  69 };
  70
  71 struct orion_spi_dev {
  72         enum orion_spi_type     typ;
  73         /*
  74          * min_divisor and max_hz should be exclusive, the only we can
  75          * have both is for managing the armada-370-spi case with old
  76          * device tree
  77          */
  78         unsigned long           max_hz;
  79         unsigned int            min_divisor;
  80         unsigned int            max_divisor;
  81         u32                     prescale_mask;
  82         bool                    is_errata_50mhz_ac;
  83 };
  84
  85 struct orion_direct_acc {
  86         void __iomem            *vaddr;
  87         u32                     size;
  88 };
  89
  90 struct orion_spi {
  91         struct spi_master       *master;
  92         void __iomem            *base;
  93         struct clk              *clk;
  94         const struct orion_spi_dev *devdata;
  95
  96         struct orion_direct_acc direct_access[ORION_NUM_CHIPSELECTS];
  97 };
  98
  99 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
 100 {
 101         return orion_spi->base + reg;
 102 }
 103
 104 static inline void
 105 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
 106 {
 107         void __iomem *reg_addr = spi_reg(orion_spi, reg);
 108         u32 val;
 109
 110         val = readl(reg_addr);
 111         val |= mask;
 112         writel(val, reg_addr);
 113 }
 114
 115 static inline void
 116 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
 117 {
 118         void __iomem *reg_addr = spi_reg(orion_spi, reg);
 119         u32 val;
 120
 121         val = readl(reg_addr);
 122         val &= ~mask;
 123         writel(val, reg_addr);
 124 }
 125
 126 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
 127 {
 128         u32 tclk_hz;
 129         u32 rate;
 130         u32 prescale;
 131         u32 reg;
 132         struct orion_spi *orion_spi;
 133         const struct orion_spi_dev *devdata;
 134
 135         orion_spi = spi_master_get_devdata(spi->master);
 136         devdata = orion_spi->devdata;
 137
 138         tclk_hz = clk_get_rate(orion_spi->clk);
 139
 140         if (devdata->typ == ARMADA_SPI) {
 141                 /*
 142                  * Given the core_clk (tclk_hz) and the target rate (speed) we
 143                  * determine the best values for SPR (in [0 .. 15]) and SPPR (in
 144                  * [0..7]) such that
 145                  *
 146                  *      core_clk / (SPR * 2 ** SPPR)
 147                  *
 148                  * is as big as possible but not bigger than speed.
 149                  */
 150
 151                 /* best integer divider: */
 152                 unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
 153                 unsigned spr, sppr;
 154
 155                 if (divider < 16) {
 156                         /* This is the easy case, divider is less than 16 */
 157                         spr = divider;
 158                         sppr = 0;
 159
 160                 } else {
 161                         unsigned two_pow_sppr;
 162                         /*
 163                          * Find the highest bit set in divider. This and the
 164                          * three next bits define SPR (apart from rounding).
 165                          * SPPR is then the number of zero bits that must be
 166                          * appended:
 167                          */
 168                         sppr = fls(divider) - 4;
 169
 170                         /*
 171                          * As SPR only has 4 bits, we have to round divider up
 172                          * to the next multiple of 2 ** sppr.
 173                          */
 174                         two_pow_sppr = 1 << sppr;
 175                         divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
 176
 177                         /*
 178                          * recalculate sppr as rounding up divider might have
 179                          * increased it enough to change the position of the
 180                          * highest set bit. In this case the bit that now
 181                          * doesn't make it into SPR is 0, so there is no need to
 182                          * round again.
 183                          */
 184                         sppr = fls(divider) - 4;
 185                         spr = divider >> sppr;
 186
 187                         /*
 188                          * Now do range checking. SPR is constructed to have a
 189                          * width of 4 bits, so this is fine for sure. So we
 190                          * still need to check for sppr to fit into 3 bits:
 191                          */
 192                         if (sppr > 7)
 193                                 return -EINVAL;
 194                 }
 195
 196                 prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
 197         } else {
 198                 /*
 199                  * the supported rates are: 4,6,8...30
 200                  * round up as we look for equal or less speed
 201                  */
 202                 rate = DIV_ROUND_UP(tclk_hz, speed);
 203                 rate = roundup(rate, 2);
 204
 205                 /* check if requested speed is too small */
 206                 if (rate > 30)
 207                         return -EINVAL;
 208
 209                 if (rate < 4)
 210                         rate = 4;
 211
 212                 /* Convert the rate to SPI clock divisor value. */
 213                 prescale = 0x10 + rate/2;
 214         }
 215
 216         reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 217         reg = ((reg & ~devdata->prescale_mask) | prescale);
 218         writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 219
 220         return 0;
 221 }
 222
 223 static void
 224 orion_spi_mode_set(struct spi_device *spi)
 225 {
 226         u32 reg;
 227         struct orion_spi *orion_spi;
 228
 229         orion_spi = spi_master_get_devdata(spi->master);
 230
 231         reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 232         reg &= ~ORION_SPI_MODE_MASK;
 233         if (spi->mode & SPI_CPOL)
 234                 reg |= ORION_SPI_MODE_CPOL;
 235         if (spi->mode & SPI_CPHA)
 236                 reg |= ORION_SPI_MODE_CPHA;
 237         writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 238 }
 239
 240 static void
 241 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
 242 {
 243         u32 reg;
 244         struct orion_spi *orion_spi;
 245
 246         orion_spi = spi_master_get_devdata(spi->master);
 247
 248         /*
 249          * Erratum description: (Erratum NO. FE-9144572) The device
 250          * SPI interface supports frequencies of up to 50 MHz.
 251          * However, due to this erratum, when the device core clock is
 252          * 250 MHz and the SPI interfaces is configured for 50MHz SPI
 253          * clock and CPOL=CPHA=1 there might occur data corruption on
 254          * reads from the SPI device.
 255          * Erratum Workaround:
 256          * Work in one of the following configurations:
 257          * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
 258          * Register".
 259          * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
 260          * Register" before setting the interface.
 261          */
 262         reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
 263         reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
 264
 265         if (clk_get_rate(orion_spi->clk) == 250000000 &&
 266                         speed == 50000000 && spi->mode & SPI_CPOL &&
 267                         spi->mode & SPI_CPHA)
 268                 reg |= ORION_SPI_TMISO_SAMPLE_2;
 269         else
 270                 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
 271
 272         writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
 273 }
 274
 275 /*
 276  * called only when no transfer is active on the bus
 277  */
 278 static int
 279 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 280 {
 281         struct orion_spi *orion_spi;
 282         unsigned int speed = spi->max_speed_hz;
 283         unsigned int bits_per_word = spi->bits_per_word;
 284         int     rc;
 285
 286         orion_spi = spi_master_get_devdata(spi->master);
 287
 288         if ((t != NULL) && t->speed_hz)
 289                 speed = t->speed_hz;
 290
 291         if ((t != NULL) && t->bits_per_word)
 292                 bits_per_word = t->bits_per_word;
 293
 294         orion_spi_mode_set(spi);
 295
 296         if (orion_spi->devdata->is_errata_50mhz_ac)
 297                 orion_spi_50mhz_ac_timing_erratum(spi, speed);
 298
 299         rc = orion_spi_baudrate_set(spi, speed);
 300         if (rc)
 301                 return rc;
 302
 303         if (bits_per_word == 16)
 304                 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
 305                                   ORION_SPI_IF_8_16_BIT_MODE);
 306         else
 307                 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
 308                                   ORION_SPI_IF_8_16_BIT_MODE);
 309
 310         return 0;
 311 }
 312
 313 static void orion_spi_set_cs(struct spi_device *spi, bool enable)
 314 {
 315         struct orion_spi *orion_spi;
 316
 317         orion_spi = spi_master_get_devdata(spi->master);
 318
 319         orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
 320         orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
 321                                 ORION_SPI_CS(spi->chip_select));
 322
 323         /* Chip select logic is inverted from spi_set_cs */
 324         if (!enable)
 325                 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
 326         else
 327                 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
 328 }
 329
 330 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
 331 {
 332         int i;
 333
 334         for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
 335                 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
 336                         return 1;
 337
 338                 udelay(1);
 339         }
 340
 341         return -1;
 342 }
 343
 344 static inline int
 345 orion_spi_write_read_8bit(struct spi_device *spi,
 346                           const u8 **tx_buf, u8 **rx_buf)
 347 {
 348         void __iomem *tx_reg, *rx_reg, *int_reg;
 349         struct orion_spi *orion_spi;
 350
 351         orion_spi = spi_master_get_devdata(spi->master);
 352         tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
 353         rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
 354         int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
 355
 356         /* clear the interrupt cause register */
 357         writel(0x0, int_reg);
 358
 359         if (tx_buf && *tx_buf)
 360                 writel(*(*tx_buf)++, tx_reg);
 361         else
 362                 writel(0, tx_reg);
 363
 364         if (orion_spi_wait_till_ready(orion_spi) < 0) {
 365                 dev_err(&spi->dev, "TXS timed out\n");
 366                 return -1;
 367         }
 368
 369         if (rx_buf && *rx_buf)
 370                 *(*rx_buf)++ = readl(rx_reg);
 371
 372         return 1;
 373 }
 374
 375 static inline int
 376 orion_spi_write_read_16bit(struct spi_device *spi,
 377                            const u16 **tx_buf, u16 **rx_buf)
 378 {
 379         void __iomem *tx_reg, *rx_reg, *int_reg;
 380         struct orion_spi *orion_spi;
 381
 382         orion_spi = spi_master_get_devdata(spi->master);
 383         tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
 384         rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
 385         int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
 386
 387         /* clear the interrupt cause register */
 388         writel(0x0, int_reg);
 389
 390         if (tx_buf && *tx_buf)
 391                 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
 392         else
 393                 writel(0, tx_reg);
 394
 395         if (orion_spi_wait_till_ready(orion_spi) < 0) {
 396                 dev_err(&spi->dev, "TXS timed out\n");
 397                 return -1;
 398         }
 399
 400         if (rx_buf && *rx_buf)
 401                 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
 402
 403         return 1;
 404 }
 405
 406 static unsigned int
 407 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 408 {
 409         unsigned int count;
 410         int word_len;
 411         struct orion_spi *orion_spi;
 412         int cs = spi->chip_select;
 413
 414         word_len = spi->bits_per_word;
 415         count = xfer->len;
 416
 417         orion_spi = spi_master_get_devdata(spi->master);
 418
 419         /*
 420          * Use SPI direct write mode if base address is available. Otherwise
 421          * fall back to PIO mode for this transfer.
 422          */
 423         if ((orion_spi->direct_access[cs].vaddr) && (xfer->tx_buf) &&
 424             (word_len == 8)) {
 425                 unsigned int cnt = count / 4;
 426                 unsigned int rem = count % 4;
 427
 428                 /*
 429                  * Send the TX-data to the SPI device via the direct
 430                  * mapped address window
 431                  */
 432                 iowrite32_rep(orion_spi->direct_access[cs].vaddr,
 433                               xfer->tx_buf, cnt);
 434                 if (rem) {
 435                         u32 *buf = (u32 *)xfer->tx_buf;
 436
 437                         iowrite8_rep(orion_spi->direct_access[cs].vaddr,
 438                                      &buf[cnt], rem);
 439                 }
 440
 441                 return count;
 442         }
 443
 444         if (word_len == 8) {
 445                 const u8 *tx = xfer->tx_buf;
 446                 u8 *rx = xfer->rx_buf;
 447
 448                 do {
 449                         if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
 450                                 goto out;
 451                         count--;
 452                 } while (count);
 453         } else if (word_len == 16) {
 454                 const u16 *tx = xfer->tx_buf;
 455                 u16 *rx = xfer->rx_buf;
 456
 457                 do {
 458                         if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
 459                                 goto out;
 460                         count -= 2;
 461                 } while (count);
 462         }
 463
 464 out:
 465         return xfer->len - count;
 466 }
 467
 468 static int orion_spi_transfer_one(struct spi_master *master,
 469                                         struct spi_device *spi,
 470                                         struct spi_transfer *t)
 471 {
 472         int status = 0;
 473
 474         status = orion_spi_setup_transfer(spi, t);
 475         if (status < 0)
 476                 return status;
 477
 478         if (t->len)
 479                 orion_spi_write_read(spi, t);
 480
 481         return status;
 482 }
 483
 484 static int orion_spi_setup(struct spi_device *spi)
 485 {
 486         return orion_spi_setup_transfer(spi, NULL);
 487 }
 488
 489 static int orion_spi_reset(struct orion_spi *orion_spi)
 490 {
 491         /* Verify that the CS is deasserted */
 492         orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
 493
 494         /* Don't deassert CS between the direct mapped SPI transfers */
 495         writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
 496
 497         return 0;
 498 }
 499
 500 static const struct orion_spi_dev orion_spi_dev_data = {
 501         .typ = ORION_SPI,
 502         .min_divisor = 4,
 503         .max_divisor = 30,
 504         .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
 505 };
 506
 507 static const struct orion_spi_dev armada_370_spi_dev_data = {
 508         .typ = ARMADA_SPI,
 509         .min_divisor = 4,
 510         .max_divisor = 1920,
 511         .max_hz = 50000000,
 512         .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
 513 };
 514
 515 static const struct orion_spi_dev armada_xp_spi_dev_data = {
 516         .typ = ARMADA_SPI,
 517         .max_hz = 50000000,
 518         .max_divisor = 1920,
 519         .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
 520 };
 521
 522 static const struct orion_spi_dev armada_375_spi_dev_data = {
 523         .typ = ARMADA_SPI,
 524         .min_divisor = 15,
 525         .max_divisor = 1920,
 526         .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
 527 };
 528
 529 static const struct orion_spi_dev armada_380_spi_dev_data = {
 530         .typ = ARMADA_SPI,
 531         .max_hz = 50000000,
 532         .max_divisor = 1920,
 533         .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
 534         .is_errata_50mhz_ac = true,
 535 };
 536
 537 static const struct of_device_id orion_spi_of_match_table[] = {
 538         {
 539                 .compatible = "marvell,orion-spi",
 540                 .data = &orion_spi_dev_data,
 541         },
 542         {
 543                 .compatible = "marvell,armada-370-spi",
 544                 .data = &armada_370_spi_dev_data,
 545         },
 546         {
 547                 .compatible = "marvell,armada-375-spi",
 548                 .data = &armada_375_spi_dev_data,
 549         },
 550         {
 551                 .compatible = "marvell,armada-380-spi",
 552                 .data = &armada_380_spi_dev_data,
 553         },
 554         {
 555                 .compatible = "marvell,armada-390-spi",
 556                 .data = &armada_xp_spi_dev_data,
 557         },
 558         {
 559                 .compatible = "marvell,armada-xp-spi",
 560                 .data = &armada_xp_spi_dev_data,
 561         },
 562
 563         {}
 564 };
 565 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
 566
 567 static int orion_spi_probe(struct platform_device *pdev)
 568 {
 569         const struct of_device_id *of_id;
 570         const struct orion_spi_dev *devdata;
 571         struct spi_master *master;
 572         struct orion_spi *spi;
 573         struct resource *r;
 574         unsigned long tclk_hz;
 575         int status = 0;
 576         struct device_node *np;
 577
 578         master = spi_alloc_master(&pdev->dev, sizeof(*spi));
 579         if (master == NULL) {
 580                 dev_dbg(&pdev->dev, "master allocation failed\n");
 581                 return -ENOMEM;
 582         }
 583
 584         if (pdev->id != -1)
 585                 master->bus_num = pdev->id;
 586         if (pdev->dev.of_node) {
 587                 u32 cell_index;
 588
 589                 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
 590                                           &cell_index))
 591                         master->bus_num = cell_index;
 592         }
 593
 594         /* we support only mode 0, and no options */
 595         master->mode_bits = SPI_CPHA | SPI_CPOL;
 596         master->set_cs = orion_spi_set_cs;
 597         master->transfer_one = orion_spi_transfer_one;
 598         master->num_chipselect = ORION_NUM_CHIPSELECTS;
 599         master->setup = orion_spi_setup;
 600         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 601         master->auto_runtime_pm = true;
 602
 603         platform_set_drvdata(pdev, master);
 604
 605         spi = spi_master_get_devdata(master);
 606         spi->master = master;
 607
 608         of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
 609         devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
 610         spi->devdata = devdata;
 611
 612         spi->clk = devm_clk_get(&pdev->dev, NULL);
 613         if (IS_ERR(spi->clk)) {
 614                 status = PTR_ERR(spi->clk);
 615                 goto out;
 616         }
 617
 618         status = clk_prepare_enable(spi->clk);
 619         if (status)
 620                 goto out;
 621
 622         tclk_hz = clk_get_rate(spi->clk);
 623
 624         /*
 625          * With old device tree, armada-370-spi could be used with
 626          * Armada XP, however for this SoC the maximum frequency is
 627          * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
 628          * higher than 200MHz. So, in order to be able to handle both
 629          * SoCs, we can take the minimum of 50MHz and tclk/4.
 630          */
 631         if (of_device_is_compatible(pdev->dev.of_node,
 632                                         "marvell,armada-370-spi"))
 633                 master->max_speed_hz = min(devdata->max_hz,
 634                                 DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
 635         else if (devdata->min_divisor)
 636                 master->max_speed_hz =
 637                         DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
 638         else
 639                 master->max_speed_hz = devdata->max_hz;
 640         master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
 641
 642         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 643         spi->base = devm_ioremap_resource(&pdev->dev, r);
 644         if (IS_ERR(spi->base)) {
 645                 status = PTR_ERR(spi->base);
 646                 goto out_rel_clk;
 647         }
 648
 649         /* Scan all SPI devices of this controller for direct mapped devices */
 650         for_each_available_child_of_node(pdev->dev.of_node, np) {
 651                 u32 cs;
 652
 653                 /* Get chip-select number from the "reg" property */
 654                 status = of_property_read_u32(np, "reg", &cs);
 655                 if (status) {
 656                         dev_err(&pdev->dev,
 657                                 "%s has no valid 'reg' property (%d)\n",
 658                                 np->full_name, status);
 659                         status = 0;
 660                         continue;
 661                 }
 662
 663                 /*
 664                  * Check if an address is configured for this SPI device. If
 665                  * not, the MBus mapping via the 'ranges' property in the 'soc'
 666                  * node is not configured and this device should not use the
 667                  * direct mode. In this case, just continue with the next
 668                  * device.
 669                  */
 670                 status = of_address_to_resource(pdev->dev.of_node, cs + 1, r);
 671                 if (status)
 672                         continue;
 673
 674                 /*
 675                  * Only map one page for direct access. This is enough for the
 676                  * simple TX transfer which only writes to the first word.
 677                  * This needs to get extended for the direct SPI-NOR / SPI-NAND
 678                  * support, once this gets implemented.
 679                  */
 680                 spi->direct_access[cs].vaddr = devm_ioremap(&pdev->dev,
 681                                                             r->start,
 682                                                             PAGE_SIZE);
 683                 if (!spi->direct_access[cs].vaddr) {
 684                         status = -ENOMEM;
 685                         goto out_rel_clk;
 686                 }
 687                 spi->direct_access[cs].size = PAGE_SIZE;
 688
 689                 dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
 690         }
 691
 692         pm_runtime_set_active(&pdev->dev);
 693         pm_runtime_use_autosuspend(&pdev->dev);
 694         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
 695         pm_runtime_enable(&pdev->dev);
 696
 697         status = orion_spi_reset(spi);
 698         if (status < 0)
 699                 goto out_rel_pm;
 700
 701         pm_runtime_mark_last_busy(&pdev->dev);
 702         pm_runtime_put_autosuspend(&pdev->dev);
 703
 704         master->dev.of_node = pdev->dev.of_node;
 705         status = spi_register_master(master);
 706         if (status < 0)
 707                 goto out_rel_pm;
 708
 709         return status;
 710
 711 out_rel_pm:
 712         pm_runtime_disable(&pdev->dev);
 713 out_rel_clk:
 714         clk_disable_unprepare(spi->clk);
 715 out:
 716         spi_master_put(master);
 717         return status;
 718 }
 719
 720
 721 static int orion_spi_remove(struct platform_device *pdev)
 722 {
 723         struct spi_master *master = platform_get_drvdata(pdev);
 724         struct orion_spi *spi = spi_master_get_devdata(master);
 725
 726         pm_runtime_get_sync(&pdev->dev);
 727         clk_disable_unprepare(spi->clk);
 728
 729         spi_unregister_master(master);
 730         pm_runtime_disable(&pdev->dev);
 731
 732         return 0;
 733 }
 734
 735 MODULE_ALIAS("platform:" DRIVER_NAME);
 736
 737 #ifdef CONFIG_PM
 738 static int orion_spi_runtime_suspend(struct device *dev)
 739 {
 740         struct spi_master *master = dev_get_drvdata(dev);
 741         struct orion_spi *spi = spi_master_get_devdata(master);
 742
 743         clk_disable_unprepare(spi->clk);
 744         return 0;
 745 }
 746
 747 static int orion_spi_runtime_resume(struct device *dev)
 748 {
 749         struct spi_master *master = dev_get_drvdata(dev);
 750         struct orion_spi *spi = spi_master_get_devdata(master);
 751
 752         return clk_prepare_enable(spi->clk);
 753 }
 754 #endif
 755
 756 static const struct dev_pm_ops orion_spi_pm_ops = {
 757         SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
 758                            orion_spi_runtime_resume,
 759                            NULL)
 760 };
 761
 762 static struct platform_driver orion_spi_driver = {
 763         .driver = {
 764                 .name   = DRIVER_NAME,
 765                 .pm     = &orion_spi_pm_ops,
 766                 .of_match_table = of_match_ptr(orion_spi_of_match_table),
 767         },
 768         .probe          = orion_spi_probe,
 769         .remove         = orion_spi_remove,
 770 };
 771
 772 module_platform_driver(orion_spi_driver);
 773
 774 MODULE_DESCRIPTION("Orion SPI driver");
 775 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
 776 MODULE_LICENSE("GPL");