2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/bitops.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/ioport.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/platform_device.h>
27 #include <linux/spi/pxa2xx_spi.h>
28 #include <linux/spi/spi.h>
29 #include <linux/delay.h>
30 #include <linux/gpio.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/slab.h>
33 #include <linux/clk.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/acpi.h>
37 #include "spi-pxa2xx.h"
39 MODULE_AUTHOR("Stephen Street");
40 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
41 MODULE_LICENSE("GPL");
42 MODULE_ALIAS("platform:pxa2xx-spi");
44 #define TIMOUT_DFLT 1000
47 * for testing SSCR1 changes that require SSP restart, basically
48 * everything except the service and interrupt enables, the pxa270 developer
49 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
50 * list, but the PXA255 dev man says all bits without really meaning the
51 * service and interrupt enables
53 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
54 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
55 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
56 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
57 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
58 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
60 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
61 | QUARK_X1000_SSCR1_EFWR \
62 | QUARK_X1000_SSCR1_RFT \
63 | QUARK_X1000_SSCR1_TFT \
64 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
66 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
67 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
68 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
69 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
70 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
71 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
73 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
74 #define LPSS_CS_CONTROL_SW_MODE BIT(0)
75 #define LPSS_CS_CONTROL_CS_HIGH BIT(1)
76 #define LPSS_CAPS_CS_EN_SHIFT 9
77 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
79 #define LPSS_PRIV_CLOCK_GATE 0x38
80 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
81 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
84 /* LPSS offset from drv_data->ioaddr */
86 /* Register offsets from drv_data->lpss_base or -1 */
95 /* Chip select control */
96 unsigned cs_sel_shift;
100 unsigned cs_clk_stays_gated : 1;
103 /* Keep these sorted with enum pxa_ssp_type */
104 static const struct lpss_config lpss_platforms[] = {
110 .reg_capabilities = -1,
112 .tx_threshold_lo = 160,
113 .tx_threshold_hi = 224,
120 .reg_capabilities = -1,
122 .tx_threshold_lo = 160,
123 .tx_threshold_hi = 224,
130 .reg_capabilities = -1,
132 .tx_threshold_lo = 160,
133 .tx_threshold_hi = 224,
135 .cs_sel_mask = 1 << 2,
143 .reg_capabilities = -1,
145 .tx_threshold_lo = 32,
146 .tx_threshold_hi = 56,
153 .reg_capabilities = 0xfc,
155 .tx_threshold_lo = 16,
156 .tx_threshold_hi = 48,
158 .cs_sel_mask = 3 << 8,
159 .cs_clk_stays_gated = true,
166 .reg_capabilities = 0xfc,
168 .tx_threshold_lo = 32,
169 .tx_threshold_hi = 56,
171 .cs_sel_mask = 3 << 8,
172 .cs_clk_stays_gated = true,
176 static inline const struct lpss_config
177 *lpss_get_config(const struct driver_data *drv_data)
179 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
182 static bool is_lpss_ssp(const struct driver_data *drv_data)
184 switch (drv_data->ssp_type) {
197 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
199 return drv_data->ssp_type == QUARK_X1000_SSP;
202 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
204 switch (drv_data->ssp_type) {
205 case QUARK_X1000_SSP:
206 return QUARK_X1000_SSCR1_CHANGE_MASK;
208 return CE4100_SSCR1_CHANGE_MASK;
210 return SSCR1_CHANGE_MASK;
215 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
217 switch (drv_data->ssp_type) {
218 case QUARK_X1000_SSP:
219 return RX_THRESH_QUARK_X1000_DFLT;
221 return RX_THRESH_CE4100_DFLT;
223 return RX_THRESH_DFLT;
227 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
231 switch (drv_data->ssp_type) {
232 case QUARK_X1000_SSP:
233 mask = QUARK_X1000_SSSR_TFL_MASK;
236 mask = CE4100_SSSR_TFL_MASK;
239 mask = SSSR_TFL_MASK;
243 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
246 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
251 switch (drv_data->ssp_type) {
252 case QUARK_X1000_SSP:
253 mask = QUARK_X1000_SSCR1_RFT;
256 mask = CE4100_SSCR1_RFT;
265 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
266 u32 *sccr1_reg, u32 threshold)
268 switch (drv_data->ssp_type) {
269 case QUARK_X1000_SSP:
270 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
273 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
276 *sccr1_reg |= SSCR1_RxTresh(threshold);
281 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
282 u32 clk_div, u8 bits)
284 switch (drv_data->ssp_type) {
285 case QUARK_X1000_SSP:
287 | QUARK_X1000_SSCR0_Motorola
288 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
293 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
295 | (bits > 16 ? SSCR0_EDSS : 0);
300 * Read and write LPSS SSP private registers. Caller must first check that
301 * is_lpss_ssp() returns true before these can be called.
303 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
305 WARN_ON(!drv_data->lpss_base);
306 return readl(drv_data->lpss_base + offset);
309 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
310 unsigned offset, u32 value)
312 WARN_ON(!drv_data->lpss_base);
313 writel(value, drv_data->lpss_base + offset);
317 * lpss_ssp_setup - perform LPSS SSP specific setup
318 * @drv_data: pointer to the driver private data
320 * Perform LPSS SSP specific setup. This function must be called first if
321 * one is going to use LPSS SSP private registers.
323 static void lpss_ssp_setup(struct driver_data *drv_data)
325 const struct lpss_config *config;
328 config = lpss_get_config(drv_data);
329 drv_data->lpss_base = drv_data->ioaddr + config->offset;
331 /* Enable software chip select control */
332 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
333 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
334 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
335 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
337 /* Enable multiblock DMA transfers */
338 if (drv_data->master_info->enable_dma) {
339 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
341 if (config->reg_general >= 0) {
342 value = __lpss_ssp_read_priv(drv_data,
343 config->reg_general);
344 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
345 __lpss_ssp_write_priv(drv_data,
346 config->reg_general, value);
351 static void lpss_ssp_select_cs(struct spi_device *spi,
352 const struct lpss_config *config)
354 struct driver_data *drv_data =
355 spi_controller_get_devdata(spi->controller);
358 if (!config->cs_sel_mask)
361 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
363 cs = spi->chip_select;
364 cs <<= config->cs_sel_shift;
365 if (cs != (value & config->cs_sel_mask)) {
367 * When switching another chip select output active the
368 * output must be selected first and wait 2 ssp_clk cycles
369 * before changing state to active. Otherwise a short
370 * glitch will occur on the previous chip select since
371 * output select is latched but state control is not.
373 value &= ~config->cs_sel_mask;
375 __lpss_ssp_write_priv(drv_data,
376 config->reg_cs_ctrl, value);
378 (drv_data->master->max_speed_hz / 2));
382 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
384 struct driver_data *drv_data =
385 spi_controller_get_devdata(spi->controller);
386 const struct lpss_config *config;
389 config = lpss_get_config(drv_data);
392 lpss_ssp_select_cs(spi, config);
394 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
396 value &= ~LPSS_CS_CONTROL_CS_HIGH;
398 value |= LPSS_CS_CONTROL_CS_HIGH;
399 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
400 if (config->cs_clk_stays_gated) {
404 * Changing CS alone when dynamic clock gating is on won't
405 * actually flip CS at that time. This ruins SPI transfers
406 * that specify delays, or have no data. Toggle the clock mode
407 * to force on briefly to poke the CS pin to move.
409 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
410 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
411 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
413 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
414 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
418 static void cs_assert(struct spi_device *spi)
420 struct chip_data *chip = spi_get_ctldata(spi);
421 struct driver_data *drv_data =
422 spi_controller_get_devdata(spi->controller);
424 if (drv_data->ssp_type == CE4100_SSP) {
425 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
429 if (chip->cs_control) {
430 chip->cs_control(PXA2XX_CS_ASSERT);
434 if (chip->gpiod_cs) {
435 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
439 if (is_lpss_ssp(drv_data))
440 lpss_ssp_cs_control(spi, true);
443 static void cs_deassert(struct spi_device *spi)
445 struct chip_data *chip = spi_get_ctldata(spi);
446 struct driver_data *drv_data =
447 spi_controller_get_devdata(spi->controller);
448 unsigned long timeout;
450 if (drv_data->ssp_type == CE4100_SSP)
453 /* Wait until SSP becomes idle before deasserting the CS */
454 timeout = jiffies + msecs_to_jiffies(10);
455 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
456 !time_after(jiffies, timeout))
459 if (chip->cs_control) {
460 chip->cs_control(PXA2XX_CS_DEASSERT);
464 if (chip->gpiod_cs) {
465 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
469 if (is_lpss_ssp(drv_data))
470 lpss_ssp_cs_control(spi, false);
473 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
481 int pxa2xx_spi_flush(struct driver_data *drv_data)
483 unsigned long limit = loops_per_jiffy << 1;
486 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
487 pxa2xx_spi_read(drv_data, SSDR);
488 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
489 write_SSSR_CS(drv_data, SSSR_ROR);
494 static int null_writer(struct driver_data *drv_data)
496 u8 n_bytes = drv_data->n_bytes;
498 if (pxa2xx_spi_txfifo_full(drv_data)
499 || (drv_data->tx == drv_data->tx_end))
502 pxa2xx_spi_write(drv_data, SSDR, 0);
503 drv_data->tx += n_bytes;
508 static int null_reader(struct driver_data *drv_data)
510 u8 n_bytes = drv_data->n_bytes;
512 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
513 && (drv_data->rx < drv_data->rx_end)) {
514 pxa2xx_spi_read(drv_data, SSDR);
515 drv_data->rx += n_bytes;
518 return drv_data->rx == drv_data->rx_end;
521 static int u8_writer(struct driver_data *drv_data)
523 if (pxa2xx_spi_txfifo_full(drv_data)
524 || (drv_data->tx == drv_data->tx_end))
527 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
533 static int u8_reader(struct driver_data *drv_data)
535 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
536 && (drv_data->rx < drv_data->rx_end)) {
537 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
541 return drv_data->rx == drv_data->rx_end;
544 static int u16_writer(struct driver_data *drv_data)
546 if (pxa2xx_spi_txfifo_full(drv_data)
547 || (drv_data->tx == drv_data->tx_end))
550 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
556 static int u16_reader(struct driver_data *drv_data)
558 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
559 && (drv_data->rx < drv_data->rx_end)) {
560 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
564 return drv_data->rx == drv_data->rx_end;
567 static int u32_writer(struct driver_data *drv_data)
569 if (pxa2xx_spi_txfifo_full(drv_data)
570 || (drv_data->tx == drv_data->tx_end))
573 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
579 static int u32_reader(struct driver_data *drv_data)
581 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
582 && (drv_data->rx < drv_data->rx_end)) {
583 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
587 return drv_data->rx == drv_data->rx_end;
590 static void reset_sccr1(struct driver_data *drv_data)
592 struct chip_data *chip =
593 spi_get_ctldata(drv_data->master->cur_msg->spi);
596 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
597 switch (drv_data->ssp_type) {
598 case QUARK_X1000_SSP:
599 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
602 sccr1_reg &= ~CE4100_SSCR1_RFT;
605 sccr1_reg &= ~SSCR1_RFT;
608 sccr1_reg |= chip->threshold;
609 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
612 static void int_error_stop(struct driver_data *drv_data, const char* msg)
614 /* Stop and reset SSP */
615 write_SSSR_CS(drv_data, drv_data->clear_sr);
616 reset_sccr1(drv_data);
617 if (!pxa25x_ssp_comp(drv_data))
618 pxa2xx_spi_write(drv_data, SSTO, 0);
619 pxa2xx_spi_flush(drv_data);
620 pxa2xx_spi_write(drv_data, SSCR0,
621 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
623 dev_err(&drv_data->pdev->dev, "%s\n", msg);
625 drv_data->master->cur_msg->status = -EIO;
626 spi_finalize_current_transfer(drv_data->master);
629 static void int_transfer_complete(struct driver_data *drv_data)
631 /* Clear and disable interrupts */
632 write_SSSR_CS(drv_data, drv_data->clear_sr);
633 reset_sccr1(drv_data);
634 if (!pxa25x_ssp_comp(drv_data))
635 pxa2xx_spi_write(drv_data, SSTO, 0);
637 spi_finalize_current_transfer(drv_data->master);
640 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
642 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
643 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
645 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
647 if (irq_status & SSSR_ROR) {
648 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
652 if (irq_status & SSSR_TINT) {
653 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
654 if (drv_data->read(drv_data)) {
655 int_transfer_complete(drv_data);
660 /* Drain rx fifo, Fill tx fifo and prevent overruns */
662 if (drv_data->read(drv_data)) {
663 int_transfer_complete(drv_data);
666 } while (drv_data->write(drv_data));
668 if (drv_data->read(drv_data)) {
669 int_transfer_complete(drv_data);
673 if (drv_data->tx == drv_data->tx_end) {
677 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
678 sccr1_reg &= ~SSCR1_TIE;
681 * PXA25x_SSP has no timeout, set up rx threshould for the
682 * remaining RX bytes.
684 if (pxa25x_ssp_comp(drv_data)) {
687 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
689 bytes_left = drv_data->rx_end - drv_data->rx;
690 switch (drv_data->n_bytes) {
697 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
698 if (rx_thre > bytes_left)
699 rx_thre = bytes_left;
701 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
703 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
706 /* We did something */
710 static void handle_bad_msg(struct driver_data *drv_data)
712 pxa2xx_spi_write(drv_data, SSCR0,
713 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
714 pxa2xx_spi_write(drv_data, SSCR1,
715 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
716 if (!pxa25x_ssp_comp(drv_data))
717 pxa2xx_spi_write(drv_data, SSTO, 0);
718 write_SSSR_CS(drv_data, drv_data->clear_sr);
720 dev_err(&drv_data->pdev->dev,
721 "bad message state in interrupt handler\n");
724 static irqreturn_t ssp_int(int irq, void *dev_id)
726 struct driver_data *drv_data = dev_id;
728 u32 mask = drv_data->mask_sr;
732 * The IRQ might be shared with other peripherals so we must first
733 * check that are we RPM suspended or not. If we are we assume that
734 * the IRQ was not for us (we shouldn't be RPM suspended when the
735 * interrupt is enabled).
737 if (pm_runtime_suspended(&drv_data->pdev->dev))
741 * If the device is not yet in RPM suspended state and we get an
742 * interrupt that is meant for another device, check if status bits
743 * are all set to one. That means that the device is already
746 status = pxa2xx_spi_read(drv_data, SSSR);
750 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
752 /* Ignore possible writes if we don't need to write */
753 if (!(sccr1_reg & SSCR1_TIE))
756 /* Ignore RX timeout interrupt if it is disabled */
757 if (!(sccr1_reg & SSCR1_TINTE))
760 if (!(status & mask))
763 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
764 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
766 if (!drv_data->master->cur_msg) {
767 handle_bad_msg(drv_data);
772 return drv_data->transfer_handler(drv_data);
776 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
777 * input frequency by fractions of 2^24. It also has a divider by 5.
779 * There are formulas to get baud rate value for given input frequency and
780 * divider parameters, such as DDS_CLK_RATE and SCR:
784 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
785 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
787 * DDS_CLK_RATE either 2^n or 2^n / 5.
788 * SCR is in range 0 .. 255
790 * Divisor = 5^i * 2^j * 2 * k
791 * i = [0, 1] i = 1 iff j = 0 or j > 3
792 * j = [0, 23] j = 0 iff i = 1
794 * Special case: j = 0, i = 1: Divisor = 2 / 5
796 * Accordingly to the specification the recommended values for DDS_CLK_RATE
798 * Case 1: 2^n, n = [0, 23]
799 * Case 2: 2^24 * 2 / 5 (0x666666)
800 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
802 * In all cases the lowest possible value is better.
804 * The function calculates parameters for all cases and chooses the one closest
805 * to the asked baud rate.
807 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
809 unsigned long xtal = 200000000;
810 unsigned long fref = xtal / 2; /* mandatory division by 2,
813 unsigned long fref1 = fref / 2; /* case 1 */
814 unsigned long fref2 = fref * 2 / 5; /* case 2 */
816 unsigned long q, q1, q2;
822 /* Set initial value for DDS_CLK_RATE */
823 mul = (1 << 24) >> 1;
825 /* Calculate initial quot */
826 q1 = DIV_ROUND_UP(fref1, rate);
828 /* Scale q1 if it's too big */
830 /* Scale q1 to range [1, 512] */
831 scale = fls_long(q1 - 1);
837 /* Round the result if we have a remainder */
841 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
846 /* Get the remainder */
847 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
851 q2 = DIV_ROUND_UP(fref2, rate);
852 r2 = abs(fref2 / q2 - rate);
855 * Choose the best between two: less remainder we have the better. We
856 * can't go case 2 if q2 is greater than 256 since SCR register can
857 * hold only values 0 .. 255.
859 if (r2 >= r1 || q2 > 256) {
860 /* case 1 is better */
864 /* case 2 is better */
867 mul = (1 << 24) * 2 / 5;
870 /* Check case 3 only if the divisor is big enough */
871 if (fref / rate >= 80) {
875 /* Calculate initial quot */
876 q1 = DIV_ROUND_UP(fref, rate);
879 /* Get the remainder */
880 fssp = (u64)fref * m;
881 do_div(fssp, 1 << 24);
882 r1 = abs(fssp - rate);
884 /* Choose this one if it suits better */
886 /* case 3 is better */
896 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
898 unsigned long ssp_clk = drv_data->master->max_speed_hz;
899 const struct ssp_device *ssp = drv_data->ssp;
901 rate = min_t(int, ssp_clk, rate);
904 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
905 * that the SSP transmission rate can be greater than the device rate
907 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
908 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
910 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff;
913 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
916 struct chip_data *chip =
917 spi_get_ctldata(drv_data->master->cur_msg->spi);
918 unsigned int clk_div;
920 switch (drv_data->ssp_type) {
921 case QUARK_X1000_SSP:
922 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
925 clk_div = ssp_get_clk_div(drv_data, rate);
931 static bool pxa2xx_spi_can_dma(struct spi_controller *master,
932 struct spi_device *spi,
933 struct spi_transfer *xfer)
935 struct chip_data *chip = spi_get_ctldata(spi);
937 return chip->enable_dma &&
938 xfer->len <= MAX_DMA_LEN &&
939 xfer->len >= chip->dma_burst_size;
942 static int pxa2xx_spi_transfer_one(struct spi_controller *master,
943 struct spi_device *spi,
944 struct spi_transfer *transfer)
946 struct driver_data *drv_data = spi_controller_get_devdata(master);
947 struct spi_message *message = master->cur_msg;
948 struct chip_data *chip = spi_get_ctldata(message->spi);
949 u32 dma_thresh = chip->dma_threshold;
950 u32 dma_burst = chip->dma_burst_size;
951 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
960 /* Check if we can DMA this transfer */
961 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
963 /* reject already-mapped transfers; PIO won't always work */
964 if (message->is_dma_mapped
965 || transfer->rx_dma || transfer->tx_dma) {
966 dev_err(&drv_data->pdev->dev,
967 "Mapped transfer length of %u is greater than %d\n",
968 transfer->len, MAX_DMA_LEN);
972 /* warn ... we force this to PIO mode */
973 dev_warn_ratelimited(&message->spi->dev,
974 "DMA disabled for transfer length %ld greater than %d\n",
975 (long)transfer->len, MAX_DMA_LEN);
978 /* Setup the transfer state based on the type of transfer */
979 if (pxa2xx_spi_flush(drv_data) == 0) {
980 dev_err(&drv_data->pdev->dev, "Flush failed\n");
983 drv_data->n_bytes = chip->n_bytes;
984 drv_data->tx = (void *)transfer->tx_buf;
985 drv_data->tx_end = drv_data->tx + transfer->len;
986 drv_data->rx = transfer->rx_buf;
987 drv_data->rx_end = drv_data->rx + transfer->len;
988 drv_data->write = drv_data->tx ? chip->write : null_writer;
989 drv_data->read = drv_data->rx ? chip->read : null_reader;
991 /* Change speed and bit per word on a per transfer */
992 bits = transfer->bits_per_word;
993 speed = transfer->speed_hz;
995 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
998 drv_data->n_bytes = 1;
999 drv_data->read = drv_data->read != null_reader ?
1000 u8_reader : null_reader;
1001 drv_data->write = drv_data->write != null_writer ?
1002 u8_writer : null_writer;
1003 } else if (bits <= 16) {
1004 drv_data->n_bytes = 2;
1005 drv_data->read = drv_data->read != null_reader ?
1006 u16_reader : null_reader;
1007 drv_data->write = drv_data->write != null_writer ?
1008 u16_writer : null_writer;
1009 } else if (bits <= 32) {
1010 drv_data->n_bytes = 4;
1011 drv_data->read = drv_data->read != null_reader ?
1012 u32_reader : null_reader;
1013 drv_data->write = drv_data->write != null_writer ?
1014 u32_writer : null_writer;
1017 * if bits/word is changed in dma mode, then must check the
1018 * thresholds and burst also
1020 if (chip->enable_dma) {
1021 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1025 dev_warn_ratelimited(&message->spi->dev,
1026 "DMA burst size reduced to match bits_per_word\n");
1029 dma_mapped = master->can_dma &&
1030 master->can_dma(master, message->spi, transfer) &&
1031 master->cur_msg_mapped;
1034 /* Ensure we have the correct interrupt handler */
1035 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1037 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1041 /* Clear status and start DMA engine */
1042 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1043 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1045 pxa2xx_spi_dma_start(drv_data);
1047 /* Ensure we have the correct interrupt handler */
1048 drv_data->transfer_handler = interrupt_transfer;
1051 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1052 write_SSSR_CS(drv_data, drv_data->clear_sr);
1055 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1056 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1057 if (!pxa25x_ssp_comp(drv_data))
1058 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1059 master->max_speed_hz
1060 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1061 dma_mapped ? "DMA" : "PIO");
1063 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1064 master->max_speed_hz / 2
1065 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1066 dma_mapped ? "DMA" : "PIO");
1068 if (is_lpss_ssp(drv_data)) {
1069 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1070 != chip->lpss_rx_threshold)
1071 pxa2xx_spi_write(drv_data, SSIRF,
1072 chip->lpss_rx_threshold);
1073 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1074 != chip->lpss_tx_threshold)
1075 pxa2xx_spi_write(drv_data, SSITF,
1076 chip->lpss_tx_threshold);
1079 if (is_quark_x1000_ssp(drv_data) &&
1080 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1081 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1083 /* see if we need to reload the config registers */
1084 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1085 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1086 != (cr1 & change_mask)) {
1087 /* stop the SSP, and update the other bits */
1088 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1089 if (!pxa25x_ssp_comp(drv_data))
1090 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1091 /* first set CR1 without interrupt and service enables */
1092 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1093 /* restart the SSP */
1094 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1097 if (!pxa25x_ssp_comp(drv_data))
1098 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1102 * Release the data by enabling service requests and interrupts,
1103 * without changing any mode bits
1105 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1110 static void pxa2xx_spi_handle_err(struct spi_controller *master,
1111 struct spi_message *msg)
1113 struct driver_data *drv_data = spi_controller_get_devdata(master);
1115 /* Disable the SSP */
1116 pxa2xx_spi_write(drv_data, SSCR0,
1117 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1118 /* Clear and disable interrupts and service requests */
1119 write_SSSR_CS(drv_data, drv_data->clear_sr);
1120 pxa2xx_spi_write(drv_data, SSCR1,
1121 pxa2xx_spi_read(drv_data, SSCR1)
1122 & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1123 if (!pxa25x_ssp_comp(drv_data))
1124 pxa2xx_spi_write(drv_data, SSTO, 0);
1127 * Stop the DMA if running. Note DMA callback handler may have unset
1128 * the dma_running already, which is fine as stopping is not needed
1129 * then but we shouldn't rely this flag for anything else than
1130 * stopping. For instance to differentiate between PIO and DMA
1133 if (atomic_read(&drv_data->dma_running))
1134 pxa2xx_spi_dma_stop(drv_data);
1137 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *master)
1139 struct driver_data *drv_data = spi_controller_get_devdata(master);
1141 /* Disable the SSP now */
1142 pxa2xx_spi_write(drv_data, SSCR0,
1143 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1148 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1149 struct pxa2xx_spi_chip *chip_info)
1151 struct driver_data *drv_data =
1152 spi_controller_get_devdata(spi->controller);
1153 struct gpio_desc *gpiod;
1159 if (drv_data->cs_gpiods) {
1160 gpiod = drv_data->cs_gpiods[spi->chip_select];
1162 chip->gpiod_cs = gpiod;
1163 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1164 gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1170 if (chip_info == NULL)
1173 /* NOTE: setup() can be called multiple times, possibly with
1174 * different chip_info, release previously requested GPIO
1176 if (chip->gpiod_cs) {
1177 gpiod_put(chip->gpiod_cs);
1178 chip->gpiod_cs = NULL;
1181 /* If (*cs_control) is provided, ignore GPIO chip select */
1182 if (chip_info->cs_control) {
1183 chip->cs_control = chip_info->cs_control;
1187 if (gpio_is_valid(chip_info->gpio_cs)) {
1188 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1190 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1191 chip_info->gpio_cs);
1195 gpiod = gpio_to_desc(chip_info->gpio_cs);
1196 chip->gpiod_cs = gpiod;
1197 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1199 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1205 static int setup(struct spi_device *spi)
1207 struct pxa2xx_spi_chip *chip_info;
1208 struct chip_data *chip;
1209 const struct lpss_config *config;
1210 struct driver_data *drv_data =
1211 spi_controller_get_devdata(spi->controller);
1212 uint tx_thres, tx_hi_thres, rx_thres;
1214 switch (drv_data->ssp_type) {
1215 case QUARK_X1000_SSP:
1216 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1218 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1221 tx_thres = TX_THRESH_CE4100_DFLT;
1223 rx_thres = RX_THRESH_CE4100_DFLT;
1231 config = lpss_get_config(drv_data);
1232 tx_thres = config->tx_threshold_lo;
1233 tx_hi_thres = config->tx_threshold_hi;
1234 rx_thres = config->rx_threshold;
1237 tx_thres = TX_THRESH_DFLT;
1239 rx_thres = RX_THRESH_DFLT;
1243 /* Only alloc on first setup */
1244 chip = spi_get_ctldata(spi);
1246 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1250 if (drv_data->ssp_type == CE4100_SSP) {
1251 if (spi->chip_select > 4) {
1253 "failed setup: cs number must not be > 4.\n");
1258 chip->frm = spi->chip_select;
1260 chip->enable_dma = drv_data->master_info->enable_dma;
1261 chip->timeout = TIMOUT_DFLT;
1264 /* protocol drivers may change the chip settings, so...
1265 * if chip_info exists, use it */
1266 chip_info = spi->controller_data;
1268 /* chip_info isn't always needed */
1271 if (chip_info->timeout)
1272 chip->timeout = chip_info->timeout;
1273 if (chip_info->tx_threshold)
1274 tx_thres = chip_info->tx_threshold;
1275 if (chip_info->tx_hi_threshold)
1276 tx_hi_thres = chip_info->tx_hi_threshold;
1277 if (chip_info->rx_threshold)
1278 rx_thres = chip_info->rx_threshold;
1279 chip->dma_threshold = 0;
1280 if (chip_info->enable_loopback)
1281 chip->cr1 = SSCR1_LBM;
1284 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1285 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1286 | SSITF_TxHiThresh(tx_hi_thres);
1288 /* set dma burst and threshold outside of chip_info path so that if
1289 * chip_info goes away after setting chip->enable_dma, the
1290 * burst and threshold can still respond to changes in bits_per_word */
1291 if (chip->enable_dma) {
1292 /* set up legal burst and threshold for dma */
1293 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1295 &chip->dma_burst_size,
1296 &chip->dma_threshold)) {
1298 "in setup: DMA burst size reduced to match bits_per_word\n");
1302 switch (drv_data->ssp_type) {
1303 case QUARK_X1000_SSP:
1304 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1305 & QUARK_X1000_SSCR1_RFT)
1306 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1307 & QUARK_X1000_SSCR1_TFT);
1310 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1311 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1314 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1315 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1319 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1320 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1321 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1323 if (spi->mode & SPI_LOOP)
1324 chip->cr1 |= SSCR1_LBM;
1326 if (spi->bits_per_word <= 8) {
1328 chip->read = u8_reader;
1329 chip->write = u8_writer;
1330 } else if (spi->bits_per_word <= 16) {
1332 chip->read = u16_reader;
1333 chip->write = u16_writer;
1334 } else if (spi->bits_per_word <= 32) {
1336 chip->read = u32_reader;
1337 chip->write = u32_writer;
1340 spi_set_ctldata(spi, chip);
1342 if (drv_data->ssp_type == CE4100_SSP)
1345 return setup_cs(spi, chip, chip_info);
1348 static void cleanup(struct spi_device *spi)
1350 struct chip_data *chip = spi_get_ctldata(spi);
1351 struct driver_data *drv_data =
1352 spi_controller_get_devdata(spi->controller);
1357 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1359 gpiod_put(chip->gpiod_cs);
1367 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1368 { "INT33C0", LPSS_LPT_SSP },
1369 { "INT33C1", LPSS_LPT_SSP },
1370 { "INT3430", LPSS_LPT_SSP },
1371 { "INT3431", LPSS_LPT_SSP },
1372 { "80860F0E", LPSS_BYT_SSP },
1373 { "8086228E", LPSS_BSW_SSP },
1376 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1378 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1383 if (adev && adev->pnp.unique_id &&
1384 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1388 #else /* !CONFIG_ACPI */
1389 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1396 * PCI IDs of compound devices that integrate both host controller and private
1397 * integrated DMA engine. Please note these are not used in module
1398 * autoloading and probing in this module but matching the LPSS SSP type.
1400 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1402 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1403 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1405 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1406 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1408 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1409 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1411 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1412 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1413 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1415 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1416 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1417 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1419 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1420 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1421 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1423 { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1424 { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1425 { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1427 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1428 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1429 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1431 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1432 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1433 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1435 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1436 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1437 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1441 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1443 return param == chan->device->dev;
1446 static struct pxa2xx_spi_master *
1447 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1449 struct pxa2xx_spi_master *pdata;
1450 struct acpi_device *adev;
1451 struct ssp_device *ssp;
1452 struct resource *res;
1453 const struct acpi_device_id *adev_id = NULL;
1454 const struct pci_device_id *pcidev_id = NULL;
1457 adev = ACPI_COMPANION(&pdev->dev);
1459 if (dev_is_pci(pdev->dev.parent))
1460 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1461 to_pci_dev(pdev->dev.parent));
1463 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1469 type = (int)adev_id->driver_data;
1471 type = (int)pcidev_id->driver_data;
1475 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1479 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1485 ssp->phys_base = res->start;
1486 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1487 if (IS_ERR(ssp->mmio_base))
1491 pdata->tx_param = pdev->dev.parent;
1492 pdata->rx_param = pdev->dev.parent;
1493 pdata->dma_filter = pxa2xx_spi_idma_filter;
1496 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1497 if (IS_ERR(ssp->clk))
1500 ssp->irq = platform_get_irq(pdev, 0);
1506 ssp->port_id = pxa2xx_spi_get_port_id(adev);
1508 pdata->num_chipselect = 1;
1509 pdata->enable_dma = true;
1514 #else /* !CONFIG_PCI */
1515 static inline struct pxa2xx_spi_master *
1516 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1522 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *master,
1525 struct driver_data *drv_data = spi_controller_get_devdata(master);
1527 if (has_acpi_companion(&drv_data->pdev->dev)) {
1528 switch (drv_data->ssp_type) {
1530 * For Atoms the ACPI DeviceSelection used by the Windows
1531 * driver starts from 1 instead of 0 so translate it here
1532 * to match what Linux expects.
1546 static int pxa2xx_spi_probe(struct platform_device *pdev)
1548 struct device *dev = &pdev->dev;
1549 struct pxa2xx_spi_master *platform_info;
1550 struct spi_controller *master;
1551 struct driver_data *drv_data;
1552 struct ssp_device *ssp;
1553 const struct lpss_config *config;
1557 platform_info = dev_get_platdata(dev);
1558 if (!platform_info) {
1559 platform_info = pxa2xx_spi_init_pdata(pdev);
1560 if (!platform_info) {
1561 dev_err(&pdev->dev, "missing platform data\n");
1566 ssp = pxa_ssp_request(pdev->id, pdev->name);
1568 ssp = &platform_info->ssp;
1570 if (!ssp->mmio_base) {
1571 dev_err(&pdev->dev, "failed to get ssp\n");
1575 master = devm_spi_alloc_master(dev, sizeof(*drv_data));
1577 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1581 drv_data = spi_controller_get_devdata(master);
1582 drv_data->master = master;
1583 drv_data->master_info = platform_info;
1584 drv_data->pdev = pdev;
1585 drv_data->ssp = ssp;
1587 master->dev.of_node = pdev->dev.of_node;
1588 /* the spi->mode bits understood by this driver: */
1589 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1591 master->bus_num = ssp->port_id;
1592 master->dma_alignment = DMA_ALIGNMENT;
1593 master->cleanup = cleanup;
1594 master->setup = setup;
1595 master->set_cs = pxa2xx_spi_set_cs;
1596 master->transfer_one = pxa2xx_spi_transfer_one;
1597 master->handle_err = pxa2xx_spi_handle_err;
1598 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1599 master->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1600 master->auto_runtime_pm = true;
1601 master->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1603 drv_data->ssp_type = ssp->type;
1605 drv_data->ioaddr = ssp->mmio_base;
1606 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1607 if (pxa25x_ssp_comp(drv_data)) {
1608 switch (drv_data->ssp_type) {
1609 case QUARK_X1000_SSP:
1610 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1613 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1617 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1618 drv_data->dma_cr1 = 0;
1619 drv_data->clear_sr = SSSR_ROR;
1620 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1622 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1623 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1624 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1625 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1626 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1629 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1632 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1633 goto out_error_master_alloc;
1636 /* Setup DMA if requested */
1637 if (platform_info->enable_dma) {
1638 status = pxa2xx_spi_dma_setup(drv_data);
1640 dev_dbg(dev, "no DMA channels available, using PIO\n");
1641 platform_info->enable_dma = false;
1643 master->can_dma = pxa2xx_spi_can_dma;
1644 master->max_dma_len = MAX_DMA_LEN;
1648 /* Enable SOC clock */
1649 status = clk_prepare_enable(ssp->clk);
1651 goto out_error_dma_irq_alloc;
1653 master->max_speed_hz = clk_get_rate(ssp->clk);
1655 /* Load default SSP configuration */
1656 pxa2xx_spi_write(drv_data, SSCR0, 0);
1657 switch (drv_data->ssp_type) {
1658 case QUARK_X1000_SSP:
1659 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1660 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1661 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1663 /* using the Motorola SPI protocol and use 8 bit frame */
1664 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1665 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1668 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1669 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1670 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1671 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1672 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1675 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1676 SSCR1_TxTresh(TX_THRESH_DFLT);
1677 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1678 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1679 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1683 if (!pxa25x_ssp_comp(drv_data))
1684 pxa2xx_spi_write(drv_data, SSTO, 0);
1686 if (!is_quark_x1000_ssp(drv_data))
1687 pxa2xx_spi_write(drv_data, SSPSP, 0);
1689 if (is_lpss_ssp(drv_data)) {
1690 lpss_ssp_setup(drv_data);
1691 config = lpss_get_config(drv_data);
1692 if (config->reg_capabilities >= 0) {
1693 tmp = __lpss_ssp_read_priv(drv_data,
1694 config->reg_capabilities);
1695 tmp &= LPSS_CAPS_CS_EN_MASK;
1696 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1697 platform_info->num_chipselect = ffz(tmp);
1698 } else if (config->cs_num) {
1699 platform_info->num_chipselect = config->cs_num;
1702 master->num_chipselect = platform_info->num_chipselect;
1704 count = gpiod_count(&pdev->dev, "cs");
1708 master->num_chipselect = max_t(int, count,
1709 master->num_chipselect);
1711 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1712 master->num_chipselect, sizeof(struct gpio_desc *),
1714 if (!drv_data->cs_gpiods) {
1716 goto out_error_clock_enabled;
1719 for (i = 0; i < master->num_chipselect; i++) {
1720 struct gpio_desc *gpiod;
1722 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1723 if (IS_ERR(gpiod)) {
1724 /* Means use native chip select */
1725 if (PTR_ERR(gpiod) == -ENOENT)
1728 status = (int)PTR_ERR(gpiod);
1729 goto out_error_clock_enabled;
1731 drv_data->cs_gpiods[i] = gpiod;
1736 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1737 pm_runtime_use_autosuspend(&pdev->dev);
1738 pm_runtime_set_active(&pdev->dev);
1739 pm_runtime_enable(&pdev->dev);
1741 /* Register with the SPI framework */
1742 platform_set_drvdata(pdev, drv_data);
1743 status = spi_register_controller(master);
1745 dev_err(&pdev->dev, "problem registering spi master\n");
1746 goto out_error_pm_runtime_enabled;
1751 out_error_pm_runtime_enabled:
1752 pm_runtime_disable(&pdev->dev);
1754 out_error_clock_enabled:
1755 clk_disable_unprepare(ssp->clk);
1757 out_error_dma_irq_alloc:
1758 pxa2xx_spi_dma_release(drv_data);
1759 free_irq(ssp->irq, drv_data);
1761 out_error_master_alloc:
1766 static int pxa2xx_spi_remove(struct platform_device *pdev)
1768 struct driver_data *drv_data = platform_get_drvdata(pdev);
1769 struct ssp_device *ssp;
1773 ssp = drv_data->ssp;
1775 pm_runtime_get_sync(&pdev->dev);
1777 spi_unregister_controller(drv_data->master);
1779 /* Disable the SSP at the peripheral and SOC level */
1780 pxa2xx_spi_write(drv_data, SSCR0, 0);
1781 clk_disable_unprepare(ssp->clk);
1784 if (drv_data->master_info->enable_dma)
1785 pxa2xx_spi_dma_release(drv_data);
1787 pm_runtime_put_noidle(&pdev->dev);
1788 pm_runtime_disable(&pdev->dev);
1791 free_irq(ssp->irq, drv_data);
1799 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1803 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1804 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1807 #ifdef CONFIG_PM_SLEEP
1808 static int pxa2xx_spi_suspend(struct device *dev)
1810 struct driver_data *drv_data = dev_get_drvdata(dev);
1811 struct ssp_device *ssp = drv_data->ssp;
1814 status = spi_controller_suspend(drv_data->master);
1817 pxa2xx_spi_write(drv_data, SSCR0, 0);
1819 if (!pm_runtime_suspended(dev))
1820 clk_disable_unprepare(ssp->clk);
1825 static int pxa2xx_spi_resume(struct device *dev)
1827 struct driver_data *drv_data = dev_get_drvdata(dev);
1828 struct ssp_device *ssp = drv_data->ssp;
1831 /* Enable the SSP clock */
1832 if (!pm_runtime_suspended(dev)) {
1833 status = clk_prepare_enable(ssp->clk);
1838 /* Restore LPSS private register bits */
1839 if (is_lpss_ssp(drv_data))
1840 lpss_ssp_setup(drv_data);
1842 /* Start the queue running */
1843 status = spi_controller_resume(drv_data->master);
1845 dev_err(dev, "problem starting queue (%d)\n", status);
1854 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1856 struct driver_data *drv_data = dev_get_drvdata(dev);
1858 clk_disable_unprepare(drv_data->ssp->clk);
1862 static int pxa2xx_spi_runtime_resume(struct device *dev)
1864 struct driver_data *drv_data = dev_get_drvdata(dev);
1867 status = clk_prepare_enable(drv_data->ssp->clk);
1872 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1873 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1874 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1875 pxa2xx_spi_runtime_resume, NULL)
1878 static struct platform_driver driver = {
1880 .name = "pxa2xx-spi",
1881 .pm = &pxa2xx_spi_pm_ops,
1882 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1884 .probe = pxa2xx_spi_probe,
1885 .remove = pxa2xx_spi_remove,
1886 .shutdown = pxa2xx_spi_shutdown,
1889 static int __init pxa2xx_spi_init(void)
1891 return platform_driver_register(&driver);
1893 subsys_initcall(pxa2xx_spi_init);
1895 static void __exit pxa2xx_spi_exit(void)
1897 platform_driver_unregister(&driver);
1899 module_exit(pxa2xx_spi_exit);