drivers/spi/spi-s3c64xx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright (c) 2009 Samsung Electronics Co., Ltd.
   4 //      Jaswinder Singh <jassi.brar@samsung.com>
   5
   6 #include <linux/init.h>
   7 #include <linux/module.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/delay.h>
  10 #include <linux/clk.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/spi/spi.h>
  16 #include <linux/gpio.h>
  17 #include <linux/of.h>
  18 #include <linux/of_gpio.h>
  19
  20 #include <linux/platform_data/spi-s3c64xx.h>
  21
  22 #define MAX_SPI_PORTS           6
  23 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
  24 #define S3C64XX_SPI_QUIRK_CS_AUTO       (1 << 1)
  25 #define AUTOSUSPEND_TIMEOUT     2000
  26
  27 /* Registers and bit-fields */
  28
  29 #define S3C64XX_SPI_CH_CFG              0x00
  30 #define S3C64XX_SPI_CLK_CFG             0x04
  31 #define S3C64XX_SPI_MODE_CFG            0x08
  32 #define S3C64XX_SPI_SLAVE_SEL           0x0C
  33 #define S3C64XX_SPI_INT_EN              0x10
  34 #define S3C64XX_SPI_STATUS              0x14
  35 #define S3C64XX_SPI_TX_DATA             0x18
  36 #define S3C64XX_SPI_RX_DATA             0x1C
  37 #define S3C64XX_SPI_PACKET_CNT          0x20
  38 #define S3C64XX_SPI_PENDING_CLR         0x24
  39 #define S3C64XX_SPI_SWAP_CFG            0x28
  40 #define S3C64XX_SPI_FB_CLK              0x2C
  41
  42 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  43 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  44 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  45 #define S3C64XX_SPI_CPOL_L              (1<<3)
  46 #define S3C64XX_SPI_CPHA_B              (1<<2)
  47 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  48 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  49
  50 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  51 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  52 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  53 #define S3C64XX_SPI_PSR_MASK            0xff
  54
  55 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  56 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  57 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  58 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  59 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  60 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  61 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  62 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  63 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  64 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  65 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  66
  67 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  68 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  69 #define S3C64XX_SPI_SLAVE_NSC_CNT_2             (2<<4)
  70
  71 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  72 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  73 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  74 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  75 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  76 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  77 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  78
  79 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  80 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR          (1<<4)
  81 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  82 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR          (1<<2)
  83 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  84 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
  85
  86 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
  87 #define S3C64XX_SPI_PACKET_CNT_MASK             GENMASK(15, 0)
  88
  89 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
  90 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
  91 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
  92 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
  93 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
  94
  95 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
  96 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
  97 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
  98 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
  99 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 100 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 101 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 102 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 103
 104 #define S3C64XX_SPI_FBCLK_MSK                   (3<<0)
 105
 106 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 107 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 108                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 109 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 110 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 111                                         FIFO_LVL_MASK(i))
 112
 113 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 114 #define S3C64XX_SPI_TRAILCNT_OFF        19
 115
 116 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 117
 118 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 119 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
 120
 121 #define RXBUSY    (1<<2)
 122 #define TXBUSY    (1<<3)
 123
 124 struct s3c64xx_spi_dma_data {
 125         struct dma_chan *ch;
 126         dma_cookie_t cookie;
 127         enum dma_transfer_direction direction;
 128 };
 129
 130 /**
 131  * struct s3c64xx_spi_info - SPI Controller hardware info
 132  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 133  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 134  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 135  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 136  * @clk_from_cmu: True, if the controller does not include a clock mux and
 137  *      prescaler unit.
 138  *
 139  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 140  * differ in some aspects such as the size of the fifo and spi bus clock
 141  * setup. Such differences are specified to the driver using this structure
 142  * which is provided as driver data to the driver.
 143  */
 144 struct s3c64xx_spi_port_config {
 145         int     fifo_lvl_mask[MAX_SPI_PORTS];
 146         int     rx_lvl_offset;
 147         int     tx_st_done;
 148         int     quirks;
 149         bool    high_speed;
 150         bool    clk_from_cmu;
 151         bool    clk_ioclk;
 152 };
 153
 154 /**
 155  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 156  * @clk: Pointer to the spi clock.
 157  * @src_clk: Pointer to the clock used to generate SPI signals.
 158  * @ioclk: Pointer to the i/o clock between master and slave
 159  * @master: Pointer to the SPI Protocol master.
 160  * @cntrlr_info: Platform specific data for the controller this driver manages.
 161  * @lock: Controller specific lock.
 162  * @state: Set of FLAGS to indicate status.
 163  * @rx_dmach: Controller's DMA channel for Rx.
 164  * @tx_dmach: Controller's DMA channel for Tx.
 165  * @sfr_start: BUS address of SPI controller regs.
 166  * @regs: Pointer to ioremap'ed controller registers.
 167  * @irq: interrupt
 168  * @xfer_completion: To indicate completion of xfer task.
 169  * @cur_mode: Stores the active configuration of the controller.
 170  * @cur_bpw: Stores the active bits per word settings.
 171  * @cur_speed: Stores the active xfer clock speed.
 172  */
 173 struct s3c64xx_spi_driver_data {
 174         void __iomem                    *regs;
 175         struct clk                      *clk;
 176         struct clk                      *src_clk;
 177         struct clk                      *ioclk;
 178         struct platform_device          *pdev;
 179         struct spi_master               *master;
 180         struct s3c64xx_spi_info  *cntrlr_info;
 181         spinlock_t                      lock;
 182         unsigned long                   sfr_start;
 183         struct completion               xfer_completion;
 184         unsigned                        state;
 185         unsigned                        cur_mode, cur_bpw;
 186         unsigned                        cur_speed;
 187         struct s3c64xx_spi_dma_data     rx_dma;
 188         struct s3c64xx_spi_dma_data     tx_dma;
 189         struct s3c64xx_spi_port_config  *port_conf;
 190         unsigned int                    port_id;
 191 };
 192
 193 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 194 {
 195         void __iomem *regs = sdd->regs;
 196         unsigned long loops;
 197         u32 val;
 198
 199         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 200
 201         val = readl(regs + S3C64XX_SPI_CH_CFG);
 202         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 203         writel(val, regs + S3C64XX_SPI_CH_CFG);
 204
 205         val = readl(regs + S3C64XX_SPI_CH_CFG);
 206         val |= S3C64XX_SPI_CH_SW_RST;
 207         val &= ~S3C64XX_SPI_CH_HS_EN;
 208         writel(val, regs + S3C64XX_SPI_CH_CFG);
 209
 210         /* Flush TxFIFO*/
 211         loops = msecs_to_loops(1);
 212         do {
 213                 val = readl(regs + S3C64XX_SPI_STATUS);
 214         } while (TX_FIFO_LVL(val, sdd) && loops--);
 215
 216         if (loops == 0)
 217                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 218
 219         /* Flush RxFIFO*/
 220         loops = msecs_to_loops(1);
 221         do {
 222                 val = readl(regs + S3C64XX_SPI_STATUS);
 223                 if (RX_FIFO_LVL(val, sdd))
 224                         readl(regs + S3C64XX_SPI_RX_DATA);
 225                 else
 226                         break;
 227         } while (loops--);
 228
 229         if (loops == 0)
 230                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 231
 232         val = readl(regs + S3C64XX_SPI_CH_CFG);
 233         val &= ~S3C64XX_SPI_CH_SW_RST;
 234         writel(val, regs + S3C64XX_SPI_CH_CFG);
 235
 236         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 237         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 238         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 239 }
 240
 241 static void s3c64xx_spi_dmacb(void *data)
 242 {
 243         struct s3c64xx_spi_driver_data *sdd;
 244         struct s3c64xx_spi_dma_data *dma = data;
 245         unsigned long flags;
 246
 247         if (dma->direction == DMA_DEV_TO_MEM)
 248                 sdd = container_of(data,
 249                         struct s3c64xx_spi_driver_data, rx_dma);
 250         else
 251                 sdd = container_of(data,
 252                         struct s3c64xx_spi_driver_data, tx_dma);
 253
 254         spin_lock_irqsave(&sdd->lock, flags);
 255
 256         if (dma->direction == DMA_DEV_TO_MEM) {
 257                 sdd->state &= ~RXBUSY;
 258                 if (!(sdd->state & TXBUSY))
 259                         complete(&sdd->xfer_completion);
 260         } else {
 261                 sdd->state &= ~TXBUSY;
 262                 if (!(sdd->state & RXBUSY))
 263                         complete(&sdd->xfer_completion);
 264         }
 265
 266         spin_unlock_irqrestore(&sdd->lock, flags);
 267 }
 268
 269 static int prepare_dma(struct s3c64xx_spi_dma_data *dma,
 270                         struct sg_table *sgt)
 271 {
 272         struct s3c64xx_spi_driver_data *sdd;
 273         struct dma_slave_config config;
 274         struct dma_async_tx_descriptor *desc;
 275         int ret;
 276
 277         memset(&config, 0, sizeof(config));
 278
 279         if (dma->direction == DMA_DEV_TO_MEM) {
 280                 sdd = container_of((void *)dma,
 281                         struct s3c64xx_spi_driver_data, rx_dma);
 282                 config.direction = dma->direction;
 283                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 284                 config.src_addr_width = sdd->cur_bpw / 8;
 285                 config.src_maxburst = 1;
 286                 dmaengine_slave_config(dma->ch, &config);
 287         } else {
 288                 sdd = container_of((void *)dma,
 289                         struct s3c64xx_spi_driver_data, tx_dma);
 290                 config.direction = dma->direction;
 291                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 292                 config.dst_addr_width = sdd->cur_bpw / 8;
 293                 config.dst_maxburst = 1;
 294                 dmaengine_slave_config(dma->ch, &config);
 295         }
 296
 297         desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
 298                                        dma->direction, DMA_PREP_INTERRUPT);
 299         if (!desc) {
 300                 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
 301                         dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
 302                 return -ENOMEM;
 303         }
 304
 305         desc->callback = s3c64xx_spi_dmacb;
 306         desc->callback_param = dma;
 307
 308         dma->cookie = dmaengine_submit(desc);
 309         ret = dma_submit_error(dma->cookie);
 310         if (ret) {
 311                 dev_err(&sdd->pdev->dev, "DMA submission failed");
 312                 return -EIO;
 313         }
 314
 315         dma_async_issue_pending(dma->ch);
 316         return 0;
 317 }
 318
 319 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
 320 {
 321         struct s3c64xx_spi_driver_data *sdd =
 322                                         spi_master_get_devdata(spi->master);
 323
 324         if (sdd->cntrlr_info->no_cs)
 325                 return;
 326
 327         if (enable) {
 328                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
 329                         writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 330                 } else {
 331                         u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 332
 333                         ssel |= (S3C64XX_SPI_SLAVE_AUTO |
 334                                                 S3C64XX_SPI_SLAVE_NSC_CNT_2);
 335                         writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 336                 }
 337         } else {
 338                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 339                         writel(S3C64XX_SPI_SLAVE_SIG_INACT,
 340                                sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 341         }
 342 }
 343
 344 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 345 {
 346         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 347
 348         if (is_polling(sdd))
 349                 return 0;
 350
 351         spi->dma_rx = sdd->rx_dma.ch;
 352         spi->dma_tx = sdd->tx_dma.ch;
 353
 354         return 0;
 355 }
 356
 357 static bool s3c64xx_spi_can_dma(struct spi_master *master,
 358                                 struct spi_device *spi,
 359                                 struct spi_transfer *xfer)
 360 {
 361         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 362
 363         return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
 364 }
 365
 366 static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 367                                     struct spi_transfer *xfer, int dma_mode)
 368 {
 369         void __iomem *regs = sdd->regs;
 370         u32 modecfg, chcfg;
 371         int ret = 0;
 372
 373         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 374         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 375
 376         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 377         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 378
 379         if (dma_mode) {
 380                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 381         } else {
 382                 /* Always shift in data in FIFO, even if xfer is Tx only,
 383                  * this helps setting PCKT_CNT value for generating clocks
 384                  * as exactly needed.
 385                  */
 386                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 387                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 388                                         | S3C64XX_SPI_PACKET_CNT_EN,
 389                                         regs + S3C64XX_SPI_PACKET_CNT);
 390         }
 391
 392         if (xfer->tx_buf != NULL) {
 393                 sdd->state |= TXBUSY;
 394                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 395                 if (dma_mode) {
 396                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 397                         ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
 398                 } else {
 399                         switch (sdd->cur_bpw) {
 400                         case 32:
 401                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 402                                         xfer->tx_buf, xfer->len / 4);
 403                                 break;
 404                         case 16:
 405                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 406                                         xfer->tx_buf, xfer->len / 2);
 407                                 break;
 408                         default:
 409                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 410                                         xfer->tx_buf, xfer->len);
 411                                 break;
 412                         }
 413                 }
 414         }
 415
 416         if (xfer->rx_buf != NULL) {
 417                 sdd->state |= RXBUSY;
 418
 419                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 420                                         && !(sdd->cur_mode & SPI_CPHA))
 421                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 422
 423                 if (dma_mode) {
 424                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 425                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 426                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 427                                         | S3C64XX_SPI_PACKET_CNT_EN,
 428                                         regs + S3C64XX_SPI_PACKET_CNT);
 429                         ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
 430                 }
 431         }
 432
 433         if (ret)
 434                 return ret;
 435
 436         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 437         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 438
 439         return 0;
 440 }
 441
 442 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
 443                                         int timeout_ms)
 444 {
 445         void __iomem *regs = sdd->regs;
 446         unsigned long val = 1;
 447         u32 status;
 448
 449         /* max fifo depth available */
 450         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 451
 452         if (timeout_ms)
 453                 val = msecs_to_loops(timeout_ms);
 454
 455         do {
 456                 status = readl(regs + S3C64XX_SPI_STATUS);
 457         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
 458
 459         /* return the actual received data length */
 460         return RX_FIFO_LVL(status, sdd);
 461 }
 462
 463 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
 464                                 struct spi_transfer *xfer)
 465 {
 466         void __iomem *regs = sdd->regs;
 467         unsigned long val;
 468         u32 status;
 469         int ms;
 470
 471         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 472         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 473         ms += 10; /* some tolerance */
 474
 475         val = msecs_to_jiffies(ms) + 10;
 476         val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 477
 478         /*
 479          * If the previous xfer was completed within timeout, then
 480          * proceed further else return -EIO.
 481          * DmaTx returns after simply writing data in the FIFO,
 482          * w/o waiting for real transmission on the bus to finish.
 483          * DmaRx returns only after Dma read data from FIFO which
 484          * needs bus transmission to finish, so we don't worry if
 485          * Xfer involved Rx(with or without Tx).
 486          */
 487         if (val && !xfer->rx_buf) {
 488                 val = msecs_to_loops(10);
 489                 status = readl(regs + S3C64XX_SPI_STATUS);
 490                 while ((TX_FIFO_LVL(status, sdd)
 491                         || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 492                        && --val) {
 493                         cpu_relax();
 494                         status = readl(regs + S3C64XX_SPI_STATUS);
 495                 }
 496
 497         }
 498
 499         /* If timed out while checking rx/tx status return error */
 500         if (!val)
 501                 return -EIO;
 502
 503         return 0;
 504 }
 505
 506 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
 507                                 struct spi_transfer *xfer)
 508 {
 509         void __iomem *regs = sdd->regs;
 510         unsigned long val;
 511         u32 status;
 512         int loops;
 513         u32 cpy_len;
 514         u8 *buf;
 515         int ms;
 516
 517         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 518         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 519         ms += 10; /* some tolerance */
 520
 521         val = msecs_to_loops(ms);
 522         do {
 523                 status = readl(regs + S3C64XX_SPI_STATUS);
 524         } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 525
 526         if (!val)
 527                 return -EIO;
 528
 529         /* If it was only Tx */
 530         if (!xfer->rx_buf) {
 531                 sdd->state &= ~TXBUSY;
 532                 return 0;
 533         }
 534
 535         /*
 536          * If the receive length is bigger than the controller fifo
 537          * size, calculate the loops and read the fifo as many times.
 538          * loops = length / max fifo size (calculated by using the
 539          * fifo mask).
 540          * For any size less than the fifo size the below code is
 541          * executed atleast once.
 542          */
 543         loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
 544         buf = xfer->rx_buf;
 545         do {
 546                 /* wait for data to be received in the fifo */
 547                 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
 548                                                        (loops ? ms : 0));
 549
 550                 switch (sdd->cur_bpw) {
 551                 case 32:
 552                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 553                                      buf, cpy_len / 4);
 554                         break;
 555                 case 16:
 556                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 557                                      buf, cpy_len / 2);
 558                         break;
 559                 default:
 560                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 561                                     buf, cpy_len);
 562                         break;
 563                 }
 564
 565                 buf = buf + cpy_len;
 566         } while (loops--);
 567         sdd->state &= ~RXBUSY;
 568
 569         return 0;
 570 }
 571
 572 static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 573 {
 574         void __iomem *regs = sdd->regs;
 575         int ret;
 576         u32 val;
 577
 578         /* Disable Clock */
 579         if (!sdd->port_conf->clk_from_cmu) {
 580                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 581                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 582                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 583         }
 584
 585         /* Set Polarity and Phase */
 586         val = readl(regs + S3C64XX_SPI_CH_CFG);
 587         val &= ~(S3C64XX_SPI_CH_SLAVE |
 588                         S3C64XX_SPI_CPOL_L |
 589                         S3C64XX_SPI_CPHA_B);
 590
 591         if (sdd->cur_mode & SPI_CPOL)
 592                 val |= S3C64XX_SPI_CPOL_L;
 593
 594         if (sdd->cur_mode & SPI_CPHA)
 595                 val |= S3C64XX_SPI_CPHA_B;
 596
 597         writel(val, regs + S3C64XX_SPI_CH_CFG);
 598
 599         /* Set Channel & DMA Mode */
 600         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 601         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 602                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 603
 604         switch (sdd->cur_bpw) {
 605         case 32:
 606                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 607                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 608                 break;
 609         case 16:
 610                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 611                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 612                 break;
 613         default:
 614                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 615                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 616                 break;
 617         }
 618
 619         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 620
 621         if (sdd->port_conf->clk_from_cmu) {
 622                 /* The src_clk clock is divided internally by 2 */
 623                 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 624                 if (ret)
 625                         return ret;
 626         } else {
 627                 /* Configure Clock */
 628                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 629                 val &= ~S3C64XX_SPI_PSR_MASK;
 630                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 631                                 & S3C64XX_SPI_PSR_MASK);
 632                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 633
 634                 /* Enable Clock */
 635                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 636                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 637                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 638         }
 639
 640         return 0;
 641 }
 642
 643 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 644
 645 static int s3c64xx_spi_prepare_message(struct spi_master *master,
 646                                        struct spi_message *msg)
 647 {
 648         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 649         struct spi_device *spi = msg->spi;
 650         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 651
 652         /* Configure feedback delay */
 653         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 654
 655         return 0;
 656 }
 657
 658 static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
 659 {
 660         struct spi_controller *ctlr = spi->controller;
 661
 662         return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
 663 }
 664
 665 static int s3c64xx_spi_transfer_one(struct spi_master *master,
 666                                     struct spi_device *spi,
 667                                     struct spi_transfer *xfer)
 668 {
 669         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 670         const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 671         const void *tx_buf = NULL;
 672         void *rx_buf = NULL;
 673         int target_len = 0, origin_len = 0;
 674         int use_dma = 0;
 675         int status;
 676         u32 speed;
 677         u8 bpw;
 678         unsigned long flags;
 679
 680         reinit_completion(&sdd->xfer_completion);
 681
 682         /* Only BPW and Speed may change across transfers */
 683         bpw = xfer->bits_per_word;
 684         speed = xfer->speed_hz;
 685
 686         if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 687                 sdd->cur_bpw = bpw;
 688                 sdd->cur_speed = speed;
 689                 sdd->cur_mode = spi->mode;
 690                 status = s3c64xx_spi_config(sdd);
 691                 if (status)
 692                         return status;
 693         }
 694
 695         if (!is_polling(sdd) && (xfer->len > fifo_len) &&
 696             sdd->rx_dma.ch && sdd->tx_dma.ch) {
 697                 use_dma = 1;
 698
 699         } else if (is_polling(sdd) && xfer->len > fifo_len) {
 700                 tx_buf = xfer->tx_buf;
 701                 rx_buf = xfer->rx_buf;
 702                 origin_len = xfer->len;
 703
 704                 target_len = xfer->len;
 705                 if (xfer->len > fifo_len)
 706                         xfer->len = fifo_len;
 707         }
 708
 709         do {
 710                 spin_lock_irqsave(&sdd->lock, flags);
 711
 712                 /* Pending only which is to be done */
 713                 sdd->state &= ~RXBUSY;
 714                 sdd->state &= ~TXBUSY;
 715
 716                 /* Start the signals */
 717                 s3c64xx_spi_set_cs(spi, true);
 718
 719                 status = s3c64xx_enable_datapath(sdd, xfer, use_dma);
 720
 721                 spin_unlock_irqrestore(&sdd->lock, flags);
 722
 723                 if (status) {
 724                         dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
 725                         break;
 726                 }
 727
 728                 if (use_dma)
 729                         status = s3c64xx_wait_for_dma(sdd, xfer);
 730                 else
 731                         status = s3c64xx_wait_for_pio(sdd, xfer);
 732
 733                 if (status) {
 734                         dev_err(&spi->dev,
 735                                 "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 736                                 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 737                                 (sdd->state & RXBUSY) ? 'f' : 'p',
 738                                 (sdd->state & TXBUSY) ? 'f' : 'p',
 739                                 xfer->len);
 740
 741                         if (use_dma) {
 742                                 if (xfer->tx_buf && (sdd->state & TXBUSY))
 743                                         dmaengine_terminate_all(sdd->tx_dma.ch);
 744                                 if (xfer->rx_buf && (sdd->state & RXBUSY))
 745                                         dmaengine_terminate_all(sdd->rx_dma.ch);
 746                         }
 747                 } else {
 748                         s3c64xx_flush_fifo(sdd);
 749                 }
 750                 if (target_len > 0) {
 751                         target_len -= xfer->len;
 752
 753                         if (xfer->tx_buf)
 754                                 xfer->tx_buf += xfer->len;
 755
 756                         if (xfer->rx_buf)
 757                                 xfer->rx_buf += xfer->len;
 758
 759                         if (target_len > fifo_len)
 760                                 xfer->len = fifo_len;
 761                         else
 762                                 xfer->len = target_len;
 763                 }
 764         } while (target_len > 0);
 765
 766         if (origin_len) {
 767                 /* Restore original xfer buffers and length */
 768                 xfer->tx_buf = tx_buf;
 769                 xfer->rx_buf = rx_buf;
 770                 xfer->len = origin_len;
 771         }
 772
 773         return status;
 774 }
 775
 776 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 777                                 struct spi_device *spi)
 778 {
 779         struct s3c64xx_spi_csinfo *cs;
 780         struct device_node *slave_np, *data_np = NULL;
 781         u32 fb_delay = 0;
 782
 783         slave_np = spi->dev.of_node;
 784         if (!slave_np) {
 785                 dev_err(&spi->dev, "device node not found\n");
 786                 return ERR_PTR(-EINVAL);
 787         }
 788
 789         data_np = of_get_child_by_name(slave_np, "controller-data");
 790         if (!data_np) {
 791                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
 792                 return ERR_PTR(-EINVAL);
 793         }
 794
 795         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 796         if (!cs) {
 797                 of_node_put(data_np);
 798                 return ERR_PTR(-ENOMEM);
 799         }
 800
 801         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
 802         cs->fb_delay = fb_delay;
 803         of_node_put(data_np);
 804         return cs;
 805 }
 806
 807 /*
 808  * Here we only check the validity of requested configuration
 809  * and save the configuration in a local data-structure.
 810  * The controller is actually configured only just before we
 811  * get a message to transfer.
 812  */
 813 static int s3c64xx_spi_setup(struct spi_device *spi)
 814 {
 815         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 816         struct s3c64xx_spi_driver_data *sdd;
 817         int err;
 818
 819         sdd = spi_master_get_devdata(spi->master);
 820         if (spi->dev.of_node) {
 821                 cs = s3c64xx_get_slave_ctrldata(spi);
 822                 spi->controller_data = cs;
 823         } else if (cs) {
 824                 /* On non-DT platforms the SPI core will set spi->cs_gpio
 825                  * to -ENOENT. The GPIO pin used to drive the chip select
 826                  * is defined by using platform data so spi->cs_gpio value
 827                  * has to be override to have the proper GPIO pin number.
 828                  */
 829                 spi->cs_gpio = cs->line;
 830         }
 831
 832         if (IS_ERR_OR_NULL(cs)) {
 833                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 834                 return -ENODEV;
 835         }
 836
 837         if (!spi_get_ctldata(spi)) {
 838                 if (gpio_is_valid(spi->cs_gpio)) {
 839                         err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
 840                                                dev_name(&spi->dev));
 841                         if (err) {
 842                                 dev_err(&spi->dev,
 843                                         "Failed to get /CS gpio [%d]: %d\n",
 844                                         spi->cs_gpio, err);
 845                                 goto err_gpio_req;
 846                         }
 847                 }
 848
 849                 spi_set_ctldata(spi, cs);
 850         }
 851
 852         pm_runtime_get_sync(&sdd->pdev->dev);
 853
 854         /* Check if we can provide the requested rate */
 855         if (!sdd->port_conf->clk_from_cmu) {
 856                 u32 psr, speed;
 857
 858                 /* Max possible */
 859                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 860
 861                 if (spi->max_speed_hz > speed)
 862                         spi->max_speed_hz = speed;
 863
 864                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 865                 psr &= S3C64XX_SPI_PSR_MASK;
 866                 if (psr == S3C64XX_SPI_PSR_MASK)
 867                         psr--;
 868
 869                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 870                 if (spi->max_speed_hz < speed) {
 871                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 872                                 psr++;
 873                         } else {
 874                                 err = -EINVAL;
 875                                 goto setup_exit;
 876                         }
 877                 }
 878
 879                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 880                 if (spi->max_speed_hz >= speed) {
 881                         spi->max_speed_hz = speed;
 882                 } else {
 883                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
 884                                 spi->max_speed_hz);
 885                         err = -EINVAL;
 886                         goto setup_exit;
 887                 }
 888         }
 889
 890         pm_runtime_mark_last_busy(&sdd->pdev->dev);
 891         pm_runtime_put_autosuspend(&sdd->pdev->dev);
 892         s3c64xx_spi_set_cs(spi, false);
 893
 894         return 0;
 895
 896 setup_exit:
 897         pm_runtime_mark_last_busy(&sdd->pdev->dev);
 898         pm_runtime_put_autosuspend(&sdd->pdev->dev);
 899         /* setup() returns with device de-selected */
 900         s3c64xx_spi_set_cs(spi, false);
 901
 902         if (gpio_is_valid(spi->cs_gpio))
 903                 gpio_free(spi->cs_gpio);
 904         spi_set_ctldata(spi, NULL);
 905
 906 err_gpio_req:
 907         if (spi->dev.of_node)
 908                 kfree(cs);
 909
 910         return err;
 911 }
 912
 913 static void s3c64xx_spi_cleanup(struct spi_device *spi)
 914 {
 915         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
 916
 917         if (gpio_is_valid(spi->cs_gpio)) {
 918                 gpio_free(spi->cs_gpio);
 919                 if (spi->dev.of_node)
 920                         kfree(cs);
 921                 else {
 922                         /* On non-DT platforms, the SPI core sets
 923                          * spi->cs_gpio to -ENOENT and .setup()
 924                          * overrides it with the GPIO pin value
 925                          * passed using platform data.
 926                          */
 927                         spi->cs_gpio = -ENOENT;
 928                 }
 929         }
 930
 931         spi_set_ctldata(spi, NULL);
 932 }
 933
 934 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 935 {
 936         struct s3c64xx_spi_driver_data *sdd = data;
 937         struct spi_master *spi = sdd->master;
 938         unsigned int val, clr = 0;
 939
 940         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
 941
 942         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
 943                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
 944                 dev_err(&spi->dev, "RX overrun\n");
 945         }
 946         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
 947                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
 948                 dev_err(&spi->dev, "RX underrun\n");
 949         }
 950         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
 951                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
 952                 dev_err(&spi->dev, "TX overrun\n");
 953         }
 954         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
 955                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 956                 dev_err(&spi->dev, "TX underrun\n");
 957         }
 958
 959         /* Clear the pending irq by setting and then clearing it */
 960         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 961         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 962
 963         return IRQ_HANDLED;
 964 }
 965
 966 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
 967 {
 968         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 969         void __iomem *regs = sdd->regs;
 970         unsigned int val;
 971
 972         sdd->cur_speed = 0;
 973
 974         if (sci->no_cs)
 975                 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 976         else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 977                 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 978
 979         /* Disable Interrupts - we use Polling if not DMA mode */
 980         writel(0, regs + S3C64XX_SPI_INT_EN);
 981
 982         if (!sdd->port_conf->clk_from_cmu)
 983                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
 984                                 regs + S3C64XX_SPI_CLK_CFG);
 985         writel(0, regs + S3C64XX_SPI_MODE_CFG);
 986         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 987
 988         /* Clear any irq pending bits, should set and clear the bits */
 989         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
 990                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
 991                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
 992                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 993         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
 994         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
 995
 996         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
 997
 998         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 999         val &= ~S3C64XX_SPI_MODE_4BURST;
1000         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1001         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1002         writel(val, regs + S3C64XX_SPI_MODE_CFG);
1003
1004         s3c64xx_flush_fifo(sdd);
1005 }
1006
1007 #ifdef CONFIG_OF
1008 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1009 {
1010         struct s3c64xx_spi_info *sci;
1011         u32 temp;
1012
1013         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1014         if (!sci)
1015                 return ERR_PTR(-ENOMEM);
1016
1017         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1018                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1019                 sci->src_clk_nr = 0;
1020         } else {
1021                 sci->src_clk_nr = temp;
1022         }
1023
1024         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1025                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1026                 sci->num_cs = 1;
1027         } else {
1028                 sci->num_cs = temp;
1029         }
1030
1031         sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
1032
1033         return sci;
1034 }
1035 #else
1036 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1037 {
1038         return dev_get_platdata(dev);
1039 }
1040 #endif
1041
1042 static const struct of_device_id s3c64xx_spi_dt_match[];
1043
1044 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1045                                                 struct platform_device *pdev)
1046 {
1047 #ifdef CONFIG_OF
1048         if (pdev->dev.of_node) {
1049                 const struct of_device_id *match;
1050                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1051                 return (struct s3c64xx_spi_port_config *)match->data;
1052         }
1053 #endif
1054         return (struct s3c64xx_spi_port_config *)
1055                          platform_get_device_id(pdev)->driver_data;
1056 }
1057
1058 static int s3c64xx_spi_probe(struct platform_device *pdev)
1059 {
1060         struct resource *mem_res;
1061         struct s3c64xx_spi_driver_data *sdd;
1062         struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1063         struct spi_master *master;
1064         int ret, irq;
1065         char clk_name[16];
1066
1067         if (!sci && pdev->dev.of_node) {
1068                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1069                 if (IS_ERR(sci))
1070                         return PTR_ERR(sci);
1071         }
1072
1073         if (!sci) {
1074                 dev_err(&pdev->dev, "platform_data missing!\n");
1075                 return -ENODEV;
1076         }
1077
1078         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1079         if (mem_res == NULL) {
1080                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1081                 return -ENXIO;
1082         }
1083
1084         irq = platform_get_irq(pdev, 0);
1085         if (irq < 0) {
1086                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1087                 return irq;
1088         }
1089
1090         master = spi_alloc_master(&pdev->dev,
1091                                 sizeof(struct s3c64xx_spi_driver_data));
1092         if (master == NULL) {
1093                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1094                 return -ENOMEM;
1095         }
1096
1097         platform_set_drvdata(pdev, master);
1098
1099         sdd = spi_master_get_devdata(master);
1100         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1101         sdd->master = master;
1102         sdd->cntrlr_info = sci;
1103         sdd->pdev = pdev;
1104         sdd->sfr_start = mem_res->start;
1105         if (pdev->dev.of_node) {
1106                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1107                 if (ret < 0) {
1108                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1109                                 ret);
1110                         goto err_deref_master;
1111                 }
1112                 sdd->port_id = ret;
1113         } else {
1114                 sdd->port_id = pdev->id;
1115         }
1116
1117         sdd->cur_bpw = 8;
1118
1119         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1120         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1121
1122         master->dev.of_node = pdev->dev.of_node;
1123         master->bus_num = sdd->port_id;
1124         master->setup = s3c64xx_spi_setup;
1125         master->cleanup = s3c64xx_spi_cleanup;
1126         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1127         master->prepare_message = s3c64xx_spi_prepare_message;
1128         master->transfer_one = s3c64xx_spi_transfer_one;
1129         master->max_transfer_size = s3c64xx_spi_max_transfer_size;
1130         master->num_chipselect = sci->num_cs;
1131         master->dma_alignment = 8;
1132         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1133                                         SPI_BPW_MASK(8);
1134         /* the spi->mode bits understood by this driver: */
1135         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1136         master->auto_runtime_pm = true;
1137         if (!is_polling(sdd))
1138                 master->can_dma = s3c64xx_spi_can_dma;
1139
1140         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1141         if (IS_ERR(sdd->regs)) {
1142                 ret = PTR_ERR(sdd->regs);
1143                 goto err_deref_master;
1144         }
1145
1146         if (sci->cfg_gpio && sci->cfg_gpio()) {
1147                 dev_err(&pdev->dev, "Unable to config gpio\n");
1148                 ret = -EBUSY;
1149                 goto err_deref_master;
1150         }
1151
1152         /* Setup clocks */
1153         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1154         if (IS_ERR(sdd->clk)) {
1155                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1156                 ret = PTR_ERR(sdd->clk);
1157                 goto err_deref_master;
1158         }
1159
1160         ret = clk_prepare_enable(sdd->clk);
1161         if (ret) {
1162                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1163                 goto err_deref_master;
1164         }
1165
1166         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1167         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1168         if (IS_ERR(sdd->src_clk)) {
1169                 dev_err(&pdev->dev,
1170                         "Unable to acquire clock '%s'\n", clk_name);
1171                 ret = PTR_ERR(sdd->src_clk);
1172                 goto err_disable_clk;
1173         }
1174
1175         ret = clk_prepare_enable(sdd->src_clk);
1176         if (ret) {
1177                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1178                 goto err_disable_clk;
1179         }
1180
1181         if (sdd->port_conf->clk_ioclk) {
1182                 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1183                 if (IS_ERR(sdd->ioclk)) {
1184                         dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1185                         ret = PTR_ERR(sdd->ioclk);
1186                         goto err_disable_src_clk;
1187                 }
1188
1189                 ret = clk_prepare_enable(sdd->ioclk);
1190                 if (ret) {
1191                         dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1192                         goto err_disable_src_clk;
1193                 }
1194         }
1195
1196         if (!is_polling(sdd)) {
1197                 /* Acquire DMA channels */
1198                 sdd->rx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1199                                                                   "rx");
1200                 if (IS_ERR(sdd->rx_dma.ch)) {
1201                         dev_err(&pdev->dev, "Failed to get RX DMA channel\n");
1202                         ret = PTR_ERR(sdd->rx_dma.ch);
1203                         goto err_disable_io_clk;
1204                 }
1205                 sdd->tx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1206                                                                   "tx");
1207                 if (IS_ERR(sdd->tx_dma.ch)) {
1208                         dev_err(&pdev->dev, "Failed to get TX DMA channel\n");
1209                         ret = PTR_ERR(sdd->tx_dma.ch);
1210                         goto err_release_rx_dma;
1211                 }
1212         }
1213
1214         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1215         pm_runtime_use_autosuspend(&pdev->dev);
1216         pm_runtime_set_active(&pdev->dev);
1217         pm_runtime_enable(&pdev->dev);
1218         pm_runtime_get_sync(&pdev->dev);
1219
1220         /* Setup Deufult Mode */
1221         s3c64xx_spi_hwinit(sdd);
1222
1223         spin_lock_init(&sdd->lock);
1224         init_completion(&sdd->xfer_completion);
1225
1226         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1227                                 "spi-s3c64xx", sdd);
1228         if (ret != 0) {
1229                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1230                         irq, ret);
1231                 goto err_pm_put;
1232         }
1233
1234         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1235                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1236                sdd->regs + S3C64XX_SPI_INT_EN);
1237
1238         ret = devm_spi_register_master(&pdev->dev, master);
1239         if (ret != 0) {
1240                 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1241                 goto err_pm_put;
1242         }
1243
1244         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1245                                         sdd->port_id, master->num_chipselect);
1246         dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1247                                         mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1248
1249         pm_runtime_mark_last_busy(&pdev->dev);
1250         pm_runtime_put_autosuspend(&pdev->dev);
1251
1252         return 0;
1253
1254 err_pm_put:
1255         pm_runtime_put_noidle(&pdev->dev);
1256         pm_runtime_disable(&pdev->dev);
1257         pm_runtime_set_suspended(&pdev->dev);
1258
1259         if (!is_polling(sdd))
1260                 dma_release_channel(sdd->tx_dma.ch);
1261 err_release_rx_dma:
1262         if (!is_polling(sdd))
1263                 dma_release_channel(sdd->rx_dma.ch);
1264 err_disable_io_clk:
1265         clk_disable_unprepare(sdd->ioclk);
1266 err_disable_src_clk:
1267         clk_disable_unprepare(sdd->src_clk);
1268 err_disable_clk:
1269         clk_disable_unprepare(sdd->clk);
1270 err_deref_master:
1271         spi_master_put(master);
1272
1273         return ret;
1274 }
1275
1276 static int s3c64xx_spi_remove(struct platform_device *pdev)
1277 {
1278         struct spi_master *master = platform_get_drvdata(pdev);
1279         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1280
1281         pm_runtime_get_sync(&pdev->dev);
1282
1283         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1284
1285         if (!is_polling(sdd)) {
1286                 dma_release_channel(sdd->rx_dma.ch);
1287                 dma_release_channel(sdd->tx_dma.ch);
1288         }
1289
1290         clk_disable_unprepare(sdd->ioclk);
1291
1292         clk_disable_unprepare(sdd->src_clk);
1293
1294         clk_disable_unprepare(sdd->clk);
1295
1296         pm_runtime_put_noidle(&pdev->dev);
1297         pm_runtime_disable(&pdev->dev);
1298         pm_runtime_set_suspended(&pdev->dev);
1299
1300         return 0;
1301 }
1302
1303 #ifdef CONFIG_PM_SLEEP
1304 static int s3c64xx_spi_suspend(struct device *dev)
1305 {
1306         struct spi_master *master = dev_get_drvdata(dev);
1307         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1308
1309         int ret = spi_master_suspend(master);
1310         if (ret)
1311                 return ret;
1312
1313         ret = pm_runtime_force_suspend(dev);
1314         if (ret < 0)
1315                 return ret;
1316
1317         sdd->cur_speed = 0; /* Output Clock is stopped */
1318
1319         return 0;
1320 }
1321
1322 static int s3c64xx_spi_resume(struct device *dev)
1323 {
1324         struct spi_master *master = dev_get_drvdata(dev);
1325         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1326         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1327         int ret;
1328
1329         if (sci->cfg_gpio)
1330                 sci->cfg_gpio();
1331
1332         ret = pm_runtime_force_resume(dev);
1333         if (ret < 0)
1334                 return ret;
1335
1336         return spi_master_resume(master);
1337 }
1338 #endif /* CONFIG_PM_SLEEP */
1339
1340 #ifdef CONFIG_PM
1341 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1342 {
1343         struct spi_master *master = dev_get_drvdata(dev);
1344         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1345
1346         clk_disable_unprepare(sdd->clk);
1347         clk_disable_unprepare(sdd->src_clk);
1348         clk_disable_unprepare(sdd->ioclk);
1349
1350         return 0;
1351 }
1352
1353 static int s3c64xx_spi_runtime_resume(struct device *dev)
1354 {
1355         struct spi_master *master = dev_get_drvdata(dev);
1356         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1357         int ret;
1358
1359         if (sdd->port_conf->clk_ioclk) {
1360                 ret = clk_prepare_enable(sdd->ioclk);
1361                 if (ret != 0)
1362                         return ret;
1363         }
1364
1365         ret = clk_prepare_enable(sdd->src_clk);
1366         if (ret != 0)
1367                 goto err_disable_ioclk;
1368
1369         ret = clk_prepare_enable(sdd->clk);
1370         if (ret != 0)
1371                 goto err_disable_src_clk;
1372
1373         s3c64xx_spi_hwinit(sdd);
1374
1375         return 0;
1376
1377 err_disable_src_clk:
1378         clk_disable_unprepare(sdd->src_clk);
1379 err_disable_ioclk:
1380         clk_disable_unprepare(sdd->ioclk);
1381
1382         return ret;
1383 }
1384 #endif /* CONFIG_PM */
1385
1386 static const struct dev_pm_ops s3c64xx_spi_pm = {
1387         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1388         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1389                            s3c64xx_spi_runtime_resume, NULL)
1390 };
1391
1392 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1393         .fifo_lvl_mask  = { 0x7f },
1394         .rx_lvl_offset  = 13,
1395         .tx_st_done     = 21,
1396         .high_speed     = true,
1397 };
1398
1399 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1400         .fifo_lvl_mask  = { 0x7f, 0x7F },
1401         .rx_lvl_offset  = 13,
1402         .tx_st_done     = 21,
1403 };
1404
1405 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1406         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1407         .rx_lvl_offset  = 15,
1408         .tx_st_done     = 25,
1409         .high_speed     = true,
1410 };
1411
1412 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1413         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1414         .rx_lvl_offset  = 15,
1415         .tx_st_done     = 25,
1416         .high_speed     = true,
1417         .clk_from_cmu   = true,
1418 };
1419
1420 static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1421         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1422         .rx_lvl_offset  = 15,
1423         .tx_st_done     = 25,
1424         .high_speed     = true,
1425         .clk_from_cmu   = true,
1426         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1427 };
1428
1429 static struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1430         .fifo_lvl_mask  = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1431         .rx_lvl_offset  = 15,
1432         .tx_st_done     = 25,
1433         .high_speed     = true,
1434         .clk_from_cmu   = true,
1435         .clk_ioclk      = true,
1436         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1437 };
1438
1439 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1440         {
1441                 .name           = "s3c2443-spi",
1442                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1443         }, {
1444                 .name           = "s3c6410-spi",
1445                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1446         },
1447         { },
1448 };
1449
1450 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1451         { .compatible = "samsung,s3c2443-spi",
1452                         .data = (void *)&s3c2443_spi_port_config,
1453         },
1454         { .compatible = "samsung,s3c6410-spi",
1455                         .data = (void *)&s3c6410_spi_port_config,
1456         },
1457         { .compatible = "samsung,s5pv210-spi",
1458                         .data = (void *)&s5pv210_spi_port_config,
1459         },
1460         { .compatible = "samsung,exynos4210-spi",
1461                         .data = (void *)&exynos4_spi_port_config,
1462         },
1463         { .compatible = "samsung,exynos7-spi",
1464                         .data = (void *)&exynos7_spi_port_config,
1465         },
1466         { .compatible = "samsung,exynos5433-spi",
1467                         .data = (void *)&exynos5433_spi_port_config,
1468         },
1469         { },
1470 };
1471 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1472
1473 static struct platform_driver s3c64xx_spi_driver = {
1474         .driver = {
1475                 .name   = "s3c64xx-spi",
1476                 .pm = &s3c64xx_spi_pm,
1477                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1478         },
1479         .probe = s3c64xx_spi_probe,
1480         .remove = s3c64xx_spi_remove,
1481         .id_table = s3c64xx_spi_driver_ids,
1482 };
1483 MODULE_ALIAS("platform:s3c64xx-spi");
1484
1485 module_platform_driver(s3c64xx_spi_driver);
1486
1487 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1488 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1489 MODULE_LICENSE("GPL");