drivers/spi/spi-ti-qspi.c

   1 /*
   2  * TI QSPI driver
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * Author: Sourav Poddar <sourav.poddar@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GPLv2.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/omap-dma.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/err.h>
  27 #include <linux/clk.h>
  28 #include <linux/io.h>
  29 #include <linux/slab.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/pinctrl/consumer.h>
  34
  35 #include <linux/spi/spi.h>
  36
  37 struct ti_qspi_regs {
  38         u32 clkctrl;
  39 };
  40
  41 struct ti_qspi {
  42         /* list synchronization */
  43         struct mutex            list_lock;
  44
  45         struct spi_master       *master;
  46         void __iomem            *base;
  47         void __iomem            *ctrl_base;
  48         void __iomem            *mmap_base;
  49         struct clk              *fclk;
  50         struct device           *dev;
  51
  52         struct ti_qspi_regs     ctx_reg;
  53
  54         u32 spi_max_frequency;
  55         u32 cmd;
  56         u32 dc;
  57
  58         bool ctrl_mod;
  59 };
  60
  61 #define QSPI_PID                        (0x0)
  62 #define QSPI_SYSCONFIG                  (0x10)
  63 #define QSPI_SPI_CLOCK_CNTRL_REG        (0x40)
  64 #define QSPI_SPI_DC_REG                 (0x44)
  65 #define QSPI_SPI_CMD_REG                (0x48)
  66 #define QSPI_SPI_STATUS_REG             (0x4c)
  67 #define QSPI_SPI_DATA_REG               (0x50)
  68 #define QSPI_SPI_SETUP0_REG             (0x54)
  69 #define QSPI_SPI_SWITCH_REG             (0x64)
  70 #define QSPI_SPI_SETUP1_REG             (0x58)
  71 #define QSPI_SPI_SETUP2_REG             (0x5c)
  72 #define QSPI_SPI_SETUP3_REG             (0x60)
  73 #define QSPI_SPI_DATA_REG_1             (0x68)
  74 #define QSPI_SPI_DATA_REG_2             (0x6c)
  75 #define QSPI_SPI_DATA_REG_3             (0x70)
  76
  77 #define QSPI_COMPLETION_TIMEOUT         msecs_to_jiffies(2000)
  78
  79 #define QSPI_FCLK                       192000000
  80
  81 /* Clock Control */
  82 #define QSPI_CLK_EN                     (1 << 31)
  83 #define QSPI_CLK_DIV_MAX                0xffff
  84
  85 /* Command */
  86 #define QSPI_EN_CS(n)                   (n << 28)
  87 #define QSPI_WLEN(n)                    ((n - 1) << 19)
  88 #define QSPI_3_PIN                      (1 << 18)
  89 #define QSPI_RD_SNGL                    (1 << 16)
  90 #define QSPI_WR_SNGL                    (2 << 16)
  91 #define QSPI_RD_DUAL                    (3 << 16)
  92 #define QSPI_RD_QUAD                    (7 << 16)
  93 #define QSPI_INVAL                      (4 << 16)
  94 #define QSPI_FLEN(n)                    ((n - 1) << 0)
  95 #define QSPI_WLEN_MAX_BITS              128
  96 #define QSPI_WLEN_MAX_BYTES             16
  97 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  98
  99 /* STATUS REGISTER */
 100 #define BUSY                            0x01
 101 #define WC                              0x02
 102
 103 /* Device Control */
 104 #define QSPI_DD(m, n)                   (m << (3 + n * 8))
 105 #define QSPI_CKPHA(n)                   (1 << (2 + n * 8))
 106 #define QSPI_CSPOL(n)                   (1 << (1 + n * 8))
 107 #define QSPI_CKPOL(n)                   (1 << (n * 8))
 108
 109 #define QSPI_FRAME                      4096
 110
 111 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
 112
 113 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
 114                 unsigned long reg)
 115 {
 116         return readl(qspi->base + reg);
 117 }
 118
 119 static inline void ti_qspi_write(struct ti_qspi *qspi,
 120                 unsigned long val, unsigned long reg)
 121 {
 122         writel(val, qspi->base + reg);
 123 }
 124
 125 static int ti_qspi_setup(struct spi_device *spi)
 126 {
 127         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 128         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 129         int clk_div = 0, ret;
 130         u32 clk_ctrl_reg, clk_rate, clk_mask;
 131
 132         if (spi->master->busy) {
 133                 dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
 134                 return -EBUSY;
 135         }
 136
 137         if (!qspi->spi_max_frequency) {
 138                 dev_err(qspi->dev, "spi max frequency not defined\n");
 139                 return -EINVAL;
 140         }
 141
 142         clk_rate = clk_get_rate(qspi->fclk);
 143
 144         clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
 145
 146         if (clk_div < 0) {
 147                 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
 148                 return -EINVAL;
 149         }
 150
 151         if (clk_div > QSPI_CLK_DIV_MAX) {
 152                 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
 153                                 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
 154                 return -EINVAL;
 155         }
 156
 157         dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
 158                         qspi->spi_max_frequency, clk_div);
 159
 160         ret = pm_runtime_get_sync(qspi->dev);
 161         if (ret < 0) {
 162                 pm_runtime_put_noidle(qspi->dev);
 163                 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
 164                 return ret;
 165         }
 166
 167         clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
 168
 169         clk_ctrl_reg &= ~QSPI_CLK_EN;
 170
 171         /* disable SCLK */
 172         ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
 173
 174         /* enable SCLK */
 175         clk_mask = QSPI_CLK_EN | clk_div;
 176         ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
 177         ctx_reg->clkctrl = clk_mask;
 178
 179         pm_runtime_mark_last_busy(qspi->dev);
 180         ret = pm_runtime_put_autosuspend(qspi->dev);
 181         if (ret < 0) {
 182                 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
 183                 return ret;
 184         }
 185
 186         return 0;
 187 }
 188
 189 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 190 {
 191         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 192
 193         ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
 194 }
 195
 196 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
 197 {
 198         u32 stat;
 199         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 200
 201         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 202         while ((stat & BUSY) && time_after(timeout, jiffies)) {
 203                 cpu_relax();
 204                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 205         }
 206
 207         WARN(stat & BUSY, "qspi busy\n");
 208         return stat & BUSY;
 209 }
 210
 211 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
 212 {
 213         u32 stat;
 214         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 215
 216         do {
 217                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 218                 if (stat & WC)
 219                         return 0;
 220                 cpu_relax();
 221         } while (time_after(timeout, jiffies));
 222
 223         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 224         if (stat & WC)
 225                 return 0;
 226         return  -ETIMEDOUT;
 227 }
 228
 229 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 230                           int count)
 231 {
 232         int wlen, xfer_len;
 233         unsigned int cmd;
 234         const u8 *txbuf;
 235         u32 data;
 236
 237         txbuf = t->tx_buf;
 238         cmd = qspi->cmd | QSPI_WR_SNGL;
 239         wlen = t->bits_per_word >> 3;   /* in bytes */
 240         xfer_len = wlen;
 241
 242         while (count) {
 243                 if (qspi_is_busy(qspi))
 244                         return -EBUSY;
 245
 246                 switch (wlen) {
 247                 case 1:
 248                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
 249                                         cmd, qspi->dc, *txbuf);
 250                         if (count >= QSPI_WLEN_MAX_BYTES) {
 251                                 u32 *txp = (u32 *)txbuf;
 252
 253                                 data = cpu_to_be32(*txp++);
 254                                 writel(data, qspi->base +
 255                                        QSPI_SPI_DATA_REG_3);
 256                                 data = cpu_to_be32(*txp++);
 257                                 writel(data, qspi->base +
 258                                        QSPI_SPI_DATA_REG_2);
 259                                 data = cpu_to_be32(*txp++);
 260                                 writel(data, qspi->base +
 261                                        QSPI_SPI_DATA_REG_1);
 262                                 data = cpu_to_be32(*txp++);
 263                                 writel(data, qspi->base +
 264                                        QSPI_SPI_DATA_REG);
 265                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 266                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 267                         } else {
 268                                 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
 269                                 cmd = qspi->cmd | QSPI_WR_SNGL;
 270                                 xfer_len = wlen;
 271                                 cmd |= QSPI_WLEN(wlen);
 272                         }
 273                         break;
 274                 case 2:
 275                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
 276                                         cmd, qspi->dc, *txbuf);
 277                         writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 278                         break;
 279                 case 4:
 280                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
 281                                         cmd, qspi->dc, *txbuf);
 282                         writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 283                         break;
 284                 }
 285
 286                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 287                 if (ti_qspi_poll_wc(qspi)) {
 288                         dev_err(qspi->dev, "write timed out\n");
 289                         return -ETIMEDOUT;
 290                 }
 291                 txbuf += xfer_len;
 292                 count -= xfer_len;
 293         }
 294
 295         return 0;
 296 }
 297
 298 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 299                          int count)
 300 {
 301         int wlen;
 302         unsigned int cmd;
 303         u8 *rxbuf;
 304
 305         rxbuf = t->rx_buf;
 306         cmd = qspi->cmd;
 307         switch (t->rx_nbits) {
 308         case SPI_NBITS_DUAL:
 309                 cmd |= QSPI_RD_DUAL;
 310                 break;
 311         case SPI_NBITS_QUAD:
 312                 cmd |= QSPI_RD_QUAD;
 313                 break;
 314         default:
 315                 cmd |= QSPI_RD_SNGL;
 316                 break;
 317         }
 318         wlen = t->bits_per_word >> 3;   /* in bytes */
 319
 320         while (count) {
 321                 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
 322                 if (qspi_is_busy(qspi))
 323                         return -EBUSY;
 324
 325                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 326                 if (ti_qspi_poll_wc(qspi)) {
 327                         dev_err(qspi->dev, "read timed out\n");
 328                         return -ETIMEDOUT;
 329                 }
 330                 switch (wlen) {
 331                 case 1:
 332                         *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
 333                         break;
 334                 case 2:
 335                         *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
 336                         break;
 337                 case 4:
 338                         *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
 339                         break;
 340                 }
 341                 rxbuf += wlen;
 342                 count -= wlen;
 343         }
 344
 345         return 0;
 346 }
 347
 348 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 349                              int count)
 350 {
 351         int ret;
 352
 353         if (t->tx_buf) {
 354                 ret = qspi_write_msg(qspi, t, count);
 355                 if (ret) {
 356                         dev_dbg(qspi->dev, "Error while writing\n");
 357                         return ret;
 358                 }
 359         }
 360
 361         if (t->rx_buf) {
 362                 ret = qspi_read_msg(qspi, t, count);
 363                 if (ret) {
 364                         dev_dbg(qspi->dev, "Error while reading\n");
 365                         return ret;
 366                 }
 367         }
 368
 369         return 0;
 370 }
 371
 372 static int ti_qspi_start_transfer_one(struct spi_master *master,
 373                 struct spi_message *m)
 374 {
 375         struct ti_qspi *qspi = spi_master_get_devdata(master);
 376         struct spi_device *spi = m->spi;
 377         struct spi_transfer *t;
 378         int status = 0, ret;
 379         unsigned int frame_len_words, transfer_len_words;
 380         int wlen;
 381
 382         /* setup device control reg */
 383         qspi->dc = 0;
 384
 385         if (spi->mode & SPI_CPHA)
 386                 qspi->dc |= QSPI_CKPHA(spi->chip_select);
 387         if (spi->mode & SPI_CPOL)
 388                 qspi->dc |= QSPI_CKPOL(spi->chip_select);
 389         if (spi->mode & SPI_CS_HIGH)
 390                 qspi->dc |= QSPI_CSPOL(spi->chip_select);
 391
 392         frame_len_words = 0;
 393         list_for_each_entry(t, &m->transfers, transfer_list)
 394                 frame_len_words += t->len / (t->bits_per_word >> 3);
 395         frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
 396
 397         /* setup command reg */
 398         qspi->cmd = 0;
 399         qspi->cmd |= QSPI_EN_CS(spi->chip_select);
 400         qspi->cmd |= QSPI_FLEN(frame_len_words);
 401
 402         ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
 403
 404         mutex_lock(&qspi->list_lock);
 405
 406         list_for_each_entry(t, &m->transfers, transfer_list) {
 407                 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
 408                              QSPI_WLEN(t->bits_per_word));
 409
 410                 wlen = t->bits_per_word >> 3;
 411                 transfer_len_words = min(t->len / wlen, frame_len_words);
 412
 413                 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
 414                 if (ret) {
 415                         dev_dbg(qspi->dev, "transfer message failed\n");
 416                         mutex_unlock(&qspi->list_lock);
 417                         return -EINVAL;
 418                 }
 419
 420                 m->actual_length += transfer_len_words * wlen;
 421                 frame_len_words -= transfer_len_words;
 422                 if (frame_len_words == 0)
 423                         break;
 424         }
 425
 426         mutex_unlock(&qspi->list_lock);
 427
 428         ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
 429         m->status = status;
 430         spi_finalize_current_message(master);
 431
 432         return status;
 433 }
 434
 435 static int ti_qspi_runtime_resume(struct device *dev)
 436 {
 437         struct ti_qspi      *qspi;
 438
 439         qspi = dev_get_drvdata(dev);
 440         ti_qspi_restore_ctx(qspi);
 441
 442         return 0;
 443 }
 444
 445 static const struct of_device_id ti_qspi_match[] = {
 446         {.compatible = "ti,dra7xxx-qspi" },
 447         {.compatible = "ti,am4372-qspi" },
 448         {},
 449 };
 450 MODULE_DEVICE_TABLE(of, ti_qspi_match);
 451
 452 static int ti_qspi_probe(struct platform_device *pdev)
 453 {
 454         struct  ti_qspi *qspi;
 455         struct spi_master *master;
 456         struct resource         *r, *res_ctrl, *res_mmap;
 457         struct device_node *np = pdev->dev.of_node;
 458         u32 max_freq;
 459         int ret = 0, num_cs, irq;
 460
 461         master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
 462         if (!master)
 463                 return -ENOMEM;
 464
 465         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
 466
 467         master->flags = SPI_MASTER_HALF_DUPLEX;
 468         master->setup = ti_qspi_setup;
 469         master->auto_runtime_pm = true;
 470         master->transfer_one_message = ti_qspi_start_transfer_one;
 471         master->dev.of_node = pdev->dev.of_node;
 472         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
 473                                      SPI_BPW_MASK(8);
 474
 475         if (!of_property_read_u32(np, "num-cs", &num_cs))
 476                 master->num_chipselect = num_cs;
 477
 478         qspi = spi_master_get_devdata(master);
 479         qspi->master = master;
 480         qspi->dev = &pdev->dev;
 481         platform_set_drvdata(pdev, qspi);
 482
 483         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
 484         if (r == NULL) {
 485                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 486                 if (r == NULL) {
 487                         dev_err(&pdev->dev, "missing platform data\n");
 488                         return -ENODEV;
 489                 }
 490         }
 491
 492         res_mmap = platform_get_resource_byname(pdev,
 493                         IORESOURCE_MEM, "qspi_mmap");
 494         if (res_mmap == NULL) {
 495                 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 496                 if (res_mmap == NULL) {
 497                         dev_err(&pdev->dev,
 498                                 "memory mapped resource not required\n");
 499                 }
 500         }
 501
 502         res_ctrl = platform_get_resource_byname(pdev,
 503                         IORESOURCE_MEM, "qspi_ctrlmod");
 504         if (res_ctrl == NULL) {
 505                 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 506                 if (res_ctrl == NULL) {
 507                         dev_dbg(&pdev->dev,
 508                                 "control module resources not required\n");
 509                 }
 510         }
 511
 512         irq = platform_get_irq(pdev, 0);
 513         if (irq < 0) {
 514                 dev_err(&pdev->dev, "no irq resource?\n");
 515                 return irq;
 516         }
 517
 518         mutex_init(&qspi->list_lock);
 519
 520         qspi->base = devm_ioremap_resource(&pdev->dev, r);
 521         if (IS_ERR(qspi->base)) {
 522                 ret = PTR_ERR(qspi->base);
 523                 goto free_master;
 524         }
 525
 526         if (res_ctrl) {
 527                 qspi->ctrl_mod = true;
 528                 qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
 529                 if (IS_ERR(qspi->ctrl_base)) {
 530                         ret = PTR_ERR(qspi->ctrl_base);
 531                         goto free_master;
 532                 }
 533         }
 534
 535         if (res_mmap) {
 536                 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
 537                 if (IS_ERR(qspi->mmap_base)) {
 538                         ret = PTR_ERR(qspi->mmap_base);
 539                         goto free_master;
 540                 }
 541         }
 542
 543         qspi->fclk = devm_clk_get(&pdev->dev, "fck");
 544         if (IS_ERR(qspi->fclk)) {
 545                 ret = PTR_ERR(qspi->fclk);
 546                 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
 547         }
 548
 549         pm_runtime_use_autosuspend(&pdev->dev);
 550         pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
 551         pm_runtime_enable(&pdev->dev);
 552
 553         if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
 554                 qspi->spi_max_frequency = max_freq;
 555
 556         ret = devm_spi_register_master(&pdev->dev, master);
 557         if (ret)
 558                 goto free_master;
 559
 560         return 0;
 561
 562 free_master:
 563         spi_master_put(master);
 564         return ret;
 565 }
 566
 567 static int ti_qspi_remove(struct platform_device *pdev)
 568 {
 569         pm_runtime_put_sync(&pdev->dev);
 570         pm_runtime_disable(&pdev->dev);
 571
 572         return 0;
 573 }
 574
 575 static const struct dev_pm_ops ti_qspi_pm_ops = {
 576         .runtime_resume = ti_qspi_runtime_resume,
 577 };
 578
 579 static struct platform_driver ti_qspi_driver = {
 580         .probe  = ti_qspi_probe,
 581         .remove = ti_qspi_remove,
 582         .driver = {
 583                 .name   = "ti-qspi",
 584                 .pm =   &ti_qspi_pm_ops,
 585                 .of_match_table = ti_qspi_match,
 586         }
 587 };
 588
 589 module_platform_driver(ti_qspi_driver);
 590
 591 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
 592 MODULE_LICENSE("GPL v2");
 593 MODULE_DESCRIPTION("TI QSPI controller driver");
 594 MODULE_ALIAS("platform:ti-qspi");