drivers/spi/spi-ti-qspi.c

   1 /*
   2  * TI QSPI driver
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * Author: Sourav Poddar <sourav.poddar@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GPLv2.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/omap-dma.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/err.h>
  27 #include <linux/clk.h>
  28 #include <linux/io.h>
  29 #include <linux/slab.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #include <linux/mfd/syscon.h>
  35 #include <linux/regmap.h>
  36 #include <linux/sizes.h>
  37
  38 #include <linux/spi/spi.h>
  39
  40 struct ti_qspi_regs {
  41         u32 clkctrl;
  42 };
  43
  44 struct ti_qspi {
  45         struct completion       transfer_complete;
  46
  47         /* list synchronization */
  48         struct mutex            list_lock;
  49
  50         struct spi_master       *master;
  51         void __iomem            *base;
  52         void __iomem            *mmap_base;
  53         struct regmap           *ctrl_base;
  54         unsigned int            ctrl_reg;
  55         struct clk              *fclk;
  56         struct device           *dev;
  57
  58         struct ti_qspi_regs     ctx_reg;
  59
  60         dma_addr_t              mmap_phys_base;
  61         dma_addr_t              rx_bb_dma_addr;
  62         void                    *rx_bb_addr;
  63         struct dma_chan         *rx_chan;
  64
  65         u32 spi_max_frequency;
  66         u32 cmd;
  67         u32 dc;
  68
  69         bool mmap_enabled;
  70 };
  71
  72 #define QSPI_PID                        (0x0)
  73 #define QSPI_SYSCONFIG                  (0x10)
  74 #define QSPI_SPI_CLOCK_CNTRL_REG        (0x40)
  75 #define QSPI_SPI_DC_REG                 (0x44)
  76 #define QSPI_SPI_CMD_REG                (0x48)
  77 #define QSPI_SPI_STATUS_REG             (0x4c)
  78 #define QSPI_SPI_DATA_REG               (0x50)
  79 #define QSPI_SPI_SETUP_REG(n)           ((0x54 + 4 * n))
  80 #define QSPI_SPI_SWITCH_REG             (0x64)
  81 #define QSPI_SPI_DATA_REG_1             (0x68)
  82 #define QSPI_SPI_DATA_REG_2             (0x6c)
  83 #define QSPI_SPI_DATA_REG_3             (0x70)
  84
  85 #define QSPI_COMPLETION_TIMEOUT         msecs_to_jiffies(2000)
  86
  87 #define QSPI_FCLK                       192000000
  88
  89 /* Clock Control */
  90 #define QSPI_CLK_EN                     (1 << 31)
  91 #define QSPI_CLK_DIV_MAX                0xffff
  92
  93 /* Command */
  94 #define QSPI_EN_CS(n)                   (n << 28)
  95 #define QSPI_WLEN(n)                    ((n - 1) << 19)
  96 #define QSPI_3_PIN                      (1 << 18)
  97 #define QSPI_RD_SNGL                    (1 << 16)
  98 #define QSPI_WR_SNGL                    (2 << 16)
  99 #define QSPI_RD_DUAL                    (3 << 16)
 100 #define QSPI_RD_QUAD                    (7 << 16)
 101 #define QSPI_INVAL                      (4 << 16)
 102 #define QSPI_FLEN(n)                    ((n - 1) << 0)
 103 #define QSPI_WLEN_MAX_BITS              128
 104 #define QSPI_WLEN_MAX_BYTES             16
 105 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
 106
 107 /* STATUS REGISTER */
 108 #define BUSY                            0x01
 109 #define WC                              0x02
 110
 111 /* Device Control */
 112 #define QSPI_DD(m, n)                   (m << (3 + n * 8))
 113 #define QSPI_CKPHA(n)                   (1 << (2 + n * 8))
 114 #define QSPI_CSPOL(n)                   (1 << (1 + n * 8))
 115 #define QSPI_CKPOL(n)                   (1 << (n * 8))
 116
 117 #define QSPI_FRAME                      4096
 118
 119 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
 120
 121 #define MEM_CS_EN(n)                    ((n + 1) << 8)
 122 #define MEM_CS_MASK                     (7 << 8)
 123
 124 #define MM_SWITCH                       0x1
 125
 126 #define QSPI_SETUP_RD_NORMAL            (0x0 << 12)
 127 #define QSPI_SETUP_RD_DUAL              (0x1 << 12)
 128 #define QSPI_SETUP_RD_QUAD              (0x3 << 12)
 129 #define QSPI_SETUP_ADDR_SHIFT           8
 130 #define QSPI_SETUP_DUMMY_SHIFT          10
 131
 132 #define QSPI_DMA_BUFFER_SIZE            SZ_64K
 133
 134 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
 135                 unsigned long reg)
 136 {
 137         return readl(qspi->base + reg);
 138 }
 139
 140 static inline void ti_qspi_write(struct ti_qspi *qspi,
 141                 unsigned long val, unsigned long reg)
 142 {
 143         writel(val, qspi->base + reg);
 144 }
 145
 146 static int ti_qspi_setup(struct spi_device *spi)
 147 {
 148         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 149         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 150         int clk_div = 0, ret;
 151         u32 clk_ctrl_reg, clk_rate, clk_mask;
 152
 153         if (spi->master->busy) {
 154                 dev_dbg(qspi->dev, "master busy doing other transfers\n");
 155                 return -EBUSY;
 156         }
 157
 158         if (!qspi->spi_max_frequency) {
 159                 dev_err(qspi->dev, "spi max frequency not defined\n");
 160                 return -EINVAL;
 161         }
 162
 163         clk_rate = clk_get_rate(qspi->fclk);
 164
 165         clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
 166
 167         if (clk_div < 0) {
 168                 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
 169                 return -EINVAL;
 170         }
 171
 172         if (clk_div > QSPI_CLK_DIV_MAX) {
 173                 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
 174                                 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
 175                 return -EINVAL;
 176         }
 177
 178         dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
 179                         qspi->spi_max_frequency, clk_div);
 180
 181         ret = pm_runtime_get_sync(qspi->dev);
 182         if (ret < 0) {
 183                 pm_runtime_put_noidle(qspi->dev);
 184                 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
 185                 return ret;
 186         }
 187
 188         clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
 189
 190         clk_ctrl_reg &= ~QSPI_CLK_EN;
 191
 192         /* disable SCLK */
 193         ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
 194
 195         /* enable SCLK */
 196         clk_mask = QSPI_CLK_EN | clk_div;
 197         ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
 198         ctx_reg->clkctrl = clk_mask;
 199
 200         pm_runtime_mark_last_busy(qspi->dev);
 201         ret = pm_runtime_put_autosuspend(qspi->dev);
 202         if (ret < 0) {
 203                 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
 204                 return ret;
 205         }
 206
 207         return 0;
 208 }
 209
 210 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 211 {
 212         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 213
 214         ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
 215 }
 216
 217 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
 218 {
 219         u32 stat;
 220         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 221
 222         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 223         while ((stat & BUSY) && time_after(timeout, jiffies)) {
 224                 cpu_relax();
 225                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 226         }
 227
 228         WARN(stat & BUSY, "qspi busy\n");
 229         return stat & BUSY;
 230 }
 231
 232 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
 233 {
 234         u32 stat;
 235         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 236
 237         do {
 238                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 239                 if (stat & WC)
 240                         return 0;
 241                 cpu_relax();
 242         } while (time_after(timeout, jiffies));
 243
 244         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 245         if (stat & WC)
 246                 return 0;
 247         return  -ETIMEDOUT;
 248 }
 249
 250 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 251                           int count)
 252 {
 253         int wlen, xfer_len;
 254         unsigned int cmd;
 255         const u8 *txbuf;
 256         u32 data;
 257
 258         txbuf = t->tx_buf;
 259         cmd = qspi->cmd | QSPI_WR_SNGL;
 260         wlen = t->bits_per_word >> 3;   /* in bytes */
 261         xfer_len = wlen;
 262
 263         while (count) {
 264                 if (qspi_is_busy(qspi))
 265                         return -EBUSY;
 266
 267                 switch (wlen) {
 268                 case 1:
 269                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
 270                                         cmd, qspi->dc, *txbuf);
 271                         if (count >= QSPI_WLEN_MAX_BYTES) {
 272                                 u32 *txp = (u32 *)txbuf;
 273
 274                                 data = cpu_to_be32(*txp++);
 275                                 writel(data, qspi->base +
 276                                        QSPI_SPI_DATA_REG_3);
 277                                 data = cpu_to_be32(*txp++);
 278                                 writel(data, qspi->base +
 279                                        QSPI_SPI_DATA_REG_2);
 280                                 data = cpu_to_be32(*txp++);
 281                                 writel(data, qspi->base +
 282                                        QSPI_SPI_DATA_REG_1);
 283                                 data = cpu_to_be32(*txp++);
 284                                 writel(data, qspi->base +
 285                                        QSPI_SPI_DATA_REG);
 286                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 287                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 288                         } else {
 289                                 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
 290                                 cmd = qspi->cmd | QSPI_WR_SNGL;
 291                                 xfer_len = wlen;
 292                                 cmd |= QSPI_WLEN(wlen);
 293                         }
 294                         break;
 295                 case 2:
 296                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
 297                                         cmd, qspi->dc, *txbuf);
 298                         writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 299                         break;
 300                 case 4:
 301                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
 302                                         cmd, qspi->dc, *txbuf);
 303                         writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 304                         break;
 305                 }
 306
 307                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 308                 if (ti_qspi_poll_wc(qspi)) {
 309                         dev_err(qspi->dev, "write timed out\n");
 310                         return -ETIMEDOUT;
 311                 }
 312                 txbuf += xfer_len;
 313                 count -= xfer_len;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 320                          int count)
 321 {
 322         int wlen;
 323         unsigned int cmd;
 324         u8 *rxbuf;
 325
 326         rxbuf = t->rx_buf;
 327         cmd = qspi->cmd;
 328         switch (t->rx_nbits) {
 329         case SPI_NBITS_DUAL:
 330                 cmd |= QSPI_RD_DUAL;
 331                 break;
 332         case SPI_NBITS_QUAD:
 333                 cmd |= QSPI_RD_QUAD;
 334                 break;
 335         default:
 336                 cmd |= QSPI_RD_SNGL;
 337                 break;
 338         }
 339         wlen = t->bits_per_word >> 3;   /* in bytes */
 340
 341         while (count) {
 342                 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
 343                 if (qspi_is_busy(qspi))
 344                         return -EBUSY;
 345
 346                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 347                 if (ti_qspi_poll_wc(qspi)) {
 348                         dev_err(qspi->dev, "read timed out\n");
 349                         return -ETIMEDOUT;
 350                 }
 351                 switch (wlen) {
 352                 case 1:
 353                         *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
 354                         break;
 355                 case 2:
 356                         *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
 357                         break;
 358                 case 4:
 359                         *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
 360                         break;
 361                 }
 362                 rxbuf += wlen;
 363                 count -= wlen;
 364         }
 365
 366         return 0;
 367 }
 368
 369 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 370                              int count)
 371 {
 372         int ret;
 373
 374         if (t->tx_buf) {
 375                 ret = qspi_write_msg(qspi, t, count);
 376                 if (ret) {
 377                         dev_dbg(qspi->dev, "Error while writing\n");
 378                         return ret;
 379                 }
 380         }
 381
 382         if (t->rx_buf) {
 383                 ret = qspi_read_msg(qspi, t, count);
 384                 if (ret) {
 385                         dev_dbg(qspi->dev, "Error while reading\n");
 386                         return ret;
 387                 }
 388         }
 389
 390         return 0;
 391 }
 392
 393 static void ti_qspi_dma_callback(void *param)
 394 {
 395         struct ti_qspi *qspi = param;
 396
 397         complete(&qspi->transfer_complete);
 398 }
 399
 400 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
 401                             dma_addr_t dma_src, size_t len)
 402 {
 403         struct dma_chan *chan = qspi->rx_chan;
 404         dma_cookie_t cookie;
 405         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 406         struct dma_async_tx_descriptor *tx;
 407         int ret;
 408         unsigned long time_left;
 409
 410         tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
 411         if (!tx) {
 412                 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
 413                 return -EIO;
 414         }
 415
 416         tx->callback = ti_qspi_dma_callback;
 417         tx->callback_param = qspi;
 418         cookie = tx->tx_submit(tx);
 419         reinit_completion(&qspi->transfer_complete);
 420
 421         ret = dma_submit_error(cookie);
 422         if (ret) {
 423                 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
 424                 return -EIO;
 425         }
 426
 427         dma_async_issue_pending(chan);
 428         time_left = wait_for_completion_timeout(&qspi->transfer_complete,
 429                                           msecs_to_jiffies(len));
 430         if (time_left == 0) {
 431                 dmaengine_terminate_sync(chan);
 432                 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
 433                 return -ETIMEDOUT;
 434         }
 435
 436         return 0;
 437 }
 438
 439 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi,
 440                                      struct spi_flash_read_message *msg)
 441 {
 442         size_t readsize = msg->len;
 443         void *to = msg->buf;
 444         dma_addr_t dma_src = qspi->mmap_phys_base + msg->from;
 445         int ret = 0;
 446
 447         /*
 448          * Use bounce buffer as FS like jffs2, ubifs may pass
 449          * buffers that does not belong to kernel lowmem region.
 450          */
 451         while (readsize != 0) {
 452                 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
 453                                         readsize);
 454
 455                 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
 456                                        dma_src, xfer_len);
 457                 if (ret != 0)
 458                         return ret;
 459                 memcpy(to, qspi->rx_bb_addr, xfer_len);
 460                 readsize -= xfer_len;
 461                 dma_src += xfer_len;
 462                 to += xfer_len;
 463         }
 464
 465         return ret;
 466 }
 467
 468 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
 469                                loff_t from)
 470 {
 471         struct scatterlist *sg;
 472         dma_addr_t dma_src = qspi->mmap_phys_base + from;
 473         dma_addr_t dma_dst;
 474         int i, len, ret;
 475
 476         for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
 477                 dma_dst = sg_dma_address(sg);
 478                 len = sg_dma_len(sg);
 479                 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
 480                 if (ret)
 481                         return ret;
 482                 dma_src += len;
 483         }
 484
 485         return 0;
 486 }
 487
 488 static void ti_qspi_enable_memory_map(struct spi_device *spi)
 489 {
 490         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 491
 492         ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
 493         if (qspi->ctrl_base) {
 494                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
 495                                    MEM_CS_MASK,
 496                                    MEM_CS_EN(spi->chip_select));
 497         }
 498         qspi->mmap_enabled = true;
 499 }
 500
 501 static void ti_qspi_disable_memory_map(struct spi_device *spi)
 502 {
 503         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 504
 505         ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
 506         if (qspi->ctrl_base)
 507                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
 508                                    MEM_CS_MASK, 0);
 509         qspi->mmap_enabled = false;
 510 }
 511
 512 static void ti_qspi_setup_mmap_read(struct spi_device *spi,
 513                                     struct spi_flash_read_message *msg)
 514 {
 515         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 516         u32 memval = msg->read_opcode;
 517
 518         switch (msg->data_nbits) {
 519         case SPI_NBITS_QUAD:
 520                 memval |= QSPI_SETUP_RD_QUAD;
 521                 break;
 522         case SPI_NBITS_DUAL:
 523                 memval |= QSPI_SETUP_RD_DUAL;
 524                 break;
 525         default:
 526                 memval |= QSPI_SETUP_RD_NORMAL;
 527                 break;
 528         }
 529         memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
 530                    msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
 531         ti_qspi_write(qspi, memval,
 532                       QSPI_SPI_SETUP_REG(spi->chip_select));
 533 }
 534
 535 static bool ti_qspi_spi_flash_can_dma(struct spi_device *spi,
 536                                       struct spi_flash_read_message *msg)
 537 {
 538         return virt_addr_valid(msg->buf);
 539 }
 540
 541 static int ti_qspi_spi_flash_read(struct spi_device *spi,
 542                                   struct spi_flash_read_message *msg)
 543 {
 544         struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
 545         int ret = 0;
 546
 547         mutex_lock(&qspi->list_lock);
 548
 549         if (!qspi->mmap_enabled)
 550                 ti_qspi_enable_memory_map(spi);
 551         ti_qspi_setup_mmap_read(spi, msg);
 552
 553         if (qspi->rx_chan) {
 554                 if (msg->cur_msg_mapped)
 555                         ret = ti_qspi_dma_xfer_sg(qspi, msg->rx_sg, msg->from);
 556                 else
 557                         ret = ti_qspi_dma_bounce_buffer(qspi, msg);
 558                 if (ret)
 559                         goto err_unlock;
 560         } else {
 561                 memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
 562         }
 563         msg->retlen = msg->len;
 564
 565 err_unlock:
 566         mutex_unlock(&qspi->list_lock);
 567
 568         return ret;
 569 }
 570
 571 static int ti_qspi_start_transfer_one(struct spi_master *master,
 572                 struct spi_message *m)
 573 {
 574         struct ti_qspi *qspi = spi_master_get_devdata(master);
 575         struct spi_device *spi = m->spi;
 576         struct spi_transfer *t;
 577         int status = 0, ret;
 578         unsigned int frame_len_words, transfer_len_words;
 579         int wlen;
 580
 581         /* setup device control reg */
 582         qspi->dc = 0;
 583
 584         if (spi->mode & SPI_CPHA)
 585                 qspi->dc |= QSPI_CKPHA(spi->chip_select);
 586         if (spi->mode & SPI_CPOL)
 587                 qspi->dc |= QSPI_CKPOL(spi->chip_select);
 588         if (spi->mode & SPI_CS_HIGH)
 589                 qspi->dc |= QSPI_CSPOL(spi->chip_select);
 590
 591         frame_len_words = 0;
 592         list_for_each_entry(t, &m->transfers, transfer_list)
 593                 frame_len_words += t->len / (t->bits_per_word >> 3);
 594         frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
 595
 596         /* setup command reg */
 597         qspi->cmd = 0;
 598         qspi->cmd |= QSPI_EN_CS(spi->chip_select);
 599         qspi->cmd |= QSPI_FLEN(frame_len_words);
 600
 601         ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
 602
 603         mutex_lock(&qspi->list_lock);
 604
 605         if (qspi->mmap_enabled)
 606                 ti_qspi_disable_memory_map(spi);
 607
 608         list_for_each_entry(t, &m->transfers, transfer_list) {
 609                 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
 610                              QSPI_WLEN(t->bits_per_word));
 611
 612                 wlen = t->bits_per_word >> 3;
 613                 transfer_len_words = min(t->len / wlen, frame_len_words);
 614
 615                 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
 616                 if (ret) {
 617                         dev_dbg(qspi->dev, "transfer message failed\n");
 618                         mutex_unlock(&qspi->list_lock);
 619                         return -EINVAL;
 620                 }
 621
 622                 m->actual_length += transfer_len_words * wlen;
 623                 frame_len_words -= transfer_len_words;
 624                 if (frame_len_words == 0)
 625                         break;
 626         }
 627
 628         mutex_unlock(&qspi->list_lock);
 629
 630         ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
 631         m->status = status;
 632         spi_finalize_current_message(master);
 633
 634         return status;
 635 }
 636
 637 static int ti_qspi_runtime_resume(struct device *dev)
 638 {
 639         struct ti_qspi      *qspi;
 640
 641         qspi = dev_get_drvdata(dev);
 642         ti_qspi_restore_ctx(qspi);
 643
 644         return 0;
 645 }
 646
 647 static void ti_qspi_dma_cleanup(struct ti_qspi *qspi)
 648 {
 649         if (qspi->rx_bb_addr)
 650                 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
 651                                   qspi->rx_bb_addr,
 652                                   qspi->rx_bb_dma_addr);
 653
 654         if (qspi->rx_chan)
 655                 dma_release_channel(qspi->rx_chan);
 656 }
 657
 658 static const struct of_device_id ti_qspi_match[] = {
 659         {.compatible = "ti,dra7xxx-qspi" },
 660         {.compatible = "ti,am4372-qspi" },
 661         {},
 662 };
 663 MODULE_DEVICE_TABLE(of, ti_qspi_match);
 664
 665 static int ti_qspi_probe(struct platform_device *pdev)
 666 {
 667         struct  ti_qspi *qspi;
 668         struct spi_master *master;
 669         struct resource         *r, *res_mmap;
 670         struct device_node *np = pdev->dev.of_node;
 671         u32 max_freq;
 672         int ret = 0, num_cs, irq;
 673         dma_cap_mask_t mask;
 674
 675         master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
 676         if (!master)
 677                 return -ENOMEM;
 678
 679         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
 680
 681         master->flags = SPI_MASTER_HALF_DUPLEX;
 682         master->setup = ti_qspi_setup;
 683         master->auto_runtime_pm = true;
 684         master->transfer_one_message = ti_qspi_start_transfer_one;
 685         master->dev.of_node = pdev->dev.of_node;
 686         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
 687                                      SPI_BPW_MASK(8);
 688         master->spi_flash_read = ti_qspi_spi_flash_read;
 689
 690         if (!of_property_read_u32(np, "num-cs", &num_cs))
 691                 master->num_chipselect = num_cs;
 692
 693         qspi = spi_master_get_devdata(master);
 694         qspi->master = master;
 695         qspi->dev = &pdev->dev;
 696         platform_set_drvdata(pdev, qspi);
 697
 698         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
 699         if (r == NULL) {
 700                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 701                 if (r == NULL) {
 702                         dev_err(&pdev->dev, "missing platform data\n");
 703                         ret = -ENODEV;
 704                         goto free_master;
 705                 }
 706         }
 707
 708         res_mmap = platform_get_resource_byname(pdev,
 709                         IORESOURCE_MEM, "qspi_mmap");
 710         if (res_mmap == NULL) {
 711                 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 712                 if (res_mmap == NULL) {
 713                         dev_err(&pdev->dev,
 714                                 "memory mapped resource not required\n");
 715                 }
 716         }
 717
 718         irq = platform_get_irq(pdev, 0);
 719         if (irq < 0) {
 720                 dev_err(&pdev->dev, "no irq resource?\n");
 721                 ret = irq;
 722                 goto free_master;
 723         }
 724
 725         mutex_init(&qspi->list_lock);
 726
 727         qspi->base = devm_ioremap_resource(&pdev->dev, r);
 728         if (IS_ERR(qspi->base)) {
 729                 ret = PTR_ERR(qspi->base);
 730                 goto free_master;
 731         }
 732
 733
 734         if (of_property_read_bool(np, "syscon-chipselects")) {
 735                 qspi->ctrl_base =
 736                 syscon_regmap_lookup_by_phandle(np,
 737                                                 "syscon-chipselects");
 738                 if (IS_ERR(qspi->ctrl_base)) {
 739                         ret = PTR_ERR(qspi->ctrl_base);
 740                         goto free_master;
 741                 }
 742                 ret = of_property_read_u32_index(np,
 743                                                  "syscon-chipselects",
 744                                                  1, &qspi->ctrl_reg);
 745                 if (ret) {
 746                         dev_err(&pdev->dev,
 747                                 "couldn't get ctrl_mod reg index\n");
 748                         goto free_master;
 749                 }
 750         }
 751
 752         qspi->fclk = devm_clk_get(&pdev->dev, "fck");
 753         if (IS_ERR(qspi->fclk)) {
 754                 ret = PTR_ERR(qspi->fclk);
 755                 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
 756         }
 757
 758         pm_runtime_use_autosuspend(&pdev->dev);
 759         pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
 760         pm_runtime_enable(&pdev->dev);
 761
 762         if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
 763                 qspi->spi_max_frequency = max_freq;
 764
 765         dma_cap_zero(mask);
 766         dma_cap_set(DMA_MEMCPY, mask);
 767
 768         qspi->rx_chan = dma_request_chan_by_mask(&mask);
 769         if (IS_ERR(qspi->rx_chan)) {
 770                 dev_err(qspi->dev,
 771                         "No Rx DMA available, trying mmap mode\n");
 772                 qspi->rx_chan = NULL;
 773                 ret = 0;
 774                 goto no_dma;
 775         }
 776         qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
 777                                               QSPI_DMA_BUFFER_SIZE,
 778                                               &qspi->rx_bb_dma_addr,
 779                                               GFP_KERNEL | GFP_DMA);
 780         if (!qspi->rx_bb_addr) {
 781                 dev_err(qspi->dev,
 782                         "dma_alloc_coherent failed, using PIO mode\n");
 783                 dma_release_channel(qspi->rx_chan);
 784                 goto no_dma;
 785         }
 786         master->spi_flash_can_dma = ti_qspi_spi_flash_can_dma;
 787         master->dma_rx = qspi->rx_chan;
 788         init_completion(&qspi->transfer_complete);
 789         if (res_mmap)
 790                 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
 791
 792 no_dma:
 793         if (!qspi->rx_chan && res_mmap) {
 794                 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
 795                 if (IS_ERR(qspi->mmap_base)) {
 796                         dev_info(&pdev->dev,
 797                                  "mmap failed with error %ld using PIO mode\n",
 798                                  PTR_ERR(qspi->mmap_base));
 799                         qspi->mmap_base = NULL;
 800                         master->spi_flash_read = NULL;
 801                 }
 802         }
 803         qspi->mmap_enabled = false;
 804
 805         ret = devm_spi_register_master(&pdev->dev, master);
 806         if (!ret)
 807                 return 0;
 808
 809         ti_qspi_dma_cleanup(qspi);
 810
 811         pm_runtime_disable(&pdev->dev);
 812 free_master:
 813         spi_master_put(master);
 814         return ret;
 815 }
 816
 817 static int ti_qspi_remove(struct platform_device *pdev)
 818 {
 819         struct ti_qspi *qspi = platform_get_drvdata(pdev);
 820         int rc;
 821
 822         rc = spi_master_suspend(qspi->master);
 823         if (rc)
 824                 return rc;
 825
 826         pm_runtime_put_sync(&pdev->dev);
 827         pm_runtime_disable(&pdev->dev);
 828
 829         ti_qspi_dma_cleanup(qspi);
 830
 831         return 0;
 832 }
 833
 834 static const struct dev_pm_ops ti_qspi_pm_ops = {
 835         .runtime_resume = ti_qspi_runtime_resume,
 836 };
 837
 838 static struct platform_driver ti_qspi_driver = {
 839         .probe  = ti_qspi_probe,
 840         .remove = ti_qspi_remove,
 841         .driver = {
 842                 .name   = "ti-qspi",
 843                 .pm =   &ti_qspi_pm_ops,
 844                 .of_match_table = ti_qspi_match,
 845         }
 846 };
 847
 848 module_platform_driver(ti_qspi_driver);
 849
 850 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
 851 MODULE_LICENSE("GPL v2");
 852 MODULE_DESCRIPTION("TI QSPI controller driver");
 853 MODULE_ALIAS("platform:ti-qspi");