drivers/spi/spi-topcliff-pch.c

   1 /*
   2  * SPI bus driver for the Topcliff PCH used by Intel SoCs
   3  *
   4  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/pci.h>
  18 #include <linux/wait.h>
  19 #include <linux/spi/spi.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/sched.h>
  22 #include <linux/spi/spidev.h>
  23 #include <linux/module.h>
  24 #include <linux/device.h>
  25 #include <linux/platform_device.h>
  26
  27 #include <linux/dmaengine.h>
  28 #include <linux/pch_dma.h>
  29
  30 /* Register offsets */
  31 #define PCH_SPCR                0x00    /* SPI control register */
  32 #define PCH_SPBRR               0x04    /* SPI baud rate register */
  33 #define PCH_SPSR                0x08    /* SPI status register */
  34 #define PCH_SPDWR               0x0C    /* SPI write data register */
  35 #define PCH_SPDRR               0x10    /* SPI read data register */
  36 #define PCH_SSNXCR              0x18    /* SSN Expand Control Register */
  37 #define PCH_SRST                0x1C    /* SPI reset register */
  38 #define PCH_ADDRESS_SIZE        0x20
  39
  40 #define PCH_SPSR_TFD            0x000007C0
  41 #define PCH_SPSR_RFD            0x0000F800
  42
  43 #define PCH_READABLE(x)         (((x) & PCH_SPSR_RFD)>>11)
  44 #define PCH_WRITABLE(x)         (((x) & PCH_SPSR_TFD)>>6)
  45
  46 #define PCH_RX_THOLD            7
  47 #define PCH_RX_THOLD_MAX        15
  48
  49 #define PCH_TX_THOLD            2
  50
  51 #define PCH_MAX_BAUDRATE        5000000
  52 #define PCH_MAX_FIFO_DEPTH      16
  53
  54 #define STATUS_RUNNING          1
  55 #define STATUS_EXITING          2
  56 #define PCH_SLEEP_TIME          10
  57
  58 #define SSN_LOW                 0x02U
  59 #define SSN_HIGH                0x03U
  60 #define SSN_NO_CONTROL          0x00U
  61 #define PCH_MAX_CS              0xFF
  62 #define PCI_DEVICE_ID_GE_SPI    0x8816
  63
  64 #define SPCR_SPE_BIT            (1 << 0)
  65 #define SPCR_MSTR_BIT           (1 << 1)
  66 #define SPCR_LSBF_BIT           (1 << 4)
  67 #define SPCR_CPHA_BIT           (1 << 5)
  68 #define SPCR_CPOL_BIT           (1 << 6)
  69 #define SPCR_TFIE_BIT           (1 << 8)
  70 #define SPCR_RFIE_BIT           (1 << 9)
  71 #define SPCR_FIE_BIT            (1 << 10)
  72 #define SPCR_ORIE_BIT           (1 << 11)
  73 #define SPCR_MDFIE_BIT          (1 << 12)
  74 #define SPCR_FICLR_BIT          (1 << 24)
  75 #define SPSR_TFI_BIT            (1 << 0)
  76 #define SPSR_RFI_BIT            (1 << 1)
  77 #define SPSR_FI_BIT             (1 << 2)
  78 #define SPSR_ORF_BIT            (1 << 3)
  79 #define SPBRR_SIZE_BIT          (1 << 10)
  80
  81 #define PCH_ALL                 (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
  82                                 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
  83
  84 #define SPCR_RFIC_FIELD         20
  85 #define SPCR_TFIC_FIELD         16
  86
  87 #define MASK_SPBRR_SPBR_BITS    ((1 << 10) - 1)
  88 #define MASK_RFIC_SPCR_BITS     (0xf << SPCR_RFIC_FIELD)
  89 #define MASK_TFIC_SPCR_BITS     (0xf << SPCR_TFIC_FIELD)
  90
  91 #define PCH_CLOCK_HZ            50000000
  92 #define PCH_MAX_SPBR            1023
  93
  94 /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
  95 #define PCI_VENDOR_ID_ROHM              0x10DB
  96 #define PCI_DEVICE_ID_ML7213_SPI        0x802c
  97 #define PCI_DEVICE_ID_ML7223_SPI        0x800F
  98 #define PCI_DEVICE_ID_ML7831_SPI        0x8816
  99
 100 /*
 101  * Set the number of SPI instance max
 102  * Intel EG20T PCH :            1ch
 103  * LAPIS Semiconductor ML7213 IOH :     2ch
 104  * LAPIS Semiconductor ML7223 IOH :     1ch
 105  * LAPIS Semiconductor ML7831 IOH :     1ch
 106 */
 107 #define PCH_SPI_MAX_DEV                 2
 108
 109 #define PCH_BUF_SIZE            4096
 110 #define PCH_DMA_TRANS_SIZE      12
 111
 112 static int use_dma = 1;
 113
 114 struct pch_spi_dma_ctrl {
 115         struct dma_async_tx_descriptor  *desc_tx;
 116         struct dma_async_tx_descriptor  *desc_rx;
 117         struct pch_dma_slave            param_tx;
 118         struct pch_dma_slave            param_rx;
 119         struct dma_chan         *chan_tx;
 120         struct dma_chan         *chan_rx;
 121         struct scatterlist              *sg_tx_p;
 122         struct scatterlist              *sg_rx_p;
 123         struct scatterlist              sg_tx;
 124         struct scatterlist              sg_rx;
 125         int                             nent;
 126         void                            *tx_buf_virt;
 127         void                            *rx_buf_virt;
 128         dma_addr_t                      tx_buf_dma;
 129         dma_addr_t                      rx_buf_dma;
 130 };
 131 /**
 132  * struct pch_spi_data - Holds the SPI channel specific details
 133  * @io_remap_addr:              The remapped PCI base address
 134  * @master:                     Pointer to the SPI master structure
 135  * @work:                       Reference to work queue handler
 136  * @wk:                         Workqueue for carrying out execution of the
 137  *                              requests
 138  * @wait:                       Wait queue for waking up upon receiving an
 139  *                              interrupt.
 140  * @transfer_complete:          Status of SPI Transfer
 141  * @bcurrent_msg_processing:    Status flag for message processing
 142  * @lock:                       Lock for protecting this structure
 143  * @queue:                      SPI Message queue
 144  * @status:                     Status of the SPI driver
 145  * @bpw_len:                    Length of data to be transferred in bits per
 146  *                              word
 147  * @transfer_active:            Flag showing active transfer
 148  * @tx_index:                   Transmit data count; for bookkeeping during
 149  *                              transfer
 150  * @rx_index:                   Receive data count; for bookkeeping during
 151  *                              transfer
 152  * @tx_buff:                    Buffer for data to be transmitted
 153  * @rx_index:                   Buffer for Received data
 154  * @n_curnt_chip:               The chip number that this SPI driver currently
 155  *                              operates on
 156  * @current_chip:               Reference to the current chip that this SPI
 157  *                              driver currently operates on
 158  * @current_msg:                The current message that this SPI driver is
 159  *                              handling
 160  * @cur_trans:                  The current transfer that this SPI driver is
 161  *                              handling
 162  * @board_dat:                  Reference to the SPI device data structure
 163  * @plat_dev:                   platform_device structure
 164  * @ch:                         SPI channel number
 165  * @irq_reg_sts:                Status of IRQ registration
 166  */
 167 struct pch_spi_data {
 168         void __iomem *io_remap_addr;
 169         unsigned long io_base_addr;
 170         struct spi_master *master;
 171         struct work_struct work;
 172         struct workqueue_struct *wk;
 173         wait_queue_head_t wait;
 174         u8 transfer_complete;
 175         u8 bcurrent_msg_processing;
 176         spinlock_t lock;
 177         struct list_head queue;
 178         u8 status;
 179         u32 bpw_len;
 180         u8 transfer_active;
 181         u32 tx_index;
 182         u32 rx_index;
 183         u16 *pkt_tx_buff;
 184         u16 *pkt_rx_buff;
 185         u8 n_curnt_chip;
 186         struct spi_device *current_chip;
 187         struct spi_message *current_msg;
 188         struct spi_transfer *cur_trans;
 189         struct pch_spi_board_data *board_dat;
 190         struct platform_device  *plat_dev;
 191         int ch;
 192         struct pch_spi_dma_ctrl dma;
 193         int use_dma;
 194         u8 irq_reg_sts;
 195         int save_total_len;
 196 };
 197
 198 /**
 199  * struct pch_spi_board_data - Holds the SPI device specific details
 200  * @pdev:               Pointer to the PCI device
 201  * @suspend_sts:        Status of suspend
 202  * @num:                The number of SPI device instance
 203  */
 204 struct pch_spi_board_data {
 205         struct pci_dev *pdev;
 206         u8 suspend_sts;
 207         int num;
 208 };
 209
 210 struct pch_pd_dev_save {
 211         int num;
 212         struct platform_device *pd_save[PCH_SPI_MAX_DEV];
 213         struct pch_spi_board_data *board_dat;
 214 };
 215
 216 static const struct pci_device_id pch_spi_pcidev_id[] = {
 217         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),    1, },
 218         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
 219         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
 220         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
 221         { }
 222 };
 223
 224 /**
 225  * pch_spi_writereg() - Performs  register writes
 226  * @master:     Pointer to struct spi_master.
 227  * @idx:        Register offset.
 228  * @val:        Value to be written to register.
 229  */
 230 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
 231 {
 232         struct pch_spi_data *data = spi_master_get_devdata(master);
 233         iowrite32(val, (data->io_remap_addr + idx));
 234 }
 235
 236 /**
 237  * pch_spi_readreg() - Performs register reads
 238  * @master:     Pointer to struct spi_master.
 239  * @idx:        Register offset.
 240  */
 241 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
 242 {
 243         struct pch_spi_data *data = spi_master_get_devdata(master);
 244         return ioread32(data->io_remap_addr + idx);
 245 }
 246
 247 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
 248                                       u32 set, u32 clr)
 249 {
 250         u32 tmp = pch_spi_readreg(master, idx);
 251         tmp = (tmp & ~clr) | set;
 252         pch_spi_writereg(master, idx, tmp);
 253 }
 254
 255 static void pch_spi_set_master_mode(struct spi_master *master)
 256 {
 257         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
 258 }
 259
 260 /**
 261  * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
 262  * @master:     Pointer to struct spi_master.
 263  */
 264 static void pch_spi_clear_fifo(struct spi_master *master)
 265 {
 266         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
 267         pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
 268 }
 269
 270 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
 271                                 void __iomem *io_remap_addr)
 272 {
 273         u32 n_read, tx_index, rx_index, bpw_len;
 274         u16 *pkt_rx_buffer, *pkt_tx_buff;
 275         int read_cnt;
 276         u32 reg_spcr_val;
 277         void __iomem *spsr;
 278         void __iomem *spdrr;
 279         void __iomem *spdwr;
 280
 281         spsr = io_remap_addr + PCH_SPSR;
 282         iowrite32(reg_spsr_val, spsr);
 283
 284         if (data->transfer_active) {
 285                 rx_index = data->rx_index;
 286                 tx_index = data->tx_index;
 287                 bpw_len = data->bpw_len;
 288                 pkt_rx_buffer = data->pkt_rx_buff;
 289                 pkt_tx_buff = data->pkt_tx_buff;
 290
 291                 spdrr = io_remap_addr + PCH_SPDRR;
 292                 spdwr = io_remap_addr + PCH_SPDWR;
 293
 294                 n_read = PCH_READABLE(reg_spsr_val);
 295
 296                 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
 297                         pkt_rx_buffer[rx_index++] = ioread32(spdrr);
 298                         if (tx_index < bpw_len)
 299                                 iowrite32(pkt_tx_buff[tx_index++], spdwr);
 300                 }
 301
 302                 /* disable RFI if not needed */
 303                 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
 304                         reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
 305                         reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
 306
 307                         /* reset rx threshold */
 308                         reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
 309                         reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
 310
 311                         iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
 312                 }
 313
 314                 /* update counts */
 315                 data->tx_index = tx_index;
 316                 data->rx_index = rx_index;
 317
 318                 /* if transfer complete interrupt */
 319                 if (reg_spsr_val & SPSR_FI_BIT) {
 320                         if ((tx_index == bpw_len) && (rx_index == tx_index)) {
 321                                 /* disable interrupts */
 322                                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
 323                                                    PCH_ALL);
 324
 325                                 /* transfer is completed;
 326                                    inform pch_spi_process_messages */
 327                                 data->transfer_complete = true;
 328                                 data->transfer_active = false;
 329                                 wake_up(&data->wait);
 330                         } else {
 331                                 dev_vdbg(&data->master->dev,
 332                                         "%s : Transfer is not completed",
 333                                         __func__);
 334                         }
 335                 }
 336         }
 337 }
 338
 339 /**
 340  * pch_spi_handler() - Interrupt handler
 341  * @irq:        The interrupt number.
 342  * @dev_id:     Pointer to struct pch_spi_board_data.
 343  */
 344 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
 345 {
 346         u32 reg_spsr_val;
 347         void __iomem *spsr;
 348         void __iomem *io_remap_addr;
 349         irqreturn_t ret = IRQ_NONE;
 350         struct pch_spi_data *data = dev_id;
 351         struct pch_spi_board_data *board_dat = data->board_dat;
 352
 353         if (board_dat->suspend_sts) {
 354                 dev_dbg(&board_dat->pdev->dev,
 355                         "%s returning due to suspend\n", __func__);
 356                 return IRQ_NONE;
 357         }
 358
 359         io_remap_addr = data->io_remap_addr;
 360         spsr = io_remap_addr + PCH_SPSR;
 361
 362         reg_spsr_val = ioread32(spsr);
 363
 364         if (reg_spsr_val & SPSR_ORF_BIT) {
 365                 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
 366                 if (data->current_msg->complete) {
 367                         data->transfer_complete = true;
 368                         data->current_msg->status = -EIO;
 369                         data->current_msg->complete(data->current_msg->context);
 370                         data->bcurrent_msg_processing = false;
 371                         data->current_msg = NULL;
 372                         data->cur_trans = NULL;
 373                 }
 374         }
 375
 376         if (data->use_dma)
 377                 return IRQ_NONE;
 378
 379         /* Check if the interrupt is for SPI device */
 380         if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
 381                 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
 382                 ret = IRQ_HANDLED;
 383         }
 384
 385         dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
 386                 __func__, ret);
 387
 388         return ret;
 389 }
 390
 391 /**
 392  * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
 393  * @master:     Pointer to struct spi_master.
 394  * @speed_hz:   Baud rate.
 395  */
 396 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
 397 {
 398         u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
 399
 400         /* if baud rate is less than we can support limit it */
 401         if (n_spbr > PCH_MAX_SPBR)
 402                 n_spbr = PCH_MAX_SPBR;
 403
 404         pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
 405 }
 406
 407 /**
 408  * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
 409  * @master:             Pointer to struct spi_master.
 410  * @bits_per_word:      Bits per word for SPI transfer.
 411  */
 412 static void pch_spi_set_bits_per_word(struct spi_master *master,
 413                                       u8 bits_per_word)
 414 {
 415         if (bits_per_word == 8)
 416                 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
 417         else
 418                 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
 419 }
 420
 421 /**
 422  * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
 423  * @spi:        Pointer to struct spi_device.
 424  */
 425 static void pch_spi_setup_transfer(struct spi_device *spi)
 426 {
 427         u32 flags = 0;
 428
 429         dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
 430                 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
 431                 spi->max_speed_hz);
 432         pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
 433
 434         /* set bits per word */
 435         pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
 436
 437         if (!(spi->mode & SPI_LSB_FIRST))
 438                 flags |= SPCR_LSBF_BIT;
 439         if (spi->mode & SPI_CPOL)
 440                 flags |= SPCR_CPOL_BIT;
 441         if (spi->mode & SPI_CPHA)
 442                 flags |= SPCR_CPHA_BIT;
 443         pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
 444                            (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
 445
 446         /* Clear the FIFO by toggling  FICLR to 1 and back to 0 */
 447         pch_spi_clear_fifo(spi->master);
 448 }
 449
 450 /**
 451  * pch_spi_reset() - Clears SPI registers
 452  * @master:     Pointer to struct spi_master.
 453  */
 454 static void pch_spi_reset(struct spi_master *master)
 455 {
 456         /* write 1 to reset SPI */
 457         pch_spi_writereg(master, PCH_SRST, 0x1);
 458
 459         /* clear reset */
 460         pch_spi_writereg(master, PCH_SRST, 0x0);
 461 }
 462
 463 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
 464 {
 465
 466         struct spi_transfer *transfer;
 467         struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
 468         int retval;
 469         unsigned long flags;
 470
 471         spin_lock_irqsave(&data->lock, flags);
 472         /* validate Tx/Rx buffers and Transfer length */
 473         list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
 474                 if (!transfer->tx_buf && !transfer->rx_buf) {
 475                         dev_err(&pspi->dev,
 476                                 "%s Tx and Rx buffer NULL\n", __func__);
 477                         retval = -EINVAL;
 478                         goto err_return_spinlock;
 479                 }
 480
 481                 if (!transfer->len) {
 482                         dev_err(&pspi->dev, "%s Transfer length invalid\n",
 483                                 __func__);
 484                         retval = -EINVAL;
 485                         goto err_return_spinlock;
 486                 }
 487
 488                 dev_dbg(&pspi->dev,
 489                         "%s Tx/Rx buffer valid. Transfer length valid\n",
 490                         __func__);
 491         }
 492         spin_unlock_irqrestore(&data->lock, flags);
 493
 494         /* We won't process any messages if we have been asked to terminate */
 495         if (data->status == STATUS_EXITING) {
 496                 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
 497                 retval = -ESHUTDOWN;
 498                 goto err_out;
 499         }
 500
 501         /* If suspended ,return -EINVAL */
 502         if (data->board_dat->suspend_sts) {
 503                 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
 504                 retval = -EINVAL;
 505                 goto err_out;
 506         }
 507
 508         /* set status of message */
 509         pmsg->actual_length = 0;
 510         dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
 511
 512         pmsg->status = -EINPROGRESS;
 513         spin_lock_irqsave(&data->lock, flags);
 514         /* add message to queue */
 515         list_add_tail(&pmsg->queue, &data->queue);
 516         spin_unlock_irqrestore(&data->lock, flags);
 517
 518         dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
 519
 520         /* schedule work queue to run */
 521         queue_work(data->wk, &data->work);
 522         dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
 523
 524         retval = 0;
 525
 526 err_out:
 527         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 528         return retval;
 529 err_return_spinlock:
 530         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 531         spin_unlock_irqrestore(&data->lock, flags);
 532         return retval;
 533 }
 534
 535 static inline void pch_spi_select_chip(struct pch_spi_data *data,
 536                                        struct spi_device *pspi)
 537 {
 538         if (data->current_chip != NULL) {
 539                 if (pspi->chip_select != data->n_curnt_chip) {
 540                         dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
 541                         data->current_chip = NULL;
 542                 }
 543         }
 544
 545         data->current_chip = pspi;
 546
 547         data->n_curnt_chip = data->current_chip->chip_select;
 548
 549         dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
 550         pch_spi_setup_transfer(pspi);
 551 }
 552
 553 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
 554 {
 555         int size;
 556         u32 n_writes;
 557         int j;
 558         struct spi_message *pmsg, *tmp;
 559         const u8 *tx_buf;
 560         const u16 *tx_sbuf;
 561
 562         /* set baud rate if needed */
 563         if (data->cur_trans->speed_hz) {
 564                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 565                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 566         }
 567
 568         /* set bits per word if needed */
 569         if (data->cur_trans->bits_per_word &&
 570             (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
 571                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
 572                 pch_spi_set_bits_per_word(data->master,
 573                                           data->cur_trans->bits_per_word);
 574                 *bpw = data->cur_trans->bits_per_word;
 575         } else {
 576                 *bpw = data->current_msg->spi->bits_per_word;
 577         }
 578
 579         /* reset Tx/Rx index */
 580         data->tx_index = 0;
 581         data->rx_index = 0;
 582
 583         data->bpw_len = data->cur_trans->len / (*bpw / 8);
 584
 585         /* find alloc size */
 586         size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
 587
 588         /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
 589         data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
 590         if (data->pkt_tx_buff != NULL) {
 591                 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
 592                 if (!data->pkt_rx_buff) {
 593                         kfree(data->pkt_tx_buff);
 594                         data->pkt_tx_buff = NULL;
 595                 }
 596         }
 597
 598         if (!data->pkt_rx_buff) {
 599                 /* flush queue and set status of all transfers to -ENOMEM */
 600                 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
 601                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
 602                         pmsg->status = -ENOMEM;
 603
 604                         if (pmsg->complete)
 605                                 pmsg->complete(pmsg->context);
 606
 607                         /* delete from queue */
 608                         list_del_init(&pmsg->queue);
 609                 }
 610                 return;
 611         }
 612
 613         /* copy Tx Data */
 614         if (data->cur_trans->tx_buf != NULL) {
 615                 if (*bpw == 8) {
 616                         tx_buf = data->cur_trans->tx_buf;
 617                         for (j = 0; j < data->bpw_len; j++)
 618                                 data->pkt_tx_buff[j] = *tx_buf++;
 619                 } else {
 620                         tx_sbuf = data->cur_trans->tx_buf;
 621                         for (j = 0; j < data->bpw_len; j++)
 622                                 data->pkt_tx_buff[j] = *tx_sbuf++;
 623                 }
 624         }
 625
 626         /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
 627         n_writes = data->bpw_len;
 628         if (n_writes > PCH_MAX_FIFO_DEPTH)
 629                 n_writes = PCH_MAX_FIFO_DEPTH;
 630
 631         dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
 632                 "0x2 to SSNXCR\n", __func__);
 633         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
 634
 635         for (j = 0; j < n_writes; j++)
 636                 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
 637
 638         /* update tx_index */
 639         data->tx_index = j;
 640
 641         /* reset transfer complete flag */
 642         data->transfer_complete = false;
 643         data->transfer_active = true;
 644 }
 645
 646 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
 647 {
 648         struct spi_message *pmsg, *tmp;
 649         dev_dbg(&data->master->dev, "%s called\n", __func__);
 650         /* Invoke complete callback
 651          * [To the spi core..indicating end of transfer] */
 652         data->current_msg->status = 0;
 653
 654         if (data->current_msg->complete) {
 655                 dev_dbg(&data->master->dev,
 656                         "%s:Invoking callback of SPI core\n", __func__);
 657                 data->current_msg->complete(data->current_msg->context);
 658         }
 659
 660         /* update status in global variable */
 661         data->bcurrent_msg_processing = false;
 662
 663         dev_dbg(&data->master->dev,
 664                 "%s:data->bcurrent_msg_processing = false\n", __func__);
 665
 666         data->current_msg = NULL;
 667         data->cur_trans = NULL;
 668
 669         /* check if we have items in list and not suspending
 670          * return 1 if list empty */
 671         if ((list_empty(&data->queue) == 0) &&
 672             (!data->board_dat->suspend_sts) &&
 673             (data->status != STATUS_EXITING)) {
 674                 /* We have some more work to do (either there is more tranint
 675                  * bpw;sfer requests in the current message or there are
 676                  *more messages)
 677                  */
 678                 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
 679                 queue_work(data->wk, &data->work);
 680         } else if (data->board_dat->suspend_sts ||
 681                    data->status == STATUS_EXITING) {
 682                 dev_dbg(&data->master->dev,
 683                         "%s suspend/remove initiated, flushing queue\n",
 684                         __func__);
 685                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
 686                         pmsg->status = -EIO;
 687
 688                         if (pmsg->complete)
 689                                 pmsg->complete(pmsg->context);
 690
 691                         /* delete from queue */
 692                         list_del_init(&pmsg->queue);
 693                 }
 694         }
 695 }
 696
 697 static void pch_spi_set_ir(struct pch_spi_data *data)
 698 {
 699         /* enable interrupts, set threshold, enable SPI */
 700         if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
 701                 /* set receive threshold to PCH_RX_THOLD */
 702                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 703                                    PCH_RX_THOLD << SPCR_RFIC_FIELD |
 704                                    SPCR_FIE_BIT | SPCR_RFIE_BIT |
 705                                    SPCR_ORIE_BIT | SPCR_SPE_BIT,
 706                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 707         else
 708                 /* set receive threshold to maximum */
 709                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 710                                    PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
 711                                    SPCR_FIE_BIT | SPCR_ORIE_BIT |
 712                                    SPCR_SPE_BIT,
 713                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 714
 715         /* Wait until the transfer completes; go to sleep after
 716                                  initiating the transfer. */
 717         dev_dbg(&data->master->dev,
 718                 "%s:waiting for transfer to get over\n", __func__);
 719
 720         wait_event_interruptible(data->wait, data->transfer_complete);
 721
 722         /* clear all interrupts */
 723         pch_spi_writereg(data->master, PCH_SPSR,
 724                          pch_spi_readreg(data->master, PCH_SPSR));
 725         /* Disable interrupts and SPI transfer */
 726         pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
 727         /* clear FIFO */
 728         pch_spi_clear_fifo(data->master);
 729 }
 730
 731 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
 732 {
 733         int j;
 734         u8 *rx_buf;
 735         u16 *rx_sbuf;
 736
 737         /* copy Rx Data */
 738         if (!data->cur_trans->rx_buf)
 739                 return;
 740
 741         if (bpw == 8) {
 742                 rx_buf = data->cur_trans->rx_buf;
 743                 for (j = 0; j < data->bpw_len; j++)
 744                         *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
 745         } else {
 746                 rx_sbuf = data->cur_trans->rx_buf;
 747                 for (j = 0; j < data->bpw_len; j++)
 748                         *rx_sbuf++ = data->pkt_rx_buff[j];
 749         }
 750 }
 751
 752 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
 753 {
 754         int j;
 755         u8 *rx_buf;
 756         u16 *rx_sbuf;
 757         const u8 *rx_dma_buf;
 758         const u16 *rx_dma_sbuf;
 759
 760         /* copy Rx Data */
 761         if (!data->cur_trans->rx_buf)
 762                 return;
 763
 764         if (bpw == 8) {
 765                 rx_buf = data->cur_trans->rx_buf;
 766                 rx_dma_buf = data->dma.rx_buf_virt;
 767                 for (j = 0; j < data->bpw_len; j++)
 768                         *rx_buf++ = *rx_dma_buf++ & 0xFF;
 769                 data->cur_trans->rx_buf = rx_buf;
 770         } else {
 771                 rx_sbuf = data->cur_trans->rx_buf;
 772                 rx_dma_sbuf = data->dma.rx_buf_virt;
 773                 for (j = 0; j < data->bpw_len; j++)
 774                         *rx_sbuf++ = *rx_dma_sbuf++;
 775                 data->cur_trans->rx_buf = rx_sbuf;
 776         }
 777 }
 778
 779 static int pch_spi_start_transfer(struct pch_spi_data *data)
 780 {
 781         struct pch_spi_dma_ctrl *dma;
 782         unsigned long flags;
 783         int rtn;
 784
 785         dma = &data->dma;
 786
 787         spin_lock_irqsave(&data->lock, flags);
 788
 789         /* disable interrupts, SPI set enable */
 790         pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
 791
 792         spin_unlock_irqrestore(&data->lock, flags);
 793
 794         /* Wait until the transfer completes; go to sleep after
 795                                  initiating the transfer. */
 796         dev_dbg(&data->master->dev,
 797                 "%s:waiting for transfer to get over\n", __func__);
 798         rtn = wait_event_interruptible_timeout(data->wait,
 799                                                data->transfer_complete,
 800                                                msecs_to_jiffies(2 * HZ));
 801         if (!rtn)
 802                 dev_err(&data->master->dev,
 803                         "%s wait-event timeout\n", __func__);
 804
 805         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
 806                             DMA_FROM_DEVICE);
 807
 808         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
 809                             DMA_FROM_DEVICE);
 810         memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
 811
 812         async_tx_ack(dma->desc_rx);
 813         async_tx_ack(dma->desc_tx);
 814         kfree(dma->sg_tx_p);
 815         kfree(dma->sg_rx_p);
 816
 817         spin_lock_irqsave(&data->lock, flags);
 818
 819         /* clear fifo threshold, disable interrupts, disable SPI transfer */
 820         pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
 821                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
 822                            SPCR_SPE_BIT);
 823         /* clear all interrupts */
 824         pch_spi_writereg(data->master, PCH_SPSR,
 825                          pch_spi_readreg(data->master, PCH_SPSR));
 826         /* clear FIFO */
 827         pch_spi_clear_fifo(data->master);
 828
 829         spin_unlock_irqrestore(&data->lock, flags);
 830
 831         return rtn;
 832 }
 833
 834 static void pch_dma_rx_complete(void *arg)
 835 {
 836         struct pch_spi_data *data = arg;
 837
 838         /* transfer is completed;inform pch_spi_process_messages_dma */
 839         data->transfer_complete = true;
 840         wake_up_interruptible(&data->wait);
 841 }
 842
 843 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
 844 {
 845         struct pch_dma_slave *param = slave;
 846
 847         if ((chan->chan_id == param->chan_id) &&
 848             (param->dma_dev == chan->device->dev)) {
 849                 chan->private = param;
 850                 return true;
 851         } else {
 852                 return false;
 853         }
 854 }
 855
 856 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
 857 {
 858         dma_cap_mask_t mask;
 859         struct dma_chan *chan;
 860         struct pci_dev *dma_dev;
 861         struct pch_dma_slave *param;
 862         struct pch_spi_dma_ctrl *dma;
 863         unsigned int width;
 864
 865         if (bpw == 8)
 866                 width = PCH_DMA_WIDTH_1_BYTE;
 867         else
 868                 width = PCH_DMA_WIDTH_2_BYTES;
 869
 870         dma = &data->dma;
 871         dma_cap_zero(mask);
 872         dma_cap_set(DMA_SLAVE, mask);
 873
 874         /* Get DMA's dev information */
 875         dma_dev = pci_get_slot(data->board_dat->pdev->bus,
 876                         PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
 877
 878         /* Set Tx DMA */
 879         param = &dma->param_tx;
 880         param->dma_dev = &dma_dev->dev;
 881         param->chan_id = data->ch * 2; /* Tx = 0, 2 */;
 882         param->tx_reg = data->io_base_addr + PCH_SPDWR;
 883         param->width = width;
 884         chan = dma_request_channel(mask, pch_spi_filter, param);
 885         if (!chan) {
 886                 dev_err(&data->master->dev,
 887                         "ERROR: dma_request_channel FAILS(Tx)\n");
 888                 data->use_dma = 0;
 889                 return;
 890         }
 891         dma->chan_tx = chan;
 892
 893         /* Set Rx DMA */
 894         param = &dma->param_rx;
 895         param->dma_dev = &dma_dev->dev;
 896         param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */;
 897         param->rx_reg = data->io_base_addr + PCH_SPDRR;
 898         param->width = width;
 899         chan = dma_request_channel(mask, pch_spi_filter, param);
 900         if (!chan) {
 901                 dev_err(&data->master->dev,
 902                         "ERROR: dma_request_channel FAILS(Rx)\n");
 903                 dma_release_channel(dma->chan_tx);
 904                 dma->chan_tx = NULL;
 905                 data->use_dma = 0;
 906                 return;
 907         }
 908         dma->chan_rx = chan;
 909 }
 910
 911 static void pch_spi_release_dma(struct pch_spi_data *data)
 912 {
 913         struct pch_spi_dma_ctrl *dma;
 914
 915         dma = &data->dma;
 916         if (dma->chan_tx) {
 917                 dma_release_channel(dma->chan_tx);
 918                 dma->chan_tx = NULL;
 919         }
 920         if (dma->chan_rx) {
 921                 dma_release_channel(dma->chan_rx);
 922                 dma->chan_rx = NULL;
 923         }
 924         return;
 925 }
 926
 927 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
 928 {
 929         const u8 *tx_buf;
 930         const u16 *tx_sbuf;
 931         u8 *tx_dma_buf;
 932         u16 *tx_dma_sbuf;
 933         struct scatterlist *sg;
 934         struct dma_async_tx_descriptor *desc_tx;
 935         struct dma_async_tx_descriptor *desc_rx;
 936         int num;
 937         int i;
 938         int size;
 939         int rem;
 940         int head;
 941         unsigned long flags;
 942         struct pch_spi_dma_ctrl *dma;
 943
 944         dma = &data->dma;
 945
 946         /* set baud rate if needed */
 947         if (data->cur_trans->speed_hz) {
 948                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 949                 spin_lock_irqsave(&data->lock, flags);
 950                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 951                 spin_unlock_irqrestore(&data->lock, flags);
 952         }
 953
 954         /* set bits per word if needed */
 955         if (data->cur_trans->bits_per_word &&
 956             (data->current_msg->spi->bits_per_word !=
 957              data->cur_trans->bits_per_word)) {
 958                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
 959                 spin_lock_irqsave(&data->lock, flags);
 960                 pch_spi_set_bits_per_word(data->master,
 961                                           data->cur_trans->bits_per_word);
 962                 spin_unlock_irqrestore(&data->lock, flags);
 963                 *bpw = data->cur_trans->bits_per_word;
 964         } else {
 965                 *bpw = data->current_msg->spi->bits_per_word;
 966         }
 967         data->bpw_len = data->cur_trans->len / (*bpw / 8);
 968
 969         if (data->bpw_len > PCH_BUF_SIZE) {
 970                 data->bpw_len = PCH_BUF_SIZE;
 971                 data->cur_trans->len -= PCH_BUF_SIZE;
 972         }
 973
 974         /* copy Tx Data */
 975         if (data->cur_trans->tx_buf != NULL) {
 976                 if (*bpw == 8) {
 977                         tx_buf = data->cur_trans->tx_buf;
 978                         tx_dma_buf = dma->tx_buf_virt;
 979                         for (i = 0; i < data->bpw_len; i++)
 980                                 *tx_dma_buf++ = *tx_buf++;
 981                 } else {
 982                         tx_sbuf = data->cur_trans->tx_buf;
 983                         tx_dma_sbuf = dma->tx_buf_virt;
 984                         for (i = 0; i < data->bpw_len; i++)
 985                                 *tx_dma_sbuf++ = *tx_sbuf++;
 986                 }
 987         }
 988
 989         /* Calculate Rx parameter for DMA transmitting */
 990         if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
 991                 if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
 992                         num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
 993                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
 994                 } else {
 995                         num = data->bpw_len / PCH_DMA_TRANS_SIZE;
 996                         rem = PCH_DMA_TRANS_SIZE;
 997                 }
 998                 size = PCH_DMA_TRANS_SIZE;
 999         } else {
1000                 num = 1;
1001                 size = data->bpw_len;
1002                 rem = data->bpw_len;
1003         }
1004         dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1005                 __func__, num, size, rem);
1006         spin_lock_irqsave(&data->lock, flags);
1007
1008         /* set receive fifo threshold and transmit fifo threshold */
1009         pch_spi_setclr_reg(data->master, PCH_SPCR,
1010                            ((size - 1) << SPCR_RFIC_FIELD) |
1011                            (PCH_TX_THOLD << SPCR_TFIC_FIELD),
1012                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1013
1014         spin_unlock_irqrestore(&data->lock, flags);
1015
1016         /* RX */
1017         dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1018         sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1019         /* offset, length setting */
1020         sg = dma->sg_rx_p;
1021         for (i = 0; i < num; i++, sg++) {
1022                 if (i == (num - 2)) {
1023                         sg->offset = size * i;
1024                         sg->offset = sg->offset * (*bpw / 8);
1025                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1026                                     sg->offset);
1027                         sg_dma_len(sg) = rem;
1028                 } else if (i == (num - 1)) {
1029                         sg->offset = size * (i - 1) + rem;
1030                         sg->offset = sg->offset * (*bpw / 8);
1031                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1032                                     sg->offset);
1033                         sg_dma_len(sg) = size;
1034                 } else {
1035                         sg->offset = size * i;
1036                         sg->offset = sg->offset * (*bpw / 8);
1037                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1038                                     sg->offset);
1039                         sg_dma_len(sg) = size;
1040                 }
1041                 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1042         }
1043         sg = dma->sg_rx_p;
1044         desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
1045                                         num, DMA_DEV_TO_MEM,
1046                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1047         if (!desc_rx) {
1048                 dev_err(&data->master->dev,
1049                         "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1050                 return;
1051         }
1052         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1053         desc_rx->callback = pch_dma_rx_complete;
1054         desc_rx->callback_param = data;
1055         dma->nent = num;
1056         dma->desc_rx = desc_rx;
1057
1058         /* Calculate Tx parameter for DMA transmitting */
1059         if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
1060                 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
1061                 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
1062                         num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1063                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
1064                 } else {
1065                         num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1066                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
1067                               PCH_DMA_TRANS_SIZE - head;
1068                 }
1069                 size = PCH_DMA_TRANS_SIZE;
1070         } else {
1071                 num = 1;
1072                 size = data->bpw_len;
1073                 rem = data->bpw_len;
1074                 head = 0;
1075         }
1076
1077         dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1078         sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1079         /* offset, length setting */
1080         sg = dma->sg_tx_p;
1081         for (i = 0; i < num; i++, sg++) {
1082                 if (i == 0) {
1083                         sg->offset = 0;
1084                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
1085                                     sg->offset);
1086                         sg_dma_len(sg) = size + head;
1087                 } else if (i == (num - 1)) {
1088                         sg->offset = head + size * i;
1089                         sg->offset = sg->offset * (*bpw / 8);
1090                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1091                                     sg->offset);
1092                         sg_dma_len(sg) = rem;
1093                 } else {
1094                         sg->offset = head + size * i;
1095                         sg->offset = sg->offset * (*bpw / 8);
1096                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1097                                     sg->offset);
1098                         sg_dma_len(sg) = size;
1099                 }
1100                 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1101         }
1102         sg = dma->sg_tx_p;
1103         desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
1104                                         sg, num, DMA_MEM_TO_DEV,
1105                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1106         if (!desc_tx) {
1107                 dev_err(&data->master->dev,
1108                         "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1109                 return;
1110         }
1111         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1112         desc_tx->callback = NULL;
1113         desc_tx->callback_param = data;
1114         dma->nent = num;
1115         dma->desc_tx = desc_tx;
1116
1117         dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1118
1119         spin_lock_irqsave(&data->lock, flags);
1120         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1121         desc_rx->tx_submit(desc_rx);
1122         desc_tx->tx_submit(desc_tx);
1123         spin_unlock_irqrestore(&data->lock, flags);
1124
1125         /* reset transfer complete flag */
1126         data->transfer_complete = false;
1127 }
1128
1129 static void pch_spi_process_messages(struct work_struct *pwork)
1130 {
1131         struct spi_message *pmsg, *tmp;
1132         struct pch_spi_data *data;
1133         int bpw;
1134
1135         data = container_of(pwork, struct pch_spi_data, work);
1136         dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1137
1138         spin_lock(&data->lock);
1139         /* check if suspend has been initiated;if yes flush queue */
1140         if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1141                 dev_dbg(&data->master->dev,
1142                         "%s suspend/remove initiated, flushing queue\n", __func__);
1143                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
1144                         pmsg->status = -EIO;
1145
1146                         if (pmsg->complete) {
1147                                 spin_unlock(&data->lock);
1148                                 pmsg->complete(pmsg->context);
1149                                 spin_lock(&data->lock);
1150                         }
1151
1152                         /* delete from queue */
1153                         list_del_init(&pmsg->queue);
1154                 }
1155
1156                 spin_unlock(&data->lock);
1157                 return;
1158         }
1159
1160         data->bcurrent_msg_processing = true;
1161         dev_dbg(&data->master->dev,
1162                 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1163
1164         /* Get the message from the queue and delete it from there. */
1165         data->current_msg = list_entry(data->queue.next, struct spi_message,
1166                                         queue);
1167
1168         list_del_init(&data->current_msg->queue);
1169
1170         data->current_msg->status = 0;
1171
1172         pch_spi_select_chip(data, data->current_msg->spi);
1173
1174         spin_unlock(&data->lock);
1175
1176         if (data->use_dma)
1177                 pch_spi_request_dma(data,
1178                                     data->current_msg->spi->bits_per_word);
1179         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1180         do {
1181                 int cnt;
1182                 /* If we are already processing a message get the next
1183                 transfer structure from the message otherwise retrieve
1184                 the 1st transfer request from the message. */
1185                 spin_lock(&data->lock);
1186                 if (data->cur_trans == NULL) {
1187                         data->cur_trans =
1188                                 list_entry(data->current_msg->transfers.next,
1189                                            struct spi_transfer, transfer_list);
1190                         dev_dbg(&data->master->dev, "%s "
1191                                 ":Getting 1st transfer message\n", __func__);
1192                 } else {
1193                         data->cur_trans =
1194                                 list_entry(data->cur_trans->transfer_list.next,
1195                                            struct spi_transfer, transfer_list);
1196                         dev_dbg(&data->master->dev, "%s "
1197                                 ":Getting next transfer message\n", __func__);
1198                 }
1199                 spin_unlock(&data->lock);
1200
1201                 if (!data->cur_trans->len)
1202                         goto out;
1203                 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
1204                 data->save_total_len = data->cur_trans->len;
1205                 if (data->use_dma) {
1206                         int i;
1207                         char *save_rx_buf = data->cur_trans->rx_buf;
1208                         for (i = 0; i < cnt; i ++) {
1209                                 pch_spi_handle_dma(data, &bpw);
1210                                 if (!pch_spi_start_transfer(data)) {
1211                                         data->transfer_complete = true;
1212                                         data->current_msg->status = -EIO;
1213                                         data->current_msg->complete
1214                                                    (data->current_msg->context);
1215                                         data->bcurrent_msg_processing = false;
1216                                         data->current_msg = NULL;
1217                                         data->cur_trans = NULL;
1218                                         goto out;
1219                                 }
1220                                 pch_spi_copy_rx_data_for_dma(data, bpw);
1221                         }
1222                         data->cur_trans->rx_buf = save_rx_buf;
1223                 } else {
1224                         pch_spi_set_tx(data, &bpw);
1225                         pch_spi_set_ir(data);
1226                         pch_spi_copy_rx_data(data, bpw);
1227                         kfree(data->pkt_rx_buff);
1228                         data->pkt_rx_buff = NULL;
1229                         kfree(data->pkt_tx_buff);
1230                         data->pkt_tx_buff = NULL;
1231                 }
1232                 /* increment message count */
1233                 data->cur_trans->len = data->save_total_len;
1234                 data->current_msg->actual_length += data->cur_trans->len;
1235
1236                 dev_dbg(&data->master->dev,
1237                         "%s:data->current_msg->actual_length=%d\n",
1238                         __func__, data->current_msg->actual_length);
1239
1240                 /* check for delay */
1241                 if (data->cur_trans->delay_usecs) {
1242                         dev_dbg(&data->master->dev, "%s:"
1243                                 "delay in usec=%d\n", __func__,
1244                                 data->cur_trans->delay_usecs);
1245                         udelay(data->cur_trans->delay_usecs);
1246                 }
1247
1248                 spin_lock(&data->lock);
1249
1250                 /* No more transfer in this message. */
1251                 if ((data->cur_trans->transfer_list.next) ==
1252                     &(data->current_msg->transfers)) {
1253                         pch_spi_nomore_transfer(data);
1254                 }
1255
1256                 spin_unlock(&data->lock);
1257
1258         } while (data->cur_trans != NULL);
1259
1260 out:
1261         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1262         if (data->use_dma)
1263                 pch_spi_release_dma(data);
1264 }
1265
1266 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1267                                    struct pch_spi_data *data)
1268 {
1269         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1270
1271         /* free workqueue */
1272         if (data->wk != NULL) {
1273                 destroy_workqueue(data->wk);
1274                 data->wk = NULL;
1275                 dev_dbg(&board_dat->pdev->dev,
1276                         "%s destroy_workqueue invoked successfully\n",
1277                         __func__);
1278         }
1279 }
1280
1281 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1282                                  struct pch_spi_data *data)
1283 {
1284         int retval = 0;
1285
1286         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1287
1288         /* create workqueue */
1289         data->wk = create_singlethread_workqueue(KBUILD_MODNAME);
1290         if (!data->wk) {
1291                 dev_err(&board_dat->pdev->dev,
1292                         "%s create_singlet hread_workqueue failed\n", __func__);
1293                 retval = -EBUSY;
1294                 goto err_return;
1295         }
1296
1297         /* reset PCH SPI h/w */
1298         pch_spi_reset(data->master);
1299         dev_dbg(&board_dat->pdev->dev,
1300                 "%s pch_spi_reset invoked successfully\n", __func__);
1301
1302         dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1303
1304 err_return:
1305         if (retval != 0) {
1306                 dev_err(&board_dat->pdev->dev,
1307                         "%s FAIL:invoking pch_spi_free_resources\n", __func__);
1308                 pch_spi_free_resources(board_dat, data);
1309         }
1310
1311         dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1312
1313         return retval;
1314 }
1315
1316 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1317                              struct pch_spi_data *data)
1318 {
1319         struct pch_spi_dma_ctrl *dma;
1320
1321         dma = &data->dma;
1322         if (dma->tx_buf_dma)
1323                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1324                                   dma->tx_buf_virt, dma->tx_buf_dma);
1325         if (dma->rx_buf_dma)
1326                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1327                                   dma->rx_buf_virt, dma->rx_buf_dma);
1328         return;
1329 }
1330
1331 static int pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1332                               struct pch_spi_data *data)
1333 {
1334         struct pch_spi_dma_ctrl *dma;
1335         int ret;
1336
1337         dma = &data->dma;
1338         ret = 0;
1339         /* Get Consistent memory for Tx DMA */
1340         dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1341                                 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1342         if (!dma->tx_buf_virt)
1343                 ret = -ENOMEM;
1344
1345         /* Get Consistent memory for Rx DMA */
1346         dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1347                                 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1348         if (!dma->rx_buf_virt)
1349                 ret = -ENOMEM;
1350
1351         return ret;
1352 }
1353
1354 static int pch_spi_pd_probe(struct platform_device *plat_dev)
1355 {
1356         int ret;
1357         struct spi_master *master;
1358         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1359         struct pch_spi_data *data;
1360
1361         dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1362
1363         master = spi_alloc_master(&board_dat->pdev->dev,
1364                                   sizeof(struct pch_spi_data));
1365         if (!master) {
1366                 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1367                         plat_dev->id);
1368                 return -ENOMEM;
1369         }
1370
1371         data = spi_master_get_devdata(master);
1372         data->master = master;
1373
1374         platform_set_drvdata(plat_dev, data);
1375
1376         /* baseaddress + address offset) */
1377         data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1378                                          PCH_ADDRESS_SIZE * plat_dev->id;
1379         data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
1380         if (!data->io_remap_addr) {
1381                 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1382                 ret = -ENOMEM;
1383                 goto err_pci_iomap;
1384         }
1385         data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id;
1386
1387         dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1388                 plat_dev->id, data->io_remap_addr);
1389
1390         /* initialize members of SPI master */
1391         master->num_chipselect = PCH_MAX_CS;
1392         master->transfer = pch_spi_transfer;
1393         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1394         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1395         master->max_speed_hz = PCH_MAX_BAUDRATE;
1396
1397         data->board_dat = board_dat;
1398         data->plat_dev = plat_dev;
1399         data->n_curnt_chip = 255;
1400         data->status = STATUS_RUNNING;
1401         data->ch = plat_dev->id;
1402         data->use_dma = use_dma;
1403
1404         INIT_LIST_HEAD(&data->queue);
1405         spin_lock_init(&data->lock);
1406         INIT_WORK(&data->work, pch_spi_process_messages);
1407         init_waitqueue_head(&data->wait);
1408
1409         ret = pch_spi_get_resources(board_dat, data);
1410         if (ret) {
1411                 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1412                 goto err_spi_get_resources;
1413         }
1414
1415         ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1416                           IRQF_SHARED, KBUILD_MODNAME, data);
1417         if (ret) {
1418                 dev_err(&plat_dev->dev,
1419                         "%s request_irq failed\n", __func__);
1420                 goto err_request_irq;
1421         }
1422         data->irq_reg_sts = true;
1423
1424         pch_spi_set_master_mode(master);
1425
1426         if (use_dma) {
1427                 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1428                 ret = pch_alloc_dma_buf(board_dat, data);
1429                 if (ret)
1430                         goto err_spi_register_master;
1431         }
1432
1433         ret = spi_register_master(master);
1434         if (ret != 0) {
1435                 dev_err(&plat_dev->dev,
1436                         "%s spi_register_master FAILED\n", __func__);
1437                 goto err_spi_register_master;
1438         }
1439
1440         return 0;
1441
1442 err_spi_register_master:
1443         pch_free_dma_buf(board_dat, data);
1444         free_irq(board_dat->pdev->irq, data);
1445 err_request_irq:
1446         pch_spi_free_resources(board_dat, data);
1447 err_spi_get_resources:
1448         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1449 err_pci_iomap:
1450         spi_master_put(master);
1451
1452         return ret;
1453 }
1454
1455 static int pch_spi_pd_remove(struct platform_device *plat_dev)
1456 {
1457         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1458         struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1459         int count;
1460         unsigned long flags;
1461
1462         dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1463                 __func__, plat_dev->id, board_dat->pdev->irq);
1464
1465         if (use_dma)
1466                 pch_free_dma_buf(board_dat, data);
1467
1468         /* check for any pending messages; no action is taken if the queue
1469          * is still full; but at least we tried.  Unload anyway */
1470         count = 500;
1471         spin_lock_irqsave(&data->lock, flags);
1472         data->status = STATUS_EXITING;
1473         while ((list_empty(&data->queue) == 0) && --count) {
1474                 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1475                         __func__);
1476                 spin_unlock_irqrestore(&data->lock, flags);
1477                 msleep(PCH_SLEEP_TIME);
1478                 spin_lock_irqsave(&data->lock, flags);
1479         }
1480         spin_unlock_irqrestore(&data->lock, flags);
1481
1482         pch_spi_free_resources(board_dat, data);
1483         /* disable interrupts & free IRQ */
1484         if (data->irq_reg_sts) {
1485                 /* disable interrupts */
1486                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1487                 data->irq_reg_sts = false;
1488                 free_irq(board_dat->pdev->irq, data);
1489         }
1490
1491         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1492         spi_unregister_master(data->master);
1493
1494         return 0;
1495 }
1496 #ifdef CONFIG_PM
1497 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1498                               pm_message_t state)
1499 {
1500         u8 count;
1501         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1502         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1503
1504         dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1505
1506         if (!board_dat) {
1507                 dev_err(&pd_dev->dev,
1508                         "%s pci_get_drvdata returned NULL\n", __func__);
1509                 return -EFAULT;
1510         }
1511
1512         /* check if the current message is processed:
1513            Only after thats done the transfer will be suspended */
1514         count = 255;
1515         while ((--count) > 0) {
1516                 if (!(data->bcurrent_msg_processing))
1517                         break;
1518                 msleep(PCH_SLEEP_TIME);
1519         }
1520
1521         /* Free IRQ */
1522         if (data->irq_reg_sts) {
1523                 /* disable all interrupts */
1524                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1525                 pch_spi_reset(data->master);
1526                 free_irq(board_dat->pdev->irq, data);
1527
1528                 data->irq_reg_sts = false;
1529                 dev_dbg(&pd_dev->dev,
1530                         "%s free_irq invoked successfully.\n", __func__);
1531         }
1532
1533         return 0;
1534 }
1535
1536 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1537 {
1538         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1539         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1540         int retval;
1541
1542         if (!board_dat) {
1543                 dev_err(&pd_dev->dev,
1544                         "%s pci_get_drvdata returned NULL\n", __func__);
1545                 return -EFAULT;
1546         }
1547
1548         if (!data->irq_reg_sts) {
1549                 /* register IRQ */
1550                 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1551                                      IRQF_SHARED, KBUILD_MODNAME, data);
1552                 if (retval < 0) {
1553                         dev_err(&pd_dev->dev,
1554                                 "%s request_irq failed\n", __func__);
1555                         return retval;
1556                 }
1557
1558                 /* reset PCH SPI h/w */
1559                 pch_spi_reset(data->master);
1560                 pch_spi_set_master_mode(data->master);
1561                 data->irq_reg_sts = true;
1562         }
1563         return 0;
1564 }
1565 #else
1566 #define pch_spi_pd_suspend NULL
1567 #define pch_spi_pd_resume NULL
1568 #endif
1569
1570 static struct platform_driver pch_spi_pd_driver = {
1571         .driver = {
1572                 .name = "pch-spi",
1573         },
1574         .probe = pch_spi_pd_probe,
1575         .remove = pch_spi_pd_remove,
1576         .suspend = pch_spi_pd_suspend,
1577         .resume = pch_spi_pd_resume
1578 };
1579
1580 static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1581 {
1582         struct pch_spi_board_data *board_dat;
1583         struct platform_device *pd_dev = NULL;
1584         int retval;
1585         int i;
1586         struct pch_pd_dev_save *pd_dev_save;
1587
1588         pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL);
1589         if (!pd_dev_save)
1590                 return -ENOMEM;
1591
1592         board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1593         if (!board_dat) {
1594                 retval = -ENOMEM;
1595                 goto err_no_mem;
1596         }
1597
1598         retval = pci_request_regions(pdev, KBUILD_MODNAME);
1599         if (retval) {
1600                 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1601                 goto pci_request_regions;
1602         }
1603
1604         board_dat->pdev = pdev;
1605         board_dat->num = id->driver_data;
1606         pd_dev_save->num = id->driver_data;
1607         pd_dev_save->board_dat = board_dat;
1608
1609         retval = pci_enable_device(pdev);
1610         if (retval) {
1611                 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1612                 goto pci_enable_device;
1613         }
1614
1615         for (i = 0; i < board_dat->num; i++) {
1616                 pd_dev = platform_device_alloc("pch-spi", i);
1617                 if (!pd_dev) {
1618                         dev_err(&pdev->dev, "platform_device_alloc failed\n");
1619                         retval = -ENOMEM;
1620                         goto err_platform_device;
1621                 }
1622                 pd_dev_save->pd_save[i] = pd_dev;
1623                 pd_dev->dev.parent = &pdev->dev;
1624
1625                 retval = platform_device_add_data(pd_dev, board_dat,
1626                                                   sizeof(*board_dat));
1627                 if (retval) {
1628                         dev_err(&pdev->dev,
1629                                 "platform_device_add_data failed\n");
1630                         platform_device_put(pd_dev);
1631                         goto err_platform_device;
1632                 }
1633
1634                 retval = platform_device_add(pd_dev);
1635                 if (retval) {
1636                         dev_err(&pdev->dev, "platform_device_add failed\n");
1637                         platform_device_put(pd_dev);
1638                         goto err_platform_device;
1639                 }
1640         }
1641
1642         pci_set_drvdata(pdev, pd_dev_save);
1643
1644         return 0;
1645
1646 err_platform_device:
1647         while (--i >= 0)
1648                 platform_device_unregister(pd_dev_save->pd_save[i]);
1649         pci_disable_device(pdev);
1650 pci_enable_device:
1651         pci_release_regions(pdev);
1652 pci_request_regions:
1653         kfree(board_dat);
1654 err_no_mem:
1655         kfree(pd_dev_save);
1656
1657         return retval;
1658 }
1659
1660 static void pch_spi_remove(struct pci_dev *pdev)
1661 {
1662         int i;
1663         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1664
1665         dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1666
1667         for (i = 0; i < pd_dev_save->num; i++)
1668                 platform_device_unregister(pd_dev_save->pd_save[i]);
1669
1670         pci_disable_device(pdev);
1671         pci_release_regions(pdev);
1672         kfree(pd_dev_save->board_dat);
1673         kfree(pd_dev_save);
1674 }
1675
1676 #ifdef CONFIG_PM
1677 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1678 {
1679         int retval;
1680         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1681
1682         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1683
1684         pd_dev_save->board_dat->suspend_sts = true;
1685
1686         /* save config space */
1687         retval = pci_save_state(pdev);
1688         if (retval == 0) {
1689                 pci_enable_wake(pdev, PCI_D3hot, 0);
1690                 pci_disable_device(pdev);
1691                 pci_set_power_state(pdev, PCI_D3hot);
1692         } else {
1693                 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1694         }
1695
1696         return retval;
1697 }
1698
1699 static int pch_spi_resume(struct pci_dev *pdev)
1700 {
1701         int retval;
1702         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1703         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1704
1705         pci_set_power_state(pdev, PCI_D0);
1706         pci_restore_state(pdev);
1707
1708         retval = pci_enable_device(pdev);
1709         if (retval < 0) {
1710                 dev_err(&pdev->dev,
1711                         "%s pci_enable_device failed\n", __func__);
1712         } else {
1713                 pci_enable_wake(pdev, PCI_D3hot, 0);
1714
1715                 /* set suspend status to false */
1716                 pd_dev_save->board_dat->suspend_sts = false;
1717         }
1718
1719         return retval;
1720 }
1721 #else
1722 #define pch_spi_suspend NULL
1723 #define pch_spi_resume NULL
1724
1725 #endif
1726
1727 static struct pci_driver pch_spi_pcidev_driver = {
1728         .name = "pch_spi",
1729         .id_table = pch_spi_pcidev_id,
1730         .probe = pch_spi_probe,
1731         .remove = pch_spi_remove,
1732         .suspend = pch_spi_suspend,
1733         .resume = pch_spi_resume,
1734 };
1735
1736 static int __init pch_spi_init(void)
1737 {
1738         int ret;
1739         ret = platform_driver_register(&pch_spi_pd_driver);
1740         if (ret)
1741                 return ret;
1742
1743         ret = pci_register_driver(&pch_spi_pcidev_driver);
1744         if (ret) {
1745                 platform_driver_unregister(&pch_spi_pd_driver);
1746                 return ret;
1747         }
1748
1749         return 0;
1750 }
1751 module_init(pch_spi_init);
1752
1753 static void __exit pch_spi_exit(void)
1754 {
1755         pci_unregister_driver(&pch_spi_pcidev_driver);
1756         platform_driver_unregister(&pch_spi_pd_driver);
1757 }
1758 module_exit(pch_spi_exit);
1759
1760 module_param(use_dma, int, 0644);
1761 MODULE_PARM_DESC(use_dma,
1762                  "to use DMA for data transfers pass 1 else 0; default 1");
1763
1764 MODULE_LICENSE("GPL");
1765 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
1766 MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
1767