drivers/spi/spi-topcliff-pch.c

   1 /*
   2  * SPI bus driver for the Topcliff PCH used by Intel SoCs
   3  *
   4  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/pci.h>
  18 #include <linux/wait.h>
  19 #include <linux/spi/spi.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/sched.h>
  22 #include <linux/spi/spidev.h>
  23 #include <linux/module.h>
  24 #include <linux/device.h>
  25 #include <linux/platform_device.h>
  26
  27 #include <linux/dmaengine.h>
  28 #include <linux/pch_dma.h>
  29
  30 /* Register offsets */
  31 #define PCH_SPCR                0x00    /* SPI control register */
  32 #define PCH_SPBRR               0x04    /* SPI baud rate register */
  33 #define PCH_SPSR                0x08    /* SPI status register */
  34 #define PCH_SPDWR               0x0C    /* SPI write data register */
  35 #define PCH_SPDRR               0x10    /* SPI read data register */
  36 #define PCH_SSNXCR              0x18    /* SSN Expand Control Register */
  37 #define PCH_SRST                0x1C    /* SPI reset register */
  38 #define PCH_ADDRESS_SIZE        0x20
  39
  40 #define PCH_SPSR_TFD            0x000007C0
  41 #define PCH_SPSR_RFD            0x0000F800
  42
  43 #define PCH_READABLE(x)         (((x) & PCH_SPSR_RFD)>>11)
  44 #define PCH_WRITABLE(x)         (((x) & PCH_SPSR_TFD)>>6)
  45
  46 #define PCH_RX_THOLD            7
  47 #define PCH_RX_THOLD_MAX        15
  48
  49 #define PCH_TX_THOLD            2
  50
  51 #define PCH_MAX_BAUDRATE        5000000
  52 #define PCH_MAX_FIFO_DEPTH      16
  53
  54 #define STATUS_RUNNING          1
  55 #define STATUS_EXITING          2
  56 #define PCH_SLEEP_TIME          10
  57
  58 #define SSN_LOW                 0x02U
  59 #define SSN_HIGH                0x03U
  60 #define SSN_NO_CONTROL          0x00U
  61 #define PCH_MAX_CS              0xFF
  62 #define PCI_DEVICE_ID_GE_SPI    0x8816
  63
  64 #define SPCR_SPE_BIT            (1 << 0)
  65 #define SPCR_MSTR_BIT           (1 << 1)
  66 #define SPCR_LSBF_BIT           (1 << 4)
  67 #define SPCR_CPHA_BIT           (1 << 5)
  68 #define SPCR_CPOL_BIT           (1 << 6)
  69 #define SPCR_TFIE_BIT           (1 << 8)
  70 #define SPCR_RFIE_BIT           (1 << 9)
  71 #define SPCR_FIE_BIT            (1 << 10)
  72 #define SPCR_ORIE_BIT           (1 << 11)
  73 #define SPCR_MDFIE_BIT          (1 << 12)
  74 #define SPCR_FICLR_BIT          (1 << 24)
  75 #define SPSR_TFI_BIT            (1 << 0)
  76 #define SPSR_RFI_BIT            (1 << 1)
  77 #define SPSR_FI_BIT             (1 << 2)
  78 #define SPSR_ORF_BIT            (1 << 3)
  79 #define SPBRR_SIZE_BIT          (1 << 10)
  80
  81 #define PCH_ALL                 (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
  82                                 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
  83
  84 #define SPCR_RFIC_FIELD         20
  85 #define SPCR_TFIC_FIELD         16
  86
  87 #define MASK_SPBRR_SPBR_BITS    ((1 << 10) - 1)
  88 #define MASK_RFIC_SPCR_BITS     (0xf << SPCR_RFIC_FIELD)
  89 #define MASK_TFIC_SPCR_BITS     (0xf << SPCR_TFIC_FIELD)
  90
  91 #define PCH_CLOCK_HZ            50000000
  92 #define PCH_MAX_SPBR            1023
  93
  94 /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
  95 #define PCI_DEVICE_ID_ML7213_SPI        0x802c
  96 #define PCI_DEVICE_ID_ML7223_SPI        0x800F
  97 #define PCI_DEVICE_ID_ML7831_SPI        0x8816
  98
  99 /*
 100  * Set the number of SPI instance max
 101  * Intel EG20T PCH :            1ch
 102  * LAPIS Semiconductor ML7213 IOH :     2ch
 103  * LAPIS Semiconductor ML7223 IOH :     1ch
 104  * LAPIS Semiconductor ML7831 IOH :     1ch
 105 */
 106 #define PCH_SPI_MAX_DEV                 2
 107
 108 #define PCH_BUF_SIZE            4096
 109 #define PCH_DMA_TRANS_SIZE      12
 110
 111 static int use_dma = 1;
 112
 113 struct pch_spi_dma_ctrl {
 114         struct dma_async_tx_descriptor  *desc_tx;
 115         struct dma_async_tx_descriptor  *desc_rx;
 116         struct pch_dma_slave            param_tx;
 117         struct pch_dma_slave            param_rx;
 118         struct dma_chan         *chan_tx;
 119         struct dma_chan         *chan_rx;
 120         struct scatterlist              *sg_tx_p;
 121         struct scatterlist              *sg_rx_p;
 122         struct scatterlist              sg_tx;
 123         struct scatterlist              sg_rx;
 124         int                             nent;
 125         void                            *tx_buf_virt;
 126         void                            *rx_buf_virt;
 127         dma_addr_t                      tx_buf_dma;
 128         dma_addr_t                      rx_buf_dma;
 129 };
 130 /**
 131  * struct pch_spi_data - Holds the SPI channel specific details
 132  * @io_remap_addr:              The remapped PCI base address
 133  * @master:                     Pointer to the SPI master structure
 134  * @work:                       Reference to work queue handler
 135  * @wait:                       Wait queue for waking up upon receiving an
 136  *                              interrupt.
 137  * @transfer_complete:          Status of SPI Transfer
 138  * @bcurrent_msg_processing:    Status flag for message processing
 139  * @lock:                       Lock for protecting this structure
 140  * @queue:                      SPI Message queue
 141  * @status:                     Status of the SPI driver
 142  * @bpw_len:                    Length of data to be transferred in bits per
 143  *                              word
 144  * @transfer_active:            Flag showing active transfer
 145  * @tx_index:                   Transmit data count; for bookkeeping during
 146  *                              transfer
 147  * @rx_index:                   Receive data count; for bookkeeping during
 148  *                              transfer
 149  * @tx_buff:                    Buffer for data to be transmitted
 150  * @rx_index:                   Buffer for Received data
 151  * @n_curnt_chip:               The chip number that this SPI driver currently
 152  *                              operates on
 153  * @current_chip:               Reference to the current chip that this SPI
 154  *                              driver currently operates on
 155  * @current_msg:                The current message that this SPI driver is
 156  *                              handling
 157  * @cur_trans:                  The current transfer that this SPI driver is
 158  *                              handling
 159  * @board_dat:                  Reference to the SPI device data structure
 160  * @plat_dev:                   platform_device structure
 161  * @ch:                         SPI channel number
 162  * @irq_reg_sts:                Status of IRQ registration
 163  */
 164 struct pch_spi_data {
 165         void __iomem *io_remap_addr;
 166         unsigned long io_base_addr;
 167         struct spi_master *master;
 168         struct work_struct work;
 169         wait_queue_head_t wait;
 170         u8 transfer_complete;
 171         u8 bcurrent_msg_processing;
 172         spinlock_t lock;
 173         struct list_head queue;
 174         u8 status;
 175         u32 bpw_len;
 176         u8 transfer_active;
 177         u32 tx_index;
 178         u32 rx_index;
 179         u16 *pkt_tx_buff;
 180         u16 *pkt_rx_buff;
 181         u8 n_curnt_chip;
 182         struct spi_device *current_chip;
 183         struct spi_message *current_msg;
 184         struct spi_transfer *cur_trans;
 185         struct pch_spi_board_data *board_dat;
 186         struct platform_device  *plat_dev;
 187         int ch;
 188         struct pch_spi_dma_ctrl dma;
 189         int use_dma;
 190         u8 irq_reg_sts;
 191         int save_total_len;
 192 };
 193
 194 /**
 195  * struct pch_spi_board_data - Holds the SPI device specific details
 196  * @pdev:               Pointer to the PCI device
 197  * @suspend_sts:        Status of suspend
 198  * @num:                The number of SPI device instance
 199  */
 200 struct pch_spi_board_data {
 201         struct pci_dev *pdev;
 202         u8 suspend_sts;
 203         int num;
 204 };
 205
 206 struct pch_pd_dev_save {
 207         int num;
 208         struct platform_device *pd_save[PCH_SPI_MAX_DEV];
 209         struct pch_spi_board_data *board_dat;
 210 };
 211
 212 static const struct pci_device_id pch_spi_pcidev_id[] = {
 213         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),    1, },
 214         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
 215         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
 216         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
 217         { }
 218 };
 219
 220 /**
 221  * pch_spi_writereg() - Performs  register writes
 222  * @master:     Pointer to struct spi_master.
 223  * @idx:        Register offset.
 224  * @val:        Value to be written to register.
 225  */
 226 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
 227 {
 228         struct pch_spi_data *data = spi_master_get_devdata(master);
 229         iowrite32(val, (data->io_remap_addr + idx));
 230 }
 231
 232 /**
 233  * pch_spi_readreg() - Performs register reads
 234  * @master:     Pointer to struct spi_master.
 235  * @idx:        Register offset.
 236  */
 237 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
 238 {
 239         struct pch_spi_data *data = spi_master_get_devdata(master);
 240         return ioread32(data->io_remap_addr + idx);
 241 }
 242
 243 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
 244                                       u32 set, u32 clr)
 245 {
 246         u32 tmp = pch_spi_readreg(master, idx);
 247         tmp = (tmp & ~clr) | set;
 248         pch_spi_writereg(master, idx, tmp);
 249 }
 250
 251 static void pch_spi_set_master_mode(struct spi_master *master)
 252 {
 253         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
 254 }
 255
 256 /**
 257  * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
 258  * @master:     Pointer to struct spi_master.
 259  */
 260 static void pch_spi_clear_fifo(struct spi_master *master)
 261 {
 262         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
 263         pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
 264 }
 265
 266 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
 267                                 void __iomem *io_remap_addr)
 268 {
 269         u32 n_read, tx_index, rx_index, bpw_len;
 270         u16 *pkt_rx_buffer, *pkt_tx_buff;
 271         int read_cnt;
 272         u32 reg_spcr_val;
 273         void __iomem *spsr;
 274         void __iomem *spdrr;
 275         void __iomem *spdwr;
 276
 277         spsr = io_remap_addr + PCH_SPSR;
 278         iowrite32(reg_spsr_val, spsr);
 279
 280         if (data->transfer_active) {
 281                 rx_index = data->rx_index;
 282                 tx_index = data->tx_index;
 283                 bpw_len = data->bpw_len;
 284                 pkt_rx_buffer = data->pkt_rx_buff;
 285                 pkt_tx_buff = data->pkt_tx_buff;
 286
 287                 spdrr = io_remap_addr + PCH_SPDRR;
 288                 spdwr = io_remap_addr + PCH_SPDWR;
 289
 290                 n_read = PCH_READABLE(reg_spsr_val);
 291
 292                 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
 293                         pkt_rx_buffer[rx_index++] = ioread32(spdrr);
 294                         if (tx_index < bpw_len)
 295                                 iowrite32(pkt_tx_buff[tx_index++], spdwr);
 296                 }
 297
 298                 /* disable RFI if not needed */
 299                 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
 300                         reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
 301                         reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
 302
 303                         /* reset rx threshold */
 304                         reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
 305                         reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
 306
 307                         iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
 308                 }
 309
 310                 /* update counts */
 311                 data->tx_index = tx_index;
 312                 data->rx_index = rx_index;
 313
 314                 /* if transfer complete interrupt */
 315                 if (reg_spsr_val & SPSR_FI_BIT) {
 316                         if ((tx_index == bpw_len) && (rx_index == tx_index)) {
 317                                 /* disable interrupts */
 318                                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
 319                                                    PCH_ALL);
 320
 321                                 /* transfer is completed;
 322                                    inform pch_spi_process_messages */
 323                                 data->transfer_complete = true;
 324                                 data->transfer_active = false;
 325                                 wake_up(&data->wait);
 326                         } else {
 327                                 dev_vdbg(&data->master->dev,
 328                                         "%s : Transfer is not completed",
 329                                         __func__);
 330                         }
 331                 }
 332         }
 333 }
 334
 335 /**
 336  * pch_spi_handler() - Interrupt handler
 337  * @irq:        The interrupt number.
 338  * @dev_id:     Pointer to struct pch_spi_board_data.
 339  */
 340 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
 341 {
 342         u32 reg_spsr_val;
 343         void __iomem *spsr;
 344         void __iomem *io_remap_addr;
 345         irqreturn_t ret = IRQ_NONE;
 346         struct pch_spi_data *data = dev_id;
 347         struct pch_spi_board_data *board_dat = data->board_dat;
 348
 349         if (board_dat->suspend_sts) {
 350                 dev_dbg(&board_dat->pdev->dev,
 351                         "%s returning due to suspend\n", __func__);
 352                 return IRQ_NONE;
 353         }
 354
 355         io_remap_addr = data->io_remap_addr;
 356         spsr = io_remap_addr + PCH_SPSR;
 357
 358         reg_spsr_val = ioread32(spsr);
 359
 360         if (reg_spsr_val & SPSR_ORF_BIT) {
 361                 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
 362                 if (data->current_msg->complete) {
 363                         data->transfer_complete = true;
 364                         data->current_msg->status = -EIO;
 365                         data->current_msg->complete(data->current_msg->context);
 366                         data->bcurrent_msg_processing = false;
 367                         data->current_msg = NULL;
 368                         data->cur_trans = NULL;
 369                 }
 370         }
 371
 372         if (data->use_dma)
 373                 return IRQ_NONE;
 374
 375         /* Check if the interrupt is for SPI device */
 376         if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
 377                 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
 378                 ret = IRQ_HANDLED;
 379         }
 380
 381         dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
 382                 __func__, ret);
 383
 384         return ret;
 385 }
 386
 387 /**
 388  * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
 389  * @master:     Pointer to struct spi_master.
 390  * @speed_hz:   Baud rate.
 391  */
 392 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
 393 {
 394         u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
 395
 396         /* if baud rate is less than we can support limit it */
 397         if (n_spbr > PCH_MAX_SPBR)
 398                 n_spbr = PCH_MAX_SPBR;
 399
 400         pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
 401 }
 402
 403 /**
 404  * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
 405  * @master:             Pointer to struct spi_master.
 406  * @bits_per_word:      Bits per word for SPI transfer.
 407  */
 408 static void pch_spi_set_bits_per_word(struct spi_master *master,
 409                                       u8 bits_per_word)
 410 {
 411         if (bits_per_word == 8)
 412                 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
 413         else
 414                 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
 415 }
 416
 417 /**
 418  * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
 419  * @spi:        Pointer to struct spi_device.
 420  */
 421 static void pch_spi_setup_transfer(struct spi_device *spi)
 422 {
 423         u32 flags = 0;
 424
 425         dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
 426                 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
 427                 spi->max_speed_hz);
 428         pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
 429
 430         /* set bits per word */
 431         pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
 432
 433         if (!(spi->mode & SPI_LSB_FIRST))
 434                 flags |= SPCR_LSBF_BIT;
 435         if (spi->mode & SPI_CPOL)
 436                 flags |= SPCR_CPOL_BIT;
 437         if (spi->mode & SPI_CPHA)
 438                 flags |= SPCR_CPHA_BIT;
 439         pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
 440                            (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
 441
 442         /* Clear the FIFO by toggling  FICLR to 1 and back to 0 */
 443         pch_spi_clear_fifo(spi->master);
 444 }
 445
 446 /**
 447  * pch_spi_reset() - Clears SPI registers
 448  * @master:     Pointer to struct spi_master.
 449  */
 450 static void pch_spi_reset(struct spi_master *master)
 451 {
 452         /* write 1 to reset SPI */
 453         pch_spi_writereg(master, PCH_SRST, 0x1);
 454
 455         /* clear reset */
 456         pch_spi_writereg(master, PCH_SRST, 0x0);
 457 }
 458
 459 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
 460 {
 461
 462         struct spi_transfer *transfer;
 463         struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
 464         int retval;
 465         unsigned long flags;
 466
 467         spin_lock_irqsave(&data->lock, flags);
 468         /* validate Tx/Rx buffers and Transfer length */
 469         list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
 470                 if (!transfer->tx_buf && !transfer->rx_buf) {
 471                         dev_err(&pspi->dev,
 472                                 "%s Tx and Rx buffer NULL\n", __func__);
 473                         retval = -EINVAL;
 474                         goto err_return_spinlock;
 475                 }
 476
 477                 if (!transfer->len) {
 478                         dev_err(&pspi->dev, "%s Transfer length invalid\n",
 479                                 __func__);
 480                         retval = -EINVAL;
 481                         goto err_return_spinlock;
 482                 }
 483
 484                 dev_dbg(&pspi->dev,
 485                         "%s Tx/Rx buffer valid. Transfer length valid\n",
 486                         __func__);
 487         }
 488         spin_unlock_irqrestore(&data->lock, flags);
 489
 490         /* We won't process any messages if we have been asked to terminate */
 491         if (data->status == STATUS_EXITING) {
 492                 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
 493                 retval = -ESHUTDOWN;
 494                 goto err_out;
 495         }
 496
 497         /* If suspended ,return -EINVAL */
 498         if (data->board_dat->suspend_sts) {
 499                 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
 500                 retval = -EINVAL;
 501                 goto err_out;
 502         }
 503
 504         /* set status of message */
 505         pmsg->actual_length = 0;
 506         dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
 507
 508         pmsg->status = -EINPROGRESS;
 509         spin_lock_irqsave(&data->lock, flags);
 510         /* add message to queue */
 511         list_add_tail(&pmsg->queue, &data->queue);
 512         spin_unlock_irqrestore(&data->lock, flags);
 513
 514         dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
 515
 516         schedule_work(&data->work);
 517         dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
 518
 519         retval = 0;
 520
 521 err_out:
 522         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 523         return retval;
 524 err_return_spinlock:
 525         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 526         spin_unlock_irqrestore(&data->lock, flags);
 527         return retval;
 528 }
 529
 530 static inline void pch_spi_select_chip(struct pch_spi_data *data,
 531                                        struct spi_device *pspi)
 532 {
 533         if (data->current_chip != NULL) {
 534                 if (pspi->chip_select != data->n_curnt_chip) {
 535                         dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
 536                         data->current_chip = NULL;
 537                 }
 538         }
 539
 540         data->current_chip = pspi;
 541
 542         data->n_curnt_chip = data->current_chip->chip_select;
 543
 544         dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
 545         pch_spi_setup_transfer(pspi);
 546 }
 547
 548 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
 549 {
 550         int size;
 551         u32 n_writes;
 552         int j;
 553         struct spi_message *pmsg, *tmp;
 554         const u8 *tx_buf;
 555         const u16 *tx_sbuf;
 556
 557         /* set baud rate if needed */
 558         if (data->cur_trans->speed_hz) {
 559                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 560                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 561         }
 562
 563         /* set bits per word if needed */
 564         if (data->cur_trans->bits_per_word &&
 565             (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
 566                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
 567                 pch_spi_set_bits_per_word(data->master,
 568                                           data->cur_trans->bits_per_word);
 569                 *bpw = data->cur_trans->bits_per_word;
 570         } else {
 571                 *bpw = data->current_msg->spi->bits_per_word;
 572         }
 573
 574         /* reset Tx/Rx index */
 575         data->tx_index = 0;
 576         data->rx_index = 0;
 577
 578         data->bpw_len = data->cur_trans->len / (*bpw / 8);
 579
 580         /* find alloc size */
 581         size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
 582
 583         /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
 584         data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
 585         if (data->pkt_tx_buff != NULL) {
 586                 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
 587                 if (!data->pkt_rx_buff) {
 588                         kfree(data->pkt_tx_buff);
 589                         data->pkt_tx_buff = NULL;
 590                 }
 591         }
 592
 593         if (!data->pkt_rx_buff) {
 594                 /* flush queue and set status of all transfers to -ENOMEM */
 595                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
 596                         pmsg->status = -ENOMEM;
 597
 598                         if (pmsg->complete)
 599                                 pmsg->complete(pmsg->context);
 600
 601                         /* delete from queue */
 602                         list_del_init(&pmsg->queue);
 603                 }
 604                 return;
 605         }
 606
 607         /* copy Tx Data */
 608         if (data->cur_trans->tx_buf != NULL) {
 609                 if (*bpw == 8) {
 610                         tx_buf = data->cur_trans->tx_buf;
 611                         for (j = 0; j < data->bpw_len; j++)
 612                                 data->pkt_tx_buff[j] = *tx_buf++;
 613                 } else {
 614                         tx_sbuf = data->cur_trans->tx_buf;
 615                         for (j = 0; j < data->bpw_len; j++)
 616                                 data->pkt_tx_buff[j] = *tx_sbuf++;
 617                 }
 618         }
 619
 620         /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
 621         n_writes = data->bpw_len;
 622         if (n_writes > PCH_MAX_FIFO_DEPTH)
 623                 n_writes = PCH_MAX_FIFO_DEPTH;
 624
 625         dev_dbg(&data->master->dev,
 626                 "\n%s:Pulling down SSN low - writing 0x2 to SSNXCR\n",
 627                 __func__);
 628         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
 629
 630         for (j = 0; j < n_writes; j++)
 631                 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
 632
 633         /* update tx_index */
 634         data->tx_index = j;
 635
 636         /* reset transfer complete flag */
 637         data->transfer_complete = false;
 638         data->transfer_active = true;
 639 }
 640
 641 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
 642 {
 643         struct spi_message *pmsg, *tmp;
 644         dev_dbg(&data->master->dev, "%s called\n", __func__);
 645         /* Invoke complete callback
 646          * [To the spi core..indicating end of transfer] */
 647         data->current_msg->status = 0;
 648
 649         if (data->current_msg->complete) {
 650                 dev_dbg(&data->master->dev,
 651                         "%s:Invoking callback of SPI core\n", __func__);
 652                 data->current_msg->complete(data->current_msg->context);
 653         }
 654
 655         /* update status in global variable */
 656         data->bcurrent_msg_processing = false;
 657
 658         dev_dbg(&data->master->dev,
 659                 "%s:data->bcurrent_msg_processing = false\n", __func__);
 660
 661         data->current_msg = NULL;
 662         data->cur_trans = NULL;
 663
 664         /* check if we have items in list and not suspending
 665          * return 1 if list empty */
 666         if ((list_empty(&data->queue) == 0) &&
 667             (!data->board_dat->suspend_sts) &&
 668             (data->status != STATUS_EXITING)) {
 669                 /* We have some more work to do (either there is more tranint
 670                  * bpw;sfer requests in the current message or there are
 671                  *more messages)
 672                  */
 673                 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
 674                 schedule_work(&data->work);
 675         } else if (data->board_dat->suspend_sts ||
 676                    data->status == STATUS_EXITING) {
 677                 dev_dbg(&data->master->dev,
 678                         "%s suspend/remove initiated, flushing queue\n",
 679                         __func__);
 680                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
 681                         pmsg->status = -EIO;
 682
 683                         if (pmsg->complete)
 684                                 pmsg->complete(pmsg->context);
 685
 686                         /* delete from queue */
 687                         list_del_init(&pmsg->queue);
 688                 }
 689         }
 690 }
 691
 692 static void pch_spi_set_ir(struct pch_spi_data *data)
 693 {
 694         /* enable interrupts, set threshold, enable SPI */
 695         if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
 696                 /* set receive threshold to PCH_RX_THOLD */
 697                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 698                                    PCH_RX_THOLD << SPCR_RFIC_FIELD |
 699                                    SPCR_FIE_BIT | SPCR_RFIE_BIT |
 700                                    SPCR_ORIE_BIT | SPCR_SPE_BIT,
 701                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 702         else
 703                 /* set receive threshold to maximum */
 704                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 705                                    PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
 706                                    SPCR_FIE_BIT | SPCR_ORIE_BIT |
 707                                    SPCR_SPE_BIT,
 708                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 709
 710         /* Wait until the transfer completes; go to sleep after
 711                                  initiating the transfer. */
 712         dev_dbg(&data->master->dev,
 713                 "%s:waiting for transfer to get over\n", __func__);
 714
 715         wait_event_interruptible(data->wait, data->transfer_complete);
 716
 717         /* clear all interrupts */
 718         pch_spi_writereg(data->master, PCH_SPSR,
 719                          pch_spi_readreg(data->master, PCH_SPSR));
 720         /* Disable interrupts and SPI transfer */
 721         pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
 722         /* clear FIFO */
 723         pch_spi_clear_fifo(data->master);
 724 }
 725
 726 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
 727 {
 728         int j;
 729         u8 *rx_buf;
 730         u16 *rx_sbuf;
 731
 732         /* copy Rx Data */
 733         if (!data->cur_trans->rx_buf)
 734                 return;
 735
 736         if (bpw == 8) {
 737                 rx_buf = data->cur_trans->rx_buf;
 738                 for (j = 0; j < data->bpw_len; j++)
 739                         *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
 740         } else {
 741                 rx_sbuf = data->cur_trans->rx_buf;
 742                 for (j = 0; j < data->bpw_len; j++)
 743                         *rx_sbuf++ = data->pkt_rx_buff[j];
 744         }
 745 }
 746
 747 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
 748 {
 749         int j;
 750         u8 *rx_buf;
 751         u16 *rx_sbuf;
 752         const u8 *rx_dma_buf;
 753         const u16 *rx_dma_sbuf;
 754
 755         /* copy Rx Data */
 756         if (!data->cur_trans->rx_buf)
 757                 return;
 758
 759         if (bpw == 8) {
 760                 rx_buf = data->cur_trans->rx_buf;
 761                 rx_dma_buf = data->dma.rx_buf_virt;
 762                 for (j = 0; j < data->bpw_len; j++)
 763                         *rx_buf++ = *rx_dma_buf++ & 0xFF;
 764                 data->cur_trans->rx_buf = rx_buf;
 765         } else {
 766                 rx_sbuf = data->cur_trans->rx_buf;
 767                 rx_dma_sbuf = data->dma.rx_buf_virt;
 768                 for (j = 0; j < data->bpw_len; j++)
 769                         *rx_sbuf++ = *rx_dma_sbuf++;
 770                 data->cur_trans->rx_buf = rx_sbuf;
 771         }
 772 }
 773
 774 static int pch_spi_start_transfer(struct pch_spi_data *data)
 775 {
 776         struct pch_spi_dma_ctrl *dma;
 777         unsigned long flags;
 778         int rtn;
 779
 780         dma = &data->dma;
 781
 782         spin_lock_irqsave(&data->lock, flags);
 783
 784         /* disable interrupts, SPI set enable */
 785         pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
 786
 787         spin_unlock_irqrestore(&data->lock, flags);
 788
 789         /* Wait until the transfer completes; go to sleep after
 790                                  initiating the transfer. */
 791         dev_dbg(&data->master->dev,
 792                 "%s:waiting for transfer to get over\n", __func__);
 793         rtn = wait_event_interruptible_timeout(data->wait,
 794                                                data->transfer_complete,
 795                                                msecs_to_jiffies(2 * HZ));
 796         if (!rtn)
 797                 dev_err(&data->master->dev,
 798                         "%s wait-event timeout\n", __func__);
 799
 800         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
 801                             DMA_FROM_DEVICE);
 802
 803         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
 804                             DMA_FROM_DEVICE);
 805         memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
 806
 807         async_tx_ack(dma->desc_rx);
 808         async_tx_ack(dma->desc_tx);
 809         kfree(dma->sg_tx_p);
 810         kfree(dma->sg_rx_p);
 811
 812         spin_lock_irqsave(&data->lock, flags);
 813
 814         /* clear fifo threshold, disable interrupts, disable SPI transfer */
 815         pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
 816                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
 817                            SPCR_SPE_BIT);
 818         /* clear all interrupts */
 819         pch_spi_writereg(data->master, PCH_SPSR,
 820                          pch_spi_readreg(data->master, PCH_SPSR));
 821         /* clear FIFO */
 822         pch_spi_clear_fifo(data->master);
 823
 824         spin_unlock_irqrestore(&data->lock, flags);
 825
 826         return rtn;
 827 }
 828
 829 static void pch_dma_rx_complete(void *arg)
 830 {
 831         struct pch_spi_data *data = arg;
 832
 833         /* transfer is completed;inform pch_spi_process_messages_dma */
 834         data->transfer_complete = true;
 835         wake_up_interruptible(&data->wait);
 836 }
 837
 838 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
 839 {
 840         struct pch_dma_slave *param = slave;
 841
 842         if ((chan->chan_id == param->chan_id) &&
 843             (param->dma_dev == chan->device->dev)) {
 844                 chan->private = param;
 845                 return true;
 846         } else {
 847                 return false;
 848         }
 849 }
 850
 851 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
 852 {
 853         dma_cap_mask_t mask;
 854         struct dma_chan *chan;
 855         struct pci_dev *dma_dev;
 856         struct pch_dma_slave *param;
 857         struct pch_spi_dma_ctrl *dma;
 858         unsigned int width;
 859
 860         if (bpw == 8)
 861                 width = PCH_DMA_WIDTH_1_BYTE;
 862         else
 863                 width = PCH_DMA_WIDTH_2_BYTES;
 864
 865         dma = &data->dma;
 866         dma_cap_zero(mask);
 867         dma_cap_set(DMA_SLAVE, mask);
 868
 869         /* Get DMA's dev information */
 870         dma_dev = pci_get_slot(data->board_dat->pdev->bus,
 871                         PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
 872
 873         /* Set Tx DMA */
 874         param = &dma->param_tx;
 875         param->dma_dev = &dma_dev->dev;
 876         param->chan_id = data->ch * 2; /* Tx = 0, 2 */;
 877         param->tx_reg = data->io_base_addr + PCH_SPDWR;
 878         param->width = width;
 879         chan = dma_request_channel(mask, pch_spi_filter, param);
 880         if (!chan) {
 881                 dev_err(&data->master->dev,
 882                         "ERROR: dma_request_channel FAILS(Tx)\n");
 883                 data->use_dma = 0;
 884                 return;
 885         }
 886         dma->chan_tx = chan;
 887
 888         /* Set Rx DMA */
 889         param = &dma->param_rx;
 890         param->dma_dev = &dma_dev->dev;
 891         param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */;
 892         param->rx_reg = data->io_base_addr + PCH_SPDRR;
 893         param->width = width;
 894         chan = dma_request_channel(mask, pch_spi_filter, param);
 895         if (!chan) {
 896                 dev_err(&data->master->dev,
 897                         "ERROR: dma_request_channel FAILS(Rx)\n");
 898                 dma_release_channel(dma->chan_tx);
 899                 dma->chan_tx = NULL;
 900                 data->use_dma = 0;
 901                 return;
 902         }
 903         dma->chan_rx = chan;
 904 }
 905
 906 static void pch_spi_release_dma(struct pch_spi_data *data)
 907 {
 908         struct pch_spi_dma_ctrl *dma;
 909
 910         dma = &data->dma;
 911         if (dma->chan_tx) {
 912                 dma_release_channel(dma->chan_tx);
 913                 dma->chan_tx = NULL;
 914         }
 915         if (dma->chan_rx) {
 916                 dma_release_channel(dma->chan_rx);
 917                 dma->chan_rx = NULL;
 918         }
 919 }
 920
 921 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
 922 {
 923         const u8 *tx_buf;
 924         const u16 *tx_sbuf;
 925         u8 *tx_dma_buf;
 926         u16 *tx_dma_sbuf;
 927         struct scatterlist *sg;
 928         struct dma_async_tx_descriptor *desc_tx;
 929         struct dma_async_tx_descriptor *desc_rx;
 930         int num;
 931         int i;
 932         int size;
 933         int rem;
 934         int head;
 935         unsigned long flags;
 936         struct pch_spi_dma_ctrl *dma;
 937
 938         dma = &data->dma;
 939
 940         /* set baud rate if needed */
 941         if (data->cur_trans->speed_hz) {
 942                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 943                 spin_lock_irqsave(&data->lock, flags);
 944                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 945                 spin_unlock_irqrestore(&data->lock, flags);
 946         }
 947
 948         /* set bits per word if needed */
 949         if (data->cur_trans->bits_per_word &&
 950             (data->current_msg->spi->bits_per_word !=
 951              data->cur_trans->bits_per_word)) {
 952                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
 953                 spin_lock_irqsave(&data->lock, flags);
 954                 pch_spi_set_bits_per_word(data->master,
 955                                           data->cur_trans->bits_per_word);
 956                 spin_unlock_irqrestore(&data->lock, flags);
 957                 *bpw = data->cur_trans->bits_per_word;
 958         } else {
 959                 *bpw = data->current_msg->spi->bits_per_word;
 960         }
 961         data->bpw_len = data->cur_trans->len / (*bpw / 8);
 962
 963         if (data->bpw_len > PCH_BUF_SIZE) {
 964                 data->bpw_len = PCH_BUF_SIZE;
 965                 data->cur_trans->len -= PCH_BUF_SIZE;
 966         }
 967
 968         /* copy Tx Data */
 969         if (data->cur_trans->tx_buf != NULL) {
 970                 if (*bpw == 8) {
 971                         tx_buf = data->cur_trans->tx_buf;
 972                         tx_dma_buf = dma->tx_buf_virt;
 973                         for (i = 0; i < data->bpw_len; i++)
 974                                 *tx_dma_buf++ = *tx_buf++;
 975                 } else {
 976                         tx_sbuf = data->cur_trans->tx_buf;
 977                         tx_dma_sbuf = dma->tx_buf_virt;
 978                         for (i = 0; i < data->bpw_len; i++)
 979                                 *tx_dma_sbuf++ = *tx_sbuf++;
 980                 }
 981         }
 982
 983         /* Calculate Rx parameter for DMA transmitting */
 984         if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
 985                 if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
 986                         num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
 987                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
 988                 } else {
 989                         num = data->bpw_len / PCH_DMA_TRANS_SIZE;
 990                         rem = PCH_DMA_TRANS_SIZE;
 991                 }
 992                 size = PCH_DMA_TRANS_SIZE;
 993         } else {
 994                 num = 1;
 995                 size = data->bpw_len;
 996                 rem = data->bpw_len;
 997         }
 998         dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
 999                 __func__, num, size, rem);
1000         spin_lock_irqsave(&data->lock, flags);
1001
1002         /* set receive fifo threshold and transmit fifo threshold */
1003         pch_spi_setclr_reg(data->master, PCH_SPCR,
1004                            ((size - 1) << SPCR_RFIC_FIELD) |
1005                            (PCH_TX_THOLD << SPCR_TFIC_FIELD),
1006                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1007
1008         spin_unlock_irqrestore(&data->lock, flags);
1009
1010         /* RX */
1011         dma->sg_rx_p = kcalloc(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC);
1012         if (!dma->sg_rx_p)
1013                 return;
1014
1015         sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1016         /* offset, length setting */
1017         sg = dma->sg_rx_p;
1018         for (i = 0; i < num; i++, sg++) {
1019                 if (i == (num - 2)) {
1020                         sg->offset = size * i;
1021                         sg->offset = sg->offset * (*bpw / 8);
1022                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1023                                     sg->offset);
1024                         sg_dma_len(sg) = rem;
1025                 } else if (i == (num - 1)) {
1026                         sg->offset = size * (i - 1) + rem;
1027                         sg->offset = sg->offset * (*bpw / 8);
1028                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1029                                     sg->offset);
1030                         sg_dma_len(sg) = size;
1031                 } else {
1032                         sg->offset = size * i;
1033                         sg->offset = sg->offset * (*bpw / 8);
1034                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1035                                     sg->offset);
1036                         sg_dma_len(sg) = size;
1037                 }
1038                 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1039         }
1040         sg = dma->sg_rx_p;
1041         desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
1042                                         num, DMA_DEV_TO_MEM,
1043                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1044         if (!desc_rx) {
1045                 dev_err(&data->master->dev,
1046                         "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1047                 return;
1048         }
1049         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1050         desc_rx->callback = pch_dma_rx_complete;
1051         desc_rx->callback_param = data;
1052         dma->nent = num;
1053         dma->desc_rx = desc_rx;
1054
1055         /* Calculate Tx parameter for DMA transmitting */
1056         if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
1057                 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
1058                 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
1059                         num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1060                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
1061                 } else {
1062                         num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1063                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
1064                               PCH_DMA_TRANS_SIZE - head;
1065                 }
1066                 size = PCH_DMA_TRANS_SIZE;
1067         } else {
1068                 num = 1;
1069                 size = data->bpw_len;
1070                 rem = data->bpw_len;
1071                 head = 0;
1072         }
1073
1074         dma->sg_tx_p = kcalloc(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC);
1075         if (!dma->sg_tx_p)
1076                 return;
1077
1078         sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1079         /* offset, length setting */
1080         sg = dma->sg_tx_p;
1081         for (i = 0; i < num; i++, sg++) {
1082                 if (i == 0) {
1083                         sg->offset = 0;
1084                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
1085                                     sg->offset);
1086                         sg_dma_len(sg) = size + head;
1087                 } else if (i == (num - 1)) {
1088                         sg->offset = head + size * i;
1089                         sg->offset = sg->offset * (*bpw / 8);
1090                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1091                                     sg->offset);
1092                         sg_dma_len(sg) = rem;
1093                 } else {
1094                         sg->offset = head + size * i;
1095                         sg->offset = sg->offset * (*bpw / 8);
1096                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1097                                     sg->offset);
1098                         sg_dma_len(sg) = size;
1099                 }
1100                 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1101         }
1102         sg = dma->sg_tx_p;
1103         desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
1104                                         sg, num, DMA_MEM_TO_DEV,
1105                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1106         if (!desc_tx) {
1107                 dev_err(&data->master->dev,
1108                         "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1109                 return;
1110         }
1111         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1112         desc_tx->callback = NULL;
1113         desc_tx->callback_param = data;
1114         dma->nent = num;
1115         dma->desc_tx = desc_tx;
1116
1117         dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1118
1119         spin_lock_irqsave(&data->lock, flags);
1120         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1121         desc_rx->tx_submit(desc_rx);
1122         desc_tx->tx_submit(desc_tx);
1123         spin_unlock_irqrestore(&data->lock, flags);
1124
1125         /* reset transfer complete flag */
1126         data->transfer_complete = false;
1127 }
1128
1129 static void pch_spi_process_messages(struct work_struct *pwork)
1130 {
1131         struct spi_message *pmsg, *tmp;
1132         struct pch_spi_data *data;
1133         int bpw;
1134
1135         data = container_of(pwork, struct pch_spi_data, work);
1136         dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1137
1138         spin_lock(&data->lock);
1139         /* check if suspend has been initiated;if yes flush queue */
1140         if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1141                 dev_dbg(&data->master->dev,
1142                         "%s suspend/remove initiated, flushing queue\n", __func__);
1143                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
1144                         pmsg->status = -EIO;
1145
1146                         if (pmsg->complete) {
1147                                 spin_unlock(&data->lock);
1148                                 pmsg->complete(pmsg->context);
1149                                 spin_lock(&data->lock);
1150                         }
1151
1152                         /* delete from queue */
1153                         list_del_init(&pmsg->queue);
1154                 }
1155
1156                 spin_unlock(&data->lock);
1157                 return;
1158         }
1159
1160         data->bcurrent_msg_processing = true;
1161         dev_dbg(&data->master->dev,
1162                 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1163
1164         /* Get the message from the queue and delete it from there. */
1165         data->current_msg = list_entry(data->queue.next, struct spi_message,
1166                                         queue);
1167
1168         list_del_init(&data->current_msg->queue);
1169
1170         data->current_msg->status = 0;
1171
1172         pch_spi_select_chip(data, data->current_msg->spi);
1173
1174         spin_unlock(&data->lock);
1175
1176         if (data->use_dma)
1177                 pch_spi_request_dma(data,
1178                                     data->current_msg->spi->bits_per_word);
1179         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1180         do {
1181                 int cnt;
1182                 /* If we are already processing a message get the next
1183                 transfer structure from the message otherwise retrieve
1184                 the 1st transfer request from the message. */
1185                 spin_lock(&data->lock);
1186                 if (data->cur_trans == NULL) {
1187                         data->cur_trans =
1188                                 list_entry(data->current_msg->transfers.next,
1189                                            struct spi_transfer, transfer_list);
1190                         dev_dbg(&data->master->dev,
1191                                 "%s :Getting 1st transfer message\n",
1192                                 __func__);
1193                 } else {
1194                         data->cur_trans =
1195                                 list_entry(data->cur_trans->transfer_list.next,
1196                                            struct spi_transfer, transfer_list);
1197                         dev_dbg(&data->master->dev,
1198                                 "%s :Getting next transfer message\n",
1199                                 __func__);
1200                 }
1201                 spin_unlock(&data->lock);
1202
1203                 if (!data->cur_trans->len)
1204                         goto out;
1205                 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
1206                 data->save_total_len = data->cur_trans->len;
1207                 if (data->use_dma) {
1208                         int i;
1209                         char *save_rx_buf = data->cur_trans->rx_buf;
1210                         for (i = 0; i < cnt; i ++) {
1211                                 pch_spi_handle_dma(data, &bpw);
1212                                 if (!pch_spi_start_transfer(data)) {
1213                                         data->transfer_complete = true;
1214                                         data->current_msg->status = -EIO;
1215                                         data->current_msg->complete
1216                                                    (data->current_msg->context);
1217                                         data->bcurrent_msg_processing = false;
1218                                         data->current_msg = NULL;
1219                                         data->cur_trans = NULL;
1220                                         goto out;
1221                                 }
1222                                 pch_spi_copy_rx_data_for_dma(data, bpw);
1223                         }
1224                         data->cur_trans->rx_buf = save_rx_buf;
1225                 } else {
1226                         pch_spi_set_tx(data, &bpw);
1227                         pch_spi_set_ir(data);
1228                         pch_spi_copy_rx_data(data, bpw);
1229                         kfree(data->pkt_rx_buff);
1230                         data->pkt_rx_buff = NULL;
1231                         kfree(data->pkt_tx_buff);
1232                         data->pkt_tx_buff = NULL;
1233                 }
1234                 /* increment message count */
1235                 data->cur_trans->len = data->save_total_len;
1236                 data->current_msg->actual_length += data->cur_trans->len;
1237
1238                 dev_dbg(&data->master->dev,
1239                         "%s:data->current_msg->actual_length=%d\n",
1240                         __func__, data->current_msg->actual_length);
1241
1242                 /* check for delay */
1243                 if (data->cur_trans->delay_usecs) {
1244                         dev_dbg(&data->master->dev, "%s:delay in usec=%d\n",
1245                                 __func__, data->cur_trans->delay_usecs);
1246                         udelay(data->cur_trans->delay_usecs);
1247                 }
1248
1249                 spin_lock(&data->lock);
1250
1251                 /* No more transfer in this message. */
1252                 if ((data->cur_trans->transfer_list.next) ==
1253                     &(data->current_msg->transfers)) {
1254                         pch_spi_nomore_transfer(data);
1255                 }
1256
1257                 spin_unlock(&data->lock);
1258
1259         } while (data->cur_trans != NULL);
1260
1261 out:
1262         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1263         if (data->use_dma)
1264                 pch_spi_release_dma(data);
1265 }
1266
1267 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1268                                    struct pch_spi_data *data)
1269 {
1270         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1271
1272         flush_work(&data->work);
1273 }
1274
1275 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1276                                  struct pch_spi_data *data)
1277 {
1278         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1279
1280         /* reset PCH SPI h/w */
1281         pch_spi_reset(data->master);
1282         dev_dbg(&board_dat->pdev->dev,
1283                 "%s pch_spi_reset invoked successfully\n", __func__);
1284
1285         dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1286
1287         return 0;
1288 }
1289
1290 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1291                              struct pch_spi_data *data)
1292 {
1293         struct pch_spi_dma_ctrl *dma;
1294
1295         dma = &data->dma;
1296         if (dma->tx_buf_dma)
1297                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1298                                   dma->tx_buf_virt, dma->tx_buf_dma);
1299         if (dma->rx_buf_dma)
1300                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1301                                   dma->rx_buf_virt, dma->rx_buf_dma);
1302 }
1303
1304 static int pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1305                               struct pch_spi_data *data)
1306 {
1307         struct pch_spi_dma_ctrl *dma;
1308         int ret;
1309
1310         dma = &data->dma;
1311         ret = 0;
1312         /* Get Consistent memory for Tx DMA */
1313         dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1314                                 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1315         if (!dma->tx_buf_virt)
1316                 ret = -ENOMEM;
1317
1318         /* Get Consistent memory for Rx DMA */
1319         dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1320                                 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1321         if (!dma->rx_buf_virt)
1322                 ret = -ENOMEM;
1323
1324         return ret;
1325 }
1326
1327 static int pch_spi_pd_probe(struct platform_device *plat_dev)
1328 {
1329         int ret;
1330         struct spi_master *master;
1331         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1332         struct pch_spi_data *data;
1333
1334         dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1335
1336         master = spi_alloc_master(&board_dat->pdev->dev,
1337                                   sizeof(struct pch_spi_data));
1338         if (!master) {
1339                 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1340                         plat_dev->id);
1341                 return -ENOMEM;
1342         }
1343
1344         data = spi_master_get_devdata(master);
1345         data->master = master;
1346
1347         platform_set_drvdata(plat_dev, data);
1348
1349         /* baseaddress + address offset) */
1350         data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1351                                          PCH_ADDRESS_SIZE * plat_dev->id;
1352         data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
1353         if (!data->io_remap_addr) {
1354                 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1355                 ret = -ENOMEM;
1356                 goto err_pci_iomap;
1357         }
1358         data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id;
1359
1360         dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1361                 plat_dev->id, data->io_remap_addr);
1362
1363         /* initialize members of SPI master */
1364         master->num_chipselect = PCH_MAX_CS;
1365         master->transfer = pch_spi_transfer;
1366         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1367         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1368         master->max_speed_hz = PCH_MAX_BAUDRATE;
1369
1370         data->board_dat = board_dat;
1371         data->plat_dev = plat_dev;
1372         data->n_curnt_chip = 255;
1373         data->status = STATUS_RUNNING;
1374         data->ch = plat_dev->id;
1375         data->use_dma = use_dma;
1376
1377         INIT_LIST_HEAD(&data->queue);
1378         spin_lock_init(&data->lock);
1379         INIT_WORK(&data->work, pch_spi_process_messages);
1380         init_waitqueue_head(&data->wait);
1381
1382         ret = pch_spi_get_resources(board_dat, data);
1383         if (ret) {
1384                 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1385                 goto err_spi_get_resources;
1386         }
1387
1388         ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1389                           IRQF_SHARED, KBUILD_MODNAME, data);
1390         if (ret) {
1391                 dev_err(&plat_dev->dev,
1392                         "%s request_irq failed\n", __func__);
1393                 goto err_request_irq;
1394         }
1395         data->irq_reg_sts = true;
1396
1397         pch_spi_set_master_mode(master);
1398
1399         if (use_dma) {
1400                 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1401                 ret = pch_alloc_dma_buf(board_dat, data);
1402                 if (ret)
1403                         goto err_spi_register_master;
1404         }
1405
1406         ret = spi_register_master(master);
1407         if (ret != 0) {
1408                 dev_err(&plat_dev->dev,
1409                         "%s spi_register_master FAILED\n", __func__);
1410                 goto err_spi_register_master;
1411         }
1412
1413         return 0;
1414
1415 err_spi_register_master:
1416         pch_free_dma_buf(board_dat, data);
1417         free_irq(board_dat->pdev->irq, data);
1418 err_request_irq:
1419         pch_spi_free_resources(board_dat, data);
1420 err_spi_get_resources:
1421         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1422 err_pci_iomap:
1423         spi_master_put(master);
1424
1425         return ret;
1426 }
1427
1428 static int pch_spi_pd_remove(struct platform_device *plat_dev)
1429 {
1430         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1431         struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1432         int count;
1433         unsigned long flags;
1434
1435         dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1436                 __func__, plat_dev->id, board_dat->pdev->irq);
1437
1438         if (use_dma)
1439                 pch_free_dma_buf(board_dat, data);
1440
1441         /* check for any pending messages; no action is taken if the queue
1442          * is still full; but at least we tried.  Unload anyway */
1443         count = 500;
1444         spin_lock_irqsave(&data->lock, flags);
1445         data->status = STATUS_EXITING;
1446         while ((list_empty(&data->queue) == 0) && --count) {
1447                 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1448                         __func__);
1449                 spin_unlock_irqrestore(&data->lock, flags);
1450                 msleep(PCH_SLEEP_TIME);
1451                 spin_lock_irqsave(&data->lock, flags);
1452         }
1453         spin_unlock_irqrestore(&data->lock, flags);
1454
1455         pch_spi_free_resources(board_dat, data);
1456         /* disable interrupts & free IRQ */
1457         if (data->irq_reg_sts) {
1458                 /* disable interrupts */
1459                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1460                 data->irq_reg_sts = false;
1461                 free_irq(board_dat->pdev->irq, data);
1462         }
1463
1464         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1465         spi_unregister_master(data->master);
1466
1467         return 0;
1468 }
1469 #ifdef CONFIG_PM
1470 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1471                               pm_message_t state)
1472 {
1473         u8 count;
1474         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1475         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1476
1477         dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1478
1479         if (!board_dat) {
1480                 dev_err(&pd_dev->dev,
1481                         "%s pci_get_drvdata returned NULL\n", __func__);
1482                 return -EFAULT;
1483         }
1484
1485         /* check if the current message is processed:
1486            Only after thats done the transfer will be suspended */
1487         count = 255;
1488         while ((--count) > 0) {
1489                 if (!(data->bcurrent_msg_processing))
1490                         break;
1491                 msleep(PCH_SLEEP_TIME);
1492         }
1493
1494         /* Free IRQ */
1495         if (data->irq_reg_sts) {
1496                 /* disable all interrupts */
1497                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1498                 pch_spi_reset(data->master);
1499                 free_irq(board_dat->pdev->irq, data);
1500
1501                 data->irq_reg_sts = false;
1502                 dev_dbg(&pd_dev->dev,
1503                         "%s free_irq invoked successfully.\n", __func__);
1504         }
1505
1506         return 0;
1507 }
1508
1509 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1510 {
1511         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1512         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1513         int retval;
1514
1515         if (!board_dat) {
1516                 dev_err(&pd_dev->dev,
1517                         "%s pci_get_drvdata returned NULL\n", __func__);
1518                 return -EFAULT;
1519         }
1520
1521         if (!data->irq_reg_sts) {
1522                 /* register IRQ */
1523                 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1524                                      IRQF_SHARED, KBUILD_MODNAME, data);
1525                 if (retval < 0) {
1526                         dev_err(&pd_dev->dev,
1527                                 "%s request_irq failed\n", __func__);
1528                         return retval;
1529                 }
1530
1531                 /* reset PCH SPI h/w */
1532                 pch_spi_reset(data->master);
1533                 pch_spi_set_master_mode(data->master);
1534                 data->irq_reg_sts = true;
1535         }
1536         return 0;
1537 }
1538 #else
1539 #define pch_spi_pd_suspend NULL
1540 #define pch_spi_pd_resume NULL
1541 #endif
1542
1543 static struct platform_driver pch_spi_pd_driver = {
1544         .driver = {
1545                 .name = "pch-spi",
1546         },
1547         .probe = pch_spi_pd_probe,
1548         .remove = pch_spi_pd_remove,
1549         .suspend = pch_spi_pd_suspend,
1550         .resume = pch_spi_pd_resume
1551 };
1552
1553 static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1554 {
1555         struct pch_spi_board_data *board_dat;
1556         struct platform_device *pd_dev = NULL;
1557         int retval;
1558         int i;
1559         struct pch_pd_dev_save *pd_dev_save;
1560
1561         pd_dev_save = kzalloc(sizeof(*pd_dev_save), GFP_KERNEL);
1562         if (!pd_dev_save)
1563                 return -ENOMEM;
1564
1565         board_dat = kzalloc(sizeof(*board_dat), GFP_KERNEL);
1566         if (!board_dat) {
1567                 retval = -ENOMEM;
1568                 goto err_no_mem;
1569         }
1570
1571         retval = pci_request_regions(pdev, KBUILD_MODNAME);
1572         if (retval) {
1573                 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1574                 goto pci_request_regions;
1575         }
1576
1577         board_dat->pdev = pdev;
1578         board_dat->num = id->driver_data;
1579         pd_dev_save->num = id->driver_data;
1580         pd_dev_save->board_dat = board_dat;
1581
1582         retval = pci_enable_device(pdev);
1583         if (retval) {
1584                 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1585                 goto pci_enable_device;
1586         }
1587
1588         for (i = 0; i < board_dat->num; i++) {
1589                 pd_dev = platform_device_alloc("pch-spi", i);
1590                 if (!pd_dev) {
1591                         dev_err(&pdev->dev, "platform_device_alloc failed\n");
1592                         retval = -ENOMEM;
1593                         goto err_platform_device;
1594                 }
1595                 pd_dev_save->pd_save[i] = pd_dev;
1596                 pd_dev->dev.parent = &pdev->dev;
1597
1598                 retval = platform_device_add_data(pd_dev, board_dat,
1599                                                   sizeof(*board_dat));
1600                 if (retval) {
1601                         dev_err(&pdev->dev,
1602                                 "platform_device_add_data failed\n");
1603                         platform_device_put(pd_dev);
1604                         goto err_platform_device;
1605                 }
1606
1607                 retval = platform_device_add(pd_dev);
1608                 if (retval) {
1609                         dev_err(&pdev->dev, "platform_device_add failed\n");
1610                         platform_device_put(pd_dev);
1611                         goto err_platform_device;
1612                 }
1613         }
1614
1615         pci_set_drvdata(pdev, pd_dev_save);
1616
1617         return 0;
1618
1619 err_platform_device:
1620         while (--i >= 0)
1621                 platform_device_unregister(pd_dev_save->pd_save[i]);
1622         pci_disable_device(pdev);
1623 pci_enable_device:
1624         pci_release_regions(pdev);
1625 pci_request_regions:
1626         kfree(board_dat);
1627 err_no_mem:
1628         kfree(pd_dev_save);
1629
1630         return retval;
1631 }
1632
1633 static void pch_spi_remove(struct pci_dev *pdev)
1634 {
1635         int i;
1636         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1637
1638         dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1639
1640         for (i = 0; i < pd_dev_save->num; i++)
1641                 platform_device_unregister(pd_dev_save->pd_save[i]);
1642
1643         pci_disable_device(pdev);
1644         pci_release_regions(pdev);
1645         kfree(pd_dev_save->board_dat);
1646         kfree(pd_dev_save);
1647 }
1648
1649 #ifdef CONFIG_PM
1650 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1651 {
1652         int retval;
1653         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1654
1655         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1656
1657         pd_dev_save->board_dat->suspend_sts = true;
1658
1659         /* save config space */
1660         retval = pci_save_state(pdev);
1661         if (retval == 0) {
1662                 pci_enable_wake(pdev, PCI_D3hot, 0);
1663                 pci_disable_device(pdev);
1664                 pci_set_power_state(pdev, PCI_D3hot);
1665         } else {
1666                 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1667         }
1668
1669         return retval;
1670 }
1671
1672 static int pch_spi_resume(struct pci_dev *pdev)
1673 {
1674         int retval;
1675         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1676         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1677
1678         pci_set_power_state(pdev, PCI_D0);
1679         pci_restore_state(pdev);
1680
1681         retval = pci_enable_device(pdev);
1682         if (retval < 0) {
1683                 dev_err(&pdev->dev,
1684                         "%s pci_enable_device failed\n", __func__);
1685         } else {
1686                 pci_enable_wake(pdev, PCI_D3hot, 0);
1687
1688                 /* set suspend status to false */
1689                 pd_dev_save->board_dat->suspend_sts = false;
1690         }
1691
1692         return retval;
1693 }
1694 #else
1695 #define pch_spi_suspend NULL
1696 #define pch_spi_resume NULL
1697
1698 #endif
1699
1700 static struct pci_driver pch_spi_pcidev_driver = {
1701         .name = "pch_spi",
1702         .id_table = pch_spi_pcidev_id,
1703         .probe = pch_spi_probe,
1704         .remove = pch_spi_remove,
1705         .suspend = pch_spi_suspend,
1706         .resume = pch_spi_resume,
1707 };
1708
1709 static int __init pch_spi_init(void)
1710 {
1711         int ret;
1712         ret = platform_driver_register(&pch_spi_pd_driver);
1713         if (ret)
1714                 return ret;
1715
1716         ret = pci_register_driver(&pch_spi_pcidev_driver);
1717         if (ret) {
1718                 platform_driver_unregister(&pch_spi_pd_driver);
1719                 return ret;
1720         }
1721
1722         return 0;
1723 }
1724 module_init(pch_spi_init);
1725
1726 static void __exit pch_spi_exit(void)
1727 {
1728         pci_unregister_driver(&pch_spi_pcidev_driver);
1729         platform_driver_unregister(&pch_spi_pd_driver);
1730 }
1731 module_exit(pch_spi_exit);
1732
1733 module_param(use_dma, int, 0644);
1734 MODULE_PARM_DESC(use_dma,
1735                  "to use DMA for data transfers pass 1 else 0; default 1");
1736
1737 MODULE_LICENSE("GPL");
1738 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
1739 MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
1740