3 * Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
8 * Tel: +19(0)7223/9493-0
9 * Fax: +49(0)7223/9493-92
10 * http://www.addi-data.com
13 * This program is free software; you can redistribute it and/or modify it under
14 * the terms of the GNU General Public License as published by the Free Software
15 * Foundation; either version 2 of the License, or (at your option) any later
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
20 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
25 * Driver: addi_apci_1564
26 * Description: ADDI-DATA APCI-1564 Digital I/O board
27 * Devices: [ADDI-DATA] APCI-1564 (addi_apci_1564)
28 * Author: H Hartley Sweeten <hsweeten@visionengravers.com>
29 * Updated: Thu, 02 Jun 2016 13:12:46 -0700
32 * Configuration Options: not applicable, uses comedi PCI auto config
34 * This board has the following features:
35 * - 32 optically isolated digital inputs (24V), 16 of which can
36 * generate change-of-state (COS) interrupts (channels 4 to 19)
37 * - 32 optically isolated digital outputs (10V to 36V)
38 * - 1 8-bit watchdog for resetting the outputs
41 * - 2 diagnostic inputs
43 * The COS, timer, and counter subdevices all use the dev->read_subdev to
44 * return the interrupt status. The sample data is updated and returned when
45 * any of these subdevices generate an interrupt. The sample data format is:
48 * ----- ------------------------------------------
51 * 29 counter 2 interrupt
52 * 28 counter 1 interrupt
53 * 27 counter 0 interrupt
55 * 19:4 COS digital input state (channels 19 to 4)
58 * The COS interrupts must be configured using an INSN_CONFIG_DIGITAL_TRIG
59 * instruction before they can be enabled by an async command. The COS
60 * interrupts will stay active until canceled.
62 * The timer subdevice does not use an async command. All control is handled
63 * by the (*insn_config).
65 * FIXME: The format of the ADDI_TCW_TIMEBASE_REG is not descibed in the
66 * datasheet I have. The INSN_CONFIG_SET_CLOCK_SRC currently just writes
67 * the raw data[1] to this register along with the raw data[2] value to the
68 * ADDI_TCW_RELOAD_REG. If anyone tests this and can determine the actual
69 * timebase/reload operation please let me know.
71 * The counter subdevice also does not use an async command. All control is
72 * handled by the (*insn_config).
74 * FIXME: The operation of the counters is not really described in the
75 * datasheet I have. The (*insn_config) needs more work.
78 #include <linux/module.h>
79 #include <linux/interrupt.h>
81 #include "../comedi_pci.h"
83 #include "addi_watchdog.h"
88 * PLD Revision 1.0 I/O Mapping
90 * 0x04 - 0x18 Timer 12-Bit
92 * PLD Revision 2.x I/O Mapping
94 * 0x04 - 0x14 Digital Input
95 * 0x18 - 0x25 Digital Output
96 * 0x28 - 0x44 Watchdog 8-Bit
97 * 0x48 - 0x64 Timer 12-Bit
99 #define APCI1564_EEPROM_REG 0x00
100 #define APCI1564_EEPROM_VCC_STATUS BIT(8)
101 #define APCI1564_EEPROM_TO_REV(x) (((x) >> 4) & 0xf)
102 #define APCI1564_EEPROM_DI BIT(3)
103 #define APCI1564_EEPROM_DO BIT(2)
104 #define APCI1564_EEPROM_CS BIT(1)
105 #define APCI1564_EEPROM_CLK BIT(0)
106 #define APCI1564_REV1_TIMER_IOBASE 0x04
107 #define APCI1564_REV2_MAIN_IOBASE 0x04
108 #define APCI1564_REV2_TIMER_IOBASE 0x48
113 * PLD Revision 1.0 I/O Mapping
114 * 0x00 - 0x10 Digital Input
115 * 0x14 - 0x20 Digital Output
116 * 0x24 - 0x3c Watchdog 8-Bit
118 * PLD Revision 2.x I/O Mapping
123 #define APCI1564_REV1_MAIN_IOBASE 0x00
126 * dev->iobase Register Map
127 * PLD Revision 1.0 - PCI BAR 1 + 0x00
128 * PLD Revision 2.x - PCI BAR 0 + 0x04
130 #define APCI1564_DI_REG 0x00
131 #define APCI1564_DI_INT_MODE1_REG 0x04
132 #define APCI1564_DI_INT_MODE2_REG 0x08
133 #define APCI1564_DI_INT_MODE_MASK 0x000ffff0 /* chans [19:4] */
134 #define APCI1564_DI_INT_STATUS_REG 0x0c
135 #define APCI1564_DI_IRQ_REG 0x10
136 #define APCI1564_DI_IRQ_ENA BIT(2)
137 #define APCI1564_DI_IRQ_MODE BIT(1) /* 1=AND, 0=OR */
138 #define APCI1564_DO_REG 0x14
139 #define APCI1564_DO_INT_CTRL_REG 0x18
140 #define APCI1564_DO_INT_CTRL_CC_INT_ENA BIT(1)
141 #define APCI1564_DO_INT_CTRL_VCC_INT_ENA BIT(0)
142 #define APCI1564_DO_INT_STATUS_REG 0x1c
143 #define APCI1564_DO_INT_STATUS_CC BIT(1)
144 #define APCI1564_DO_INT_STATUS_VCC BIT(0)
145 #define APCI1564_DO_IRQ_REG 0x20
146 #define APCI1564_DO_IRQ_INTR BIT(0)
147 #define APCI1564_WDOG_IOBASE 0x24
150 * devpriv->timer Register Map (see addi_tcw.h for register/bit defines)
151 * PLD Revision 1.0 - PCI BAR 0 + 0x04
152 * PLD Revision 2.x - PCI BAR 0 + 0x48
156 * devpriv->counters Register Map (see addi_tcw.h for register/bit defines)
157 * PLD Revision 2.x - PCI BAR 1 + 0x00
159 #define APCI1564_COUNTER(x) ((x) * 0x20)
162 * The dev->read_subdev is used to return the interrupt events along with
163 * the state of the interrupt capable inputs.
165 #define APCI1564_EVENT_COS BIT(31)
166 #define APCI1564_EVENT_TIMER BIT(30)
167 #define APCI1564_EVENT_COUNTER(x) BIT(27 + (x)) /* counter 0-2 */
168 #define APCI1564_EVENT_MASK 0xfff0000f /* all but [19:4] */
170 struct apci1564_private {
171 unsigned long eeprom; /* base address of EEPROM register */
172 unsigned long timer; /* base address of 12-bit timer */
173 unsigned long counters; /* base address of 32-bit counters */
174 unsigned int mode1; /* rising-edge/high level channels */
175 unsigned int mode2; /* falling-edge/low level channels */
176 unsigned int ctrl; /* interrupt mode OR (edge) . AND (level) */
179 static int apci1564_reset(struct comedi_device *dev)
181 struct apci1564_private *devpriv = dev->private;
183 /* Disable the input interrupts and reset status register */
184 outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
185 inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
186 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
187 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
189 /* Reset the output channels and disable interrupts */
190 outl(0x0, dev->iobase + APCI1564_DO_REG);
191 outl(0x0, dev->iobase + APCI1564_DO_INT_CTRL_REG);
193 /* Reset the watchdog registers */
194 addi_watchdog_reset(dev->iobase + APCI1564_WDOG_IOBASE);
196 /* Reset the timer registers */
197 outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
198 outl(0x0, devpriv->timer + ADDI_TCW_RELOAD_REG);
200 if (devpriv->counters) {
201 unsigned long iobase = devpriv->counters + ADDI_TCW_CTRL_REG;
203 /* Reset the counter registers */
204 outl(0x0, iobase + APCI1564_COUNTER(0));
205 outl(0x0, iobase + APCI1564_COUNTER(1));
206 outl(0x0, iobase + APCI1564_COUNTER(2));
212 static irqreturn_t apci1564_interrupt(int irq, void *d)
214 struct comedi_device *dev = d;
215 struct apci1564_private *devpriv = dev->private;
216 struct comedi_subdevice *s = dev->read_subdev;
221 s->state &= ~APCI1564_EVENT_MASK;
223 status = inl(dev->iobase + APCI1564_DI_IRQ_REG);
224 if (status & APCI1564_DI_IRQ_ENA) {
225 /* get the COS interrupt state and set the event flag */
226 s->state = inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
227 s->state &= APCI1564_DI_INT_MODE_MASK;
228 s->state |= APCI1564_EVENT_COS;
230 /* clear the interrupt */
231 outl(status & ~APCI1564_DI_IRQ_ENA,
232 dev->iobase + APCI1564_DI_IRQ_REG);
233 outl(status, dev->iobase + APCI1564_DI_IRQ_REG);
236 status = inl(devpriv->timer + ADDI_TCW_IRQ_REG);
237 if (status & ADDI_TCW_IRQ) {
238 s->state |= APCI1564_EVENT_TIMER;
240 /* clear the interrupt */
241 ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
242 outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
243 outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG);
246 if (devpriv->counters) {
247 for (chan = 0; chan < 3; chan++) {
248 unsigned long iobase;
250 iobase = devpriv->counters + APCI1564_COUNTER(chan);
252 status = inl(iobase + ADDI_TCW_IRQ_REG);
253 if (status & ADDI_TCW_IRQ) {
254 s->state |= APCI1564_EVENT_COUNTER(chan);
256 /* clear the interrupt */
257 ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
258 outl(0x0, iobase + ADDI_TCW_CTRL_REG);
259 outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
264 if (s->state & APCI1564_EVENT_MASK) {
265 comedi_buf_write_samples(s, &s->state, 1);
266 comedi_handle_events(dev, s);
272 static int apci1564_di_insn_bits(struct comedi_device *dev,
273 struct comedi_subdevice *s,
274 struct comedi_insn *insn,
277 data[1] = inl(dev->iobase + APCI1564_DI_REG);
282 static int apci1564_do_insn_bits(struct comedi_device *dev,
283 struct comedi_subdevice *s,
284 struct comedi_insn *insn,
287 s->state = inl(dev->iobase + APCI1564_DO_REG);
289 if (comedi_dio_update_state(s, data))
290 outl(s->state, dev->iobase + APCI1564_DO_REG);
297 static int apci1564_diag_insn_bits(struct comedi_device *dev,
298 struct comedi_subdevice *s,
299 struct comedi_insn *insn,
302 data[1] = inl(dev->iobase + APCI1564_DO_INT_STATUS_REG) & 3;
308 * Change-Of-State (COS) interrupt configuration
310 * Channels 4 to 19 are interruptible. These channels can be configured
311 * to generate interrupts based on AND/OR logic for the desired channels.
314 * - reacts to rising or falling edges
315 * - interrupt is generated when any enabled channel
316 * meet the desired interrupt condition
319 * - reacts to changes in level of the selected inputs
320 * - interrupt is generated when all enabled channels
321 * meet the desired interrupt condition
322 * - after an interrupt, a change in level must occur on
323 * the selected inputs to release the IRQ logic
325 * The COS interrupt must be configured before it can be enabled.
327 * data[0] : INSN_CONFIG_DIGITAL_TRIG
328 * data[1] : trigger number (= 0)
329 * data[2] : configuration operation:
330 * COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
331 * COMEDI_DIGITAL_TRIG_ENABLE_EDGES = OR (edge) interrupts
332 * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = AND (level) interrupts
333 * data[3] : left-shift for data[4] and data[5]
334 * data[4] : rising-edge/high level channels
335 * data[5] : falling-edge/low level channels
337 static int apci1564_cos_insn_config(struct comedi_device *dev,
338 struct comedi_subdevice *s,
339 struct comedi_insn *insn,
342 struct apci1564_private *devpriv = dev->private;
343 unsigned int shift, oldmask, himask, lomask;
346 case INSN_CONFIG_DIGITAL_TRIG:
351 oldmask = (1U << shift) - 1;
352 himask = data[4] << shift;
353 lomask = data[5] << shift;
355 oldmask = 0xffffffffu;
360 case COMEDI_DIGITAL_TRIG_DISABLE:
364 outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
365 inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
366 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
367 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
369 case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
370 if (devpriv->ctrl != APCI1564_DI_IRQ_ENA) {
371 /* switching to 'OR' mode */
372 devpriv->ctrl = APCI1564_DI_IRQ_ENA;
373 /* wipe old channels */
377 /* preserve unspecified channels */
378 devpriv->mode1 &= oldmask;
379 devpriv->mode2 &= oldmask;
381 /* configure specified channels */
382 devpriv->mode1 |= himask;
383 devpriv->mode2 |= lomask;
385 case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS:
386 if (devpriv->ctrl != (APCI1564_DI_IRQ_ENA |
387 APCI1564_DI_IRQ_MODE)) {
388 /* switching to 'AND' mode */
389 devpriv->ctrl = APCI1564_DI_IRQ_ENA |
390 APCI1564_DI_IRQ_MODE;
391 /* wipe old channels */
395 /* preserve unspecified channels */
396 devpriv->mode1 &= oldmask;
397 devpriv->mode2 &= oldmask;
399 /* configure specified channels */
400 devpriv->mode1 |= himask;
401 devpriv->mode2 |= lomask;
407 /* ensure the mode bits are in-range for channels [19:4] */
408 devpriv->mode1 &= APCI1564_DI_INT_MODE_MASK;
409 devpriv->mode2 &= APCI1564_DI_INT_MODE_MASK;
417 static int apci1564_cos_insn_bits(struct comedi_device *dev,
418 struct comedi_subdevice *s,
419 struct comedi_insn *insn,
427 static int apci1564_cos_cmdtest(struct comedi_device *dev,
428 struct comedi_subdevice *s,
429 struct comedi_cmd *cmd)
433 /* Step 1 : check if triggers are trivially valid */
435 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
436 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
437 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
438 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
439 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
444 /* Step 2a : make sure trigger sources are unique */
445 /* Step 2b : and mutually compatible */
447 /* Step 3: check if arguments are trivially valid */
449 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
450 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
451 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
452 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
454 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
459 /* Step 4: fix up any arguments */
461 /* Step 5: check channel list if it exists */
467 * Change-Of-State (COS) 'do_cmd' operation
469 * Enable the COS interrupt as configured by apci1564_cos_insn_config().
471 static int apci1564_cos_cmd(struct comedi_device *dev,
472 struct comedi_subdevice *s)
474 struct apci1564_private *devpriv = dev->private;
476 if (!devpriv->ctrl && !(devpriv->mode1 || devpriv->mode2)) {
477 dev_warn(dev->class_dev,
478 "Interrupts disabled due to mode configuration!\n");
482 outl(devpriv->mode1, dev->iobase + APCI1564_DI_INT_MODE1_REG);
483 outl(devpriv->mode2, dev->iobase + APCI1564_DI_INT_MODE2_REG);
484 outl(devpriv->ctrl, dev->iobase + APCI1564_DI_IRQ_REG);
489 static int apci1564_cos_cancel(struct comedi_device *dev,
490 struct comedi_subdevice *s)
492 outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
493 inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
494 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
495 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
500 static int apci1564_timer_insn_config(struct comedi_device *dev,
501 struct comedi_subdevice *s,
502 struct comedi_insn *insn,
505 struct apci1564_private *devpriv = dev->private;
509 case INSN_CONFIG_ARM:
510 if (data[1] > s->maxdata)
512 outl(data[1], devpriv->timer + ADDI_TCW_RELOAD_REG);
513 outl(ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_TIMER_ENA,
514 devpriv->timer + ADDI_TCW_CTRL_REG);
516 case INSN_CONFIG_DISARM:
517 outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
519 case INSN_CONFIG_GET_COUNTER_STATUS:
521 val = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
522 if (val & ADDI_TCW_CTRL_IRQ_ENA)
523 data[1] |= COMEDI_COUNTER_ARMED;
524 if (val & ADDI_TCW_CTRL_TIMER_ENA)
525 data[1] |= COMEDI_COUNTER_COUNTING;
526 val = inl(devpriv->timer + ADDI_TCW_STATUS_REG);
527 if (val & ADDI_TCW_STATUS_OVERFLOW)
528 data[1] |= COMEDI_COUNTER_TERMINAL_COUNT;
529 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING |
530 COMEDI_COUNTER_TERMINAL_COUNT;
532 case INSN_CONFIG_SET_CLOCK_SRC:
533 if (data[2] > s->maxdata)
535 outl(data[1], devpriv->timer + ADDI_TCW_TIMEBASE_REG);
536 outl(data[2], devpriv->timer + ADDI_TCW_RELOAD_REG);
538 case INSN_CONFIG_GET_CLOCK_SRC:
539 data[1] = inl(devpriv->timer + ADDI_TCW_TIMEBASE_REG);
540 data[2] = inl(devpriv->timer + ADDI_TCW_RELOAD_REG);
549 static int apci1564_timer_insn_write(struct comedi_device *dev,
550 struct comedi_subdevice *s,
551 struct comedi_insn *insn,
554 struct apci1564_private *devpriv = dev->private;
556 /* just write the last last to the reload register */
558 unsigned int val = data[insn->n - 1];
560 outl(val, devpriv->timer + ADDI_TCW_RELOAD_REG);
566 static int apci1564_timer_insn_read(struct comedi_device *dev,
567 struct comedi_subdevice *s,
568 struct comedi_insn *insn,
571 struct apci1564_private *devpriv = dev->private;
574 /* return the actual value of the timer */
575 for (i = 0; i < insn->n; i++)
576 data[i] = inl(devpriv->timer + ADDI_TCW_VAL_REG);
581 static int apci1564_counter_insn_config(struct comedi_device *dev,
582 struct comedi_subdevice *s,
583 struct comedi_insn *insn,
586 struct apci1564_private *devpriv = dev->private;
587 unsigned int chan = CR_CHAN(insn->chanspec);
588 unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
592 case INSN_CONFIG_ARM:
593 val = inl(iobase + ADDI_TCW_CTRL_REG);
594 val |= ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_CNTR_ENA;
595 outl(data[1], iobase + ADDI_TCW_RELOAD_REG);
596 outl(val, iobase + ADDI_TCW_CTRL_REG);
598 case INSN_CONFIG_DISARM:
599 val = inl(iobase + ADDI_TCW_CTRL_REG);
600 val &= ~(ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_CNTR_ENA);
601 outl(val, iobase + ADDI_TCW_CTRL_REG);
603 case INSN_CONFIG_SET_COUNTER_MODE:
605 * FIXME: The counter operation is not described in the
606 * datasheet. For now just write the raw data[1] value to
607 * the control register.
609 outl(data[1], iobase + ADDI_TCW_CTRL_REG);
611 case INSN_CONFIG_GET_COUNTER_STATUS:
613 val = inl(iobase + ADDI_TCW_CTRL_REG);
614 if (val & ADDI_TCW_CTRL_IRQ_ENA)
615 data[1] |= COMEDI_COUNTER_ARMED;
616 if (val & ADDI_TCW_CTRL_CNTR_ENA)
617 data[1] |= COMEDI_COUNTER_COUNTING;
618 val = inl(iobase + ADDI_TCW_STATUS_REG);
619 if (val & ADDI_TCW_STATUS_OVERFLOW)
620 data[1] |= COMEDI_COUNTER_TERMINAL_COUNT;
621 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING |
622 COMEDI_COUNTER_TERMINAL_COUNT;
631 static int apci1564_counter_insn_write(struct comedi_device *dev,
632 struct comedi_subdevice *s,
633 struct comedi_insn *insn,
636 struct apci1564_private *devpriv = dev->private;
637 unsigned int chan = CR_CHAN(insn->chanspec);
638 unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
640 /* just write the last last to the reload register */
642 unsigned int val = data[insn->n - 1];
644 outl(val, iobase + ADDI_TCW_RELOAD_REG);
650 static int apci1564_counter_insn_read(struct comedi_device *dev,
651 struct comedi_subdevice *s,
652 struct comedi_insn *insn,
655 struct apci1564_private *devpriv = dev->private;
656 unsigned int chan = CR_CHAN(insn->chanspec);
657 unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
660 /* return the actual value of the counter */
661 for (i = 0; i < insn->n; i++)
662 data[i] = inl(iobase + ADDI_TCW_VAL_REG);
667 static int apci1564_auto_attach(struct comedi_device *dev,
668 unsigned long context_unused)
670 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
671 struct apci1564_private *devpriv;
672 struct comedi_subdevice *s;
676 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
680 ret = comedi_pci_enable(dev);
684 /* read the EEPROM register and check the I/O map revision */
685 devpriv->eeprom = pci_resource_start(pcidev, 0);
686 val = inl(devpriv->eeprom + APCI1564_EEPROM_REG);
687 if (APCI1564_EEPROM_TO_REV(val) == 0) {
688 /* PLD Revision 1.0 I/O Mapping */
689 dev->iobase = pci_resource_start(pcidev, 1) +
690 APCI1564_REV1_MAIN_IOBASE;
691 devpriv->timer = devpriv->eeprom + APCI1564_REV1_TIMER_IOBASE;
693 /* PLD Revision 2.x I/O Mapping */
694 dev->iobase = devpriv->eeprom + APCI1564_REV2_MAIN_IOBASE;
695 devpriv->timer = devpriv->eeprom + APCI1564_REV2_TIMER_IOBASE;
696 devpriv->counters = pci_resource_start(pcidev, 1);
701 if (pcidev->irq > 0) {
702 ret = request_irq(pcidev->irq, apci1564_interrupt, IRQF_SHARED,
703 dev->board_name, dev);
705 dev->irq = pcidev->irq;
708 ret = comedi_alloc_subdevices(dev, 7);
712 /* Allocate and Initialise DI Subdevice Structures */
713 s = &dev->subdevices[0];
714 s->type = COMEDI_SUBD_DI;
715 s->subdev_flags = SDF_READABLE;
718 s->range_table = &range_digital;
719 s->insn_bits = apci1564_di_insn_bits;
721 /* Allocate and Initialise DO Subdevice Structures */
722 s = &dev->subdevices[1];
723 s->type = COMEDI_SUBD_DO;
724 s->subdev_flags = SDF_WRITABLE;
727 s->range_table = &range_digital;
728 s->insn_bits = apci1564_do_insn_bits;
730 /* Change-Of-State (COS) interrupt subdevice */
731 s = &dev->subdevices[2];
733 dev->read_subdev = s;
734 s->type = COMEDI_SUBD_DI;
735 s->subdev_flags = SDF_READABLE | SDF_CMD_READ | SDF_LSAMPL;
738 s->range_table = &range_digital;
740 s->insn_config = apci1564_cos_insn_config;
741 s->insn_bits = apci1564_cos_insn_bits;
742 s->do_cmdtest = apci1564_cos_cmdtest;
743 s->do_cmd = apci1564_cos_cmd;
744 s->cancel = apci1564_cos_cancel;
746 s->type = COMEDI_SUBD_UNUSED;
749 /* Timer subdevice */
750 s = &dev->subdevices[3];
751 s->type = COMEDI_SUBD_TIMER;
752 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
755 s->range_table = &range_digital;
756 s->insn_config = apci1564_timer_insn_config;
757 s->insn_write = apci1564_timer_insn_write;
758 s->insn_read = apci1564_timer_insn_read;
760 /* Counter subdevice */
761 s = &dev->subdevices[4];
762 if (devpriv->counters) {
763 s->type = COMEDI_SUBD_COUNTER;
764 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
766 s->maxdata = 0xffffffff;
767 s->range_table = &range_digital;
768 s->insn_config = apci1564_counter_insn_config;
769 s->insn_write = apci1564_counter_insn_write;
770 s->insn_read = apci1564_counter_insn_read;
772 s->type = COMEDI_SUBD_UNUSED;
775 /* Initialize the watchdog subdevice */
776 s = &dev->subdevices[5];
777 ret = addi_watchdog_init(s, dev->iobase + APCI1564_WDOG_IOBASE);
781 /* Initialize the diagnostic status subdevice */
782 s = &dev->subdevices[6];
783 s->type = COMEDI_SUBD_DI;
784 s->subdev_flags = SDF_READABLE;
787 s->range_table = &range_digital;
788 s->insn_bits = apci1564_diag_insn_bits;
793 static void apci1564_detach(struct comedi_device *dev)
797 comedi_pci_detach(dev);
800 static struct comedi_driver apci1564_driver = {
801 .driver_name = "addi_apci_1564",
802 .module = THIS_MODULE,
803 .auto_attach = apci1564_auto_attach,
804 .detach = apci1564_detach,
807 static int apci1564_pci_probe(struct pci_dev *dev,
808 const struct pci_device_id *id)
810 return comedi_pci_auto_config(dev, &apci1564_driver, id->driver_data);
813 static const struct pci_device_id apci1564_pci_table[] = {
814 { PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA, 0x1006) },
817 MODULE_DEVICE_TABLE(pci, apci1564_pci_table);
819 static struct pci_driver apci1564_pci_driver = {
820 .name = "addi_apci_1564",
821 .id_table = apci1564_pci_table,
822 .probe = apci1564_pci_probe,
823 .remove = comedi_pci_auto_unconfig,
825 module_comedi_pci_driver(apci1564_driver, apci1564_pci_driver);
827 MODULE_AUTHOR("Comedi http://www.comedi.org");
828 MODULE_DESCRIPTION("ADDI-DATA APCI-1564, 32 channel DI / 32 channel DO boards");
829 MODULE_LICENSE("GPL");