drivers/staging/comedi/drivers/cb_pcidas64.c

   1 /*
   2  * comedi/drivers/cb_pcidas64.c
   3  * This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
   4  * 64xx, 60xx, and 4020 cards.
   5  *
   6  * Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7  * Copyright (C) 2001, 2002 Frank Mori Hess
   8  *
   9  * Thanks also go to the following people:
  10  *
  11  * Steve Rosenbluth, for providing the source code for
  12  * his pci-das6402 driver, and source code for working QNX pci-6402
  13  * drivers by Greg Laird and Mariusz Bogacz.  None of the code was
  14  * used directly here, but it was useful as an additional source of
  15  * documentation on how to program the boards.
  16  *
  17  * John Sims, for much testing and feedback on pcidas-4020 support.
  18  *
  19  * COMEDI - Linux Control and Measurement Device Interface
  20  * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  21  *
  22  * This program is free software; you can redistribute it and/or modify
  23  * it under the terms of the GNU General Public License as published by
  24  * the Free Software Foundation; either version 2 of the License, or
  25  * (at your option) any later version.
  26  *
  27  * This program is distributed in the hope that it will be useful,
  28  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  29  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30  * GNU General Public License for more details.
  31  */
  32
  33 /*
  34  * Driver: cb_pcidas64
  35  * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
  36  *   with the PLX 9080 PCI controller
  37  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  38  * Status: works
  39  * Updated: Fri, 02 Nov 2012 18:58:55 +0000
  40  * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
  41  *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
  42  *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
  43  *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
  44  *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
  45  *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
  46  *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
  47  *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
  48  *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
  49  *
  50  * Configuration options:
  51  *   None.
  52  *
  53  * Manual attachment of PCI cards with the comedi_config utility is not
  54  * supported by this driver; they are attached automatically.
  55  *
  56  * These boards may be autocalibrated with the comedi_calibrate utility.
  57  *
  58  * To select the bnc trigger input on the 4020 (instead of the dio input),
  59  * specify a nonzero channel in the chanspec.  If you wish to use an external
  60  * master clock on the 4020, you may do so by setting the scan_begin_src
  61  * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
  62  * to configure the divisor to use for the external clock.
  63  *
  64  * Some devices are not identified because the PCI device IDs are not yet
  65  * known. If you have such a board, please let the maintainers know.
  66  */
  67
  68 /*
  69  * TODO:
  70  * make it return error if user attempts an ai command that uses the
  71  * external queue, and an ao command simultaneously user counter subdevice
  72  * there are a number of boards this driver will support when they are
  73  * fully released, but does not yet since the pci device id numbers
  74  * are not yet available.
  75  *
  76  * support prescaled 100khz clock for slow pacing (not available on 6000
  77  * series?)
  78  *
  79  * make ao fifo size adjustable like ai fifo
  80  */
  81
  82 #include <linux/module.h>
  83 #include <linux/delay.h>
  84 #include <linux/interrupt.h>
  85
  86 #include "../comedi_pci.h"
  87
  88 #include "8255.h"
  89 #include "plx9080.h"
  90
  91 #define TIMER_BASE 25           /*  40MHz master clock */
  92 /*
  93  * 100kHz 'prescaled' clock for slow acquisition,
  94  * maybe I'll support this someday
  95  */
  96 #define PRESCALED_TIMER_BASE    10000
  97 #define DMA_BUFFER_SIZE         0x1000
  98 #define DAC_FIFO_SIZE           0x2000
  99
 100 /* maximum value that can be loaded into board's 24-bit counters */
 101 static const int max_counter_value = 0xffffff;
 102
 103 /* PCI-DAS64xxx base addresses */
 104
 105 /* devpriv->main_iobase registers */
 106 enum write_only_registers {
 107         INTR_ENABLE_REG = 0x0,          /* interrupt enable register */
 108         HW_CONFIG_REG = 0x2,            /* hardware config register */
 109         DAQ_SYNC_REG = 0xc,
 110         DAQ_ATRIG_LOW_4020_REG = 0xc,
 111         ADC_CONTROL0_REG = 0x10,        /* adc control register 0 */
 112         ADC_CONTROL1_REG = 0x12,        /* adc control register 1 */
 113         CALIBRATION_REG = 0x14,
 114         /* lower 16 bits of adc sample interval counter */
 115         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
 116         /* upper 8 bits of adc sample interval counter */
 117         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
 118         /* lower 16 bits of delay interval counter */
 119         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
 120         /* upper 8 bits of delay interval counter */
 121         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
 122         /* lower 16 bits of hardware conversion/scan counter */
 123         ADC_COUNT_LOWER_REG = 0x1e,
 124         /* upper 8 bits of hardware conversion/scan counter */
 125         ADC_COUNT_UPPER_REG = 0x20,
 126         ADC_START_REG = 0x22,   /* software trigger to start acquisition */
 127         ADC_CONVERT_REG = 0x24, /* initiates single conversion */
 128         ADC_QUEUE_CLEAR_REG = 0x26,     /* clears adc queue */
 129         ADC_QUEUE_LOAD_REG = 0x28,      /* loads adc queue */
 130         ADC_BUFFER_CLEAR_REG = 0x2a,
 131         /* high channel for internal queue, use adc_chan_bits() inline above */
 132         ADC_QUEUE_HIGH_REG = 0x2c,
 133         DAC_CONTROL0_REG = 0x50,        /* dac control register 0 */
 134         DAC_CONTROL1_REG = 0x52,        /* dac control register 0 */
 135         /* lower 16 bits of dac sample interval counter */
 136         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
 137         /* upper 8 bits of dac sample interval counter */
 138         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
 139         DAC_SELECT_REG = 0x60,
 140         DAC_START_REG = 0x64,
 141         DAC_BUFFER_CLEAR_REG = 0x66,    /* clear dac buffer */
 142 };
 143
 144 static inline unsigned int dac_convert_reg(unsigned int channel)
 145 {
 146         return 0x70 + (2 * (channel & 0x1));
 147 }
 148
 149 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
 150 {
 151         return 0x70 + (4 * (channel & 0x1));
 152 }
 153
 154 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
 155 {
 156         return 0x72 + (4 * (channel & 0x1));
 157 }
 158
 159 enum read_only_registers {
 160         /*
 161          * hardware status register,
 162          * reading this apparently clears pending interrupts as well
 163          */
 164         HW_STATUS_REG = 0x0,
 165         PIPE1_READ_REG = 0x4,
 166         ADC_READ_PNTR_REG = 0x8,
 167         LOWER_XFER_REG = 0x10,
 168         ADC_WRITE_PNTR_REG = 0xc,
 169         PREPOST_REG = 0x14,
 170 };
 171
 172 enum read_write_registers {
 173         I8255_4020_REG = 0x48,  /* 8255 offset, for 4020 only */
 174         /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
 175         ADC_QUEUE_FIFO_REG = 0x100,
 176         ADC_FIFO_REG = 0x200,   /* adc data fifo */
 177         /* dac data fifo, has weird interactions with external channel queue */
 178         DAC_FIFO_REG = 0x300,
 179 };
 180
 181 /* dev->mmio registers */
 182 enum dio_counter_registers {
 183         DIO_8255_OFFSET = 0x0,
 184         DO_REG = 0x20,
 185         DI_REG = 0x28,
 186         DIO_DIRECTION_60XX_REG = 0x40,
 187         DIO_DATA_60XX_REG = 0x48,
 188 };
 189
 190 /* bit definitions for write-only registers */
 191
 192 enum intr_enable_contents {
 193         ADC_INTR_SRC_MASK = 0x3,        /* adc interrupt source mask */
 194         ADC_INTR_QFULL_BITS = 0x0,      /* interrupt fifo quarter full */
 195         ADC_INTR_EOC_BITS = 0x1,        /* interrupt end of conversion */
 196         ADC_INTR_EOSCAN_BITS = 0x2,     /* interrupt end of scan */
 197         ADC_INTR_EOSEQ_BITS = 0x3,      /* interrupt end of sequence mask */
 198         EN_ADC_INTR_SRC_BIT = 0x4,      /* enable adc interrupt source */
 199         EN_ADC_DONE_INTR_BIT = 0x8,     /* enable adc acquisition done intr */
 200         DAC_INTR_SRC_MASK = 0x30,
 201         DAC_INTR_QEMPTY_BITS = 0x0,
 202         DAC_INTR_HIGH_CHAN_BITS = 0x10,
 203         EN_DAC_INTR_SRC_BIT = 0x40,     /* enable dac interrupt source */
 204         EN_DAC_DONE_INTR_BIT = 0x80,
 205         EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */
 206         EN_ADC_STOP_INTR_BIT = 0x400,   /* enable adc stop trigger interrupt */
 207         EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */
 208         EN_DAC_UNDERRUN_BIT = 0x4000,   /* enable dac underrun status bit */
 209         EN_ADC_OVERRUN_BIT = 0x8000,    /* enable adc overrun status bit */
 210 };
 211
 212 enum hw_config_contents {
 213         MASTER_CLOCK_4020_MASK = 0x3,   /* master clock source mask for 4020 */
 214         INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock */
 215         BNC_CLOCK_4020_BITS = 0x2,      /* use BNC input for master clock */
 216         EXT_CLOCK_4020_BITS = 0x3,      /* use dio input for master clock */
 217         EXT_QUEUE_BIT = 0x200,          /* use external channel/gain queue */
 218         /* use 225 nanosec strobe when loading dac instead of 50 nanosec */
 219         SLOW_DAC_BIT = 0x400,
 220         /*
 221          * bit with unknown function yet given as default value in pci-das64
 222          * manual
 223          */
 224         HW_CONFIG_DUMMY_BITS = 0x2000,
 225         /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */
 226         DMA_CH_SELECT_BIT = 0x8000,
 227         FIFO_SIZE_REG = 0x4,            /* allows adjustment of fifo sizes */
 228         DAC_FIFO_SIZE_MASK = 0xff00,    /* bits that set dac fifo size */
 229         DAC_FIFO_BITS = 0xf800,         /* 8k sample ao fifo */
 230 };
 231
 232 enum daq_atrig_low_4020_contents {
 233         /* use trig/ext clk bnc input for analog gate signal */
 234         EXT_AGATE_BNC_BIT = 0x8000,
 235         /* use trig/ext clk bnc input for external stop trigger signal */
 236         EXT_STOP_TRIG_BNC_BIT = 0x4000,
 237         /* use trig/ext clk bnc input for external start trigger signal */
 238         EXT_START_TRIG_BNC_BIT = 0x2000,
 239 };
 240
 241 static inline u16 analog_trig_low_threshold_bits(u16 threshold)
 242 {
 243         return threshold & 0xfff;
 244 }
 245
 246 enum adc_control0_contents {
 247         ADC_GATE_SRC_MASK = 0x3,        /* bits that select gate */
 248         ADC_SOFT_GATE_BITS = 0x1,       /* software gate */
 249         ADC_EXT_GATE_BITS = 0x2,        /* external digital gate */
 250         ADC_ANALOG_GATE_BITS = 0x3,     /* analog level gate */
 251         /* level-sensitive gate (for digital) */
 252         ADC_GATE_LEVEL_BIT = 0x4,
 253         ADC_GATE_POLARITY_BIT = 0x8,    /* gate active low */
 254         ADC_START_TRIG_SOFT_BITS = 0x10,
 255         ADC_START_TRIG_EXT_BITS = 0x20,
 256         ADC_START_TRIG_ANALOG_BITS = 0x30,
 257         ADC_START_TRIG_MASK = 0x30,
 258         ADC_START_TRIG_FALLING_BIT = 0x40,      /* trig 1 uses falling edge */
 259         /* external pacing uses falling edge */
 260         ADC_EXT_CONV_FALLING_BIT = 0x800,
 261         /* enable hardware scan counter */
 262         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
 263         ADC_DMA_DISABLE_BIT = 0x4000,   /* disables dma */
 264         ADC_ENABLE_BIT = 0x8000,        /* master adc enable */
 265 };
 266
 267 enum adc_control1_contents {
 268         /* should be set for boards with > 16 channels */
 269         ADC_QUEUE_CONFIG_BIT = 0x1,
 270         CONVERT_POLARITY_BIT = 0x10,
 271         EOC_POLARITY_BIT = 0x20,
 272         ADC_SW_GATE_BIT = 0x40,         /* software gate of adc */
 273         ADC_DITHER_BIT = 0x200,         /* turn on extra noise for dithering */
 274         RETRIGGER_BIT = 0x800,
 275         ADC_LO_CHANNEL_4020_MASK = 0x300,
 276         ADC_HI_CHANNEL_4020_MASK = 0xc00,
 277         TWO_CHANNEL_4020_BITS = 0x1000,         /* two channel mode for 4020 */
 278         FOUR_CHANNEL_4020_BITS = 0x2000,        /* four channel mode for 4020 */
 279         CHANNEL_MODE_4020_MASK = 0x3000,
 280         ADC_MODE_MASK = 0xf000,
 281 };
 282
 283 static inline u16 adc_lo_chan_4020_bits(unsigned int channel)
 284 {
 285         return (channel & 0x3) << 8;
 286 };
 287
 288 static inline u16 adc_hi_chan_4020_bits(unsigned int channel)
 289 {
 290         return (channel & 0x3) << 10;
 291 };
 292
 293 static inline u16 adc_mode_bits(unsigned int mode)
 294 {
 295         return (mode & 0xf) << 12;
 296 };
 297
 298 enum calibration_contents {
 299         SELECT_8800_BIT = 0x1,
 300         SELECT_8402_64XX_BIT = 0x2,
 301         SELECT_1590_60XX_BIT = 0x2,
 302         CAL_EN_64XX_BIT = 0x40,         /* calibration enable for 64xx series */
 303         SERIAL_DATA_IN_BIT = 0x80,
 304         SERIAL_CLOCK_BIT = 0x100,
 305         CAL_EN_60XX_BIT = 0x200,        /* calibration enable for 60xx series */
 306         CAL_GAIN_BIT = 0x800,
 307 };
 308
 309 /*
 310  * calibration sources for 6025 are:
 311  *  0 : ground
 312  *  1 : 10V
 313  *  2 : 5V
 314  *  3 : 0.5V
 315  *  4 : 0.05V
 316  *  5 : ground
 317  *  6 : dac channel 0
 318  *  7 : dac channel 1
 319  */
 320
 321 static inline u16 adc_src_bits(unsigned int source)
 322 {
 323         return (source & 0xf) << 3;
 324 };
 325
 326 static inline u16 adc_convert_chan_4020_bits(unsigned int channel)
 327 {
 328         return (channel & 0x3) << 8;
 329 };
 330
 331 enum adc_queue_load_contents {
 332         UNIP_BIT = 0x800,               /* unipolar/bipolar bit */
 333         ADC_SE_DIFF_BIT = 0x1000,       /* single-ended/ differential bit */
 334         /* non-referenced single-ended (common-mode input) */
 335         ADC_COMMON_BIT = 0x2000,
 336         QUEUE_EOSEQ_BIT = 0x4000,       /* queue end of sequence */
 337         QUEUE_EOSCAN_BIT = 0x8000,      /* queue end of scan */
 338 };
 339
 340 static inline u16 adc_chan_bits(unsigned int channel)
 341 {
 342         return channel & 0x3f;
 343 };
 344
 345 enum dac_control0_contents {
 346         DAC_ENABLE_BIT = 0x8000,        /* dac controller enable bit */
 347         DAC_CYCLIC_STOP_BIT = 0x4000,
 348         DAC_WAVEFORM_MODE_BIT = 0x100,
 349         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
 350         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
 351         WAVEFORM_TRIG_MASK = 0x30,
 352         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
 353         WAVEFORM_TRIG_SOFT_BITS = 0x10,
 354         WAVEFORM_TRIG_EXT_BITS = 0x20,
 355         WAVEFORM_TRIG_ADC1_BITS = 0x30,
 356         WAVEFORM_TRIG_FALLING_BIT = 0x8,
 357         WAVEFORM_GATE_LEVEL_BIT = 0x4,
 358         WAVEFORM_GATE_ENABLE_BIT = 0x2,
 359         WAVEFORM_GATE_SELECT_BIT = 0x1,
 360 };
 361
 362 enum dac_control1_contents {
 363         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
 364         DAC1_EXT_REF_BIT = 0x200,
 365         DAC0_EXT_REF_BIT = 0x100,
 366         DAC_OUTPUT_ENABLE_BIT = 0x80,   /* dac output enable bit */
 367         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
 368         DAC_SW_GATE_BIT = 0x20,
 369         DAC1_UNIPOLAR_BIT = 0x8,
 370         DAC0_UNIPOLAR_BIT = 0x2,
 371 };
 372
 373 /* bit definitions for read-only registers */
 374 enum hw_status_contents {
 375         DAC_UNDERRUN_BIT = 0x1,
 376         ADC_OVERRUN_BIT = 0x2,
 377         DAC_ACTIVE_BIT = 0x4,
 378         ADC_ACTIVE_BIT = 0x8,
 379         DAC_INTR_PENDING_BIT = 0x10,
 380         ADC_INTR_PENDING_BIT = 0x20,
 381         DAC_DONE_BIT = 0x40,
 382         ADC_DONE_BIT = 0x80,
 383         EXT_INTR_PENDING_BIT = 0x100,
 384         ADC_STOP_BIT = 0x200,
 385 };
 386
 387 static inline u16 pipe_full_bits(u16 hw_status_bits)
 388 {
 389         return (hw_status_bits >> 10) & 0x3;
 390 };
 391
 392 static inline unsigned int dma_chain_flag_bits(u16 prepost_bits)
 393 {
 394         return (prepost_bits >> 6) & 0x3;
 395 }
 396
 397 static inline unsigned int adc_upper_read_ptr_code(u16 prepost_bits)
 398 {
 399         return (prepost_bits >> 12) & 0x3;
 400 }
 401
 402 static inline unsigned int adc_upper_write_ptr_code(u16 prepost_bits)
 403 {
 404         return (prepost_bits >> 14) & 0x3;
 405 }
 406
 407 /* I2C addresses for 4020 */
 408 enum i2c_addresses {
 409         RANGE_CAL_I2C_ADDR = 0x20,
 410         CALDAC0_I2C_ADDR = 0xc,
 411         CALDAC1_I2C_ADDR = 0xd,
 412 };
 413
 414 enum range_cal_i2c_contents {
 415         /* bits that set what source the adc converter measures */
 416         ADC_SRC_4020_MASK = 0x70,
 417         /* make bnc trig/ext clock threshold 0V instead of 2.5V */
 418         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
 419 };
 420
 421 static inline u8 adc_src_4020_bits(unsigned int source)
 422 {
 423         return (source << 4) & ADC_SRC_4020_MASK;
 424 };
 425
 426 static inline u8 attenuate_bit(unsigned int channel)
 427 {
 428         /* attenuate channel (+-5V input range) */
 429         return 1 << (channel & 0x3);
 430 };
 431
 432 /* analog input ranges for 64xx boards */
 433 static const struct comedi_lrange ai_ranges_64xx = {
 434         8, {
 435                 BIP_RANGE(10),
 436                 BIP_RANGE(5),
 437                 BIP_RANGE(2.5),
 438                 BIP_RANGE(1.25),
 439                 UNI_RANGE(10),
 440                 UNI_RANGE(5),
 441                 UNI_RANGE(2.5),
 442                 UNI_RANGE(1.25)
 443         }
 444 };
 445
 446 static const u8 ai_range_code_64xx[8] = {
 447         0x0, 0x1, 0x2, 0x3,     /* bipolar 10, 5, 2,5, 1.25 */
 448         0x8, 0x9, 0xa, 0xb      /* unipolar 10, 5, 2.5, 1.25 */
 449 };
 450
 451 /* analog input ranges for 64-Mx boards */
 452 static const struct comedi_lrange ai_ranges_64_mx = {
 453         7, {
 454                 BIP_RANGE(5),
 455                 BIP_RANGE(2.5),
 456                 BIP_RANGE(1.25),
 457                 BIP_RANGE(0.625),
 458                 UNI_RANGE(5),
 459                 UNI_RANGE(2.5),
 460                 UNI_RANGE(1.25)
 461         }
 462 };
 463
 464 static const u8 ai_range_code_64_mx[7] = {
 465         0x0, 0x1, 0x2, 0x3,     /* bipolar 5, 2.5, 1.25, 0.625 */
 466         0x9, 0xa, 0xb           /* unipolar 5, 2.5, 1.25 */
 467 };
 468
 469 /* analog input ranges for 60xx boards */
 470 static const struct comedi_lrange ai_ranges_60xx = {
 471         4, {
 472                 BIP_RANGE(10),
 473                 BIP_RANGE(5),
 474                 BIP_RANGE(0.5),
 475                 BIP_RANGE(0.05)
 476         }
 477 };
 478
 479 static const u8 ai_range_code_60xx[4] = {
 480         0x0, 0x1, 0x4, 0x7      /* bipolar 10, 5, 0.5, 0.05 */
 481 };
 482
 483 /* analog input ranges for 6030, etc boards */
 484 static const struct comedi_lrange ai_ranges_6030 = {
 485         14, {
 486                 BIP_RANGE(10),
 487                 BIP_RANGE(5),
 488                 BIP_RANGE(2),
 489                 BIP_RANGE(1),
 490                 BIP_RANGE(0.5),
 491                 BIP_RANGE(0.2),
 492                 BIP_RANGE(0.1),
 493                 UNI_RANGE(10),
 494                 UNI_RANGE(5),
 495                 UNI_RANGE(2),
 496                 UNI_RANGE(1),
 497                 UNI_RANGE(0.5),
 498                 UNI_RANGE(0.2),
 499                 UNI_RANGE(0.1)
 500         }
 501 };
 502
 503 static const u8 ai_range_code_6030[14] = {
 504         0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, /* bip 10, 5, 2, 1, 0.5, 0.2, 0.1 */
 505         0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf  /* uni 10, 5, 2, 1, 0.5, 0.2, 0.1 */
 506 };
 507
 508 /* analog input ranges for 6052, etc boards */
 509 static const struct comedi_lrange ai_ranges_6052 = {
 510         15, {
 511                 BIP_RANGE(10),
 512                 BIP_RANGE(5),
 513                 BIP_RANGE(2.5),
 514                 BIP_RANGE(1),
 515                 BIP_RANGE(0.5),
 516                 BIP_RANGE(0.25),
 517                 BIP_RANGE(0.1),
 518                 BIP_RANGE(0.05),
 519                 UNI_RANGE(10),
 520                 UNI_RANGE(5),
 521                 UNI_RANGE(2),
 522                 UNI_RANGE(1),
 523                 UNI_RANGE(0.5),
 524                 UNI_RANGE(0.2),
 525                 UNI_RANGE(0.1)
 526         }
 527 };
 528
 529 static const u8 ai_range_code_6052[15] = {
 530         0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, /* bipolar 10 ... 0.05 */
 531         0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf       /* unipolar 10 ... 0.1 */
 532 };
 533
 534 /* analog input ranges for 4020 board */
 535 static const struct comedi_lrange ai_ranges_4020 = {
 536         2, {
 537                 BIP_RANGE(5),
 538                 BIP_RANGE(1)
 539         }
 540 };
 541
 542 /* analog output ranges */
 543 static const struct comedi_lrange ao_ranges_64xx = {
 544         4, {
 545                 BIP_RANGE(5),
 546                 BIP_RANGE(10),
 547                 UNI_RANGE(5),
 548                 UNI_RANGE(10)
 549         }
 550 };
 551
 552 static const int ao_range_code_64xx[] = {
 553         0x0,
 554         0x1,
 555         0x2,
 556         0x3,
 557 };
 558
 559 static const int ao_range_code_60xx[] = {
 560         0x0,
 561 };
 562
 563 static const struct comedi_lrange ao_ranges_6030 = {
 564         2, {
 565                 BIP_RANGE(10),
 566                 UNI_RANGE(10)
 567         }
 568 };
 569
 570 static const int ao_range_code_6030[] = {
 571         0x0,
 572         0x2,
 573 };
 574
 575 static const struct comedi_lrange ao_ranges_4020 = {
 576         2, {
 577                 BIP_RANGE(5),
 578                 BIP_RANGE(10)
 579         }
 580 };
 581
 582 static const int ao_range_code_4020[] = {
 583         0x1,
 584         0x0,
 585 };
 586
 587 enum register_layout {
 588         LAYOUT_60XX,
 589         LAYOUT_64XX,
 590         LAYOUT_4020,
 591 };
 592
 593 struct hw_fifo_info {
 594         unsigned int num_segments;
 595         unsigned int max_segment_length;
 596         unsigned int sample_packing_ratio;
 597         u16 fifo_size_reg_mask;
 598 };
 599
 600 enum pcidas64_boardid {
 601         BOARD_PCIDAS6402_16,
 602         BOARD_PCIDAS6402_12,
 603         BOARD_PCIDAS64_M1_16,
 604         BOARD_PCIDAS64_M2_16,
 605         BOARD_PCIDAS64_M3_16,
 606         BOARD_PCIDAS6013,
 607         BOARD_PCIDAS6014,
 608         BOARD_PCIDAS6023,
 609         BOARD_PCIDAS6025,
 610         BOARD_PCIDAS6030,
 611         BOARD_PCIDAS6031,
 612         BOARD_PCIDAS6032,
 613         BOARD_PCIDAS6033,
 614         BOARD_PCIDAS6034,
 615         BOARD_PCIDAS6035,
 616         BOARD_PCIDAS6036,
 617         BOARD_PCIDAS6040,
 618         BOARD_PCIDAS6052,
 619         BOARD_PCIDAS6070,
 620         BOARD_PCIDAS6071,
 621         BOARD_PCIDAS4020_12,
 622         BOARD_PCIDAS6402_16_JR,
 623         BOARD_PCIDAS64_M1_16_JR,
 624         BOARD_PCIDAS64_M2_16_JR,
 625         BOARD_PCIDAS64_M3_16_JR,
 626         BOARD_PCIDAS64_M1_14,
 627         BOARD_PCIDAS64_M2_14,
 628         BOARD_PCIDAS64_M3_14,
 629 };
 630
 631 struct pcidas64_board {
 632         const char *name;
 633         int ai_se_chans;        /* number of ai inputs in single-ended mode */
 634         int ai_bits;            /* analog input resolution */
 635         int ai_speed;           /* fastest conversion period in ns */
 636         const struct comedi_lrange *ai_range_table;
 637         const u8 *ai_range_code;
 638         int ao_nchan;           /* number of analog out channels */
 639         int ao_bits;            /* analog output resolution */
 640         int ao_scan_speed;      /* analog output scan speed */
 641         const struct comedi_lrange *ao_range_table;
 642         const int *ao_range_code;
 643         const struct hw_fifo_info *const ai_fifo;
 644         /* different board families have slightly different registers */
 645         enum register_layout layout;
 646         unsigned has_8255:1;
 647 };
 648
 649 static const struct hw_fifo_info ai_fifo_4020 = {
 650         .num_segments = 2,
 651         .max_segment_length = 0x8000,
 652         .sample_packing_ratio = 2,
 653         .fifo_size_reg_mask = 0x7f,
 654 };
 655
 656 static const struct hw_fifo_info ai_fifo_64xx = {
 657         .num_segments = 4,
 658         .max_segment_length = 0x800,
 659         .sample_packing_ratio = 1,
 660         .fifo_size_reg_mask = 0x3f,
 661 };
 662
 663 static const struct hw_fifo_info ai_fifo_60xx = {
 664         .num_segments = 4,
 665         .max_segment_length = 0x800,
 666         .sample_packing_ratio = 1,
 667         .fifo_size_reg_mask = 0x7f,
 668 };
 669
 670 /*
 671  * maximum number of dma transfers we will chain together into a ring
 672  * (and the maximum number of dma buffers we maintain)
 673  */
 674 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
 675 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 676 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 677 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
 678 {
 679         if (board->layout == LAYOUT_4020)
 680                 return MAX_AI_DMA_RING_COUNT;
 681
 682         return MIN_AI_DMA_RING_COUNT;
 683 }
 684
 685 static const int bytes_in_sample = 2;
 686
 687 static const struct pcidas64_board pcidas64_boards[] = {
 688         [BOARD_PCIDAS6402_16] = {
 689                 .name           = "pci-das6402/16",
 690                 .ai_se_chans    = 64,
 691                 .ai_bits        = 16,
 692                 .ai_speed       = 5000,
 693                 .ao_nchan       = 2,
 694                 .ao_bits        = 16,
 695                 .ao_scan_speed  = 10000,
 696                 .layout         = LAYOUT_64XX,
 697                 .ai_range_table = &ai_ranges_64xx,
 698                 .ai_range_code  = ai_range_code_64xx,
 699                 .ao_range_table = &ao_ranges_64xx,
 700                 .ao_range_code  = ao_range_code_64xx,
 701                 .ai_fifo        = &ai_fifo_64xx,
 702                 .has_8255       = 1,
 703         },
 704         [BOARD_PCIDAS6402_12] = {
 705                 .name           = "pci-das6402/12",     /* XXX check */
 706                 .ai_se_chans    = 64,
 707                 .ai_bits        = 12,
 708                 .ai_speed       = 5000,
 709                 .ao_nchan       = 2,
 710                 .ao_bits        = 12,
 711                 .ao_scan_speed  = 10000,
 712                 .layout         = LAYOUT_64XX,
 713                 .ai_range_table = &ai_ranges_64xx,
 714                 .ai_range_code  = ai_range_code_64xx,
 715                 .ao_range_table = &ao_ranges_64xx,
 716                 .ao_range_code  = ao_range_code_64xx,
 717                 .ai_fifo        = &ai_fifo_64xx,
 718                 .has_8255       = 1,
 719         },
 720         [BOARD_PCIDAS64_M1_16] = {
 721                 .name           = "pci-das64/m1/16",
 722                 .ai_se_chans    = 64,
 723                 .ai_bits        = 16,
 724                 .ai_speed       = 1000,
 725                 .ao_nchan       = 2,
 726                 .ao_bits        = 16,
 727                 .ao_scan_speed  = 10000,
 728                 .layout         = LAYOUT_64XX,
 729                 .ai_range_table = &ai_ranges_64_mx,
 730                 .ai_range_code  = ai_range_code_64_mx,
 731                 .ao_range_table = &ao_ranges_64xx,
 732                 .ao_range_code  = ao_range_code_64xx,
 733                 .ai_fifo        = &ai_fifo_64xx,
 734                 .has_8255       = 1,
 735         },
 736         [BOARD_PCIDAS64_M2_16] = {
 737                 .name = "pci-das64/m2/16",
 738                 .ai_se_chans    = 64,
 739                 .ai_bits        = 16,
 740                 .ai_speed       = 500,
 741                 .ao_nchan       = 2,
 742                 .ao_bits        = 16,
 743                 .ao_scan_speed  = 10000,
 744                 .layout         = LAYOUT_64XX,
 745                 .ai_range_table = &ai_ranges_64_mx,
 746                 .ai_range_code  = ai_range_code_64_mx,
 747                 .ao_range_table = &ao_ranges_64xx,
 748                 .ao_range_code  = ao_range_code_64xx,
 749                 .ai_fifo        = &ai_fifo_64xx,
 750                 .has_8255       = 1,
 751         },
 752         [BOARD_PCIDAS64_M3_16] = {
 753                 .name           = "pci-das64/m3/16",
 754                 .ai_se_chans    = 64,
 755                 .ai_bits        = 16,
 756                 .ai_speed       = 333,
 757                 .ao_nchan       = 2,
 758                 .ao_bits        = 16,
 759                 .ao_scan_speed  = 10000,
 760                 .layout         = LAYOUT_64XX,
 761                 .ai_range_table = &ai_ranges_64_mx,
 762                 .ai_range_code  = ai_range_code_64_mx,
 763                 .ao_range_table = &ao_ranges_64xx,
 764                 .ao_range_code  = ao_range_code_64xx,
 765                 .ai_fifo        = &ai_fifo_64xx,
 766                 .has_8255       = 1,
 767         },
 768         [BOARD_PCIDAS6013] = {
 769                 .name           = "pci-das6013",
 770                 .ai_se_chans    = 16,
 771                 .ai_bits        = 16,
 772                 .ai_speed       = 5000,
 773                 .ao_nchan       = 0,
 774                 .ao_bits        = 16,
 775                 .layout         = LAYOUT_60XX,
 776                 .ai_range_table = &ai_ranges_60xx,
 777                 .ai_range_code  = ai_range_code_60xx,
 778                 .ao_range_table = &range_bipolar10,
 779                 .ao_range_code  = ao_range_code_60xx,
 780                 .ai_fifo        = &ai_fifo_60xx,
 781                 .has_8255       = 0,
 782         },
 783         [BOARD_PCIDAS6014] = {
 784                 .name           = "pci-das6014",
 785                 .ai_se_chans    = 16,
 786                 .ai_bits        = 16,
 787                 .ai_speed       = 5000,
 788                 .ao_nchan       = 2,
 789                 .ao_bits        = 16,
 790                 .ao_scan_speed  = 100000,
 791                 .layout         = LAYOUT_60XX,
 792                 .ai_range_table = &ai_ranges_60xx,
 793                 .ai_range_code  = ai_range_code_60xx,
 794                 .ao_range_table = &range_bipolar10,
 795                 .ao_range_code  = ao_range_code_60xx,
 796                 .ai_fifo        = &ai_fifo_60xx,
 797                 .has_8255       = 0,
 798         },
 799         [BOARD_PCIDAS6023] = {
 800                 .name           = "pci-das6023",
 801                 .ai_se_chans    = 16,
 802                 .ai_bits        = 12,
 803                 .ai_speed       = 5000,
 804                 .ao_nchan       = 0,
 805                 .ao_scan_speed  = 100000,
 806                 .layout         = LAYOUT_60XX,
 807                 .ai_range_table = &ai_ranges_60xx,
 808                 .ai_range_code  = ai_range_code_60xx,
 809                 .ao_range_table = &range_bipolar10,
 810                 .ao_range_code  = ao_range_code_60xx,
 811                 .ai_fifo        = &ai_fifo_60xx,
 812                 .has_8255       = 1,
 813         },
 814         [BOARD_PCIDAS6025] = {
 815                 .name           = "pci-das6025",
 816                 .ai_se_chans    = 16,
 817                 .ai_bits        = 12,
 818                 .ai_speed       = 5000,
 819                 .ao_nchan       = 2,
 820                 .ao_bits        = 12,
 821                 .ao_scan_speed  = 100000,
 822                 .layout         = LAYOUT_60XX,
 823                 .ai_range_table = &ai_ranges_60xx,
 824                 .ai_range_code  = ai_range_code_60xx,
 825                 .ao_range_table = &range_bipolar10,
 826                 .ao_range_code  = ao_range_code_60xx,
 827                 .ai_fifo        = &ai_fifo_60xx,
 828                 .has_8255       = 1,
 829         },
 830         [BOARD_PCIDAS6030] = {
 831                 .name           = "pci-das6030",
 832                 .ai_se_chans    = 16,
 833                 .ai_bits        = 16,
 834                 .ai_speed       = 10000,
 835                 .ao_nchan       = 2,
 836                 .ao_bits        = 16,
 837                 .ao_scan_speed  = 10000,
 838                 .layout         = LAYOUT_60XX,
 839                 .ai_range_table = &ai_ranges_6030,
 840                 .ai_range_code  = ai_range_code_6030,
 841                 .ao_range_table = &ao_ranges_6030,
 842                 .ao_range_code  = ao_range_code_6030,
 843                 .ai_fifo        = &ai_fifo_60xx,
 844                 .has_8255       = 0,
 845         },
 846         [BOARD_PCIDAS6031] = {
 847                 .name           = "pci-das6031",
 848                 .ai_se_chans    = 64,
 849                 .ai_bits        = 16,
 850                 .ai_speed       = 10000,
 851                 .ao_nchan       = 2,
 852                 .ao_bits        = 16,
 853                 .ao_scan_speed  = 10000,
 854                 .layout         = LAYOUT_60XX,
 855                 .ai_range_table = &ai_ranges_6030,
 856                 .ai_range_code  = ai_range_code_6030,
 857                 .ao_range_table = &ao_ranges_6030,
 858                 .ao_range_code  = ao_range_code_6030,
 859                 .ai_fifo        = &ai_fifo_60xx,
 860                 .has_8255       = 0,
 861         },
 862         [BOARD_PCIDAS6032] = {
 863                 .name           = "pci-das6032",
 864                 .ai_se_chans    = 16,
 865                 .ai_bits        = 16,
 866                 .ai_speed       = 10000,
 867                 .ao_nchan       = 0,
 868                 .layout         = LAYOUT_60XX,
 869                 .ai_range_table = &ai_ranges_6030,
 870                 .ai_range_code  = ai_range_code_6030,
 871                 .ai_fifo        = &ai_fifo_60xx,
 872                 .has_8255       = 0,
 873         },
 874         [BOARD_PCIDAS6033] = {
 875                 .name           = "pci-das6033",
 876                 .ai_se_chans    = 64,
 877                 .ai_bits        = 16,
 878                 .ai_speed       = 10000,
 879                 .ao_nchan       = 0,
 880                 .layout         = LAYOUT_60XX,
 881                 .ai_range_table = &ai_ranges_6030,
 882                 .ai_range_code  = ai_range_code_6030,
 883                 .ai_fifo        = &ai_fifo_60xx,
 884                 .has_8255       = 0,
 885         },
 886         [BOARD_PCIDAS6034] = {
 887                 .name           = "pci-das6034",
 888                 .ai_se_chans    = 16,
 889                 .ai_bits        = 16,
 890                 .ai_speed       = 5000,
 891                 .ao_nchan       = 0,
 892                 .ao_scan_speed  = 0,
 893                 .layout         = LAYOUT_60XX,
 894                 .ai_range_table = &ai_ranges_60xx,
 895                 .ai_range_code  = ai_range_code_60xx,
 896                 .ai_fifo        = &ai_fifo_60xx,
 897                 .has_8255       = 0,
 898         },
 899         [BOARD_PCIDAS6035] = {
 900                 .name           = "pci-das6035",
 901                 .ai_se_chans    = 16,
 902                 .ai_bits        = 16,
 903                 .ai_speed       = 5000,
 904                 .ao_nchan       = 2,
 905                 .ao_bits        = 12,
 906                 .ao_scan_speed  = 100000,
 907                 .layout         = LAYOUT_60XX,
 908                 .ai_range_table = &ai_ranges_60xx,
 909                 .ai_range_code  = ai_range_code_60xx,
 910                 .ao_range_table = &range_bipolar10,
 911                 .ao_range_code  = ao_range_code_60xx,
 912                 .ai_fifo        = &ai_fifo_60xx,
 913                 .has_8255       = 0,
 914         },
 915         [BOARD_PCIDAS6036] = {
 916                 .name           = "pci-das6036",
 917                 .ai_se_chans    = 16,
 918                 .ai_bits        = 16,
 919                 .ai_speed       = 5000,
 920                 .ao_nchan       = 2,
 921                 .ao_bits        = 16,
 922                 .ao_scan_speed  = 100000,
 923                 .layout         = LAYOUT_60XX,
 924                 .ai_range_table = &ai_ranges_60xx,
 925                 .ai_range_code  = ai_range_code_60xx,
 926                 .ao_range_table = &range_bipolar10,
 927                 .ao_range_code  = ao_range_code_60xx,
 928                 .ai_fifo        = &ai_fifo_60xx,
 929                 .has_8255       = 0,
 930         },
 931         [BOARD_PCIDAS6040] = {
 932                 .name           = "pci-das6040",
 933                 .ai_se_chans    = 16,
 934                 .ai_bits        = 12,
 935                 .ai_speed       = 2000,
 936                 .ao_nchan       = 2,
 937                 .ao_bits        = 12,
 938                 .ao_scan_speed  = 1000,
 939                 .layout         = LAYOUT_60XX,
 940                 .ai_range_table = &ai_ranges_6052,
 941                 .ai_range_code  = ai_range_code_6052,
 942                 .ao_range_table = &ao_ranges_6030,
 943                 .ao_range_code  = ao_range_code_6030,
 944                 .ai_fifo        = &ai_fifo_60xx,
 945                 .has_8255       = 0,
 946         },
 947         [BOARD_PCIDAS6052] = {
 948                 .name           = "pci-das6052",
 949                 .ai_se_chans    = 16,
 950                 .ai_bits        = 16,
 951                 .ai_speed       = 3333,
 952                 .ao_nchan       = 2,
 953                 .ao_bits        = 16,
 954                 .ao_scan_speed  = 3333,
 955                 .layout         = LAYOUT_60XX,
 956                 .ai_range_table = &ai_ranges_6052,
 957                 .ai_range_code  = ai_range_code_6052,
 958                 .ao_range_table = &ao_ranges_6030,
 959                 .ao_range_code  = ao_range_code_6030,
 960                 .ai_fifo        = &ai_fifo_60xx,
 961                 .has_8255       = 0,
 962         },
 963         [BOARD_PCIDAS6070] = {
 964                 .name           = "pci-das6070",
 965                 .ai_se_chans    = 16,
 966                 .ai_bits        = 12,
 967                 .ai_speed       = 800,
 968                 .ao_nchan       = 2,
 969                 .ao_bits        = 12,
 970                 .ao_scan_speed  = 1000,
 971                 .layout         = LAYOUT_60XX,
 972                 .ai_range_table = &ai_ranges_6052,
 973                 .ai_range_code  = ai_range_code_6052,
 974                 .ao_range_table = &ao_ranges_6030,
 975                 .ao_range_code  = ao_range_code_6030,
 976                 .ai_fifo        = &ai_fifo_60xx,
 977                 .has_8255       = 0,
 978         },
 979         [BOARD_PCIDAS6071] = {
 980                 .name           = "pci-das6071",
 981                 .ai_se_chans    = 64,
 982                 .ai_bits        = 12,
 983                 .ai_speed       = 800,
 984                 .ao_nchan       = 2,
 985                 .ao_bits        = 12,
 986                 .ao_scan_speed  = 1000,
 987                 .layout         = LAYOUT_60XX,
 988                 .ai_range_table = &ai_ranges_6052,
 989                 .ai_range_code  = ai_range_code_6052,
 990                 .ao_range_table = &ao_ranges_6030,
 991                 .ao_range_code  = ao_range_code_6030,
 992                 .ai_fifo        = &ai_fifo_60xx,
 993                 .has_8255       = 0,
 994         },
 995         [BOARD_PCIDAS4020_12] = {
 996                 .name           = "pci-das4020/12",
 997                 .ai_se_chans    = 4,
 998                 .ai_bits        = 12,
 999                 .ai_speed       = 50,
1000                 .ao_bits        = 12,
1001                 .ao_nchan       = 2,
1002                 .ao_scan_speed  = 0,    /* no hardware pacing on ao */
1003                 .layout         = LAYOUT_4020,
1004                 .ai_range_table = &ai_ranges_4020,
1005                 .ao_range_table = &ao_ranges_4020,
1006                 .ao_range_code  = ao_range_code_4020,
1007                 .ai_fifo        = &ai_fifo_4020,
1008                 .has_8255       = 1,
1009         },
1010 #if 0
1011         /* The device id for these boards is unknown */
1012
1013         [BOARD_PCIDAS6402_16_JR] = {
1014                 .name           = "pci-das6402/16/jr",
1015                 .ai_se_chans    = 64,
1016                 .ai_bits        = 16,
1017                 .ai_speed       = 5000,
1018                 .ao_nchan       = 0,
1019                 .ao_scan_speed  = 10000,
1020                 .layout         = LAYOUT_64XX,
1021                 .ai_range_table = &ai_ranges_64xx,
1022                 .ai_range_code  = ai_range_code_64xx,
1023                 .ai_fifo        = ai_fifo_64xx,
1024                 .has_8255       = 1,
1025         },
1026         [BOARD_PCIDAS64_M1_16_JR] = {
1027                 .name           = "pci-das64/m1/16/jr",
1028                 .ai_se_chans    = 64,
1029                 .ai_bits        = 16,
1030                 .ai_speed       = 1000,
1031                 .ao_nchan       = 0,
1032                 .ao_scan_speed  = 10000,
1033                 .layout         = LAYOUT_64XX,
1034                 .ai_range_table = &ai_ranges_64_mx,
1035                 .ai_range_code  = ai_range_code_64_mx,
1036                 .ai_fifo        = ai_fifo_64xx,
1037                 .has_8255       = 1,
1038         },
1039         [BOARD_PCIDAS64_M2_16_JR] = {
1040                 .name = "pci-das64/m2/16/jr",
1041                 .ai_se_chans    = 64,
1042                 .ai_bits        = 16,
1043                 .ai_speed       = 500,
1044                 .ao_nchan       = 0,
1045                 .ao_scan_speed  = 10000,
1046                 .layout         = LAYOUT_64XX,
1047                 .ai_range_table = &ai_ranges_64_mx,
1048                 .ai_range_code  = ai_range_code_64_mx,
1049                 .ai_fifo        = ai_fifo_64xx,
1050                 .has_8255       = 1,
1051         },
1052         [BOARD_PCIDAS64_M3_16_JR] = {
1053                 .name           = "pci-das64/m3/16/jr",
1054                 .ai_se_chans    = 64,
1055                 .ai_bits        = 16,
1056                 .ai_speed       = 333,
1057                 .ao_nchan       = 0,
1058                 .ao_scan_speed  = 10000,
1059                 .layout         = LAYOUT_64XX,
1060                 .ai_range_table = &ai_ranges_64_mx,
1061                 .ai_range_code  = ai_range_code_64_mx,
1062                 .ai_fifo        = ai_fifo_64xx,
1063                 .has_8255       = 1,
1064         },
1065         [BOARD_PCIDAS64_M1_14] = {
1066                 .name           = "pci-das64/m1/14",
1067                 .ai_se_chans    = 64,
1068                 .ai_bits        = 14,
1069                 .ai_speed       = 1000,
1070                 .ao_nchan       = 2,
1071                 .ao_scan_speed  = 10000,
1072                 .layout         = LAYOUT_64XX,
1073                 .ai_range_table = &ai_ranges_64_mx,
1074                 .ai_range_code  = ai_range_code_64_mx,
1075                 .ai_fifo        = ai_fifo_64xx,
1076                 .has_8255       = 1,
1077         },
1078         [BOARD_PCIDAS64_M2_14] = {
1079                 .name           = "pci-das64/m2/14",
1080                 .ai_se_chans    = 64,
1081                 .ai_bits        = 14,
1082                 .ai_speed       = 500,
1083                 .ao_nchan       = 2,
1084                 .ao_scan_speed  = 10000,
1085                 .layout         = LAYOUT_64XX,
1086                 .ai_range_table = &ai_ranges_64_mx,
1087                 .ai_range_code  = ai_range_code_64_mx,
1088                 .ai_fifo        = ai_fifo_64xx,
1089                 .has_8255       = 1,
1090         },
1091         [BOARD_PCIDAS64_M3_14] = {
1092                 .name           = "pci-das64/m3/14",
1093                 .ai_se_chans    = 64,
1094                 .ai_bits        = 14,
1095                 .ai_speed       = 333,
1096                 .ao_nchan       = 2,
1097                 .ao_scan_speed  = 10000,
1098                 .layout         = LAYOUT_64XX,
1099                 .ai_range_table = &ai_ranges_64_mx,
1100                 .ai_range_code  = ai_range_code_64_mx,
1101                 .ai_fifo        = ai_fifo_64xx,
1102                 .has_8255       = 1,
1103         },
1104 #endif
1105 };
1106
1107 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1108                                               int use_differential)
1109 {
1110         const struct pcidas64_board *board = dev->board_ptr;
1111
1112         if ((board->layout == LAYOUT_64XX && !use_differential) ||
1113             (board->layout == LAYOUT_60XX && use_differential))
1114                 return ADC_SE_DIFF_BIT;
1115
1116         return 0;
1117 }
1118
1119 struct ext_clock_info {
1120         /* master clock divisor to use for scans with external master clock */
1121         unsigned int divisor;
1122         /* chanspec for master clock input when used as scan begin src */
1123         unsigned int chanspec;
1124 };
1125
1126 /* this structure is for data unique to this hardware driver. */
1127 struct pcidas64_private {
1128         /* base addresses (physical) */
1129         resource_size_t main_phys_iobase;
1130         resource_size_t dio_counter_phys_iobase;
1131         /* base addresses (ioremapped) */
1132         void __iomem *plx9080_iobase;
1133         void __iomem *main_iobase;
1134         /* local address (used by dma controller) */
1135         u32 local0_iobase;
1136         u32 local1_iobase;
1137         /* dma buffers for analog input */
1138         u16 *ai_buffer[MAX_AI_DMA_RING_COUNT];
1139         /* physical addresses of ai dma buffers */
1140         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1141         /*
1142          * array of ai dma descriptors read by plx9080,
1143          * allocated to get proper alignment
1144          */
1145         struct plx_dma_desc *ai_dma_desc;
1146         /* physical address of ai dma descriptor array */
1147         dma_addr_t ai_dma_desc_bus_addr;
1148         /*
1149          * index of the ai dma descriptor/buffer
1150          * that is currently being used
1151          */
1152         unsigned int ai_dma_index;
1153         /* dma buffers for analog output */
1154         u16 *ao_buffer[AO_DMA_RING_COUNT];
1155         /* physical addresses of ao dma buffers */
1156         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1157         struct plx_dma_desc *ao_dma_desc;
1158         dma_addr_t ao_dma_desc_bus_addr;
1159         /* keeps track of buffer where the next ao sample should go */
1160         unsigned int ao_dma_index;
1161         unsigned int hw_revision;       /* stc chip hardware revision number */
1162         /* last bits sent to INTR_ENABLE_REG register */
1163         unsigned int intr_enable_bits;
1164         /* last bits sent to ADC_CONTROL1_REG register */
1165         u16 adc_control1_bits;
1166         /* last bits sent to FIFO_SIZE_REG register */
1167         u16 fifo_size_bits;
1168         /* last bits sent to HW_CONFIG_REG register */
1169         u16 hw_config_bits;
1170         u16 dac_control1_bits;
1171         /* last bits written to plx9080 control register */
1172         u32 plx_control_bits;
1173         /* last bits written to plx interrupt control and status register */
1174         u32 plx_intcsr_bits;
1175         /* index of calibration source readable through ai ch0 */
1176         int calibration_source;
1177         /* bits written to i2c calibration/range register */
1178         u8 i2c_cal_range_bits;
1179         /* configure digital triggers to trigger on falling edge */
1180         unsigned int ext_trig_falling;
1181         short ai_cmd_running;
1182         unsigned int ai_fifo_segment_length;
1183         struct ext_clock_info ext_clock;
1184         unsigned short ao_bounce_buffer[DAC_FIFO_SIZE];
1185 };
1186
1187 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1188                                        unsigned int range_index)
1189 {
1190         const struct pcidas64_board *board = dev->board_ptr;
1191
1192         return board->ai_range_code[range_index] << 8;
1193 }
1194
1195 static unsigned int hw_revision(const struct comedi_device *dev,
1196                                 u16 hw_status_bits)
1197 {
1198         const struct pcidas64_board *board = dev->board_ptr;
1199
1200         if (board->layout == LAYOUT_4020)
1201                 return (hw_status_bits >> 13) & 0x7;
1202
1203         return (hw_status_bits >> 12) & 0xf;
1204 }
1205
1206 static void set_dac_range_bits(struct comedi_device *dev,
1207                                u16 *bits, unsigned int channel,
1208                                unsigned int range)
1209 {
1210         const struct pcidas64_board *board = dev->board_ptr;
1211         unsigned int code = board->ao_range_code[range];
1212
1213         if (channel > 1)
1214                 dev_err(dev->class_dev, "bug! bad channel?\n");
1215         if (code & ~0x3)
1216                 dev_err(dev->class_dev, "bug! bad range code?\n");
1217
1218         *bits &= ~(0x3 << (2 * channel));
1219         *bits |= code << (2 * channel);
1220 };
1221
1222 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1223 {
1224         return board->ao_nchan && board->layout != LAYOUT_4020;
1225 }
1226
1227 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1228 {
1229         struct pcidas64_private *devpriv = dev->private;
1230         unsigned long flags;
1231
1232         /* spinlock for plx dma control/status reg */
1233         spin_lock_irqsave(&dev->spinlock, flags);
1234
1235         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1236
1237         spin_unlock_irqrestore(&dev->spinlock, flags);
1238 }
1239
1240 static void disable_plx_interrupts(struct comedi_device *dev)
1241 {
1242         struct pcidas64_private *devpriv = dev->private;
1243
1244         devpriv->plx_intcsr_bits = 0;
1245         writel(devpriv->plx_intcsr_bits,
1246                devpriv->plx9080_iobase + PLX_REG_INTCSR);
1247 }
1248
1249 static void disable_ai_interrupts(struct comedi_device *dev)
1250 {
1251         struct pcidas64_private *devpriv = dev->private;
1252         unsigned long flags;
1253
1254         spin_lock_irqsave(&dev->spinlock, flags);
1255         devpriv->intr_enable_bits &=
1256                 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1257                 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1258                 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1259         writew(devpriv->intr_enable_bits,
1260                devpriv->main_iobase + INTR_ENABLE_REG);
1261         spin_unlock_irqrestore(&dev->spinlock, flags);
1262 }
1263
1264 static void enable_ai_interrupts(struct comedi_device *dev,
1265                                  const struct comedi_cmd *cmd)
1266 {
1267         const struct pcidas64_board *board = dev->board_ptr;
1268         struct pcidas64_private *devpriv = dev->private;
1269         u32 bits;
1270         unsigned long flags;
1271
1272         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1273                EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1274         /*
1275          * Use pio transfer and interrupt on end of conversion
1276          * if CMDF_WAKE_EOS flag is set.
1277          */
1278         if (cmd->flags & CMDF_WAKE_EOS) {
1279                 /* 4020 doesn't support pio transfers except for fifo dregs */
1280                 if (board->layout != LAYOUT_4020)
1281                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1282         }
1283         spin_lock_irqsave(&dev->spinlock, flags);
1284         devpriv->intr_enable_bits |= bits;
1285         writew(devpriv->intr_enable_bits,
1286                devpriv->main_iobase + INTR_ENABLE_REG);
1287         spin_unlock_irqrestore(&dev->spinlock, flags);
1288 }
1289
1290 /* initialize plx9080 chip */
1291 static void init_plx9080(struct comedi_device *dev)
1292 {
1293         const struct pcidas64_board *board = dev->board_ptr;
1294         struct pcidas64_private *devpriv = dev->private;
1295         u32 bits;
1296         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1297
1298         devpriv->plx_control_bits =
1299                 readl(devpriv->plx9080_iobase + PLX_REG_CNTRL);
1300
1301 #ifdef __BIG_ENDIAN
1302         bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1;
1303 #else
1304         bits = 0;
1305 #endif
1306         writel(bits, devpriv->plx9080_iobase + PLX_REG_BIGEND);
1307
1308         disable_plx_interrupts(dev);
1309
1310         abort_dma(dev, 0);
1311         abort_dma(dev, 1);
1312
1313         /* configure dma0 mode */
1314         bits = 0;
1315         /* enable ready input, not sure if this is necessary */
1316         bits |= PLX_DMAMODE_READYIEN;
1317         /* enable bterm, not sure if this is necessary */
1318         bits |= PLX_DMAMODE_BTERMIEN;
1319         /* enable dma chaining */
1320         bits |= PLX_DMAMODE_CHAINEN;
1321         /*
1322          * enable interrupt on dma done
1323          * (probably don't need this, since chain never finishes)
1324          */
1325         bits |= PLX_DMAMODE_DONEIEN;
1326         /*
1327          * don't increment local address during transfers
1328          * (we are transferring from a fixed fifo register)
1329          */
1330         bits |= PLX_DMAMODE_LACONST;
1331         /* route dma interrupt to pci bus */
1332         bits |= PLX_DMAMODE_INTRPCI;
1333         /* enable demand mode */
1334         bits |= PLX_DMAMODE_DEMAND;
1335         /* enable local burst mode */
1336         bits |= PLX_DMAMODE_BURSTEN;
1337         /* 4020 uses 32 bit dma */
1338         if (board->layout == LAYOUT_4020)
1339                 bits |= PLX_DMAMODE_WIDTH_32;
1340         else                            /* localspace0 bus is 16 bits wide */
1341                 bits |= PLX_DMAMODE_WIDTH_16;
1342         writel(bits, plx_iobase + PLX_REG_DMAMODE1);
1343         if (ao_cmd_is_supported(board))
1344                 writel(bits, plx_iobase + PLX_REG_DMAMODE0);
1345
1346         /* enable interrupts on plx 9080 */
1347         devpriv->plx_intcsr_bits |=
1348             PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN |
1349             PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN |
1350             PLX_INTCSR_DMA0IEN | PLX_INTCSR_DMA1IEN;
1351         writel(devpriv->plx_intcsr_bits,
1352                devpriv->plx9080_iobase + PLX_REG_INTCSR);
1353 }
1354
1355 static void disable_ai_pacing(struct comedi_device *dev)
1356 {
1357         struct pcidas64_private *devpriv = dev->private;
1358         unsigned long flags;
1359
1360         disable_ai_interrupts(dev);
1361
1362         spin_lock_irqsave(&dev->spinlock, flags);
1363         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1364         writew(devpriv->adc_control1_bits,
1365                devpriv->main_iobase + ADC_CONTROL1_REG);
1366         spin_unlock_irqrestore(&dev->spinlock, flags);
1367
1368         /* disable pacing, triggering, etc */
1369         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1370                devpriv->main_iobase + ADC_CONTROL0_REG);
1371 }
1372
1373 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1374                                       unsigned int num_entries)
1375 {
1376         const struct pcidas64_board *board = dev->board_ptr;
1377         struct pcidas64_private *devpriv = dev->private;
1378         static const int increment_size = 0x100;
1379         const struct hw_fifo_info *const fifo = board->ai_fifo;
1380         unsigned int num_increments;
1381         u16 bits;
1382
1383         if (num_entries < increment_size)
1384                 num_entries = increment_size;
1385         if (num_entries > fifo->max_segment_length)
1386                 num_entries = fifo->max_segment_length;
1387
1388         /* 1 == 256 entries, 2 == 512 entries, etc */
1389         num_increments = DIV_ROUND_CLOSEST(num_entries, increment_size);
1390
1391         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1392         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1393         devpriv->fifo_size_bits |= bits;
1394         writew(devpriv->fifo_size_bits,
1395                devpriv->main_iobase + FIFO_SIZE_REG);
1396
1397         devpriv->ai_fifo_segment_length = num_increments * increment_size;
1398
1399         return devpriv->ai_fifo_segment_length;
1400 }
1401
1402 /*
1403  * adjusts the size of hardware fifo (which determines block size for dma xfers)
1404  */
1405 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1406 {
1407         const struct pcidas64_board *board = dev->board_ptr;
1408         unsigned int num_fifo_entries;
1409         int retval;
1410         const struct hw_fifo_info *const fifo = board->ai_fifo;
1411
1412         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1413
1414         retval = set_ai_fifo_segment_length(dev,
1415                                             num_fifo_entries /
1416                                             fifo->num_segments);
1417         if (retval < 0)
1418                 return retval;
1419
1420         return retval * fifo->num_segments * fifo->sample_packing_ratio;
1421 }
1422
1423 /* query length of fifo */
1424 static unsigned int ai_fifo_size(struct comedi_device *dev)
1425 {
1426         const struct pcidas64_board *board = dev->board_ptr;
1427         struct pcidas64_private *devpriv = dev->private;
1428
1429         return devpriv->ai_fifo_segment_length *
1430                board->ai_fifo->num_segments *
1431                board->ai_fifo->sample_packing_ratio;
1432 }
1433
1434 static void init_stc_registers(struct comedi_device *dev)
1435 {
1436         const struct pcidas64_board *board = dev->board_ptr;
1437         struct pcidas64_private *devpriv = dev->private;
1438         u16 bits;
1439         unsigned long flags;
1440
1441         spin_lock_irqsave(&dev->spinlock, flags);
1442
1443         /*
1444          * bit should be set for 6025,
1445          * although docs say boards with <= 16 chans should be cleared XXX
1446          */
1447         if (1)
1448                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1449         writew(devpriv->adc_control1_bits,
1450                devpriv->main_iobase + ADC_CONTROL1_REG);
1451
1452         /* 6402/16 manual says this register must be initialized to 0xff? */
1453         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1454
1455         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1456         if (board->layout == LAYOUT_4020)
1457                 bits |= INTERNAL_CLOCK_4020_BITS;
1458         devpriv->hw_config_bits |= bits;
1459         writew(devpriv->hw_config_bits,
1460                devpriv->main_iobase + HW_CONFIG_REG);
1461
1462         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1463         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1464
1465         spin_unlock_irqrestore(&dev->spinlock, flags);
1466
1467         /* set fifos to maximum size */
1468         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1469         set_ai_fifo_segment_length(dev, board->ai_fifo->max_segment_length);
1470
1471         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1472         devpriv->intr_enable_bits =
1473                 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1474                 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1475         writew(devpriv->intr_enable_bits,
1476                devpriv->main_iobase + INTR_ENABLE_REG);
1477
1478         disable_ai_pacing(dev);
1479 };
1480
1481 static int alloc_and_init_dma_members(struct comedi_device *dev)
1482 {
1483         const struct pcidas64_board *board = dev->board_ptr;
1484         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1485         struct pcidas64_private *devpriv = dev->private;
1486         int i;
1487
1488         /* allocate pci dma buffers */
1489         for (i = 0; i < ai_dma_ring_count(board); i++) {
1490                 devpriv->ai_buffer[i] =
1491                         dma_alloc_coherent(&pcidev->dev, DMA_BUFFER_SIZE,
1492                                            &devpriv->ai_buffer_bus_addr[i],
1493                                            GFP_KERNEL);
1494                 if (!devpriv->ai_buffer[i])
1495                         return -ENOMEM;
1496         }
1497         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1498                 if (ao_cmd_is_supported(board)) {
1499                         devpriv->ao_buffer[i] =
1500                                 dma_alloc_coherent(&pcidev->dev,
1501                                                    DMA_BUFFER_SIZE,
1502                                                    &devpriv->
1503                                                    ao_buffer_bus_addr[i],
1504                                                    GFP_KERNEL);
1505                         if (!devpriv->ao_buffer[i])
1506                                 return -ENOMEM;
1507                 }
1508         }
1509         /* allocate dma descriptors */
1510         devpriv->ai_dma_desc =
1511                 dma_alloc_coherent(&pcidev->dev, sizeof(struct plx_dma_desc) *
1512                                    ai_dma_ring_count(board),
1513                                    &devpriv->ai_dma_desc_bus_addr, GFP_KERNEL);
1514         if (!devpriv->ai_dma_desc)
1515                 return -ENOMEM;
1516
1517         if (ao_cmd_is_supported(board)) {
1518                 devpriv->ao_dma_desc =
1519                         dma_alloc_coherent(&pcidev->dev,
1520                                            sizeof(struct plx_dma_desc) *
1521                                            AO_DMA_RING_COUNT,
1522                                            &devpriv->ao_dma_desc_bus_addr,
1523                                            GFP_KERNEL);
1524                 if (!devpriv->ao_dma_desc)
1525                         return -ENOMEM;
1526         }
1527         /* initialize dma descriptors */
1528         for (i = 0; i < ai_dma_ring_count(board); i++) {
1529                 devpriv->ai_dma_desc[i].pci_start_addr =
1530                         cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1531                 if (board->layout == LAYOUT_4020)
1532                         devpriv->ai_dma_desc[i].local_start_addr =
1533                                 cpu_to_le32(devpriv->local1_iobase +
1534                                             ADC_FIFO_REG);
1535                 else
1536                         devpriv->ai_dma_desc[i].local_start_addr =
1537                                 cpu_to_le32(devpriv->local0_iobase +
1538                                             ADC_FIFO_REG);
1539                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1540                 devpriv->ai_dma_desc[i].next =
1541                         cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1542                                      ((i + 1) % ai_dma_ring_count(board)) *
1543                                      sizeof(devpriv->ai_dma_desc[0])) |
1544                                     PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR |
1545                                     PLX_DMADPR_XFERL2P);
1546         }
1547         if (ao_cmd_is_supported(board)) {
1548                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1549                         devpriv->ao_dma_desc[i].pci_start_addr =
1550                                 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1551                         devpriv->ao_dma_desc[i].local_start_addr =
1552                                 cpu_to_le32(devpriv->local0_iobase +
1553                                             DAC_FIFO_REG);
1554                         devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1555                         devpriv->ao_dma_desc[i].next =
1556                                 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1557                                              ((i + 1) % (AO_DMA_RING_COUNT)) *
1558                                              sizeof(devpriv->ao_dma_desc[0])) |
1559                                             PLX_DMADPR_DESCPCI |
1560                                             PLX_DMADPR_TCINTR);
1561                 }
1562         }
1563         return 0;
1564 }
1565
1566 static void cb_pcidas64_free_dma(struct comedi_device *dev)
1567 {
1568         const struct pcidas64_board *board = dev->board_ptr;
1569         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1570         struct pcidas64_private *devpriv = dev->private;
1571         int i;
1572
1573         if (!devpriv)
1574                 return;
1575
1576         /* free pci dma buffers */
1577         for (i = 0; i < ai_dma_ring_count(board); i++) {
1578                 if (devpriv->ai_buffer[i])
1579                         dma_free_coherent(&pcidev->dev,
1580                                           DMA_BUFFER_SIZE,
1581                                           devpriv->ai_buffer[i],
1582                                           devpriv->ai_buffer_bus_addr[i]);
1583         }
1584         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1585                 if (devpriv->ao_buffer[i])
1586                         dma_free_coherent(&pcidev->dev,
1587                                           DMA_BUFFER_SIZE,
1588                                           devpriv->ao_buffer[i],
1589                                           devpriv->ao_buffer_bus_addr[i]);
1590         }
1591         /* free dma descriptors */
1592         if (devpriv->ai_dma_desc)
1593                 dma_free_coherent(&pcidev->dev,
1594                                   sizeof(struct plx_dma_desc) *
1595                                   ai_dma_ring_count(board),
1596                                   devpriv->ai_dma_desc,
1597                                   devpriv->ai_dma_desc_bus_addr);
1598         if (devpriv->ao_dma_desc)
1599                 dma_free_coherent(&pcidev->dev,
1600                                   sizeof(struct plx_dma_desc) *
1601                                   AO_DMA_RING_COUNT,
1602                                   devpriv->ao_dma_desc,
1603                                   devpriv->ao_dma_desc_bus_addr);
1604 }
1605
1606 static inline void warn_external_queue(struct comedi_device *dev)
1607 {
1608         dev_err(dev->class_dev,
1609                 "AO command and AI external channel queue cannot be used simultaneously\n");
1610         dev_err(dev->class_dev,
1611                 "Use internal AI channel queue (channels must be consecutive and use same range/aref)\n");
1612 }
1613
1614 /*
1615  * their i2c requires a huge delay on setting clock or data high for some reason
1616  */
1617 static const int i2c_high_udelay = 1000;
1618 static const int i2c_low_udelay = 10;
1619
1620 /* set i2c data line high or low */
1621 static void i2c_set_sda(struct comedi_device *dev, int state)
1622 {
1623         struct pcidas64_private *devpriv = dev->private;
1624         static const int data_bit = PLX_CNTRL_EEWB;
1625         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1626                                          PLX_REG_CNTRL;
1627
1628         if (state) {                            /* set data line high */
1629                 devpriv->plx_control_bits &= ~data_bit;
1630                 writel(devpriv->plx_control_bits, plx_control_addr);
1631                 udelay(i2c_high_udelay);
1632         } else {                                /* set data line low */
1633                 devpriv->plx_control_bits |= data_bit;
1634                 writel(devpriv->plx_control_bits, plx_control_addr);
1635                 udelay(i2c_low_udelay);
1636         }
1637 }
1638
1639 /* set i2c clock line high or low */
1640 static void i2c_set_scl(struct comedi_device *dev, int state)
1641 {
1642         struct pcidas64_private *devpriv = dev->private;
1643         static const int clock_bit = PLX_CNTRL_USERO;
1644         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1645                                          PLX_REG_CNTRL;
1646
1647         if (state) {                            /* set clock line high */
1648                 devpriv->plx_control_bits &= ~clock_bit;
1649                 writel(devpriv->plx_control_bits, plx_control_addr);
1650                 udelay(i2c_high_udelay);
1651         } else {                                /* set clock line low */
1652                 devpriv->plx_control_bits |= clock_bit;
1653                 writel(devpriv->plx_control_bits, plx_control_addr);
1654                 udelay(i2c_low_udelay);
1655         }
1656 }
1657
1658 static void i2c_write_byte(struct comedi_device *dev, u8 byte)
1659 {
1660         u8 bit;
1661         unsigned int num_bits = 8;
1662
1663         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1664                 i2c_set_scl(dev, 0);
1665                 if ((byte & bit))
1666                         i2c_set_sda(dev, 1);
1667                 else
1668                         i2c_set_sda(dev, 0);
1669                 i2c_set_scl(dev, 1);
1670         }
1671 }
1672
1673 /* we can't really read the lines, so fake it */
1674 static int i2c_read_ack(struct comedi_device *dev)
1675 {
1676         i2c_set_scl(dev, 0);
1677         i2c_set_sda(dev, 1);
1678         i2c_set_scl(dev, 1);
1679
1680         return 0;               /* return fake acknowledge bit */
1681 }
1682
1683 /* send start bit */
1684 static void i2c_start(struct comedi_device *dev)
1685 {
1686         i2c_set_scl(dev, 1);
1687         i2c_set_sda(dev, 1);
1688         i2c_set_sda(dev, 0);
1689 }
1690
1691 /* send stop bit */
1692 static void i2c_stop(struct comedi_device *dev)
1693 {
1694         i2c_set_scl(dev, 0);
1695         i2c_set_sda(dev, 0);
1696         i2c_set_scl(dev, 1);
1697         i2c_set_sda(dev, 1);
1698 }
1699
1700 static void i2c_write(struct comedi_device *dev, unsigned int address,
1701                       const u8 *data, unsigned int length)
1702 {
1703         struct pcidas64_private *devpriv = dev->private;
1704         unsigned int i;
1705         u8 bitstream;
1706         static const int read_bit = 0x1;
1707
1708         /*
1709          * XXX need mutex to prevent simultaneous attempts to access
1710          * eeprom and i2c bus
1711          */
1712
1713         /* make sure we dont send anything to eeprom */
1714         devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;
1715
1716         i2c_stop(dev);
1717         i2c_start(dev);
1718
1719         /* send address and write bit */
1720         bitstream = (address << 1) & ~read_bit;
1721         i2c_write_byte(dev, bitstream);
1722
1723         /* get acknowledge */
1724         if (i2c_read_ack(dev) != 0) {
1725                 dev_err(dev->class_dev, "failed: no acknowledge\n");
1726                 i2c_stop(dev);
1727                 return;
1728         }
1729         /* write data bytes */
1730         for (i = 0; i < length; i++) {
1731                 i2c_write_byte(dev, data[i]);
1732                 if (i2c_read_ack(dev) != 0) {
1733                         dev_err(dev->class_dev, "failed: no acknowledge\n");
1734                         i2c_stop(dev);
1735                         return;
1736                 }
1737         }
1738         i2c_stop(dev);
1739 }
1740
1741 static int cb_pcidas64_ai_eoc(struct comedi_device *dev,
1742                               struct comedi_subdevice *s,
1743                               struct comedi_insn *insn,
1744                               unsigned long context)
1745 {
1746         const struct pcidas64_board *board = dev->board_ptr;
1747         struct pcidas64_private *devpriv = dev->private;
1748         unsigned int status;
1749
1750         status = readw(devpriv->main_iobase + HW_STATUS_REG);
1751         if (board->layout == LAYOUT_4020) {
1752                 status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG);
1753                 if (status)
1754                         return 0;
1755         } else {
1756                 if (pipe_full_bits(status))
1757                         return 0;
1758         }
1759         return -EBUSY;
1760 }
1761
1762 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1763                     struct comedi_insn *insn, unsigned int *data)
1764 {
1765         const struct pcidas64_board *board = dev->board_ptr;
1766         struct pcidas64_private *devpriv = dev->private;
1767         unsigned int bits = 0, n;
1768         unsigned int channel, range, aref;
1769         unsigned long flags;
1770         int ret;
1771
1772         channel = CR_CHAN(insn->chanspec);
1773         range = CR_RANGE(insn->chanspec);
1774         aref = CR_AREF(insn->chanspec);
1775
1776         /* disable card's analog input interrupt sources and pacing */
1777         /* 4020 generates dac done interrupts even though they are disabled */
1778         disable_ai_pacing(dev);
1779
1780         spin_lock_irqsave(&dev->spinlock, flags);
1781         if (insn->chanspec & CR_ALT_FILTER)
1782                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1783         else
1784                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1785         writew(devpriv->adc_control1_bits,
1786                devpriv->main_iobase + ADC_CONTROL1_REG);
1787         spin_unlock_irqrestore(&dev->spinlock, flags);
1788
1789         if (board->layout != LAYOUT_4020) {
1790                 /* use internal queue */
1791                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1792                 writew(devpriv->hw_config_bits,
1793                        devpriv->main_iobase + HW_CONFIG_REG);
1794
1795                 /* ALT_SOURCE is internal calibration reference */
1796                 if (insn->chanspec & CR_ALT_SOURCE) {
1797                         unsigned int cal_en_bit;
1798
1799                         if (board->layout == LAYOUT_60XX)
1800                                 cal_en_bit = CAL_EN_60XX_BIT;
1801                         else
1802                                 cal_en_bit = CAL_EN_64XX_BIT;
1803                         /*
1804                          * select internal reference source to connect
1805                          * to channel 0
1806                          */
1807                         writew(cal_en_bit |
1808                                adc_src_bits(devpriv->calibration_source),
1809                                devpriv->main_iobase + CALIBRATION_REG);
1810                 } else {
1811                         /*
1812                          * make sure internal calibration source
1813                          * is turned off
1814                          */
1815                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1816                 }
1817                 /* load internal queue */
1818                 bits = 0;
1819                 /* set gain */
1820                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1821                 /* set single-ended / differential */
1822                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1823                 if (aref == AREF_COMMON)
1824                         bits |= ADC_COMMON_BIT;
1825                 bits |= adc_chan_bits(channel);
1826                 /* set stop channel */
1827                 writew(adc_chan_bits(channel),
1828                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1829                 /* set start channel, and rest of settings */
1830                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1831         } else {
1832                 u8 old_cal_range_bits = devpriv->i2c_cal_range_bits;
1833
1834                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1835                 if (insn->chanspec & CR_ALT_SOURCE) {
1836                         devpriv->i2c_cal_range_bits |=
1837                                 adc_src_4020_bits(devpriv->calibration_source);
1838                 } else {        /* select BNC inputs */
1839                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1840                 }
1841                 /* select range */
1842                 if (range == 0)
1843                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1844                 else
1845                         devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1846                 /*
1847                  * update calibration/range i2c register only if necessary,
1848                  * as it is very slow
1849                  */
1850                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1851                         u8 i2c_data = devpriv->i2c_cal_range_bits;
1852
1853                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1854                                   sizeof(i2c_data));
1855                 }
1856
1857                 /*
1858                  * 4020 manual asks that sample interval register to be set
1859                  * before writing to convert register.
1860                  * Using somewhat arbitrary setting of 4 master clock ticks
1861                  * = 0.1 usec
1862                  */
1863                 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1864                 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1865         }
1866
1867         for (n = 0; n < insn->n; n++) {
1868                 /* clear adc buffer (inside loop for 4020 sake) */
1869                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1870
1871                 /* trigger conversion, bits sent only matter for 4020 */
1872                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1873                        devpriv->main_iobase + ADC_CONVERT_REG);
1874
1875                 /* wait for data */
1876                 ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0);
1877                 if (ret)
1878                         return ret;
1879
1880                 if (board->layout == LAYOUT_4020)
1881                         data[n] = readl(dev->mmio + ADC_FIFO_REG) & 0xffff;
1882                 else
1883                         data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1884         }
1885
1886         return n;
1887 }
1888
1889 static int ai_config_calibration_source(struct comedi_device *dev,
1890                                         unsigned int *data)
1891 {
1892         const struct pcidas64_board *board = dev->board_ptr;
1893         struct pcidas64_private *devpriv = dev->private;
1894         unsigned int source = data[1];
1895         int num_calibration_sources;
1896
1897         if (board->layout == LAYOUT_60XX)
1898                 num_calibration_sources = 16;
1899         else
1900                 num_calibration_sources = 8;
1901         if (source >= num_calibration_sources) {
1902                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1903                         source);
1904                 return -EINVAL;
1905         }
1906
1907         devpriv->calibration_source = source;
1908
1909         return 2;
1910 }
1911
1912 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1913 {
1914         const struct pcidas64_board *board = dev->board_ptr;
1915         int fifo_size;
1916         const struct hw_fifo_info *const fifo = board->ai_fifo;
1917         unsigned int block_size, requested_block_size;
1918         int retval;
1919
1920         requested_block_size = data[1];
1921
1922         if (requested_block_size) {
1923                 fifo_size = requested_block_size * fifo->num_segments /
1924                             bytes_in_sample;
1925
1926                 retval = set_ai_fifo_size(dev, fifo_size);
1927                 if (retval < 0)
1928                         return retval;
1929         }
1930
1931         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1932
1933         data[1] = block_size;
1934
1935         return 2;
1936 }
1937
1938 static int ai_config_master_clock_4020(struct comedi_device *dev,
1939                                        unsigned int *data)
1940 {
1941         struct pcidas64_private *devpriv = dev->private;
1942         unsigned int divisor = data[4];
1943         int retval = 0;
1944
1945         if (divisor < 2) {
1946                 divisor = 2;
1947                 retval = -EAGAIN;
1948         }
1949
1950         switch (data[1]) {
1951         case COMEDI_EV_SCAN_BEGIN:
1952                 devpriv->ext_clock.divisor = divisor;
1953                 devpriv->ext_clock.chanspec = data[2];
1954                 break;
1955         default:
1956                 return -EINVAL;
1957         }
1958
1959         data[4] = divisor;
1960
1961         return retval ? retval : 5;
1962 }
1963
1964 /* XXX could add support for 60xx series */
1965 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1966 {
1967         const struct pcidas64_board *board = dev->board_ptr;
1968
1969         switch (board->layout) {
1970         case LAYOUT_4020:
1971                 return ai_config_master_clock_4020(dev, data);
1972         default:
1973                 return -EINVAL;
1974         }
1975
1976         return -EINVAL;
1977 }
1978
1979 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1980                           struct comedi_insn *insn, unsigned int *data)
1981 {
1982         int id = data[0];
1983
1984         switch (id) {
1985         case INSN_CONFIG_ALT_SOURCE:
1986                 return ai_config_calibration_source(dev, data);
1987         case INSN_CONFIG_BLOCK_SIZE:
1988                 return ai_config_block_size(dev, data);
1989         case INSN_CONFIG_TIMER_1:
1990                 return ai_config_master_clock(dev, data);
1991         default:
1992                 return -EINVAL;
1993         }
1994         return -EINVAL;
1995 }
1996
1997 /*
1998  * Gets nearest achievable timing given master clock speed, does not
1999  * take into account possible minimum/maximum divisor values.  Used
2000  * by other timing checking functions.
2001  */
2002 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
2003 {
2004         unsigned int divisor;
2005
2006         switch (flags & CMDF_ROUND_MASK) {
2007         case CMDF_ROUND_UP:
2008                 divisor = DIV_ROUND_UP(ns, TIMER_BASE);
2009                 break;
2010         case CMDF_ROUND_DOWN:
2011                 divisor = ns / TIMER_BASE;
2012                 break;
2013         case CMDF_ROUND_NEAREST:
2014         default:
2015                 divisor = DIV_ROUND_CLOSEST(ns, TIMER_BASE);
2016                 break;
2017         }
2018         return divisor;
2019 }
2020
2021 /*
2022  * utility function that rounds desired timing to an achievable time, and
2023  * sets cmd members appropriately.
2024  * adc paces conversions from master clock by dividing by (x + 3) where x is
2025  * 24 bit number
2026  */
2027 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
2028 {
2029         const struct pcidas64_board *board = dev->board_ptr;
2030         unsigned long long convert_divisor = 0;
2031         unsigned int scan_divisor;
2032         static const int min_convert_divisor = 3;
2033         static const int max_convert_divisor =
2034                 max_counter_value + min_convert_divisor;
2035         static const int min_scan_divisor_4020 = 2;
2036         unsigned long long max_scan_divisor, min_scan_divisor;
2037
2038         if (cmd->convert_src == TRIG_TIMER) {
2039                 if (board->layout == LAYOUT_4020) {
2040                         cmd->convert_arg = 0;
2041                 } else {
2042                         convert_divisor = get_divisor(cmd->convert_arg,
2043                                                       cmd->flags);
2044                         if (convert_divisor > max_convert_divisor)
2045                                 convert_divisor = max_convert_divisor;
2046                         if (convert_divisor < min_convert_divisor)
2047                                 convert_divisor = min_convert_divisor;
2048                         cmd->convert_arg = convert_divisor * TIMER_BASE;
2049                 }
2050         } else if (cmd->convert_src == TRIG_NOW) {
2051                 cmd->convert_arg = 0;
2052         }
2053
2054         if (cmd->scan_begin_src == TRIG_TIMER) {
2055                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2056                 if (cmd->convert_src == TRIG_TIMER) {
2057                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
2058                         max_scan_divisor =
2059                                 (convert_divisor * cmd->chanlist_len - 1) +
2060                                 max_counter_value;
2061                 } else {
2062                         min_scan_divisor = min_scan_divisor_4020;
2063                         max_scan_divisor = max_counter_value + min_scan_divisor;
2064                 }
2065                 if (scan_divisor > max_scan_divisor)
2066                         scan_divisor = max_scan_divisor;
2067                 if (scan_divisor < min_scan_divisor)
2068                         scan_divisor = min_scan_divisor;
2069                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2070         }
2071 }
2072
2073 static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev,
2074                                          struct comedi_subdevice *s,
2075                                          struct comedi_cmd *cmd)
2076 {
2077         const struct pcidas64_board *board = dev->board_ptr;
2078         unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
2079         int i;
2080
2081         for (i = 1; i < cmd->chanlist_len; i++) {
2082                 unsigned int aref = CR_AREF(cmd->chanlist[i]);
2083
2084                 if (aref != aref0) {
2085                         dev_dbg(dev->class_dev,
2086                                 "all elements in chanlist must use the same analog reference\n");
2087                         return -EINVAL;
2088                 }
2089         }
2090
2091         if (board->layout == LAYOUT_4020) {
2092                 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
2093
2094                 for (i = 1; i < cmd->chanlist_len; i++) {
2095                         unsigned int chan = CR_CHAN(cmd->chanlist[i]);
2096
2097                         if (chan != (chan0 + i)) {
2098                                 dev_dbg(dev->class_dev,
2099                                         "chanlist must use consecutive channels\n");
2100                                 return -EINVAL;
2101                         }
2102                 }
2103                 if (cmd->chanlist_len == 3) {
2104                         dev_dbg(dev->class_dev,
2105                                 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels\n");
2106                         return -EINVAL;
2107                 }
2108         }
2109
2110         return 0;
2111 }
2112
2113 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2114                       struct comedi_cmd *cmd)
2115 {
2116         const struct pcidas64_board *board = dev->board_ptr;
2117         int err = 0;
2118         unsigned int tmp_arg, tmp_arg2;
2119         unsigned int triggers;
2120
2121         /* Step 1 : check if triggers are trivially valid */
2122
2123         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2124
2125         triggers = TRIG_TIMER;
2126         if (board->layout == LAYOUT_4020)
2127                 triggers |= TRIG_OTHER;
2128         else
2129                 triggers |= TRIG_FOLLOW;
2130         err |= comedi_check_trigger_src(&cmd->scan_begin_src, triggers);
2131
2132         triggers = TRIG_TIMER;
2133         if (board->layout == LAYOUT_4020)
2134                 triggers |= TRIG_NOW;
2135         else
2136                 triggers |= TRIG_EXT;
2137         err |= comedi_check_trigger_src(&cmd->convert_src, triggers);
2138         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2139         err |= comedi_check_trigger_src(&cmd->stop_src,
2140                                         TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2141
2142         if (err)
2143                 return 1;
2144
2145         /* Step 2a : make sure trigger sources are unique */
2146
2147         err |= comedi_check_trigger_is_unique(cmd->start_src);
2148         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2149         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2150         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2151
2152         /* Step 2b : and mutually compatible */
2153
2154         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2155                 err |= -EINVAL;
2156
2157         if (err)
2158                 return 2;
2159
2160         /* Step 3: check if arguments are trivially valid */
2161
2162         switch (cmd->start_src) {
2163         case TRIG_NOW:
2164                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2165                 break;
2166         case TRIG_EXT:
2167                 /*
2168                  * start_arg is the CR_CHAN | CR_INVERT of the
2169                  * external trigger.
2170                  */
2171                 break;
2172         }
2173
2174         if (cmd->convert_src == TRIG_TIMER) {
2175                 if (board->layout == LAYOUT_4020) {
2176                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2177                                                            0);
2178                 } else {
2179                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2180                                                             board->ai_speed);
2181                         /*
2182                          * if scans are timed faster than conversion rate
2183                          * allows
2184                          */
2185                         if (cmd->scan_begin_src == TRIG_TIMER) {
2186                                 err |= comedi_check_trigger_arg_min(
2187                                                 &cmd->scan_begin_arg,
2188                                                 cmd->convert_arg *
2189                                                 cmd->chanlist_len);
2190                         }
2191                 }
2192         }
2193
2194         err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
2195         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2196                                            cmd->chanlist_len);
2197
2198         switch (cmd->stop_src) {
2199         case TRIG_EXT:
2200                 break;
2201         case TRIG_COUNT:
2202                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2203                 break;
2204         case TRIG_NONE:
2205                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2206                 break;
2207         default:
2208                 break;
2209         }
2210
2211         if (err)
2212                 return 3;
2213
2214         /* step 4: fix up any arguments */
2215
2216         if (cmd->convert_src == TRIG_TIMER) {
2217                 tmp_arg = cmd->convert_arg;
2218                 tmp_arg2 = cmd->scan_begin_arg;
2219                 check_adc_timing(dev, cmd);
2220                 if (tmp_arg != cmd->convert_arg)
2221                         err++;
2222                 if (tmp_arg2 != cmd->scan_begin_arg)
2223                         err++;
2224         }
2225
2226         if (err)
2227                 return 4;
2228
2229         /* Step 5: check channel list if it exists */
2230         if (cmd->chanlist && cmd->chanlist_len > 0)
2231                 err |= cb_pcidas64_ai_check_chanlist(dev, s, cmd);
2232
2233         if (err)
2234                 return 5;
2235
2236         return 0;
2237 }
2238
2239 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2240 {
2241 /* disable for now until I work out a race */
2242         return 0;
2243
2244         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2245                 return 1;
2246
2247         return 0;
2248 }
2249
2250 static void setup_sample_counters(struct comedi_device *dev,
2251                                   struct comedi_cmd *cmd)
2252 {
2253         struct pcidas64_private *devpriv = dev->private;
2254
2255         /* load hardware conversion counter */
2256         if (use_hw_sample_counter(cmd)) {
2257                 writew(cmd->stop_arg & 0xffff,
2258                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2259                 writew((cmd->stop_arg >> 16) & 0xff,
2260                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2261         } else {
2262                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2263         }
2264 }
2265
2266 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2267 {
2268         const struct pcidas64_board *board = dev->board_ptr;
2269         struct pcidas64_private *devpriv = dev->private;
2270         unsigned int num_samples;
2271
2272         num_samples = devpriv->ai_fifo_segment_length *
2273                       board->ai_fifo->sample_packing_ratio;
2274         if (num_samples > DMA_BUFFER_SIZE / sizeof(u16))
2275                 num_samples = DMA_BUFFER_SIZE / sizeof(u16);
2276
2277         return num_samples;
2278 }
2279
2280 static u32 ai_convert_counter_6xxx(const struct comedi_device *dev,
2281                                         const struct comedi_cmd *cmd)
2282 {
2283         /* supposed to load counter with desired divisor minus 3 */
2284         return cmd->convert_arg / TIMER_BASE - 3;
2285 }
2286
2287 static u32 ai_scan_counter_6xxx(struct comedi_device *dev,
2288                                      struct comedi_cmd *cmd)
2289 {
2290         u32 count;
2291
2292         /* figure out how long we need to delay at end of scan */
2293         switch (cmd->scan_begin_src) {
2294         case TRIG_TIMER:
2295                 count = (cmd->scan_begin_arg -
2296                          (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2297                         TIMER_BASE;
2298                 break;
2299         case TRIG_FOLLOW:
2300                 count = cmd->convert_arg / TIMER_BASE;
2301                 break;
2302         default:
2303                 return 0;
2304         }
2305         return count - 3;
2306 }
2307
2308 static u32 ai_convert_counter_4020(struct comedi_device *dev,
2309                                         struct comedi_cmd *cmd)
2310 {
2311         struct pcidas64_private *devpriv = dev->private;
2312         unsigned int divisor;
2313
2314         switch (cmd->scan_begin_src) {
2315         case TRIG_TIMER:
2316                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2317                 break;
2318         case TRIG_OTHER:
2319                 divisor = devpriv->ext_clock.divisor;
2320                 break;
2321         default:                /* should never happen */
2322                 dev_err(dev->class_dev, "bug! failed to set ai pacing!\n");
2323                 divisor = 1000;
2324                 break;
2325         }
2326
2327         /* supposed to load counter with desired divisor minus 2 for 4020 */
2328         return divisor - 2;
2329 }
2330
2331 static void select_master_clock_4020(struct comedi_device *dev,
2332                                      const struct comedi_cmd *cmd)
2333 {
2334         struct pcidas64_private *devpriv = dev->private;
2335
2336         /* select internal/external master clock */
2337         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2338         if (cmd->scan_begin_src == TRIG_OTHER) {
2339                 int chanspec = devpriv->ext_clock.chanspec;
2340
2341                 if (CR_CHAN(chanspec))
2342                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2343                 else
2344                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2345         } else {
2346                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2347         }
2348         writew(devpriv->hw_config_bits,
2349                devpriv->main_iobase + HW_CONFIG_REG);
2350 }
2351
2352 static void select_master_clock(struct comedi_device *dev,
2353                                 const struct comedi_cmd *cmd)
2354 {
2355         const struct pcidas64_board *board = dev->board_ptr;
2356
2357         switch (board->layout) {
2358         case LAYOUT_4020:
2359                 select_master_clock_4020(dev, cmd);
2360                 break;
2361         default:
2362                 break;
2363         }
2364 }
2365
2366 static inline void dma_start_sync(struct comedi_device *dev,
2367                                   unsigned int channel)
2368 {
2369         struct pcidas64_private *devpriv = dev->private;
2370         unsigned long flags;
2371
2372         /* spinlock for plx dma control/status reg */
2373         spin_lock_irqsave(&dev->spinlock, flags);
2374         writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR,
2375                devpriv->plx9080_iobase + PLX_REG_DMACSR(channel));
2376         spin_unlock_irqrestore(&dev->spinlock, flags);
2377 }
2378
2379 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2380 {
2381         const struct pcidas64_board *board = dev->board_ptr;
2382         struct pcidas64_private *devpriv = dev->private;
2383         u32 convert_counter = 0, scan_counter = 0;
2384
2385         check_adc_timing(dev, cmd);
2386
2387         select_master_clock(dev, cmd);
2388
2389         if (board->layout == LAYOUT_4020) {
2390                 convert_counter = ai_convert_counter_4020(dev, cmd);
2391         } else {
2392                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2393                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2394         }
2395
2396         /* load lower 16 bits of convert interval */
2397         writew(convert_counter & 0xffff,
2398                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2399         /* load upper 8 bits of convert interval */
2400         writew((convert_counter >> 16) & 0xff,
2401                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2402         /* load lower 16 bits of scan delay */
2403         writew(scan_counter & 0xffff,
2404                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2405         /* load upper 8 bits of scan delay */
2406         writew((scan_counter >> 16) & 0xff,
2407                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2408 }
2409
2410 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2411 {
2412         int i;
2413
2414         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2415                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2416                     CR_CHAN(cmd->chanlist[i]) + 1)
2417                         return 0;
2418                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2419                     CR_RANGE(cmd->chanlist[i]))
2420                         return 0;
2421                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2422                         return 0;
2423         }
2424         return 1;
2425 }
2426
2427 static int setup_channel_queue(struct comedi_device *dev,
2428                                const struct comedi_cmd *cmd)
2429 {
2430         const struct pcidas64_board *board = dev->board_ptr;
2431         struct pcidas64_private *devpriv = dev->private;
2432         unsigned short bits;
2433         int i;
2434
2435         if (board->layout != LAYOUT_4020) {
2436                 if (use_internal_queue_6xxx(cmd)) {
2437                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2438                         writew(devpriv->hw_config_bits,
2439                                devpriv->main_iobase + HW_CONFIG_REG);
2440                         bits = 0;
2441                         /* set channel */
2442                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2443                         /* set gain */
2444                         bits |= ai_range_bits_6xxx(dev,
2445                                                    CR_RANGE(cmd->chanlist[0]));
2446                         /* set single-ended / differential */
2447                         bits |= se_diff_bit_6xxx(dev,
2448                                                  CR_AREF(cmd->chanlist[0]) ==
2449                                                  AREF_DIFF);
2450                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2451                                 bits |= ADC_COMMON_BIT;
2452                         /* set stop channel */
2453                         writew(adc_chan_bits
2454                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2455                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2456                         /* set start channel, and rest of settings */
2457                         writew(bits,
2458                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2459                 } else {
2460                         /* use external queue */
2461                         if (dev->write_subdev && dev->write_subdev->busy) {
2462                                 warn_external_queue(dev);
2463                                 return -EBUSY;
2464                         }
2465                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2466                         writew(devpriv->hw_config_bits,
2467                                devpriv->main_iobase + HW_CONFIG_REG);
2468                         /* clear DAC buffer to prevent weird interactions */
2469                         writew(0,
2470                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2471                         /* clear queue pointer */
2472                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2473                         /* load external queue */
2474                         for (i = 0; i < cmd->chanlist_len; i++) {
2475                                 bits = 0;
2476                                 /* set channel */
2477                                 bits |= adc_chan_bits(CR_CHAN(cmd->
2478                                                               chanlist[i]));
2479                                 /* set gain */
2480                                 bits |= ai_range_bits_6xxx(dev,
2481                                                            CR_RANGE(cmd->
2482                                                                     chanlist
2483                                                                     [i]));
2484                                 /* set single-ended / differential */
2485                                 bits |= se_diff_bit_6xxx(dev,
2486                                                          CR_AREF(cmd->
2487                                                                  chanlist[i]) ==
2488                                                          AREF_DIFF);
2489                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2490                                         bits |= ADC_COMMON_BIT;
2491                                 /* mark end of queue */
2492                                 if (i == cmd->chanlist_len - 1)
2493                                         bits |= QUEUE_EOSCAN_BIT |
2494                                                 QUEUE_EOSEQ_BIT;
2495                                 writew(bits,
2496                                        devpriv->main_iobase +
2497                                        ADC_QUEUE_FIFO_REG);
2498                         }
2499                         /*
2500                          * doing a queue clear is not specified in board docs,
2501                          * but required for reliable operation
2502                          */
2503                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2504                         /* prime queue holding register */
2505                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2506                 }
2507         } else {
2508                 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2509
2510                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2511                 /* select BNC inputs */
2512                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2513                 /* select ranges */
2514                 for (i = 0; i < cmd->chanlist_len; i++) {
2515                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2516                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2517
2518                         if (range == 0)
2519                                 devpriv->i2c_cal_range_bits |=
2520                                         attenuate_bit(channel);
2521                         else
2522                                 devpriv->i2c_cal_range_bits &=
2523                                         ~attenuate_bit(channel);
2524                 }
2525                 /*
2526                  * update calibration/range i2c register only if necessary,
2527                  * as it is very slow
2528                  */
2529                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2530                         u8 i2c_data = devpriv->i2c_cal_range_bits;
2531
2532                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2533                                   sizeof(i2c_data));
2534                 }
2535         }
2536         return 0;
2537 }
2538
2539 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2540                                              unsigned int dma_channel,
2541                                              unsigned int descriptor_bits)
2542 {
2543         struct pcidas64_private *devpriv = dev->private;
2544
2545         /*
2546          * The transfer size, pci address, and local address registers
2547          * are supposedly unused during chained dma,
2548          * but I have found that left over values from last operation
2549          * occasionally cause problems with transfer of first dma
2550          * block.  Initializing them to zero seems to fix the problem.
2551          */
2552         if (dma_channel) {
2553                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ1);
2554                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR1);
2555                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR1);
2556                 writel(descriptor_bits,
2557                        devpriv->plx9080_iobase + PLX_REG_DMADPR1);
2558         } else {
2559                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ0);
2560                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR0);
2561                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR0);
2562                 writel(descriptor_bits,
2563                        devpriv->plx9080_iobase + PLX_REG_DMADPR0);
2564         }
2565 }
2566
2567 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2568 {
2569         const struct pcidas64_board *board = dev->board_ptr;
2570         struct pcidas64_private *devpriv = dev->private;
2571         struct comedi_async *async = s->async;
2572         struct comedi_cmd *cmd = &async->cmd;
2573         u32 bits;
2574         unsigned int i;
2575         unsigned long flags;
2576         int retval;
2577
2578         disable_ai_pacing(dev);
2579         abort_dma(dev, 1);
2580
2581         retval = setup_channel_queue(dev, cmd);
2582         if (retval < 0)
2583                 return retval;
2584
2585         /* make sure internal calibration source is turned off */
2586         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2587
2588         set_ai_pacing(dev, cmd);
2589
2590         setup_sample_counters(dev, cmd);
2591
2592         enable_ai_interrupts(dev, cmd);
2593
2594         spin_lock_irqsave(&dev->spinlock, flags);
2595         /* set mode, allow conversions through software gate */
2596         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2597         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2598         if (board->layout != LAYOUT_4020) {
2599                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2600                 if (cmd->convert_src == TRIG_EXT)
2601                         /* good old mode 13 */
2602                         devpriv->adc_control1_bits |= adc_mode_bits(13);
2603                 else
2604                         /* mode 8.  What else could you need? */
2605                         devpriv->adc_control1_bits |= adc_mode_bits(8);
2606         } else {
2607                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2608                 if (cmd->chanlist_len == 4)
2609                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2610                 else if (cmd->chanlist_len == 2)
2611                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2612                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2613                 devpriv->adc_control1_bits |=
2614                         adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2615                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2616                 devpriv->adc_control1_bits |=
2617                         adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2618                                                       [cmd->chanlist_len - 1]));
2619         }
2620         writew(devpriv->adc_control1_bits,
2621                devpriv->main_iobase + ADC_CONTROL1_REG);
2622         spin_unlock_irqrestore(&dev->spinlock, flags);
2623
2624         /* clear adc buffer */
2625         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2626
2627         if ((cmd->flags & CMDF_WAKE_EOS) == 0 ||
2628             board->layout == LAYOUT_4020) {
2629                 devpriv->ai_dma_index = 0;
2630
2631                 /* set dma transfer size */
2632                 for (i = 0; i < ai_dma_ring_count(board); i++)
2633                         devpriv->ai_dma_desc[i].transfer_size =
2634                                 cpu_to_le32(dma_transfer_size(dev) *
2635                                             sizeof(u16));
2636
2637                 /* give location of first dma descriptor */
2638                 load_first_dma_descriptor(dev, 1,
2639                                           devpriv->ai_dma_desc_bus_addr |
2640                                           PLX_DMADPR_DESCPCI |
2641                                           PLX_DMADPR_TCINTR |
2642                                           PLX_DMADPR_XFERL2P);
2643
2644                 dma_start_sync(dev, 1);
2645         }
2646
2647         if (board->layout == LAYOUT_4020) {
2648                 /* set source for external triggers */
2649                 bits = 0;
2650                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2651                         bits |= EXT_START_TRIG_BNC_BIT;
2652                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2653                         bits |= EXT_STOP_TRIG_BNC_BIT;
2654                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2655         }
2656
2657         spin_lock_irqsave(&dev->spinlock, flags);
2658
2659         /* enable pacing, triggering, etc */
2660         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2661         if (cmd->flags & CMDF_WAKE_EOS)
2662                 bits |= ADC_DMA_DISABLE_BIT;
2663         /* set start trigger */
2664         if (cmd->start_src == TRIG_EXT) {
2665                 bits |= ADC_START_TRIG_EXT_BITS;
2666                 if (cmd->start_arg & CR_INVERT)
2667                         bits |= ADC_START_TRIG_FALLING_BIT;
2668         } else if (cmd->start_src == TRIG_NOW) {
2669                 bits |= ADC_START_TRIG_SOFT_BITS;
2670         }
2671         if (use_hw_sample_counter(cmd))
2672                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2673         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2674
2675         devpriv->ai_cmd_running = 1;
2676
2677         spin_unlock_irqrestore(&dev->spinlock, flags);
2678
2679         /* start acquisition */
2680         if (cmd->start_src == TRIG_NOW)
2681                 writew(0, devpriv->main_iobase + ADC_START_REG);
2682
2683         return 0;
2684 }
2685
2686 /* read num_samples from 16 bit wide ai fifo */
2687 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2688 {
2689         struct pcidas64_private *devpriv = dev->private;
2690         struct comedi_subdevice *s = dev->read_subdev;
2691         unsigned int i;
2692         u16 prepost_bits;
2693         int read_segment, read_index, write_segment, write_index;
2694         int num_samples;
2695
2696         do {
2697                 /* get least significant 15 bits */
2698                 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2699                              0x7fff;
2700                 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2701                               0x7fff;
2702                 /*
2703                  * Get most significant bits (grey code).
2704                  * Different boards use different code so use a scheme
2705                  * that doesn't depend on encoding.  This read must
2706                  * occur after reading least significant 15 bits to avoid race
2707                  * with fifo switching to next segment.
2708                  */
2709                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2710
2711                 /*
2712                  * if read and write pointers are not on the same fifo segment,
2713                  * read to the end of the read segment
2714                  */
2715                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2716                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2717
2718                 if (read_segment != write_segment)
2719                         num_samples =
2720                                 devpriv->ai_fifo_segment_length - read_index;
2721                 else
2722                         num_samples = write_index - read_index;
2723                 if (num_samples < 0) {
2724                         dev_err(dev->class_dev,
2725                                 "cb_pcidas64: bug! num_samples < 0\n");
2726                         break;
2727                 }
2728
2729                 num_samples = comedi_nsamples_left(s, num_samples);
2730                 if (num_samples == 0)
2731                         break;
2732
2733                 for (i = 0; i < num_samples; i++) {
2734                         unsigned short val;
2735
2736                         val = readw(devpriv->main_iobase + ADC_FIFO_REG);
2737                         comedi_buf_write_samples(s, &val, 1);
2738                 }
2739
2740         } while (read_segment != write_segment);
2741 }
2742
2743 /*
2744  * Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2745  * pointers.  The pci-4020 hardware only supports dma transfers (it only
2746  * supports the use of pio for draining the last remaining points from the
2747  * fifo when a data acquisition operation has completed).
2748  */
2749 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2750 {
2751         struct pcidas64_private *devpriv = dev->private;
2752         struct comedi_subdevice *s = dev->read_subdev;
2753         unsigned int nsamples;
2754         unsigned int i;
2755         u32 fifo_data;
2756         int write_code =
2757                 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2758         int read_code =
2759                 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2760
2761         nsamples = comedi_nsamples_left(s, 100000);
2762         for (i = 0; read_code != write_code && i < nsamples;) {
2763                 unsigned short val;
2764
2765                 fifo_data = readl(dev->mmio + ADC_FIFO_REG);
2766                 val = fifo_data & 0xffff;
2767                 comedi_buf_write_samples(s, &val, 1);
2768                 i++;
2769                 if (i < nsamples) {
2770                         val = (fifo_data >> 16) & 0xffff;
2771                         comedi_buf_write_samples(s, &val, 1);
2772                         i++;
2773                 }
2774                 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2775                             0x7fff;
2776         }
2777 }
2778
2779 /* empty fifo */
2780 static void pio_drain_ai_fifo(struct comedi_device *dev)
2781 {
2782         const struct pcidas64_board *board = dev->board_ptr;
2783
2784         if (board->layout == LAYOUT_4020)
2785                 pio_drain_ai_fifo_32(dev);
2786         else
2787                 pio_drain_ai_fifo_16(dev);
2788 }
2789
2790 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2791 {
2792         const struct pcidas64_board *board = dev->board_ptr;
2793         struct pcidas64_private *devpriv = dev->private;
2794         struct comedi_subdevice *s = dev->read_subdev;
2795         u32 next_transfer_addr;
2796         int j;
2797         int num_samples = 0;
2798         void __iomem *pci_addr_reg;
2799
2800         pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR(channel);
2801
2802         /* loop until we have read all the full buffers */
2803         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2804              (next_transfer_addr <
2805               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2806               next_transfer_addr >=
2807               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2808               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board); j++) {
2809                 /* transfer data from dma buffer to comedi buffer */
2810                 num_samples = comedi_nsamples_left(s, dma_transfer_size(dev));
2811                 comedi_buf_write_samples(s,
2812                                 devpriv->ai_buffer[devpriv->ai_dma_index],
2813                                 num_samples);
2814                 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2815                                         ai_dma_ring_count(board);
2816         }
2817         /*
2818          * XXX check for dma ring buffer overrun
2819          * (use end-of-chain bit to mark last unused buffer)
2820          */
2821 }
2822
2823 static void handle_ai_interrupt(struct comedi_device *dev,
2824                                 unsigned short status,
2825                                 unsigned int plx_status)
2826 {
2827         const struct pcidas64_board *board = dev->board_ptr;
2828         struct pcidas64_private *devpriv = dev->private;
2829         struct comedi_subdevice *s = dev->read_subdev;
2830         struct comedi_async *async = s->async;
2831         struct comedi_cmd *cmd = &async->cmd;
2832         u8 dma1_status;
2833         unsigned long flags;
2834
2835         /* check for fifo overrun */
2836         if (status & ADC_OVERRUN_BIT) {
2837                 dev_err(dev->class_dev, "fifo overrun\n");
2838                 async->events |= COMEDI_CB_ERROR;
2839         }
2840         /* spin lock makes sure no one else changes plx dma control reg */
2841         spin_lock_irqsave(&dev->spinlock, flags);
2842         dma1_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR1);
2843         if (plx_status & PLX_INTCSR_DMA1IA) {   /* dma chan 1 interrupt */
2844                 writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
2845                        devpriv->plx9080_iobase + PLX_REG_DMACSR1);
2846
2847                 if (dma1_status & PLX_DMACSR_ENABLE)
2848                         drain_dma_buffers(dev, 1);
2849         }
2850         spin_unlock_irqrestore(&dev->spinlock, flags);
2851
2852         /* drain fifo with pio */
2853         if ((status & ADC_DONE_BIT) ||
2854             ((cmd->flags & CMDF_WAKE_EOS) &&
2855              (status & ADC_INTR_PENDING_BIT) &&
2856              (board->layout != LAYOUT_4020))) {
2857                 spin_lock_irqsave(&dev->spinlock, flags);
2858                 if (devpriv->ai_cmd_running) {
2859                         spin_unlock_irqrestore(&dev->spinlock, flags);
2860                         pio_drain_ai_fifo(dev);
2861                 } else {
2862                         spin_unlock_irqrestore(&dev->spinlock, flags);
2863                 }
2864         }
2865         /* if we are have all the data, then quit */
2866         if ((cmd->stop_src == TRIG_COUNT &&
2867              async->scans_done >= cmd->stop_arg) ||
2868             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT)))
2869                 async->events |= COMEDI_CB_EOA;
2870
2871         comedi_handle_events(dev, s);
2872 }
2873
2874 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2875 {
2876         struct pcidas64_private *devpriv = dev->private;
2877         unsigned int buffer_index;
2878
2879         if (devpriv->ao_dma_index == 0)
2880                 buffer_index = AO_DMA_RING_COUNT - 1;
2881         else
2882                 buffer_index = devpriv->ao_dma_index - 1;
2883         return buffer_index;
2884 }
2885
2886 static int last_ao_dma_load_completed(struct comedi_device *dev)
2887 {
2888         struct pcidas64_private *devpriv = dev->private;
2889         unsigned int buffer_index;
2890         unsigned int transfer_address;
2891         unsigned short dma_status;
2892
2893         buffer_index = prev_ao_dma_index(dev);
2894         dma_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
2895         if ((dma_status & PLX_DMACSR_DONE) == 0)
2896                 return 0;
2897
2898         transfer_address =
2899                 readl(devpriv->plx9080_iobase + PLX_REG_DMAPADR0);
2900         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2901                 return 0;
2902
2903         return 1;
2904 }
2905
2906 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2907                                        unsigned short dma_status)
2908 {
2909         if ((dma_status & PLX_DMACSR_DONE) == 0 ||
2910             (dma_status & PLX_DMACSR_ENABLE) == 0)
2911                 return 0;
2912         if (last_ao_dma_load_completed(dev))
2913                 return 0;
2914
2915         return 1;
2916 }
2917
2918 static void restart_ao_dma(struct comedi_device *dev)
2919 {
2920         struct pcidas64_private *devpriv = dev->private;
2921         unsigned int dma_desc_bits;
2922
2923         dma_desc_bits = readl(devpriv->plx9080_iobase + PLX_REG_DMADPR0);
2924         dma_desc_bits &= ~PLX_DMADPR_CHAINEND;
2925         load_first_dma_descriptor(dev, 0, dma_desc_bits);
2926
2927         dma_start_sync(dev, 0);
2928 }
2929
2930 static unsigned int cb_pcidas64_ao_fill_buffer(struct comedi_device *dev,
2931                                                struct comedi_subdevice *s,
2932                                                unsigned short *dest,
2933                                                unsigned int max_bytes)
2934 {
2935         unsigned int nsamples = comedi_bytes_to_samples(s, max_bytes);
2936         unsigned int actual_bytes;
2937
2938         nsamples = comedi_nsamples_left(s, nsamples);
2939         actual_bytes = comedi_buf_read_samples(s, dest, nsamples);
2940
2941         return comedi_bytes_to_samples(s, actual_bytes);
2942 }
2943
2944 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2945                                        const struct comedi_cmd *cmd)
2946 {
2947         struct pcidas64_private *devpriv = dev->private;
2948         struct comedi_subdevice *s = dev->write_subdev;
2949         unsigned int buffer_index = devpriv->ao_dma_index;
2950         unsigned int prev_buffer_index = prev_ao_dma_index(dev);
2951         unsigned int nsamples;
2952         unsigned int nbytes;
2953         unsigned int next_bits;
2954
2955         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
2956                                               devpriv->ao_buffer[buffer_index],
2957                                               DMA_BUFFER_SIZE);
2958         if (nsamples == 0)
2959                 return 0;
2960
2961         nbytes = comedi_samples_to_bytes(s, nsamples);
2962         devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes);
2963         /* set end of chain bit so we catch underruns */
2964         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2965         next_bits |= PLX_DMADPR_CHAINEND;
2966         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2967         /*
2968          * clear end of chain bit on previous buffer now that we have set it
2969          * for the last buffer
2970          */
2971         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2972         next_bits &= ~PLX_DMADPR_CHAINEND;
2973         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2974
2975         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2976
2977         return nbytes;
2978 }
2979
2980 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
2981 {
2982         struct pcidas64_private *devpriv = dev->private;
2983         unsigned int num_bytes;
2984         unsigned int next_transfer_addr;
2985         void __iomem *pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR0;
2986         unsigned int buffer_index;
2987
2988         do {
2989                 buffer_index = devpriv->ao_dma_index;
2990                 /* don't overwrite data that hasn't been transferred yet */
2991                 next_transfer_addr = readl(pci_addr_reg);
2992                 if (next_transfer_addr >=
2993                     devpriv->ao_buffer_bus_addr[buffer_index] &&
2994                     next_transfer_addr <
2995                     devpriv->ao_buffer_bus_addr[buffer_index] +
2996                     DMA_BUFFER_SIZE)
2997                         return;
2998                 num_bytes = load_ao_dma_buffer(dev, cmd);
2999         } while (num_bytes >= DMA_BUFFER_SIZE);
3000 }
3001
3002 static void handle_ao_interrupt(struct comedi_device *dev,
3003                                 unsigned short status, unsigned int plx_status)
3004 {
3005         struct pcidas64_private *devpriv = dev->private;
3006         struct comedi_subdevice *s = dev->write_subdev;
3007         struct comedi_async *async;
3008         struct comedi_cmd *cmd;
3009         u8 dma0_status;
3010         unsigned long flags;
3011
3012         /* board might not support ao, in which case write_subdev is NULL */
3013         if (!s)
3014                 return;
3015         async = s->async;
3016         cmd = &async->cmd;
3017
3018         /* spin lock makes sure no one else changes plx dma control reg */
3019         spin_lock_irqsave(&dev->spinlock, flags);
3020         dma0_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
3021         if (plx_status & PLX_INTCSR_DMA0IA) {   /*  dma chan 0 interrupt */
3022                 if ((dma0_status & PLX_DMACSR_ENABLE) &&
3023                     !(dma0_status & PLX_DMACSR_DONE)) {
3024                         writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_CLEARINTR,
3025                                devpriv->plx9080_iobase + PLX_REG_DMACSR0);
3026                 } else {
3027                         writeb(PLX_DMACSR_CLEARINTR,
3028                                devpriv->plx9080_iobase + PLX_REG_DMACSR0);
3029                 }
3030                 spin_unlock_irqrestore(&dev->spinlock, flags);
3031                 if (dma0_status & PLX_DMACSR_ENABLE) {
3032                         load_ao_dma(dev, cmd);
3033                         /* try to recover from dma end-of-chain event */
3034                         if (ao_dma_needs_restart(dev, dma0_status))
3035                                 restart_ao_dma(dev);
3036                 }
3037         } else {
3038                 spin_unlock_irqrestore(&dev->spinlock, flags);
3039         }
3040
3041         if ((status & DAC_DONE_BIT)) {
3042                 if ((cmd->stop_src == TRIG_COUNT &&
3043                      async->scans_done >= cmd->stop_arg) ||
3044                     last_ao_dma_load_completed(dev))
3045                         async->events |= COMEDI_CB_EOA;
3046                 else
3047                         async->events |= COMEDI_CB_ERROR;
3048         }
3049         comedi_handle_events(dev, s);
3050 }
3051
3052 static irqreturn_t handle_interrupt(int irq, void *d)
3053 {
3054         struct comedi_device *dev = d;
3055         struct pcidas64_private *devpriv = dev->private;
3056         unsigned short status;
3057         u32 plx_status;
3058         u32 plx_bits;
3059
3060         plx_status = readl(devpriv->plx9080_iobase + PLX_REG_INTCSR);
3061         status = readw(devpriv->main_iobase + HW_STATUS_REG);
3062
3063         /*
3064          * an interrupt before all the postconfig stuff gets done could
3065          * cause a NULL dereference if we continue through the
3066          * interrupt handler
3067          */
3068         if (!dev->attached)
3069                 return IRQ_HANDLED;
3070
3071         handle_ai_interrupt(dev, status, plx_status);
3072         handle_ao_interrupt(dev, status, plx_status);
3073
3074         /* clear possible plx9080 interrupt sources */
3075         if (plx_status & PLX_INTCSR_LDBIA) {
3076                 /* clear local doorbell interrupt */
3077                 plx_bits = readl(devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
3078                 writel(plx_bits, devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
3079         }
3080
3081         return IRQ_HANDLED;
3082 }
3083
3084 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3085 {
3086         struct pcidas64_private *devpriv = dev->private;
3087         unsigned long flags;
3088
3089         spin_lock_irqsave(&dev->spinlock, flags);
3090         if (devpriv->ai_cmd_running == 0) {
3091                 spin_unlock_irqrestore(&dev->spinlock, flags);
3092                 return 0;
3093         }
3094         devpriv->ai_cmd_running = 0;
3095         spin_unlock_irqrestore(&dev->spinlock, flags);
3096
3097         disable_ai_pacing(dev);
3098
3099         abort_dma(dev, 1);
3100
3101         return 0;
3102 }
3103
3104 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3105                     struct comedi_insn *insn, unsigned int *data)
3106 {
3107         const struct pcidas64_board *board = dev->board_ptr;
3108         struct pcidas64_private *devpriv = dev->private;
3109         int chan = CR_CHAN(insn->chanspec);
3110         int range = CR_RANGE(insn->chanspec);
3111
3112         /* do some initializing */
3113         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3114
3115         /* set range */
3116         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3117         writew(devpriv->dac_control1_bits,
3118                devpriv->main_iobase + DAC_CONTROL1_REG);
3119
3120         /* write to channel */
3121         if (board->layout == LAYOUT_4020) {
3122                 writew(data[0] & 0xff,
3123                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3124                 writew((data[0] >> 8) & 0xf,
3125                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3126         } else {
3127                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3128         }
3129
3130         /* remember output value */
3131         s->readback[chan] = data[0];
3132
3133         return 1;
3134 }
3135
3136 static void set_dac_control0_reg(struct comedi_device *dev,
3137                                  const struct comedi_cmd *cmd)
3138 {
3139         struct pcidas64_private *devpriv = dev->private;
3140         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3141                             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3142
3143         if (cmd->start_src == TRIG_EXT) {
3144                 bits |= WAVEFORM_TRIG_EXT_BITS;
3145                 if (cmd->start_arg & CR_INVERT)
3146                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3147         } else {
3148                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3149         }
3150         if (cmd->scan_begin_src == TRIG_EXT) {
3151                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3152                 if (cmd->scan_begin_arg & CR_INVERT)
3153                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3154         }
3155         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3156 }
3157
3158 static void set_dac_control1_reg(struct comedi_device *dev,
3159                                  const struct comedi_cmd *cmd)
3160 {
3161         struct pcidas64_private *devpriv = dev->private;
3162         int i;
3163
3164         for (i = 0; i < cmd->chanlist_len; i++) {
3165                 int channel, range;
3166
3167                 channel = CR_CHAN(cmd->chanlist[i]);
3168                 range = CR_RANGE(cmd->chanlist[i]);
3169                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3170                                    range);
3171         }
3172         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3173         writew(devpriv->dac_control1_bits,
3174                devpriv->main_iobase + DAC_CONTROL1_REG);
3175 }
3176
3177 static void set_dac_select_reg(struct comedi_device *dev,
3178                                const struct comedi_cmd *cmd)
3179 {
3180         struct pcidas64_private *devpriv = dev->private;
3181         u16 bits;
3182         unsigned int first_channel, last_channel;
3183
3184         first_channel = CR_CHAN(cmd->chanlist[0]);
3185         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3186         if (last_channel < first_channel)
3187                 dev_err(dev->class_dev,
3188                         "bug! last ao channel < first ao channel\n");
3189
3190         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3191
3192         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3193 }
3194
3195 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3196 {
3197         return get_divisor(ns, flags) - 2;
3198 }
3199
3200 static void set_dac_interval_regs(struct comedi_device *dev,
3201                                   const struct comedi_cmd *cmd)
3202 {
3203         struct pcidas64_private *devpriv = dev->private;
3204         unsigned int divisor;
3205
3206         if (cmd->scan_begin_src != TRIG_TIMER)
3207                 return;
3208
3209         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3210         if (divisor > max_counter_value) {
3211                 dev_err(dev->class_dev, "bug! ao divisor too big\n");
3212                 divisor = max_counter_value;
3213         }
3214         writew(divisor & 0xffff,
3215                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3216         writew((divisor >> 16) & 0xff,
3217                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3218 }
3219
3220 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3221 {
3222         struct pcidas64_private *devpriv = dev->private;
3223         struct comedi_subdevice *s = dev->write_subdev;
3224         unsigned int nsamples;
3225         unsigned int nbytes;
3226         int i;
3227
3228         /*
3229          * clear queue pointer too, since external queue has
3230          * weird interactions with ao fifo
3231          */
3232         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3233         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3234
3235         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
3236                                               devpriv->ao_bounce_buffer,
3237                                               DAC_FIFO_SIZE);
3238         if (nsamples == 0)
3239                 return -1;
3240
3241         for (i = 0; i < nsamples; i++) {
3242                 writew(devpriv->ao_bounce_buffer[i],
3243                        devpriv->main_iobase + DAC_FIFO_REG);
3244         }
3245
3246         if (cmd->stop_src == TRIG_COUNT &&
3247             s->async->scans_done >= cmd->stop_arg)
3248                 return 0;
3249
3250         nbytes = load_ao_dma_buffer(dev, cmd);
3251         if (nbytes == 0)
3252                 return -1;
3253         load_ao_dma(dev, cmd);
3254
3255         dma_start_sync(dev, 0);
3256
3257         return 0;
3258 }
3259
3260 static inline int external_ai_queue_in_use(struct comedi_device *dev,
3261                                            struct comedi_subdevice *s,
3262                                            struct comedi_cmd *cmd)
3263 {
3264         const struct pcidas64_board *board = dev->board_ptr;
3265
3266         if (s->busy)
3267                 return 0;
3268         if (board->layout == LAYOUT_4020)
3269                 return 0;
3270         else if (use_internal_queue_6xxx(cmd))
3271                 return 0;
3272         return 1;
3273 }
3274
3275 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3276                       unsigned int trig_num)
3277 {
3278         struct pcidas64_private *devpriv = dev->private;
3279         struct comedi_cmd *cmd = &s->async->cmd;
3280         int retval;
3281
3282         if (trig_num != cmd->start_arg)
3283                 return -EINVAL;
3284
3285         retval = prep_ao_dma(dev, cmd);
3286         if (retval < 0)
3287                 return -EPIPE;
3288
3289         set_dac_control0_reg(dev, cmd);
3290
3291         if (cmd->start_src == TRIG_INT)
3292                 writew(0, devpriv->main_iobase + DAC_START_REG);
3293
3294         s->async->inttrig = NULL;
3295
3296         return 0;
3297 }
3298
3299 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3300 {
3301         struct pcidas64_private *devpriv = dev->private;
3302         struct comedi_cmd *cmd = &s->async->cmd;
3303
3304         if (external_ai_queue_in_use(dev, s, cmd)) {
3305                 warn_external_queue(dev);
3306                 return -EBUSY;
3307         }
3308         /* disable analog output system during setup */
3309         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3310
3311         devpriv->ao_dma_index = 0;
3312
3313         set_dac_select_reg(dev, cmd);
3314         set_dac_interval_regs(dev, cmd);
3315         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3316                                   PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR);
3317
3318         set_dac_control1_reg(dev, cmd);
3319         s->async->inttrig = ao_inttrig;
3320
3321         return 0;
3322 }
3323
3324 static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev,
3325                                          struct comedi_subdevice *s,
3326                                          struct comedi_cmd *cmd)
3327 {
3328         unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
3329         int i;
3330
3331         for (i = 1; i < cmd->chanlist_len; i++) {
3332                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3333
3334                 if (chan != (chan0 + i)) {
3335                         dev_dbg(dev->class_dev,
3336                                 "chanlist must use consecutive channels\n");
3337                         return -EINVAL;
3338                 }
3339         }
3340
3341         return 0;
3342 }
3343
3344 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3345                       struct comedi_cmd *cmd)
3346 {
3347         const struct pcidas64_board *board = dev->board_ptr;
3348         int err = 0;
3349         unsigned int tmp_arg;
3350
3351         /* Step 1 : check if triggers are trivially valid */
3352
3353         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3354         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3355                                         TRIG_TIMER | TRIG_EXT);
3356         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3357         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3358         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3359
3360         if (err)
3361                 return 1;
3362
3363         /* Step 2a : make sure trigger sources are unique */
3364
3365         err |= comedi_check_trigger_is_unique(cmd->start_src);
3366         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3367
3368         /* Step 2b : and mutually compatible */
3369
3370         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3371                 err |= -EINVAL;
3372         if (cmd->stop_src != TRIG_COUNT &&
3373             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3374                 err |= -EINVAL;
3375
3376         if (err)
3377                 return 2;
3378
3379         /* Step 3: check if arguments are trivially valid */
3380
3381         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3382
3383         if (cmd->scan_begin_src == TRIG_TIMER) {
3384                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3385                                                     board->ao_scan_speed);
3386                 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3387                     max_counter_value) {
3388                         cmd->scan_begin_arg = (max_counter_value + 2) *
3389                                               TIMER_BASE;
3390                         err |= -EINVAL;
3391                 }
3392         }
3393
3394         err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
3395         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3396                                            cmd->chanlist_len);
3397
3398         if (err)
3399                 return 3;
3400
3401         /* step 4: fix up any arguments */
3402
3403         if (cmd->scan_begin_src == TRIG_TIMER) {
3404                 tmp_arg = cmd->scan_begin_arg;
3405                 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3406                                                   cmd->flags) * TIMER_BASE;
3407                 if (tmp_arg != cmd->scan_begin_arg)
3408                         err++;
3409         }
3410
3411         if (err)
3412                 return 4;
3413
3414         /* Step 5: check channel list if it exists */
3415         if (cmd->chanlist && cmd->chanlist_len > 0)
3416                 err |= cb_pcidas64_ao_check_chanlist(dev, s, cmd);
3417
3418         if (err)
3419                 return 5;
3420
3421         return 0;
3422 }
3423
3424 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3425 {
3426         struct pcidas64_private *devpriv = dev->private;
3427
3428         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3429         abort_dma(dev, 0);
3430         return 0;
3431 }
3432
3433 static int dio_callback_4020(struct comedi_device *dev,
3434                              int dir, int port, int data, unsigned long iobase)
3435 {
3436         struct pcidas64_private *devpriv = dev->private;
3437
3438         if (dir) {
3439                 writew(data, devpriv->main_iobase + iobase + 2 * port);
3440                 return 0;
3441         }
3442         return readw(devpriv->main_iobase + iobase + 2 * port);
3443 }
3444
3445 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3446                     struct comedi_insn *insn, unsigned int *data)
3447 {
3448         unsigned int bits;
3449
3450         bits = readb(dev->mmio + DI_REG);
3451         bits &= 0xf;
3452         data[1] = bits;
3453         data[0] = 0;
3454
3455         return insn->n;
3456 }
3457
3458 static int do_wbits(struct comedi_device *dev,
3459                     struct comedi_subdevice *s,
3460                     struct comedi_insn *insn,
3461                     unsigned int *data)
3462 {
3463         if (comedi_dio_update_state(s, data))
3464                 writeb(s->state, dev->mmio + DO_REG);
3465
3466         data[1] = s->state;
3467
3468         return insn->n;
3469 }
3470
3471 static int dio_60xx_config_insn(struct comedi_device *dev,
3472                                 struct comedi_subdevice *s,
3473                                 struct comedi_insn *insn,
3474                                 unsigned int *data)
3475 {
3476         int ret;
3477
3478         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3479         if (ret)
3480                 return ret;
3481
3482         writeb(s->io_bits, dev->mmio + DIO_DIRECTION_60XX_REG);
3483
3484         return insn->n;
3485 }
3486
3487 static int dio_60xx_wbits(struct comedi_device *dev,
3488                           struct comedi_subdevice *s,
3489                           struct comedi_insn *insn,
3490                           unsigned int *data)
3491 {
3492         if (comedi_dio_update_state(s, data))
3493                 writeb(s->state, dev->mmio + DIO_DATA_60XX_REG);
3494
3495         data[1] = readb(dev->mmio + DIO_DATA_60XX_REG);
3496
3497         return insn->n;
3498 }
3499
3500 /*
3501  * pci-6025 8800 caldac:
3502  * address 0 == dac channel 0 offset
3503  * address 1 == dac channel 0 gain
3504  * address 2 == dac channel 1 offset
3505  * address 3 == dac channel 1 gain
3506  * address 4 == fine adc offset
3507  * address 5 == coarse adc offset
3508  * address 6 == coarse adc gain
3509  * address 7 == fine adc gain
3510  */
3511 /*
3512  * pci-6402/16 uses all 8 channels for dac:
3513  * address 0 == dac channel 0 fine gain
3514  * address 1 == dac channel 0 coarse gain
3515  * address 2 == dac channel 0 coarse offset
3516  * address 3 == dac channel 1 coarse offset
3517  * address 4 == dac channel 1 fine gain
3518  * address 5 == dac channel 1 coarse gain
3519  * address 6 == dac channel 0 fine offset
3520  * address 7 == dac channel 1 fine offset
3521  */
3522
3523 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3524                              u8 value)
3525 {
3526         struct pcidas64_private *devpriv = dev->private;
3527         static const int num_caldac_channels = 8;
3528         static const int bitstream_length = 11;
3529         unsigned int bitstream = ((address & 0x7) << 8) | value;
3530         unsigned int bit, register_bits;
3531         static const int caldac_8800_udelay = 1;
3532
3533         if (address >= num_caldac_channels) {
3534                 dev_err(dev->class_dev, "illegal caldac channel\n");
3535                 return -1;
3536         }
3537         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3538                 register_bits = 0;
3539                 if (bitstream & bit)
3540                         register_bits |= SERIAL_DATA_IN_BIT;
3541                 udelay(caldac_8800_udelay);
3542                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3543                 register_bits |= SERIAL_CLOCK_BIT;
3544                 udelay(caldac_8800_udelay);
3545                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3546         }
3547         udelay(caldac_8800_udelay);
3548         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3549         udelay(caldac_8800_udelay);
3550         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3551         udelay(caldac_8800_udelay);
3552         return 0;
3553 }
3554
3555 /* 4020 caldacs */
3556 static int caldac_i2c_write(struct comedi_device *dev,
3557                             unsigned int caldac_channel, unsigned int value)
3558 {
3559         u8 serial_bytes[3];
3560         u8 i2c_addr;
3561         enum pointer_bits {
3562                 /* manual has gain and offset bits switched */
3563                 OFFSET_0_2 = 0x1,
3564                 GAIN_0_2 = 0x2,
3565                 OFFSET_1_3 = 0x4,
3566                 GAIN_1_3 = 0x8,
3567         };
3568         enum data_bits {
3569                 NOT_CLEAR_REGISTERS = 0x20,
3570         };
3571
3572         switch (caldac_channel) {
3573         case 0:                                 /* chan 0 offset */
3574                 i2c_addr = CALDAC0_I2C_ADDR;
3575                 serial_bytes[0] = OFFSET_0_2;
3576                 break;
3577         case 1:                                 /* chan 1 offset */
3578                 i2c_addr = CALDAC0_I2C_ADDR;
3579                 serial_bytes[0] = OFFSET_1_3;
3580                 break;
3581         case 2:                                 /* chan 2 offset */
3582                 i2c_addr = CALDAC1_I2C_ADDR;
3583                 serial_bytes[0] = OFFSET_0_2;
3584                 break;
3585         case 3:                                 /* chan 3 offset */
3586                 i2c_addr = CALDAC1_I2C_ADDR;
3587                 serial_bytes[0] = OFFSET_1_3;
3588                 break;
3589         case 4:                                 /* chan 0 gain */
3590                 i2c_addr = CALDAC0_I2C_ADDR;
3591                 serial_bytes[0] = GAIN_0_2;
3592                 break;
3593         case 5:                                 /* chan 1 gain */
3594                 i2c_addr = CALDAC0_I2C_ADDR;
3595                 serial_bytes[0] = GAIN_1_3;
3596                 break;
3597         case 6:                                 /* chan 2 gain */
3598                 i2c_addr = CALDAC1_I2C_ADDR;
3599                 serial_bytes[0] = GAIN_0_2;
3600                 break;
3601         case 7:                                 /* chan 3 gain */
3602                 i2c_addr = CALDAC1_I2C_ADDR;
3603                 serial_bytes[0] = GAIN_1_3;
3604                 break;
3605         default:
3606                 dev_err(dev->class_dev, "invalid caldac channel\n");
3607                 return -1;
3608         }
3609         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3610         serial_bytes[2] = value & 0xff;
3611         i2c_write(dev, i2c_addr, serial_bytes, 3);
3612         return 0;
3613 }
3614
3615 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3616                          unsigned int value)
3617 {
3618         const struct pcidas64_board *board = dev->board_ptr;
3619
3620         switch (board->layout) {
3621         case LAYOUT_60XX:
3622         case LAYOUT_64XX:
3623                 caldac_8800_write(dev, channel, value);
3624                 break;
3625         case LAYOUT_4020:
3626                 caldac_i2c_write(dev, channel, value);
3627                 break;
3628         default:
3629                 break;
3630         }
3631 }
3632
3633 static int cb_pcidas64_calib_insn_write(struct comedi_device *dev,
3634                                         struct comedi_subdevice *s,
3635                                         struct comedi_insn *insn,
3636                                         unsigned int *data)
3637 {
3638         unsigned int chan = CR_CHAN(insn->chanspec);
3639
3640         /*
3641          * Programming the calib device is slow. Only write the
3642          * last data value if the value has changed.
3643          */
3644         if (insn->n) {
3645                 unsigned int val = data[insn->n - 1];
3646
3647                 if (s->readback[chan] != val) {
3648                         caldac_write(dev, chan, val);
3649                         s->readback[chan] = val;
3650                 }
3651         }
3652
3653         return insn->n;
3654 }
3655
3656 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3657                          unsigned int value)
3658 {
3659         struct pcidas64_private *devpriv = dev->private;
3660         static const int bitstream_length = 10;
3661         unsigned int bit, register_bits;
3662         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3663         static const int ad8402_udelay = 1;
3664
3665         register_bits = SELECT_8402_64XX_BIT;
3666         udelay(ad8402_udelay);
3667         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3668
3669         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3670                 if (bitstream & bit)
3671                         register_bits |= SERIAL_DATA_IN_BIT;
3672                 else
3673                         register_bits &= ~SERIAL_DATA_IN_BIT;
3674                 udelay(ad8402_udelay);
3675                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3676                 udelay(ad8402_udelay);
3677                 writew(register_bits | SERIAL_CLOCK_BIT,
3678                        devpriv->main_iobase + CALIBRATION_REG);
3679         }
3680
3681         udelay(ad8402_udelay);
3682         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3683 }
3684
3685 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3686 static int cb_pcidas64_ad8402_insn_write(struct comedi_device *dev,
3687                                          struct comedi_subdevice *s,
3688                                          struct comedi_insn *insn,
3689                                          unsigned int *data)
3690 {
3691         unsigned int chan = CR_CHAN(insn->chanspec);
3692
3693         /*
3694          * Programming the calib device is slow. Only write the
3695          * last data value if the value has changed.
3696          */
3697         if (insn->n) {
3698                 unsigned int val = data[insn->n - 1];
3699
3700                 if (s->readback[chan] != val) {
3701                         ad8402_write(dev, chan, val);
3702                         s->readback[chan] = val;
3703                 }
3704         }
3705
3706         return insn->n;
3707 }
3708
3709 static u16 read_eeprom(struct comedi_device *dev, u8 address)
3710 {
3711         struct pcidas64_private *devpriv = dev->private;
3712         static const int bitstream_length = 11;
3713         static const int read_command = 0x6;
3714         unsigned int bitstream = (read_command << 8) | address;
3715         unsigned int bit;
3716         void __iomem * const plx_control_addr =
3717                 devpriv->plx9080_iobase + PLX_REG_CNTRL;
3718         u16 value;
3719         static const int value_length = 16;
3720         static const int eeprom_udelay = 1;
3721
3722         udelay(eeprom_udelay);
3723         devpriv->plx_control_bits &= ~PLX_CNTRL_EESK & ~PLX_CNTRL_EECS;
3724         /* make sure we don't send anything to the i2c bus on 4020 */
3725         devpriv->plx_control_bits |= PLX_CNTRL_USERO;
3726         writel(devpriv->plx_control_bits, plx_control_addr);
3727         /* activate serial eeprom */
3728         udelay(eeprom_udelay);
3729         devpriv->plx_control_bits |= PLX_CNTRL_EECS;
3730         writel(devpriv->plx_control_bits, plx_control_addr);
3731
3732         /* write read command and desired memory address */
3733         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3734                 /* set bit to be written */
3735                 udelay(eeprom_udelay);
3736                 if (bitstream & bit)
3737                         devpriv->plx_control_bits |= PLX_CNTRL_EEWB;
3738                 else
3739                         devpriv->plx_control_bits &= ~PLX_CNTRL_EEWB;
3740                 writel(devpriv->plx_control_bits, plx_control_addr);
3741                 /* clock in bit */
3742                 udelay(eeprom_udelay);
3743                 devpriv->plx_control_bits |= PLX_CNTRL_EESK;
3744                 writel(devpriv->plx_control_bits, plx_control_addr);
3745                 udelay(eeprom_udelay);
3746                 devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;
3747                 writel(devpriv->plx_control_bits, plx_control_addr);
3748         }
3749         /* read back value from eeprom memory location */
3750         value = 0;
3751         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3752                 /* clock out bit */
3753                 udelay(eeprom_udelay);
3754                 devpriv->plx_control_bits |= PLX_CNTRL_EESK;
3755                 writel(devpriv->plx_control_bits, plx_control_addr);
3756                 udelay(eeprom_udelay);
3757                 devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;
3758                 writel(devpriv->plx_control_bits, plx_control_addr);
3759                 udelay(eeprom_udelay);
3760                 if (readl(plx_control_addr) & PLX_CNTRL_EERB)
3761                         value |= bit;
3762         }
3763
3764         /* deactivate eeprom serial input */
3765         udelay(eeprom_udelay);
3766         devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;
3767         writel(devpriv->plx_control_bits, plx_control_addr);
3768
3769         return value;
3770 }
3771
3772 static int eeprom_read_insn(struct comedi_device *dev,
3773                             struct comedi_subdevice *s,
3774                             struct comedi_insn *insn, unsigned int *data)
3775 {
3776         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3777
3778         return 1;
3779 }
3780
3781 /* Allocate and initialize the subdevice structures. */
3782 static int setup_subdevices(struct comedi_device *dev)
3783 {
3784         const struct pcidas64_board *board = dev->board_ptr;
3785         struct pcidas64_private *devpriv = dev->private;
3786         struct comedi_subdevice *s;
3787         int i;
3788         int ret;
3789
3790         ret = comedi_alloc_subdevices(dev, 10);
3791         if (ret)
3792                 return ret;
3793
3794         s = &dev->subdevices[0];
3795         /* analog input subdevice */
3796         dev->read_subdev = s;
3797         s->type = COMEDI_SUBD_AI;
3798         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3799         if (board->layout == LAYOUT_60XX)
3800                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3801         else if (board->layout == LAYOUT_64XX)
3802                 s->subdev_flags |= SDF_DIFF;
3803         /* XXX Number of inputs in differential mode is ignored */
3804         s->n_chan = board->ai_se_chans;
3805         s->len_chanlist = 0x2000;
3806         s->maxdata = (1 << board->ai_bits) - 1;
3807         s->range_table = board->ai_range_table;
3808         s->insn_read = ai_rinsn;
3809         s->insn_config = ai_config_insn;
3810         s->do_cmd = ai_cmd;
3811         s->do_cmdtest = ai_cmdtest;
3812         s->cancel = ai_cancel;
3813         if (board->layout == LAYOUT_4020) {
3814                 u8 data;
3815                 /*
3816                  * set adc to read from inputs
3817                  * (not internal calibration sources)
3818                  */
3819                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3820                 /* set channels to +-5 volt input ranges */
3821                 for (i = 0; i < s->n_chan; i++)
3822                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3823                 data = devpriv->i2c_cal_range_bits;
3824                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3825         }
3826
3827         /* analog output subdevice */
3828         s = &dev->subdevices[1];
3829         if (board->ao_nchan) {
3830                 s->type = COMEDI_SUBD_AO;
3831                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3832                                   SDF_GROUND | SDF_CMD_WRITE;
3833                 s->n_chan = board->ao_nchan;
3834                 s->maxdata = (1 << board->ao_bits) - 1;
3835                 s->range_table = board->ao_range_table;
3836                 s->insn_write = ao_winsn;
3837
3838                 ret = comedi_alloc_subdev_readback(s);
3839                 if (ret)
3840                         return ret;
3841
3842                 if (ao_cmd_is_supported(board)) {
3843                         dev->write_subdev = s;
3844                         s->do_cmdtest = ao_cmdtest;
3845                         s->do_cmd = ao_cmd;
3846                         s->len_chanlist = board->ao_nchan;
3847                         s->cancel = ao_cancel;
3848                 }
3849         } else {
3850                 s->type = COMEDI_SUBD_UNUSED;
3851         }
3852
3853         /* digital input */
3854         s = &dev->subdevices[2];
3855         if (board->layout == LAYOUT_64XX) {
3856                 s->type = COMEDI_SUBD_DI;
3857                 s->subdev_flags = SDF_READABLE;
3858                 s->n_chan = 4;
3859                 s->maxdata = 1;
3860                 s->range_table = &range_digital;
3861                 s->insn_bits = di_rbits;
3862         } else {
3863                 s->type = COMEDI_SUBD_UNUSED;
3864         }
3865
3866         /* digital output */
3867         if (board->layout == LAYOUT_64XX) {
3868                 s = &dev->subdevices[3];
3869                 s->type = COMEDI_SUBD_DO;
3870                 s->subdev_flags = SDF_WRITABLE;
3871                 s->n_chan = 4;
3872                 s->maxdata = 1;
3873                 s->range_table = &range_digital;
3874                 s->insn_bits = do_wbits;
3875         } else {
3876                 s->type = COMEDI_SUBD_UNUSED;
3877         }
3878
3879         /* 8255 */
3880         s = &dev->subdevices[4];
3881         if (board->has_8255) {
3882                 if (board->layout == LAYOUT_4020) {
3883                         ret = subdev_8255_init(dev, s, dio_callback_4020,
3884                                                I8255_4020_REG);
3885                 } else {
3886                         ret = subdev_8255_mm_init(dev, s, NULL,
3887                                                   DIO_8255_OFFSET);
3888                 }
3889                 if (ret)
3890                         return ret;
3891         } else {
3892                 s->type = COMEDI_SUBD_UNUSED;
3893         }
3894
3895         /* 8 channel dio for 60xx */
3896         s = &dev->subdevices[5];
3897         if (board->layout == LAYOUT_60XX) {
3898                 s->type = COMEDI_SUBD_DIO;
3899                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3900                 s->n_chan = 8;
3901                 s->maxdata = 1;
3902                 s->range_table = &range_digital;
3903                 s->insn_config = dio_60xx_config_insn;
3904                 s->insn_bits = dio_60xx_wbits;
3905         } else {
3906                 s->type = COMEDI_SUBD_UNUSED;
3907         }
3908
3909         /* caldac */
3910         s = &dev->subdevices[6];
3911         s->type = COMEDI_SUBD_CALIB;
3912         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3913         s->n_chan = 8;
3914         if (board->layout == LAYOUT_4020)
3915                 s->maxdata = 0xfff;
3916         else
3917                 s->maxdata = 0xff;
3918         s->insn_write = cb_pcidas64_calib_insn_write;
3919
3920         ret = comedi_alloc_subdev_readback(s);
3921         if (ret)
3922                 return ret;
3923
3924         for (i = 0; i < s->n_chan; i++) {
3925                 caldac_write(dev, i, s->maxdata / 2);
3926                 s->readback[i] = s->maxdata / 2;
3927         }
3928
3929         /* 2 channel ad8402 potentiometer */
3930         s = &dev->subdevices[7];
3931         if (board->layout == LAYOUT_64XX) {
3932                 s->type = COMEDI_SUBD_CALIB;
3933                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3934                 s->n_chan = 2;
3935                 s->maxdata = 0xff;
3936                 s->insn_write = cb_pcidas64_ad8402_insn_write;
3937
3938                 ret = comedi_alloc_subdev_readback(s);
3939                 if (ret)
3940                         return ret;
3941
3942                 for (i = 0; i < s->n_chan; i++) {
3943                         ad8402_write(dev, i, s->maxdata / 2);
3944                         s->readback[i] = s->maxdata / 2;
3945                 }
3946         } else {
3947                 s->type = COMEDI_SUBD_UNUSED;
3948         }
3949
3950         /* serial EEPROM, if present */
3951         s = &dev->subdevices[8];
3952         if (readl(devpriv->plx9080_iobase + PLX_REG_CNTRL) &
3953             PLX_CNTRL_EEPRESENT) {
3954                 s->type = COMEDI_SUBD_MEMORY;
3955                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
3956                 s->n_chan = 128;
3957                 s->maxdata = 0xffff;
3958                 s->insn_read = eeprom_read_insn;
3959         } else {
3960                 s->type = COMEDI_SUBD_UNUSED;
3961         }
3962
3963         /* user counter subd XXX */
3964         s = &dev->subdevices[9];
3965         s->type = COMEDI_SUBD_UNUSED;
3966
3967         return 0;
3968 }
3969
3970 static int auto_attach(struct comedi_device *dev,
3971                        unsigned long context)
3972 {
3973         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
3974         const struct pcidas64_board *board = NULL;
3975         struct pcidas64_private *devpriv;
3976         u32 local_range, local_decode;
3977         int retval;
3978
3979         if (context < ARRAY_SIZE(pcidas64_boards))
3980                 board = &pcidas64_boards[context];
3981         if (!board)
3982                 return -ENODEV;
3983         dev->board_ptr = board;
3984
3985         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
3986         if (!devpriv)
3987                 return -ENOMEM;
3988
3989         retval = comedi_pci_enable(dev);
3990         if (retval)
3991                 return retval;
3992         pci_set_master(pcidev);
3993
3994         /* Initialize dev->board_name */
3995         dev->board_name = board->name;
3996
3997         devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
3998         devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
3999
4000         devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
4001         devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
4002         dev->mmio = pci_ioremap_bar(pcidev, 3);
4003
4004         if (!devpriv->plx9080_iobase || !devpriv->main_iobase || !dev->mmio) {
4005                 dev_warn(dev->class_dev, "failed to remap io memory\n");
4006                 return -ENOMEM;
4007         }
4008
4009         /* figure out what local addresses are */
4010         local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS0RR) &
4011                       PLX_LASRR_MEM_MASK;
4012         local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) &
4013                        local_range & PLX_LASBA_MEM_MASK;
4014         devpriv->local0_iobase = ((u32)devpriv->main_phys_iobase &
4015                                   ~local_range) | local_decode;
4016         local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS1RR) &
4017                       PLX_LASRR_MEM_MASK;
4018         local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS1BA) &
4019                        local_range & PLX_LASBA_MEM_MASK;
4020         devpriv->local1_iobase = ((u32)devpriv->dio_counter_phys_iobase &
4021                                   ~local_range) | local_decode;
4022
4023         retval = alloc_and_init_dma_members(dev);
4024         if (retval < 0)
4025                 return retval;
4026
4027         devpriv->hw_revision =
4028                 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
4029         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
4030                 devpriv->hw_revision);
4031         init_plx9080(dev);
4032         init_stc_registers(dev);
4033
4034         retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4035                              "cb_pcidas64", dev);
4036         if (retval) {
4037                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4038                         pcidev->irq);
4039                 return retval;
4040         }
4041         dev->irq = pcidev->irq;
4042         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4043
4044         retval = setup_subdevices(dev);
4045         if (retval < 0)
4046                 return retval;
4047
4048         return 0;
4049 }
4050
4051 static void detach(struct comedi_device *dev)
4052 {
4053         struct pcidas64_private *devpriv = dev->private;
4054
4055         if (dev->irq)
4056                 free_irq(dev->irq, dev);
4057         if (devpriv) {
4058                 if (devpriv->plx9080_iobase) {
4059                         disable_plx_interrupts(dev);
4060                         iounmap(devpriv->plx9080_iobase);
4061                 }
4062                 if (devpriv->main_iobase)
4063                         iounmap(devpriv->main_iobase);
4064                 if (dev->mmio)
4065                         iounmap(dev->mmio);
4066         }
4067         comedi_pci_disable(dev);
4068         cb_pcidas64_free_dma(dev);
4069 }
4070
4071 static struct comedi_driver cb_pcidas64_driver = {
4072         .driver_name    = "cb_pcidas64",
4073         .module         = THIS_MODULE,
4074         .auto_attach    = auto_attach,
4075         .detach         = detach,
4076 };
4077
4078 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4079                                  const struct pci_device_id *id)
4080 {
4081         return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4082                                       id->driver_data);
4083 }
4084
4085 static const struct pci_device_id cb_pcidas64_pci_table[] = {
4086         { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4087         { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4088         { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4089         { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4090         { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4091         { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4092         { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4093         { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4094         { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4095         { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4096         { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4097         { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4098         { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4099         { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4100         { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4101         { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4102         { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4103         { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4104         { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4105         { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4106         { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4107         { 0 }
4108 };
4109 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4110
4111 static struct pci_driver cb_pcidas64_pci_driver = {
4112         .name           = "cb_pcidas64",
4113         .id_table       = cb_pcidas64_pci_table,
4114         .probe          = cb_pcidas64_pci_probe,
4115         .remove         = comedi_pci_auto_unconfig,
4116 };
4117 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4118
4119 MODULE_AUTHOR("Comedi http://www.comedi.org");
4120 MODULE_DESCRIPTION("Comedi low-level driver");
4121 MODULE_LICENSE("GPL");