drivers/staging/comedi/drivers/ni_mio_common.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Hardware driver for DAQ-STC based boards
   4  *
   5  * COMEDI - Linux Control and Measurement Device Interface
   6  * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7  * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8  */
   9
  10 /*
  11  * This file is meant to be included by another file, e.g.,
  12  * ni_atmio.c or ni_pcimio.c.
  13  *
  14  * Interrupt support originally added by Truxton Fulton <trux@truxton.com>
  15  *
  16  * References (ftp://ftp.natinst.com/support/manuals):
  17  *   340747b.pdf  AT-MIO E series Register Level Programmer Manual
  18  *   341079b.pdf  PCI E Series RLPM
  19  *   340934b.pdf  DAQ-STC reference manual
  20  *
  21  * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  22  *   release_ni611x.pdf
  23  *   release_ni67xx.pdf
  24  *
  25  * Other possibly relevant info:
  26  *   320517c.pdf  User manual (obsolete)
  27  *   320517f.pdf  User manual (new)
  28  *   320889a.pdf  delete
  29  *   320906c.pdf  maximum signal ratings
  30  *   321066a.pdf  about 16x
  31  *   321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  32  *   321808a.pdf  about at-mio-16e-10 rev P
  33  *   321837a.pdf  discontinuation of at-mio-16de-10 rev d
  34  *   321838a.pdf  about at-mio-16de-10 rev N
  35  *
  36  * ISSUES:
  37  *   - the interrupt routine needs to be cleaned up
  38  *
  39  * 2006-02-07: S-Series PCI-6143: Support has been added but is not
  40  * fully tested as yet. Terry Barnaby, BEAM Ltd.
  41  */
  42
  43 #include <linux/interrupt.h>
  44 #include <linux/sched.h>
  45 #include <linux/delay.h>
  46 #include "8255.h"
  47 #include "mite.h"
  48
  49 /* A timeout count */
  50 #define NI_TIMEOUT 1000
  51
  52 /* Note: this table must match the ai_gain_* definitions */
  53 static const short ni_gainlkup[][16] = {
  54         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  55                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  56         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  57         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  58                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  59         [ai_gain_4] = {0, 1, 4, 7},
  60         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  61                           0x003, 0x004, 0x005, 0x006},
  62         [ai_gain_622x] = {0, 1, 4, 5},
  63         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  64         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  65 };
  66
  67 static const struct comedi_lrange range_ni_E_ai = {
  68         16, {
  69                 BIP_RANGE(10),
  70                 BIP_RANGE(5),
  71                 BIP_RANGE(2.5),
  72                 BIP_RANGE(1),
  73                 BIP_RANGE(0.5),
  74                 BIP_RANGE(0.25),
  75                 BIP_RANGE(0.1),
  76                 BIP_RANGE(0.05),
  77                 UNI_RANGE(20),
  78                 UNI_RANGE(10),
  79                 UNI_RANGE(5),
  80                 UNI_RANGE(2),
  81                 UNI_RANGE(1),
  82                 UNI_RANGE(0.5),
  83                 UNI_RANGE(0.2),
  84                 UNI_RANGE(0.1)
  85         }
  86 };
  87
  88 static const struct comedi_lrange range_ni_E_ai_limited = {
  89         8, {
  90                 BIP_RANGE(10),
  91                 BIP_RANGE(5),
  92                 BIP_RANGE(1),
  93                 BIP_RANGE(0.1),
  94                 UNI_RANGE(10),
  95                 UNI_RANGE(5),
  96                 UNI_RANGE(1),
  97                 UNI_RANGE(0.1)
  98         }
  99 };
 100
 101 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 102         14, {
 103                 BIP_RANGE(10),
 104                 BIP_RANGE(5),
 105                 BIP_RANGE(2),
 106                 BIP_RANGE(1),
 107                 BIP_RANGE(0.5),
 108                 BIP_RANGE(0.2),
 109                 BIP_RANGE(0.1),
 110                 UNI_RANGE(10),
 111                 UNI_RANGE(5),
 112                 UNI_RANGE(2),
 113                 UNI_RANGE(1),
 114                 UNI_RANGE(0.5),
 115                 UNI_RANGE(0.2),
 116                 UNI_RANGE(0.1)
 117         }
 118 };
 119
 120 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 121         4, {
 122                 BIP_RANGE(10),
 123                 BIP_RANGE(5),
 124                 BIP_RANGE(0.5),
 125                 BIP_RANGE(0.05)
 126         }
 127 };
 128
 129 static const struct comedi_lrange range_ni_E_ai_611x = {
 130         8, {
 131                 BIP_RANGE(50),
 132                 BIP_RANGE(20),
 133                 BIP_RANGE(10),
 134                 BIP_RANGE(5),
 135                 BIP_RANGE(2),
 136                 BIP_RANGE(1),
 137                 BIP_RANGE(0.5),
 138                 BIP_RANGE(0.2)
 139         }
 140 };
 141
 142 static const struct comedi_lrange range_ni_M_ai_622x = {
 143         4, {
 144                 BIP_RANGE(10),
 145                 BIP_RANGE(5),
 146                 BIP_RANGE(1),
 147                 BIP_RANGE(0.2)
 148         }
 149 };
 150
 151 static const struct comedi_lrange range_ni_M_ai_628x = {
 152         7, {
 153                 BIP_RANGE(10),
 154                 BIP_RANGE(5),
 155                 BIP_RANGE(2),
 156                 BIP_RANGE(1),
 157                 BIP_RANGE(0.5),
 158                 BIP_RANGE(0.2),
 159                 BIP_RANGE(0.1)
 160         }
 161 };
 162
 163 static const struct comedi_lrange range_ni_E_ao_ext = {
 164         4, {
 165                 BIP_RANGE(10),
 166                 UNI_RANGE(10),
 167                 RANGE_ext(-1, 1),
 168                 RANGE_ext(0, 1)
 169         }
 170 };
 171
 172 static const struct comedi_lrange *const ni_range_lkup[] = {
 173         [ai_gain_16] = &range_ni_E_ai,
 174         [ai_gain_8] = &range_ni_E_ai_limited,
 175         [ai_gain_14] = &range_ni_E_ai_limited14,
 176         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 177         [ai_gain_611x] = &range_ni_E_ai_611x,
 178         [ai_gain_622x] = &range_ni_M_ai_622x,
 179         [ai_gain_628x] = &range_ni_M_ai_628x,
 180         [ai_gain_6143] = &range_bipolar5
 181 };
 182
 183 enum aimodes {
 184         AIMODE_NONE = 0,
 185         AIMODE_HALF_FULL = 1,
 186         AIMODE_SCAN = 2,
 187         AIMODE_SAMPLE = 3,
 188 };
 189
 190 enum ni_common_subdevices {
 191         NI_AI_SUBDEV,
 192         NI_AO_SUBDEV,
 193         NI_DIO_SUBDEV,
 194         NI_8255_DIO_SUBDEV,
 195         NI_UNUSED_SUBDEV,
 196         NI_CALIBRATION_SUBDEV,
 197         NI_EEPROM_SUBDEV,
 198         NI_PFI_DIO_SUBDEV,
 199         NI_CS5529_CALIBRATION_SUBDEV,
 200         NI_SERIAL_SUBDEV,
 201         NI_RTSI_SUBDEV,
 202         NI_GPCT0_SUBDEV,
 203         NI_GPCT1_SUBDEV,
 204         NI_FREQ_OUT_SUBDEV,
 205         NI_NUM_SUBDEVICES
 206 };
 207
 208 #define NI_GPCT_SUBDEV(x)       (NI_GPCT0_SUBDEV + (x))
 209
 210 enum timebase_nanoseconds {
 211         TIMEBASE_1_NS = 50,
 212         TIMEBASE_2_NS = 10000
 213 };
 214
 215 #define SERIAL_DISABLED         0
 216 #define SERIAL_600NS            600
 217 #define SERIAL_1_2US            1200
 218 #define SERIAL_10US                     10000
 219
 220 static const int num_adc_stages_611x = 3;
 221
 222 static void ni_writel(struct comedi_device *dev, unsigned int data, int reg)
 223 {
 224         if (dev->mmio)
 225                 writel(data, dev->mmio + reg);
 226         else
 227                 outl(data, dev->iobase + reg);
 228 }
 229
 230 static void ni_writew(struct comedi_device *dev, unsigned int data, int reg)
 231 {
 232         if (dev->mmio)
 233                 writew(data, dev->mmio + reg);
 234         else
 235                 outw(data, dev->iobase + reg);
 236 }
 237
 238 static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg)
 239 {
 240         if (dev->mmio)
 241                 writeb(data, dev->mmio + reg);
 242         else
 243                 outb(data, dev->iobase + reg);
 244 }
 245
 246 static unsigned int ni_readl(struct comedi_device *dev, int reg)
 247 {
 248         if (dev->mmio)
 249                 return readl(dev->mmio + reg);
 250
 251         return inl(dev->iobase + reg);
 252 }
 253
 254 static unsigned int ni_readw(struct comedi_device *dev, int reg)
 255 {
 256         if (dev->mmio)
 257                 return readw(dev->mmio + reg);
 258
 259         return inw(dev->iobase + reg);
 260 }
 261
 262 static unsigned int ni_readb(struct comedi_device *dev, int reg)
 263 {
 264         if (dev->mmio)
 265                 return readb(dev->mmio + reg);
 266
 267         return inb(dev->iobase + reg);
 268 }
 269
 270 /*
 271  * We automatically take advantage of STC registers that can be
 272  * read/written directly in the I/O space of the board.
 273  *
 274  * The AT-MIO and DAQCard devices map the low 8 STC registers to
 275  * iobase+reg*2.
 276  *
 277  * Most PCIMIO devices also map the low 8 STC registers but the
 278  * 611x devices map the read registers to iobase+(addr-1)*2.
 279  * For now non-windowed STC access is disabled if a PCIMIO device
 280  * is detected (devpriv->mite has been initialized).
 281  *
 282  * The M series devices do not used windowed registers for the
 283  * STC registers. The functions below handle the mapping of the
 284  * windowed STC registers to the m series register offsets.
 285  */
 286
 287 struct mio_regmap {
 288         unsigned int mio_reg;
 289         int size;
 290 };
 291
 292 static const struct mio_regmap m_series_stc_write_regmap[] = {
 293         [NISTC_INTA_ACK_REG]            = { 0x104, 2 },
 294         [NISTC_INTB_ACK_REG]            = { 0x106, 2 },
 295         [NISTC_AI_CMD2_REG]             = { 0x108, 2 },
 296         [NISTC_AO_CMD2_REG]             = { 0x10a, 2 },
 297         [NISTC_G0_CMD_REG]              = { 0x10c, 2 },
 298         [NISTC_G1_CMD_REG]              = { 0x10e, 2 },
 299         [NISTC_AI_CMD1_REG]             = { 0x110, 2 },
 300         [NISTC_AO_CMD1_REG]             = { 0x112, 2 },
 301         /*
 302          * NISTC_DIO_OUT_REG maps to:
 303          * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
 304          */
 305         [NISTC_DIO_OUT_REG]             = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 306         [NISTC_DIO_CTRL_REG]            = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 307         [NISTC_AI_MODE1_REG]            = { 0x118, 2 },
 308         [NISTC_AI_MODE2_REG]            = { 0x11a, 2 },
 309         [NISTC_AI_SI_LOADA_REG]         = { 0x11c, 4 },
 310         [NISTC_AI_SI_LOADB_REG]         = { 0x120, 4 },
 311         [NISTC_AI_SC_LOADA_REG]         = { 0x124, 4 },
 312         [NISTC_AI_SC_LOADB_REG]         = { 0x128, 4 },
 313         [NISTC_AI_SI2_LOADA_REG]        = { 0x12c, 4 },
 314         [NISTC_AI_SI2_LOADB_REG]        = { 0x130, 4 },
 315         [NISTC_G0_MODE_REG]             = { 0x134, 2 },
 316         [NISTC_G1_MODE_REG]             = { 0x136, 2 },
 317         [NISTC_G0_LOADA_REG]            = { 0x138, 4 },
 318         [NISTC_G0_LOADB_REG]            = { 0x13c, 4 },
 319         [NISTC_G1_LOADA_REG]            = { 0x140, 4 },
 320         [NISTC_G1_LOADB_REG]            = { 0x144, 4 },
 321         [NISTC_G0_INPUT_SEL_REG]        = { 0x148, 2 },
 322         [NISTC_G1_INPUT_SEL_REG]        = { 0x14a, 2 },
 323         [NISTC_AO_MODE1_REG]            = { 0x14c, 2 },
 324         [NISTC_AO_MODE2_REG]            = { 0x14e, 2 },
 325         [NISTC_AO_UI_LOADA_REG]         = { 0x150, 4 },
 326         [NISTC_AO_UI_LOADB_REG]         = { 0x154, 4 },
 327         [NISTC_AO_BC_LOADA_REG]         = { 0x158, 4 },
 328         [NISTC_AO_BC_LOADB_REG]         = { 0x15c, 4 },
 329         [NISTC_AO_UC_LOADA_REG]         = { 0x160, 4 },
 330         [NISTC_AO_UC_LOADB_REG]         = { 0x164, 4 },
 331         [NISTC_CLK_FOUT_REG]            = { 0x170, 2 },
 332         [NISTC_IO_BIDIR_PIN_REG]        = { 0x172, 2 },
 333         [NISTC_RTSI_TRIG_DIR_REG]       = { 0x174, 2 },
 334         [NISTC_INT_CTRL_REG]            = { 0x176, 2 },
 335         [NISTC_AI_OUT_CTRL_REG]         = { 0x178, 2 },
 336         [NISTC_ATRIG_ETC_REG]           = { 0x17a, 2 },
 337         [NISTC_AI_START_STOP_REG]       = { 0x17c, 2 },
 338         [NISTC_AI_TRIG_SEL_REG]         = { 0x17e, 2 },
 339         [NISTC_AI_DIV_LOADA_REG]        = { 0x180, 4 },
 340         [NISTC_AO_START_SEL_REG]        = { 0x184, 2 },
 341         [NISTC_AO_TRIG_SEL_REG]         = { 0x186, 2 },
 342         [NISTC_G0_AUTOINC_REG]          = { 0x188, 2 },
 343         [NISTC_G1_AUTOINC_REG]          = { 0x18a, 2 },
 344         [NISTC_AO_MODE3_REG]            = { 0x18c, 2 },
 345         [NISTC_RESET_REG]               = { 0x190, 2 },
 346         [NISTC_INTA_ENA_REG]            = { 0x192, 2 },
 347         [NISTC_INTA2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 348         [NISTC_INTB_ENA_REG]            = { 0x196, 2 },
 349         [NISTC_INTB2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 350         [NISTC_AI_PERSONAL_REG]         = { 0x19a, 2 },
 351         [NISTC_AO_PERSONAL_REG]         = { 0x19c, 2 },
 352         [NISTC_RTSI_TRIGA_OUT_REG]      = { 0x19e, 2 },
 353         [NISTC_RTSI_TRIGB_OUT_REG]      = { 0x1a0, 2 },
 354         [NISTC_RTSI_BOARD_REG]          = { 0, 0 }, /* Unknown */
 355         [NISTC_CFG_MEM_CLR_REG]         = { 0x1a4, 2 },
 356         [NISTC_ADC_FIFO_CLR_REG]        = { 0x1a6, 2 },
 357         [NISTC_DAC_FIFO_CLR_REG]        = { 0x1a8, 2 },
 358         [NISTC_AO_OUT_CTRL_REG]         = { 0x1ac, 2 },
 359         [NISTC_AI_MODE3_REG]            = { 0x1ae, 2 },
 360 };
 361
 362 static void m_series_stc_write(struct comedi_device *dev,
 363                                unsigned int data, unsigned int reg)
 364 {
 365         const struct mio_regmap *regmap;
 366
 367         if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
 368                 regmap = &m_series_stc_write_regmap[reg];
 369         } else {
 370                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 371                          __func__, reg);
 372                 return;
 373         }
 374
 375         switch (regmap->size) {
 376         case 4:
 377                 ni_writel(dev, data, regmap->mio_reg);
 378                 break;
 379         case 2:
 380                 ni_writew(dev, data, regmap->mio_reg);
 381                 break;
 382         default:
 383                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 384                          __func__, reg);
 385                 break;
 386         }
 387 }
 388
 389 static const struct mio_regmap m_series_stc_read_regmap[] = {
 390         [NISTC_AI_STATUS1_REG]          = { 0x104, 2 },
 391         [NISTC_AO_STATUS1_REG]          = { 0x106, 2 },
 392         [NISTC_G01_STATUS_REG]          = { 0x108, 2 },
 393         [NISTC_AI_STATUS2_REG]          = { 0, 0 }, /* Unknown */
 394         [NISTC_AO_STATUS2_REG]          = { 0x10c, 2 },
 395         [NISTC_DIO_IN_REG]              = { 0, 0 }, /* Unknown */
 396         [NISTC_G0_HW_SAVE_REG]          = { 0x110, 4 },
 397         [NISTC_G1_HW_SAVE_REG]          = { 0x114, 4 },
 398         [NISTC_G0_SAVE_REG]             = { 0x118, 4 },
 399         [NISTC_G1_SAVE_REG]             = { 0x11c, 4 },
 400         [NISTC_AO_UI_SAVE_REG]          = { 0x120, 4 },
 401         [NISTC_AO_BC_SAVE_REG]          = { 0x124, 4 },
 402         [NISTC_AO_UC_SAVE_REG]          = { 0x128, 4 },
 403         [NISTC_STATUS1_REG]             = { 0x136, 2 },
 404         [NISTC_DIO_SERIAL_IN_REG]       = { 0x009, 1 },
 405         [NISTC_STATUS2_REG]             = { 0x13a, 2 },
 406         [NISTC_AI_SI_SAVE_REG]          = { 0x180, 4 },
 407         [NISTC_AI_SC_SAVE_REG]          = { 0x184, 4 },
 408 };
 409
 410 static unsigned int m_series_stc_read(struct comedi_device *dev,
 411                                       unsigned int reg)
 412 {
 413         const struct mio_regmap *regmap;
 414
 415         if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
 416                 regmap = &m_series_stc_read_regmap[reg];
 417         } else {
 418                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 419                          __func__, reg);
 420                 return 0;
 421         }
 422
 423         switch (regmap->size) {
 424         case 4:
 425                 return ni_readl(dev, regmap->mio_reg);
 426         case 2:
 427                 return ni_readw(dev, regmap->mio_reg);
 428         case 1:
 429                 return ni_readb(dev, regmap->mio_reg);
 430         default:
 431                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 432                          __func__, reg);
 433                 return 0;
 434         }
 435 }
 436
 437 static void ni_stc_writew(struct comedi_device *dev,
 438                           unsigned int data, int reg)
 439 {
 440         struct ni_private *devpriv = dev->private;
 441         unsigned long flags;
 442
 443         if (devpriv->is_m_series) {
 444                 m_series_stc_write(dev, data, reg);
 445         } else {
 446                 spin_lock_irqsave(&devpriv->window_lock, flags);
 447                 if (!devpriv->mite && reg < 8) {
 448                         ni_writew(dev, data, reg * 2);
 449                 } else {
 450                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 451                         ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
 452                 }
 453                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 454         }
 455 }
 456
 457 static void ni_stc_writel(struct comedi_device *dev,
 458                           unsigned int data, int reg)
 459 {
 460         struct ni_private *devpriv = dev->private;
 461
 462         if (devpriv->is_m_series) {
 463                 m_series_stc_write(dev, data, reg);
 464         } else {
 465                 ni_stc_writew(dev, data >> 16, reg);
 466                 ni_stc_writew(dev, data & 0xffff, reg + 1);
 467         }
 468 }
 469
 470 static unsigned int ni_stc_readw(struct comedi_device *dev, int reg)
 471 {
 472         struct ni_private *devpriv = dev->private;
 473         unsigned long flags;
 474         unsigned int val;
 475
 476         if (devpriv->is_m_series) {
 477                 val = m_series_stc_read(dev, reg);
 478         } else {
 479                 spin_lock_irqsave(&devpriv->window_lock, flags);
 480                 if (!devpriv->mite && reg < 8) {
 481                         val = ni_readw(dev, reg * 2);
 482                 } else {
 483                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 484                         val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
 485                 }
 486                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 487         }
 488         return val;
 489 }
 490
 491 static unsigned int ni_stc_readl(struct comedi_device *dev, int reg)
 492 {
 493         struct ni_private *devpriv = dev->private;
 494         unsigned int val;
 495
 496         if (devpriv->is_m_series) {
 497                 val = m_series_stc_read(dev, reg);
 498         } else {
 499                 val = ni_stc_readw(dev, reg) << 16;
 500                 val |= ni_stc_readw(dev, reg + 1);
 501         }
 502         return val;
 503 }
 504
 505 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 506                                    unsigned int bit_mask,
 507                                    unsigned int bit_values)
 508 {
 509         struct ni_private *devpriv = dev->private;
 510         unsigned long flags;
 511
 512         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 513         switch (reg) {
 514         case NISTC_INTA_ENA_REG:
 515                 devpriv->int_a_enable_reg &= ~bit_mask;
 516                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 517                 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
 518                 break;
 519         case NISTC_INTB_ENA_REG:
 520                 devpriv->int_b_enable_reg &= ~bit_mask;
 521                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 522                 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
 523                 break;
 524         case NISTC_IO_BIDIR_PIN_REG:
 525                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 526                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 527                 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
 528                 break;
 529         case NI_E_DMA_AI_AO_SEL_REG:
 530                 devpriv->ai_ao_select_reg &= ~bit_mask;
 531                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 532                 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
 533                 break;
 534         case NI_E_DMA_G0_G1_SEL_REG:
 535                 devpriv->g0_g1_select_reg &= ~bit_mask;
 536                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 537                 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
 538                 break;
 539         case NI_M_CDIO_DMA_SEL_REG:
 540                 devpriv->cdio_dma_select_reg &= ~bit_mask;
 541                 devpriv->cdio_dma_select_reg |= bit_values & bit_mask;
 542                 ni_writeb(dev, devpriv->cdio_dma_select_reg, reg);
 543                 break;
 544         default:
 545                 dev_err(dev->class_dev, "called with invalid register %d\n",
 546                         reg);
 547                 break;
 548         }
 549         mmiowb();
 550         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 551 }
 552
 553 #ifdef PCIDMA
 554
 555 /* selects the MITE channel to use for DMA */
 556 #define NI_STC_DMA_CHAN_SEL(x)  (((x) < 4) ? BIT(x) :   \
 557                                  ((x) == 4) ? 0x3 :     \
 558                                  ((x) == 5) ? 0x5 : 0x0)
 559
 560 /* DMA channel setup */
 561 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 562 {
 563         struct ni_private *devpriv = dev->private;
 564         struct mite_channel *mite_chan;
 565         unsigned long flags;
 566         unsigned int bits;
 567
 568         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 569         mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 570         if (!mite_chan) {
 571                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 572                 dev_err(dev->class_dev,
 573                         "failed to reserve mite dma channel for analog input\n");
 574                 return -EBUSY;
 575         }
 576         mite_chan->dir = COMEDI_INPUT;
 577         devpriv->ai_mite_chan = mite_chan;
 578
 579         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 580         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 581                         NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
 582
 583         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 584         return 0;
 585 }
 586
 587 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 588 {
 589         struct ni_private *devpriv = dev->private;
 590         struct mite_channel *mite_chan;
 591         unsigned long flags;
 592         unsigned int bits;
 593
 594         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 595         mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 596         if (!mite_chan) {
 597                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 598                 dev_err(dev->class_dev,
 599                         "failed to reserve mite dma channel for analog outut\n");
 600                 return -EBUSY;
 601         }
 602         mite_chan->dir = COMEDI_OUTPUT;
 603         devpriv->ao_mite_chan = mite_chan;
 604
 605         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 606         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 607                         NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
 608
 609         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 610         return 0;
 611 }
 612
 613 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 614                                         unsigned int gpct_index,
 615                                         enum comedi_io_direction direction)
 616 {
 617         struct ni_private *devpriv = dev->private;
 618         struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index];
 619         struct mite_channel *mite_chan;
 620         unsigned long flags;
 621         unsigned int bits;
 622
 623         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 624         mite_chan = mite_request_channel(devpriv->mite,
 625                                          devpriv->gpct_mite_ring[gpct_index]);
 626         if (!mite_chan) {
 627                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 628                 dev_err(dev->class_dev,
 629                         "failed to reserve mite dma channel for counter\n");
 630                 return -EBUSY;
 631         }
 632         mite_chan->dir = direction;
 633         ni_tio_set_mite_channel(counter, mite_chan);
 634
 635         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 636         ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 637                         NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
 638                         NI_E_DMA_G0_G1_SEL(gpct_index, bits));
 639
 640         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 641         return 0;
 642 }
 643
 644 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 645 {
 646         struct ni_private *devpriv = dev->private;
 647         struct mite_channel *mite_chan;
 648         unsigned long flags;
 649         unsigned int bits;
 650
 651         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 652         mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 653         if (!mite_chan) {
 654                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 655                 dev_err(dev->class_dev,
 656                         "failed to reserve mite dma channel for correlated digital output\n");
 657                 return -EBUSY;
 658         }
 659         mite_chan->dir = COMEDI_OUTPUT;
 660         devpriv->cdo_mite_chan = mite_chan;
 661
 662         /*
 663          * XXX just guessing NI_STC_DMA_CHAN_SEL()
 664          * returns the right bits, under the assumption the cdio dma
 665          * selection works just like ai/ao/gpct.
 666          * Definitely works for dma channels 0 and 1.
 667          */
 668         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 669         ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
 670                         NI_M_CDIO_DMA_SEL_CDO_MASK,
 671                         NI_M_CDIO_DMA_SEL_CDO(bits));
 672
 673         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 674         return 0;
 675 }
 676 #endif /*  PCIDMA */
 677
 678 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 679 {
 680 #ifdef PCIDMA
 681         struct ni_private *devpriv = dev->private;
 682         unsigned long flags;
 683
 684         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 685         if (devpriv->ai_mite_chan) {
 686                 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 687                                 NI_E_DMA_AI_SEL_MASK, 0);
 688                 mite_release_channel(devpriv->ai_mite_chan);
 689                 devpriv->ai_mite_chan = NULL;
 690         }
 691         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 692 #endif /*  PCIDMA */
 693 }
 694
 695 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 696 {
 697 #ifdef PCIDMA
 698         struct ni_private *devpriv = dev->private;
 699         unsigned long flags;
 700
 701         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 702         if (devpriv->ao_mite_chan) {
 703                 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 704                                 NI_E_DMA_AO_SEL_MASK, 0);
 705                 mite_release_channel(devpriv->ao_mite_chan);
 706                 devpriv->ao_mite_chan = NULL;
 707         }
 708         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 709 #endif /*  PCIDMA */
 710 }
 711
 712 #ifdef PCIDMA
 713 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 714                                          unsigned int gpct_index)
 715 {
 716         struct ni_private *devpriv = dev->private;
 717         unsigned long flags;
 718
 719         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 720         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 721                 struct mite_channel *mite_chan =
 722                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 723
 724                 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 725                                 NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
 726                 ni_tio_set_mite_channel(&devpriv->
 727                                         counter_dev->counters[gpct_index],
 728                                         NULL);
 729                 mite_release_channel(mite_chan);
 730         }
 731         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 732 }
 733
 734 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 735 {
 736         struct ni_private *devpriv = dev->private;
 737         unsigned long flags;
 738
 739         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 740         if (devpriv->cdo_mite_chan) {
 741                 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
 742                                 NI_M_CDIO_DMA_SEL_CDO_MASK, 0);
 743                 mite_release_channel(devpriv->cdo_mite_chan);
 744                 devpriv->cdo_mite_chan = NULL;
 745         }
 746         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 747 }
 748
 749 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 750                                           unsigned int gpct_index, short enable)
 751 {
 752         struct ni_private *devpriv = dev->private;
 753         unsigned int val = 0;
 754         int reg;
 755
 756         if (devpriv->is_m_series || gpct_index > 1)
 757                 return;
 758
 759         /*
 760          * e-series boards use the second irq signals to generate
 761          * dma requests for their counters
 762          */
 763         if (gpct_index == 0) {
 764                 reg = NISTC_INTA2_ENA_REG;
 765                 if (enable)
 766                         val = NISTC_INTA_ENA_G0_GATE;
 767         } else {
 768                 reg = NISTC_INTB2_ENA_REG;
 769                 if (enable)
 770                         val = NISTC_INTB_ENA_G1_GATE;
 771         }
 772         ni_stc_writew(dev, val, reg);
 773 }
 774 #endif /*  PCIDMA */
 775
 776 static void ni_clear_ai_fifo(struct comedi_device *dev)
 777 {
 778         struct ni_private *devpriv = dev->private;
 779         static const int timeout = 10000;
 780         int i;
 781
 782         if (devpriv->is_6143) {
 783                 /*  Flush the 6143 data FIFO */
 784                 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
 785                 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
 786                 /*  Wait for complete */
 787                 for (i = 0; i < timeout; i++) {
 788                         if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
 789                                 break;
 790                         udelay(1);
 791                 }
 792                 if (i == timeout)
 793                         dev_err(dev->class_dev, "FIFO flush timeout\n");
 794         } else {
 795                 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
 796                 if (devpriv->is_625x) {
 797                         ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
 798                         ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
 799 #if 0
 800                         /*
 801                          * The NI example code does 3 convert pulses for 625x
 802                          * boards, But that appears to be wrong in practice.
 803                          */
 804                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 805                                       NISTC_AI_CMD1_REG);
 806                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 807                                       NISTC_AI_CMD1_REG);
 808                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 809                                       NISTC_AI_CMD1_REG);
 810 #endif
 811                 }
 812         }
 813 }
 814
 815 static inline void ni_ao_win_outw(struct comedi_device *dev,
 816                                   unsigned int data, int addr)
 817 {
 818         struct ni_private *devpriv = dev->private;
 819         unsigned long flags;
 820
 821         spin_lock_irqsave(&devpriv->window_lock, flags);
 822         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 823         ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
 824         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 825 }
 826
 827 static inline void ni_ao_win_outl(struct comedi_device *dev,
 828                                   unsigned int data, int addr)
 829 {
 830         struct ni_private *devpriv = dev->private;
 831         unsigned long flags;
 832
 833         spin_lock_irqsave(&devpriv->window_lock, flags);
 834         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 835         ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
 836         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 837 }
 838
 839 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 840 {
 841         struct ni_private *devpriv = dev->private;
 842         unsigned long flags;
 843         unsigned short data;
 844
 845         spin_lock_irqsave(&devpriv->window_lock, flags);
 846         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 847         data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
 848         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 849         return data;
 850 }
 851
 852 /*
 853  * ni_set_bits( ) allows different parts of the ni_mio_common driver to
 854  * share registers (such as Interrupt_A_Register) without interfering with
 855  * each other.
 856  *
 857  * NOTE: the switch/case statements are optimized out for a constant argument
 858  * so this is actually quite fast---  If you must wrap another function around
 859  * this make it inline to avoid a large speed penalty.
 860  *
 861  * value should only be 1 or 0.
 862  */
 863 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 864                                unsigned int bits, unsigned int value)
 865 {
 866         unsigned int bit_values;
 867
 868         if (value)
 869                 bit_values = bits;
 870         else
 871                 bit_values = 0;
 872         ni_set_bitfield(dev, reg, bits, bit_values);
 873 }
 874
 875 #ifdef PCIDMA
 876 static void ni_sync_ai_dma(struct comedi_device *dev)
 877 {
 878         struct ni_private *devpriv = dev->private;
 879         struct comedi_subdevice *s = dev->read_subdev;
 880         unsigned long flags;
 881
 882         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 883         if (devpriv->ai_mite_chan)
 884                 mite_sync_dma(devpriv->ai_mite_chan, s);
 885         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 886 }
 887
 888 static int ni_ai_drain_dma(struct comedi_device *dev)
 889 {
 890         struct ni_private *devpriv = dev->private;
 891         int i;
 892         static const int timeout = 10000;
 893         unsigned long flags;
 894         int retval = 0;
 895
 896         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 897         if (devpriv->ai_mite_chan) {
 898                 for (i = 0; i < timeout; i++) {
 899                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
 900                              NISTC_AI_STATUS1_FIFO_E) &&
 901                             mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
 902                                 break;
 903                         udelay(5);
 904                 }
 905                 if (i == timeout) {
 906                         dev_err(dev->class_dev, "timed out\n");
 907                         dev_err(dev->class_dev,
 908                                 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
 909                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
 910                                 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
 911                         retval = -1;
 912                 }
 913         }
 914         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 915
 916         ni_sync_ai_dma(dev);
 917
 918         return retval;
 919 }
 920
 921 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 922 {
 923         static const int timeout = 10000;
 924         int i;
 925
 926         for (i = 0; i < timeout; i++) {
 927                 unsigned short b_status;
 928
 929                 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
 930                 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
 931                         break;
 932                 /*
 933                  * If we poll too often, the pci bus activity seems
 934                  * to slow the dma transfer down.
 935                  */
 936                 usleep_range(10, 100);
 937         }
 938         if (i == timeout) {
 939                 dev_err(dev->class_dev, "timed out waiting for dma load\n");
 940                 return -EPIPE;
 941         }
 942         return 0;
 943 }
 944 #endif /* PCIDMA */
 945
 946 #ifndef PCIDMA
 947
 948 static void ni_ao_fifo_load(struct comedi_device *dev,
 949                             struct comedi_subdevice *s, int n)
 950 {
 951         struct ni_private *devpriv = dev->private;
 952         int i;
 953         unsigned short d;
 954         unsigned int packed_data;
 955
 956         for (i = 0; i < n; i++) {
 957                 comedi_buf_read_samples(s, &d, 1);
 958
 959                 if (devpriv->is_6xxx) {
 960                         packed_data = d & 0xffff;
 961                         /* 6711 only has 16 bit wide ao fifo */
 962                         if (!devpriv->is_6711) {
 963                                 comedi_buf_read_samples(s, &d, 1);
 964                                 i++;
 965                                 packed_data |= (d << 16) & 0xffff0000;
 966                         }
 967                         ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
 968                 } else {
 969                         ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
 970                 }
 971         }
 972 }
 973
 974 /*
 975  *  There's a small problem if the FIFO gets really low and we
 976  *  don't have the data to fill it.  Basically, if after we fill
 977  *  the FIFO with all the data available, the FIFO is _still_
 978  *  less than half full, we never clear the interrupt.  If the
 979  *  IRQ is in edge mode, we never get another interrupt, because
 980  *  this one wasn't cleared.  If in level mode, we get flooded
 981  *  with interrupts that we can't fulfill, because nothing ever
 982  *  gets put into the buffer.
 983  *
 984  *  This kind of situation is recoverable, but it is easier to
 985  *  just pretend we had a FIFO underrun, since there is a good
 986  *  chance it will happen anyway.  This is _not_ the case for
 987  *  RT code, as RT code might purposely be running close to the
 988  *  metal.  Needs to be fixed eventually.
 989  */
 990 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
 991                                  struct comedi_subdevice *s)
 992 {
 993         const struct ni_board_struct *board = dev->board_ptr;
 994         unsigned int nbytes;
 995         unsigned int nsamples;
 996
 997         nbytes = comedi_buf_read_n_available(s);
 998         if (nbytes == 0) {
 999                 s->async->events |= COMEDI_CB_OVERFLOW;
1000                 return 0;
1001         }
1002
1003         nsamples = comedi_bytes_to_samples(s, nbytes);
1004         if (nsamples > board->ao_fifo_depth / 2)
1005                 nsamples = board->ao_fifo_depth / 2;
1006
1007         ni_ao_fifo_load(dev, s, nsamples);
1008
1009         return 1;
1010 }
1011
1012 static int ni_ao_prep_fifo(struct comedi_device *dev,
1013                            struct comedi_subdevice *s)
1014 {
1015         const struct ni_board_struct *board = dev->board_ptr;
1016         struct ni_private *devpriv = dev->private;
1017         unsigned int nbytes;
1018         unsigned int nsamples;
1019
1020         /* reset fifo */
1021         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1022         if (devpriv->is_6xxx)
1023                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1024
1025         /* load some data */
1026         nbytes = comedi_buf_read_n_available(s);
1027         if (nbytes == 0)
1028                 return 0;
1029
1030         nsamples = comedi_bytes_to_samples(s, nbytes);
1031         if (nsamples > board->ao_fifo_depth)
1032                 nsamples = board->ao_fifo_depth;
1033
1034         ni_ao_fifo_load(dev, s, nsamples);
1035
1036         return nsamples;
1037 }
1038
1039 static void ni_ai_fifo_read(struct comedi_device *dev,
1040                             struct comedi_subdevice *s, int n)
1041 {
1042         struct ni_private *devpriv = dev->private;
1043         struct comedi_async *async = s->async;
1044         unsigned int dl;
1045         unsigned short data;
1046         int i;
1047
1048         if (devpriv->is_611x) {
1049                 for (i = 0; i < n / 2; i++) {
1050                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1051                         /* This may get the hi/lo data in the wrong order */
1052                         data = (dl >> 16) & 0xffff;
1053                         comedi_buf_write_samples(s, &data, 1);
1054                         data = dl & 0xffff;
1055                         comedi_buf_write_samples(s, &data, 1);
1056                 }
1057                 /* Check if there's a single sample stuck in the FIFO */
1058                 if (n % 2) {
1059                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1060                         data = dl & 0xffff;
1061                         comedi_buf_write_samples(s, &data, 1);
1062                 }
1063         } else if (devpriv->is_6143) {
1064                 /*
1065                  * This just reads the FIFO assuming the data is present,
1066                  * no checks on the FIFO status are performed.
1067                  */
1068                 for (i = 0; i < n / 2; i++) {
1069                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1070
1071                         data = (dl >> 16) & 0xffff;
1072                         comedi_buf_write_samples(s, &data, 1);
1073                         data = dl & 0xffff;
1074                         comedi_buf_write_samples(s, &data, 1);
1075                 }
1076                 if (n % 2) {
1077                         /* Assume there is a single sample stuck in the FIFO */
1078                         /* Get stranded sample into FIFO */
1079                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1080                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1081                         data = (dl >> 16) & 0xffff;
1082                         comedi_buf_write_samples(s, &data, 1);
1083                 }
1084         } else {
1085                 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) {
1086                         dev_err(dev->class_dev,
1087                                 "bug! ai_fifo_buffer too small\n");
1088                         async->events |= COMEDI_CB_ERROR;
1089                         return;
1090                 }
1091                 for (i = 0; i < n; i++) {
1092                         devpriv->ai_fifo_buffer[i] =
1093                             ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1094                 }
1095                 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1096         }
1097 }
1098
1099 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1100 {
1101         const struct ni_board_struct *board = dev->board_ptr;
1102         struct comedi_subdevice *s = dev->read_subdev;
1103         int n;
1104
1105         n = board->ai_fifo_depth / 2;
1106
1107         ni_ai_fifo_read(dev, s, n);
1108 }
1109 #endif
1110
1111 /* Empties the AI fifo */
1112 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1113 {
1114         struct ni_private *devpriv = dev->private;
1115         struct comedi_subdevice *s = dev->read_subdev;
1116         unsigned int dl;
1117         unsigned short data;
1118         int i;
1119
1120         if (devpriv->is_611x) {
1121                 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1122                         NISTC_AI_STATUS1_FIFO_E) == 0) {
1123                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1124
1125                         /* This may get the hi/lo data in the wrong order */
1126                         data = dl >> 16;
1127                         comedi_buf_write_samples(s, &data, 1);
1128                         data = dl & 0xffff;
1129                         comedi_buf_write_samples(s, &data, 1);
1130                 }
1131         } else if (devpriv->is_6143) {
1132                 i = 0;
1133                 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1134                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1135
1136                         /* This may get the hi/lo data in the wrong order */
1137                         data = dl >> 16;
1138                         comedi_buf_write_samples(s, &data, 1);
1139                         data = dl & 0xffff;
1140                         comedi_buf_write_samples(s, &data, 1);
1141                         i += 2;
1142                 }
1143                 /*  Check if stranded sample is present */
1144                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1145                         /* Get stranded sample into FIFO */
1146                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1147                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1148                         data = (dl >> 16) & 0xffff;
1149                         comedi_buf_write_samples(s, &data, 1);
1150                 }
1151
1152         } else {
1153                 unsigned short fe;      /* fifo empty */
1154
1155                 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1156                      NISTC_AI_STATUS1_FIFO_E;
1157                 while (fe == 0) {
1158                         for (i = 0;
1159                              i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) {
1160                                 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1161                                      NISTC_AI_STATUS1_FIFO_E;
1162                                 if (fe)
1163                                         break;
1164                                 devpriv->ai_fifo_buffer[i] =
1165                                     ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1166                         }
1167                         comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1168                 }
1169         }
1170 }
1171
1172 static void get_last_sample_611x(struct comedi_device *dev)
1173 {
1174         struct ni_private *devpriv = dev->private;
1175         struct comedi_subdevice *s = dev->read_subdev;
1176         unsigned short data;
1177         unsigned int dl;
1178
1179         if (!devpriv->is_611x)
1180                 return;
1181
1182         /* Check if there's a single sample stuck in the FIFO */
1183         if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1184                 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1185                 data = dl & 0xffff;
1186                 comedi_buf_write_samples(s, &data, 1);
1187         }
1188 }
1189
1190 static void get_last_sample_6143(struct comedi_device *dev)
1191 {
1192         struct ni_private *devpriv = dev->private;
1193         struct comedi_subdevice *s = dev->read_subdev;
1194         unsigned short data;
1195         unsigned int dl;
1196
1197         if (!devpriv->is_6143)
1198                 return;
1199
1200         /* Check if there's a single sample stuck in the FIFO */
1201         if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1202                 /* Get stranded sample into FIFO */
1203                 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1204                 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1205
1206                 /* This may get the hi/lo data in the wrong order */
1207                 data = (dl >> 16) & 0xffff;
1208                 comedi_buf_write_samples(s, &data, 1);
1209         }
1210 }
1211
1212 static void shutdown_ai_command(struct comedi_device *dev)
1213 {
1214         struct comedi_subdevice *s = dev->read_subdev;
1215
1216 #ifdef PCIDMA
1217         ni_ai_drain_dma(dev);
1218 #endif
1219         ni_handle_fifo_dregs(dev);
1220         get_last_sample_611x(dev);
1221         get_last_sample_6143(dev);
1222
1223         s->async->events |= COMEDI_CB_EOA;
1224 }
1225
1226 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1227 {
1228         struct ni_private *devpriv = dev->private;
1229
1230         if (devpriv->aimode == AIMODE_SCAN) {
1231 #ifdef PCIDMA
1232                 static const int timeout = 10;
1233                 int i;
1234
1235                 for (i = 0; i < timeout; i++) {
1236                         ni_sync_ai_dma(dev);
1237                         if ((s->async->events & COMEDI_CB_EOS))
1238                                 break;
1239                         udelay(1);
1240                 }
1241 #else
1242                 ni_handle_fifo_dregs(dev);
1243                 s->async->events |= COMEDI_CB_EOS;
1244 #endif
1245         }
1246         /* handle special case of single scan */
1247         if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1248                 shutdown_ai_command(dev);
1249 }
1250
1251 static void handle_gpct_interrupt(struct comedi_device *dev,
1252                                   unsigned short counter_index)
1253 {
1254 #ifdef PCIDMA
1255         struct ni_private *devpriv = dev->private;
1256         struct comedi_subdevice *s;
1257
1258         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1259
1260         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1261                                 s);
1262         comedi_handle_events(dev, s);
1263 #endif
1264 }
1265
1266 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1267 {
1268         unsigned short ack = 0;
1269
1270         if (a_status & NISTC_AI_STATUS1_SC_TC)
1271                 ack |= NISTC_INTA_ACK_AI_SC_TC;
1272         if (a_status & NISTC_AI_STATUS1_START1)
1273                 ack |= NISTC_INTA_ACK_AI_START1;
1274         if (a_status & NISTC_AI_STATUS1_START)
1275                 ack |= NISTC_INTA_ACK_AI_START;
1276         if (a_status & NISTC_AI_STATUS1_STOP)
1277                 ack |= NISTC_INTA_ACK_AI_STOP;
1278         if (a_status & NISTC_AI_STATUS1_OVER)
1279                 ack |= NISTC_INTA_ACK_AI_ERR;
1280         if (ack)
1281                 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1282 }
1283
1284 static void handle_a_interrupt(struct comedi_device *dev,
1285                                struct comedi_subdevice *s,
1286                                unsigned short status)
1287 {
1288         struct comedi_cmd *cmd = &s->async->cmd;
1289
1290         /* test for all uncommon interrupt events at the same time */
1291         if (status & (NISTC_AI_STATUS1_ERR |
1292                       NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1293                 if (status == 0xffff) {
1294                         dev_err(dev->class_dev, "Card removed?\n");
1295                         /*
1296                          * We probably aren't even running a command now,
1297                          * so it's a good idea to be careful.
1298                          */
1299                         if (comedi_is_subdevice_running(s))
1300                                 s->async->events |= COMEDI_CB_ERROR;
1301                         return;
1302                 }
1303                 if (status & NISTC_AI_STATUS1_ERR) {
1304                         dev_err(dev->class_dev, "ai error a_status=%04x\n",
1305                                 status);
1306
1307                         shutdown_ai_command(dev);
1308
1309                         s->async->events |= COMEDI_CB_ERROR;
1310                         if (status & NISTC_AI_STATUS1_OVER)
1311                                 s->async->events |= COMEDI_CB_OVERFLOW;
1312                         return;
1313                 }
1314                 if (status & NISTC_AI_STATUS1_SC_TC) {
1315                         if (cmd->stop_src == TRIG_COUNT)
1316                                 shutdown_ai_command(dev);
1317                 }
1318         }
1319 #ifndef PCIDMA
1320         if (status & NISTC_AI_STATUS1_FIFO_HF) {
1321                 int i;
1322                 static const int timeout = 10;
1323                 /*
1324                  * PCMCIA cards (at least 6036) seem to stop producing
1325                  * interrupts if we fail to get the fifo less than half
1326                  * full, so loop to be sure.
1327                  */
1328                 for (i = 0; i < timeout; ++i) {
1329                         ni_handle_fifo_half_full(dev);
1330                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1331                              NISTC_AI_STATUS1_FIFO_HF) == 0)
1332                                 break;
1333                 }
1334         }
1335 #endif /*  !PCIDMA */
1336
1337         if (status & NISTC_AI_STATUS1_STOP)
1338                 ni_handle_eos(dev, s);
1339 }
1340
1341 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1342 {
1343         unsigned short ack = 0;
1344
1345         if (b_status & NISTC_AO_STATUS1_BC_TC)
1346                 ack |= NISTC_INTB_ACK_AO_BC_TC;
1347         if (b_status & NISTC_AO_STATUS1_OVERRUN)
1348                 ack |= NISTC_INTB_ACK_AO_ERR;
1349         if (b_status & NISTC_AO_STATUS1_START)
1350                 ack |= NISTC_INTB_ACK_AO_START;
1351         if (b_status & NISTC_AO_STATUS1_START1)
1352                 ack |= NISTC_INTB_ACK_AO_START1;
1353         if (b_status & NISTC_AO_STATUS1_UC_TC)
1354                 ack |= NISTC_INTB_ACK_AO_UC_TC;
1355         if (b_status & NISTC_AO_STATUS1_UI2_TC)
1356                 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1357         if (b_status & NISTC_AO_STATUS1_UPDATE)
1358                 ack |= NISTC_INTB_ACK_AO_UPDATE;
1359         if (ack)
1360                 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1361 }
1362
1363 static void handle_b_interrupt(struct comedi_device *dev,
1364                                struct comedi_subdevice *s,
1365                                unsigned short b_status)
1366 {
1367         if (b_status == 0xffff)
1368                 return;
1369         if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1370                 dev_err(dev->class_dev,
1371                         "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1372                         b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1373                 s->async->events |= COMEDI_CB_OVERFLOW;
1374         }
1375
1376         if (s->async->cmd.stop_src != TRIG_NONE &&
1377             b_status & NISTC_AO_STATUS1_BC_TC)
1378                 s->async->events |= COMEDI_CB_EOA;
1379
1380 #ifndef PCIDMA
1381         if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1382                 int ret;
1383
1384                 ret = ni_ao_fifo_half_empty(dev, s);
1385                 if (!ret) {
1386                         dev_err(dev->class_dev, "AO buffer underrun\n");
1387                         ni_set_bits(dev, NISTC_INTB_ENA_REG,
1388                                     NISTC_INTB_ENA_AO_FIFO |
1389                                     NISTC_INTB_ENA_AO_ERR, 0);
1390                         s->async->events |= COMEDI_CB_OVERFLOW;
1391                 }
1392         }
1393 #endif
1394 }
1395
1396 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1397                         void *data, unsigned int num_bytes,
1398                         unsigned int chan_index)
1399 {
1400         struct ni_private *devpriv = dev->private;
1401         struct comedi_async *async = s->async;
1402         struct comedi_cmd *cmd = &async->cmd;
1403         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1404         unsigned short *array = data;
1405         unsigned int *larray = data;
1406         unsigned int i;
1407 #ifdef PCIDMA
1408         __le16 *barray = data;
1409         __le32 *blarray = data;
1410 #endif
1411
1412         for (i = 0; i < nsamples; i++) {
1413 #ifdef PCIDMA
1414                 if (s->subdev_flags & SDF_LSAMPL)
1415                         larray[i] = le32_to_cpu(blarray[i]);
1416                 else
1417                         array[i] = le16_to_cpu(barray[i]);
1418 #endif
1419                 if (s->subdev_flags & SDF_LSAMPL)
1420                         larray[i] += devpriv->ai_offset[chan_index];
1421                 else
1422                         array[i] += devpriv->ai_offset[chan_index];
1423                 chan_index++;
1424                 chan_index %= cmd->chanlist_len;
1425         }
1426 }
1427
1428 #ifdef PCIDMA
1429
1430 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1431 {
1432         struct ni_private *devpriv = dev->private;
1433         struct comedi_subdevice *s = dev->read_subdev;
1434         int retval;
1435         unsigned long flags;
1436
1437         retval = ni_request_ai_mite_channel(dev);
1438         if (retval)
1439                 return retval;
1440
1441         /* write alloc the entire buffer */
1442         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1443
1444         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1445         if (!devpriv->ai_mite_chan) {
1446                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1447                 return -EIO;
1448         }
1449
1450         if (devpriv->is_611x || devpriv->is_6143)
1451                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1452         else if (devpriv->is_628x)
1453                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1454         else
1455                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1456
1457         /*start the MITE */
1458         mite_dma_arm(devpriv->ai_mite_chan);
1459         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1460
1461         return 0;
1462 }
1463
1464 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1465 {
1466         struct ni_private *devpriv = dev->private;
1467         struct comedi_subdevice *s = dev->write_subdev;
1468         int retval;
1469         unsigned long flags;
1470
1471         retval = ni_request_ao_mite_channel(dev);
1472         if (retval)
1473                 return retval;
1474
1475         /* read alloc the entire buffer */
1476         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1477
1478         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1479         if (devpriv->ao_mite_chan) {
1480                 if (devpriv->is_611x || devpriv->is_6713) {
1481                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1482                 } else {
1483                         /*
1484                          * Doing 32 instead of 16 bit wide transfers from
1485                          * memory makes the mite do 32 bit pci transfers,
1486                          * doubling pci bandwidth.
1487                          */
1488                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1489                 }
1490                 mite_dma_arm(devpriv->ao_mite_chan);
1491         } else {
1492                 retval = -EIO;
1493         }
1494         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1495
1496         return retval;
1497 }
1498
1499 #endif /*  PCIDMA */
1500
1501 /*
1502  * used for both cancel ioctl and board initialization
1503  *
1504  * this is pretty harsh for a cancel, but it works...
1505  */
1506 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1507 {
1508         struct ni_private *devpriv = dev->private;
1509         unsigned int ai_personal;
1510         unsigned int ai_out_ctrl;
1511
1512         ni_release_ai_mite_channel(dev);
1513         /* ai configuration */
1514         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1515                       NISTC_RESET_REG);
1516
1517         ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1518
1519         ni_clear_ai_fifo(dev);
1520
1521         if (!devpriv->is_6143)
1522                 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1523
1524         ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1525         ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1526                            NISTC_AI_MODE1_RSVD
1527                             /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1528                       NISTC_AI_MODE1_REG);
1529         ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1530         /* generate FIFO interrupts on non-empty */
1531         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1532                       NISTC_AI_MODE3_REG);
1533
1534         ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1535                       NISTC_AI_PERSONAL_SOC_POLARITY |
1536                       NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1537         ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1538                       NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1539                       NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1540                       NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1541         if (devpriv->is_611x) {
1542                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1543         } else if (devpriv->is_6143) {
1544                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1545         } else {
1546                 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1547                 if (devpriv->is_622x)
1548                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1549                 else
1550                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1551         }
1552         ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1553         ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1554
1555         /* the following registers should not be changed, because there
1556          * are no backup registers in devpriv.  If you want to change
1557          * any of these, add a backup register and other appropriate code:
1558          *      NISTC_AI_MODE1_REG
1559          *      NISTC_AI_MODE3_REG
1560          *      NISTC_AI_PERSONAL_REG
1561          *      NISTC_AI_OUT_CTRL_REG
1562          */
1563
1564         /* clear interrupts */
1565         ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1566
1567         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1568
1569         return 0;
1570 }
1571
1572 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1573 {
1574         unsigned long flags;
1575         int count;
1576
1577         /*  lock to avoid race with interrupt handler */
1578         spin_lock_irqsave(&dev->spinlock, flags);
1579 #ifndef PCIDMA
1580         ni_handle_fifo_dregs(dev);
1581 #else
1582         ni_sync_ai_dma(dev);
1583 #endif
1584         count = comedi_buf_n_bytes_ready(s);
1585         spin_unlock_irqrestore(&dev->spinlock, flags);
1586
1587         return count;
1588 }
1589
1590 static void ni_prime_channelgain_list(struct comedi_device *dev)
1591 {
1592         int i;
1593
1594         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1595         for (i = 0; i < NI_TIMEOUT; ++i) {
1596                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1597                       NISTC_AI_STATUS1_FIFO_E)) {
1598                         ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1599                         return;
1600                 }
1601                 udelay(1);
1602         }
1603         dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1604 }
1605
1606 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1607                                               unsigned int n_chan,
1608                                               unsigned int *list)
1609 {
1610         const struct ni_board_struct *board = dev->board_ptr;
1611         struct ni_private *devpriv = dev->private;
1612         unsigned int chan, range, aref;
1613         unsigned int i;
1614         unsigned int dither;
1615         unsigned int range_code;
1616
1617         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1618
1619         if ((list[0] & CR_ALT_SOURCE)) {
1620                 unsigned int bypass_bits;
1621
1622                 chan = CR_CHAN(list[0]);
1623                 range = CR_RANGE(list[0]);
1624                 range_code = ni_gainlkup[board->gainlkup][range];
1625                 dither = (list[0] & CR_ALT_FILTER) != 0;
1626                 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1627                               NI_M_CFG_BYPASS_AI_CHAN(chan) |
1628                               NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1629                               devpriv->ai_calib_source;
1630                 if (dither)
1631                         bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1632                 /*  don't use 2's complement encoding */
1633                 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1634                 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1635         } else {
1636                 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1637         }
1638         for (i = 0; i < n_chan; i++) {
1639                 unsigned int config_bits = 0;
1640
1641                 chan = CR_CHAN(list[i]);
1642                 aref = CR_AREF(list[i]);
1643                 range = CR_RANGE(list[i]);
1644                 dither = (list[i] & CR_ALT_FILTER) != 0;
1645
1646                 range_code = ni_gainlkup[board->gainlkup][range];
1647                 devpriv->ai_offset[i] = 0;
1648                 switch (aref) {
1649                 case AREF_DIFF:
1650                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1651                         break;
1652                 case AREF_COMMON:
1653                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1654                         break;
1655                 case AREF_GROUND:
1656                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1657                         break;
1658                 case AREF_OTHER:
1659                         break;
1660                 }
1661                 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1662                 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1663                 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1664                 if (i == n_chan - 1)
1665                         config_bits |= NI_M_AI_CFG_LAST_CHAN;
1666                 if (dither)
1667                         config_bits |= NI_M_AI_CFG_DITHER;
1668                 /*  don't use 2's complement encoding */
1669                 config_bits |= NI_M_AI_CFG_POLARITY;
1670                 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1671         }
1672         ni_prime_channelgain_list(dev);
1673 }
1674
1675 /*
1676  * Notes on the 6110 and 6111:
1677  * These boards a slightly different than the rest of the series, since
1678  * they have multiple A/D converters.
1679  * From the driver side, the configuration memory is a
1680  * little different.
1681  * Configuration Memory Low:
1682  *   bits 15-9: same
1683  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1684  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1685  *       1001 gain=0.1 (+/- 50)
1686  *       1010 0.2
1687  *       1011 0.1
1688  *       0001 1
1689  *       0010 2
1690  *       0011 5
1691  *       0100 10
1692  *       0101 20
1693  *       0110 50
1694  * Configuration Memory High:
1695  *   bits 12-14: Channel Type
1696  *       001 for differential
1697  *       000 for calibration
1698  *   bit 11: coupling  (this is not currently handled)
1699  *       1 AC coupling
1700  *       0 DC coupling
1701  *   bits 0-2: channel
1702  *       valid channels are 0-3
1703  */
1704 static void ni_load_channelgain_list(struct comedi_device *dev,
1705                                      struct comedi_subdevice *s,
1706                                      unsigned int n_chan, unsigned int *list)
1707 {
1708         const struct ni_board_struct *board = dev->board_ptr;
1709         struct ni_private *devpriv = dev->private;
1710         unsigned int offset = (s->maxdata + 1) >> 1;
1711         unsigned int chan, range, aref;
1712         unsigned int i;
1713         unsigned int hi, lo;
1714         unsigned int dither;
1715
1716         if (devpriv->is_m_series) {
1717                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1718                 return;
1719         }
1720         if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1721                 if (devpriv->changain_state &&
1722                     devpriv->changain_spec == list[0]) {
1723                         /*  ready to go. */
1724                         return;
1725                 }
1726                 devpriv->changain_state = 1;
1727                 devpriv->changain_spec = list[0];
1728         } else {
1729                 devpriv->changain_state = 0;
1730         }
1731
1732         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1733
1734         /*  Set up Calibration mode if required */
1735         if (devpriv->is_6143) {
1736                 if ((list[0] & CR_ALT_SOURCE) &&
1737                     !devpriv->ai_calib_source_enabled) {
1738                         /*  Strobe Relay enable bit */
1739                         ni_writew(dev, devpriv->ai_calib_source |
1740                                        NI6143_CALIB_CHAN_RELAY_ON,
1741                                   NI6143_CALIB_CHAN_REG);
1742                         ni_writew(dev, devpriv->ai_calib_source,
1743                                   NI6143_CALIB_CHAN_REG);
1744                         devpriv->ai_calib_source_enabled = 1;
1745                         /* Allow relays to change */
1746                         msleep_interruptible(100);
1747                 } else if (!(list[0] & CR_ALT_SOURCE) &&
1748                            devpriv->ai_calib_source_enabled) {
1749                         /*  Strobe Relay disable bit */
1750                         ni_writew(dev, devpriv->ai_calib_source |
1751                                        NI6143_CALIB_CHAN_RELAY_OFF,
1752                                   NI6143_CALIB_CHAN_REG);
1753                         ni_writew(dev, devpriv->ai_calib_source,
1754                                   NI6143_CALIB_CHAN_REG);
1755                         devpriv->ai_calib_source_enabled = 0;
1756                         /* Allow relays to change */
1757                         msleep_interruptible(100);
1758                 }
1759         }
1760
1761         for (i = 0; i < n_chan; i++) {
1762                 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1763                         chan = devpriv->ai_calib_source;
1764                 else
1765                         chan = CR_CHAN(list[i]);
1766                 aref = CR_AREF(list[i]);
1767                 range = CR_RANGE(list[i]);
1768                 dither = (list[i] & CR_ALT_FILTER) != 0;
1769
1770                 /* fix the external/internal range differences */
1771                 range = ni_gainlkup[board->gainlkup][range];
1772                 if (devpriv->is_611x)
1773                         devpriv->ai_offset[i] = offset;
1774                 else
1775                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1776
1777                 hi = 0;
1778                 if ((list[i] & CR_ALT_SOURCE)) {
1779                         if (devpriv->is_611x)
1780                                 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1781                                           NI611X_CALIB_CHAN_SEL_REG);
1782                 } else {
1783                         if (devpriv->is_611x)
1784                                 aref = AREF_DIFF;
1785                         else if (devpriv->is_6143)
1786                                 aref = AREF_OTHER;
1787                         switch (aref) {
1788                         case AREF_DIFF:
1789                                 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1790                                 break;
1791                         case AREF_COMMON:
1792                                 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1793                                 break;
1794                         case AREF_GROUND:
1795                                 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1796                                 break;
1797                         case AREF_OTHER:
1798                                 break;
1799                         }
1800                 }
1801                 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1802
1803                 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1804
1805                 if (!devpriv->is_6143) {
1806                         lo = NI_E_AI_CFG_LO_GAIN(range);
1807
1808                         if (i == n_chan - 1)
1809                                 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1810                         if (dither)
1811                                 lo |= NI_E_AI_CFG_LO_DITHER;
1812
1813                         ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1814                 }
1815         }
1816
1817         /* prime the channel/gain list */
1818         if (!devpriv->is_611x && !devpriv->is_6143)
1819                 ni_prime_channelgain_list(dev);
1820 }
1821
1822 static int ni_ai_insn_read(struct comedi_device *dev,
1823                            struct comedi_subdevice *s,
1824                            struct comedi_insn *insn,
1825                            unsigned int *data)
1826 {
1827         struct ni_private *devpriv = dev->private;
1828         unsigned int mask = s->maxdata;
1829         int i, n;
1830         unsigned int signbits;
1831         unsigned int d;
1832
1833         ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1834
1835         ni_clear_ai_fifo(dev);
1836
1837         signbits = devpriv->ai_offset[0];
1838         if (devpriv->is_611x) {
1839                 for (n = 0; n < num_adc_stages_611x; n++) {
1840                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1841                                       NISTC_AI_CMD1_REG);
1842                         udelay(1);
1843                 }
1844                 for (n = 0; n < insn->n; n++) {
1845                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1846                                       NISTC_AI_CMD1_REG);
1847                         /* The 611x has screwy 32-bit FIFOs. */
1848                         d = 0;
1849                         for (i = 0; i < NI_TIMEOUT; i++) {
1850                                 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1851                                         d = ni_readl(dev,
1852                                                      NI611X_AI_FIFO_DATA_REG);
1853                                         d >>= 16;
1854                                         d &= 0xffff;
1855                                         break;
1856                                 }
1857                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1858                                       NISTC_AI_STATUS1_FIFO_E)) {
1859                                         d = ni_readl(dev,
1860                                                      NI611X_AI_FIFO_DATA_REG);
1861                                         d &= 0xffff;
1862                                         break;
1863                                 }
1864                         }
1865                         if (i == NI_TIMEOUT) {
1866                                 dev_err(dev->class_dev, "timeout\n");
1867                                 return -ETIME;
1868                         }
1869                         d += signbits;
1870                         data[n] = d & 0xffff;
1871                 }
1872         } else if (devpriv->is_6143) {
1873                 for (n = 0; n < insn->n; n++) {
1874                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1875                                       NISTC_AI_CMD1_REG);
1876
1877                         /*
1878                          * The 6143 has 32-bit FIFOs. You need to strobe a
1879                          * bit to move a single 16bit stranded sample into
1880                          * the FIFO.
1881                          */
1882                         d = 0;
1883                         for (i = 0; i < NI_TIMEOUT; i++) {
1884                                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1885                                     0x01) {
1886                                         /* Get stranded sample into FIFO */
1887                                         ni_writel(dev, 0x01,
1888                                                   NI6143_AI_FIFO_CTRL_REG);
1889                                         d = ni_readl(dev,
1890                                                      NI6143_AI_FIFO_DATA_REG);
1891                                         break;
1892                                 }
1893                         }
1894                         if (i == NI_TIMEOUT) {
1895                                 dev_err(dev->class_dev, "timeout\n");
1896                                 return -ETIME;
1897                         }
1898                         data[n] = (((d >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1899                 }
1900         } else {
1901                 for (n = 0; n < insn->n; n++) {
1902                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1903                                       NISTC_AI_CMD1_REG);
1904                         for (i = 0; i < NI_TIMEOUT; i++) {
1905                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1906                                       NISTC_AI_STATUS1_FIFO_E))
1907                                         break;
1908                         }
1909                         if (i == NI_TIMEOUT) {
1910                                 dev_err(dev->class_dev, "timeout\n");
1911                                 return -ETIME;
1912                         }
1913                         if (devpriv->is_m_series) {
1914                                 d = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
1915                                 d &= mask;
1916                                 data[n] = d;
1917                         } else {
1918                                 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1919                                 d += signbits;
1920                                 data[n] = d & 0xffff;
1921                         }
1922                 }
1923         }
1924         return insn->n;
1925 }
1926
1927 static int ni_ns_to_timer(const struct comedi_device *dev,
1928                           unsigned int nanosec, unsigned int flags)
1929 {
1930         struct ni_private *devpriv = dev->private;
1931         int divider;
1932
1933         switch (flags & CMDF_ROUND_MASK) {
1934         case CMDF_ROUND_NEAREST:
1935         default:
1936                 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
1937                 break;
1938         case CMDF_ROUND_DOWN:
1939                 divider = (nanosec) / devpriv->clock_ns;
1940                 break;
1941         case CMDF_ROUND_UP:
1942                 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
1943                 break;
1944         }
1945         return divider - 1;
1946 }
1947
1948 static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer)
1949 {
1950         struct ni_private *devpriv = dev->private;
1951
1952         return devpriv->clock_ns * (timer + 1);
1953 }
1954
1955 static void ni_cmd_set_mite_transfer(struct mite_ring *ring,
1956                                      struct comedi_subdevice *sdev,
1957                                      const struct comedi_cmd *cmd,
1958                                      unsigned int max_count)
1959 {
1960 #ifdef PCIDMA
1961         unsigned int nbytes = max_count;
1962
1963         if (cmd->stop_arg > 0 && cmd->stop_arg < max_count)
1964                 nbytes = cmd->stop_arg;
1965         nbytes *= comedi_bytes_per_scan(sdev);
1966
1967         if (nbytes > sdev->async->prealloc_bufsz) {
1968                 if (cmd->stop_arg > 0)
1969                         dev_err(sdev->device->class_dev,
1970                                 "%s: tried exact data transfer limits greater than buffer size\n",
1971                                 __func__);
1972
1973                 /*
1974                  * we can only transfer up to the size of the buffer.  In this
1975                  * case, the user is expected to continue to write into the
1976                  * comedi buffer (already implemented as a ring buffer).
1977                  */
1978                 nbytes = sdev->async->prealloc_bufsz;
1979         }
1980
1981         mite_init_ring_descriptors(ring, sdev, nbytes);
1982 #else
1983         dev_err(sdev->device->class_dev,
1984                 "%s: exact data transfer limits not implemented yet without DMA\n",
1985                 __func__);
1986 #endif
1987 }
1988
1989 static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev,
1990                                              unsigned int num_channels)
1991 {
1992         const struct ni_board_struct *board = dev->board_ptr;
1993         struct ni_private *devpriv = dev->private;
1994
1995         /* simultaneously-sampled inputs */
1996         if (devpriv->is_611x || devpriv->is_6143)
1997                 return board->ai_speed;
1998
1999         /* multiplexed inputs */
2000         return board->ai_speed * num_channels;
2001 }
2002
2003 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2004                          struct comedi_cmd *cmd)
2005 {
2006         const struct ni_board_struct *board = dev->board_ptr;
2007         struct ni_private *devpriv = dev->private;
2008         int err = 0;
2009         unsigned int tmp;
2010         unsigned int sources;
2011
2012         /* Step 1 : check if triggers are trivially valid */
2013
2014         err |= comedi_check_trigger_src(&cmd->start_src,
2015                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2016         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2017                                         TRIG_TIMER | TRIG_EXT);
2018
2019         sources = TRIG_TIMER | TRIG_EXT;
2020         if (devpriv->is_611x || devpriv->is_6143)
2021                 sources |= TRIG_NOW;
2022         err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2023
2024         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2025         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2026
2027         if (err)
2028                 return 1;
2029
2030         /* Step 2a : make sure trigger sources are unique */
2031
2032         err |= comedi_check_trigger_is_unique(cmd->start_src);
2033         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2034         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2035         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2036
2037         /* Step 2b : and mutually compatible */
2038
2039         if (err)
2040                 return 2;
2041
2042         /* Step 3: check if arguments are trivially valid */
2043
2044         switch (cmd->start_src) {
2045         case TRIG_NOW:
2046         case TRIG_INT:
2047                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2048                 break;
2049         case TRIG_EXT:
2050                 tmp = CR_CHAN(cmd->start_arg);
2051
2052                 if (tmp > 16)
2053                         tmp = 16;
2054                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2055                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2056                 break;
2057         }
2058
2059         if (cmd->scan_begin_src == TRIG_TIMER) {
2060                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2061                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2062                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2063                                                     devpriv->clock_ns *
2064                                                     0xffffff);
2065         } else if (cmd->scan_begin_src == TRIG_EXT) {
2066                 /* external trigger */
2067                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2068
2069                 if (tmp > 16)
2070                         tmp = 16;
2071                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2072                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2073         } else {                /* TRIG_OTHER */
2074                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2075         }
2076
2077         if (cmd->convert_src == TRIG_TIMER) {
2078                 if (devpriv->is_611x || devpriv->is_6143) {
2079                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2080                                                            0);
2081                 } else {
2082                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2083                                                             board->ai_speed);
2084                         err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2085                                                             devpriv->clock_ns *
2086                                                             0xffff);
2087                 }
2088         } else if (cmd->convert_src == TRIG_EXT) {
2089                 /* external trigger */
2090                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2091
2092                 if (tmp > 16)
2093                         tmp = 16;
2094                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2095                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2096         } else if (cmd->convert_src == TRIG_NOW) {
2097                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2098         }
2099
2100         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2101                                            cmd->chanlist_len);
2102
2103         if (cmd->stop_src == TRIG_COUNT) {
2104                 unsigned int max_count = 0x01000000;
2105
2106                 if (devpriv->is_611x)
2107                         max_count -= num_adc_stages_611x;
2108                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2109                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2110         } else {
2111                 /* TRIG_NONE */
2112                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2113         }
2114
2115         if (err)
2116                 return 3;
2117
2118         /* step 4: fix up any arguments */
2119
2120         if (cmd->scan_begin_src == TRIG_TIMER) {
2121                 tmp = cmd->scan_begin_arg;
2122                 cmd->scan_begin_arg =
2123                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2124                                                        cmd->scan_begin_arg,
2125                                                        cmd->flags));
2126                 if (tmp != cmd->scan_begin_arg)
2127                         err++;
2128         }
2129         if (cmd->convert_src == TRIG_TIMER) {
2130                 if (!devpriv->is_611x && !devpriv->is_6143) {
2131                         tmp = cmd->convert_arg;
2132                         cmd->convert_arg =
2133                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2134                                                                cmd->convert_arg,
2135                                                                cmd->flags));
2136                         if (tmp != cmd->convert_arg)
2137                                 err++;
2138                         if (cmd->scan_begin_src == TRIG_TIMER &&
2139                             cmd->scan_begin_arg <
2140                             cmd->convert_arg * cmd->scan_end_arg) {
2141                                 cmd->scan_begin_arg =
2142                                     cmd->convert_arg * cmd->scan_end_arg;
2143                                 err++;
2144                         }
2145                 }
2146         }
2147
2148         if (err)
2149                 return 4;
2150
2151         return 0;
2152 }
2153
2154 static int ni_ai_inttrig(struct comedi_device *dev,
2155                          struct comedi_subdevice *s,
2156                          unsigned int trig_num)
2157 {
2158         struct ni_private *devpriv = dev->private;
2159         struct comedi_cmd *cmd = &s->async->cmd;
2160
2161         if (trig_num != cmd->start_arg)
2162                 return -EINVAL;
2163
2164         ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2165                       NISTC_AI_CMD2_REG);
2166         s->async->inttrig = NULL;
2167
2168         return 1;
2169 }
2170
2171 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2172 {
2173         struct ni_private *devpriv = dev->private;
2174         const struct comedi_cmd *cmd = &s->async->cmd;
2175         int timer;
2176         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2177         int mode2 = 0;
2178         int start_stop_select = 0;
2179         unsigned int stop_count;
2180         int interrupt_a_enable = 0;
2181         unsigned int ai_trig;
2182
2183         if (dev->irq == 0) {
2184                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2185                 return -EIO;
2186         }
2187         ni_clear_ai_fifo(dev);
2188
2189         ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2190
2191         /* start configuration */
2192         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2193
2194         /*
2195          * Disable analog triggering for now, since it interferes
2196          * with the use of pfi0.
2197          */
2198         devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2199         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2200
2201         ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2202         switch (cmd->start_src) {
2203         case TRIG_INT:
2204         case TRIG_NOW:
2205                 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2206                            NISTC_AI_TRIG_START1_SEL(0);
2207                 break;
2208         case TRIG_EXT:
2209                 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2210                                                     1);
2211
2212                 if (cmd->start_arg & CR_INVERT)
2213                         ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2214                 if (cmd->start_arg & CR_EDGE)
2215                         ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2216                 break;
2217         }
2218         ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2219
2220         mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2221         mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2222         mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2223         ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2224
2225         if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2226                 /* logic low */
2227                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2228                                      NISTC_AI_STOP_SEL(31) |
2229                                      NISTC_AI_STOP_SYNC;
2230         } else {
2231                 /*  ai configuration memory */
2232                 start_stop_select |= NISTC_AI_STOP_SEL(19);
2233         }
2234         ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2235
2236         devpriv->ai_cmd2 = 0;
2237         switch (cmd->stop_src) {
2238         case TRIG_COUNT:
2239                 stop_count = cmd->stop_arg - 1;
2240
2241                 if (devpriv->is_611x) {
2242                         /*  have to take 3 stage adc pipeline into account */
2243                         stop_count += num_adc_stages_611x;
2244                 }
2245                 /* stage number of scans */
2246                 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2247
2248                 mode1 |= NISTC_AI_MODE1_START_STOP |
2249                          NISTC_AI_MODE1_RSVD |
2250                          NISTC_AI_MODE1_TRIGGER_ONCE;
2251                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2252                 /* load SC (Scan Count) */
2253                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2254
2255                 if (stop_count == 0) {
2256                         devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2257                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2258                         /*
2259                          * This is required to get the last sample for
2260                          * chanlist_len > 1, not sure why.
2261                          */
2262                         if (cmd->chanlist_len > 1)
2263                                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2264                                                      NISTC_AI_STOP_EDGE;
2265                 }
2266                 break;
2267         case TRIG_NONE:
2268                 /* stage number of scans */
2269                 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2270
2271                 mode1 |= NISTC_AI_MODE1_START_STOP |
2272                          NISTC_AI_MODE1_RSVD |
2273                          NISTC_AI_MODE1_CONTINUOUS;
2274                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2275
2276                 /* load SC (Scan Count) */
2277                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2278                 break;
2279         }
2280
2281         switch (cmd->scan_begin_src) {
2282         case TRIG_TIMER:
2283                 /*
2284                  * stop bits for non 611x boards
2285                  * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2286                  * NISTC_AI_MODE2_PRE_TRIGGER=0
2287                  * NISTC_AI_START_STOP_REG:
2288                  * NISTC_AI_START_POLARITY=0    (?) rising edge
2289                  * NISTC_AI_START_EDGE=1        edge triggered
2290                  * NISTC_AI_START_SYNC=1        (?)
2291                  * NISTC_AI_START_SEL=0         SI_TC
2292                  * NISTC_AI_STOP_POLARITY=0     rising edge
2293                  * NISTC_AI_STOP_EDGE=0         level
2294                  * NISTC_AI_STOP_SYNC=1
2295                  * NISTC_AI_STOP_SEL=19         external pin (configuration mem)
2296                  */
2297                 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2298                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2299
2300                 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC;      /* A */
2301                 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2302                 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2303                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2304
2305                 /* load SI */
2306                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2307                                        CMDF_ROUND_NEAREST);
2308                 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2309                 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2310                 break;
2311         case TRIG_EXT:
2312                 if (cmd->scan_begin_arg & CR_EDGE)
2313                         start_stop_select |= NISTC_AI_START_EDGE;
2314                 if (cmd->scan_begin_arg & CR_INVERT)    /* falling edge */
2315                         start_stop_select |= NISTC_AI_START_POLARITY;
2316                 if (cmd->scan_begin_src != cmd->convert_src ||
2317                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2318                     (cmd->convert_arg & ~CR_EDGE))
2319                         start_stop_select |= NISTC_AI_START_SYNC;
2320                 start_stop_select |=
2321                     NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2322                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2323                 break;
2324         }
2325
2326         switch (cmd->convert_src) {
2327         case TRIG_TIMER:
2328         case TRIG_NOW:
2329                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2330                         timer = 1;
2331                 else
2332                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2333                                                CMDF_ROUND_NEAREST);
2334                 /* 0,0 does not work */
2335                 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2336                 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2337
2338                 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;     /* A */
2339                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2340                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2341
2342                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2343
2344                 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;      /* B */
2345                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2346                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2347                 break;
2348         case TRIG_EXT:
2349                 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 +
2350                                                     CR_CHAN(cmd->convert_arg));
2351                 if ((cmd->convert_arg & CR_INVERT) == 0)
2352                         mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2353                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2354
2355                 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2356                          NISTC_AI_MODE2_START_STOP_GATE_ENA;
2357                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2358
2359                 break;
2360         }
2361
2362         if (dev->irq) {
2363                 /* interrupt on FIFO, errors, SC_TC */
2364                 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2365                                       NISTC_INTA_ENA_AI_SC_TC;
2366
2367 #ifndef PCIDMA
2368                 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2369 #endif
2370
2371                 if ((cmd->flags & CMDF_WAKE_EOS) ||
2372                     (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2373                         /* wake on end-of-scan */
2374                         devpriv->aimode = AIMODE_SCAN;
2375                 } else {
2376                         devpriv->aimode = AIMODE_HALF_FULL;
2377                 }
2378
2379                 switch (devpriv->aimode) {
2380                 case AIMODE_HALF_FULL:
2381                         /* FIFO interrupts and DMA requests on half-full */
2382 #ifdef PCIDMA
2383                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2384                                       NISTC_AI_MODE3_REG);
2385 #else
2386                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2387                                       NISTC_AI_MODE3_REG);
2388 #endif
2389                         break;
2390                 case AIMODE_SAMPLE:
2391                         /*generate FIFO interrupts on non-empty */
2392                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2393                                       NISTC_AI_MODE3_REG);
2394                         break;
2395                 case AIMODE_SCAN:
2396 #ifdef PCIDMA
2397                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2398                                       NISTC_AI_MODE3_REG);
2399 #else
2400                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2401                                       NISTC_AI_MODE3_REG);
2402 #endif
2403                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2404                         break;
2405                 default:
2406                         break;
2407                 }
2408
2409                 /* clear interrupts */
2410                 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2411
2412                 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2413         } else {
2414                 /* interrupt on nothing */
2415                 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2416
2417                 /* XXX start polling if necessary */
2418         }
2419
2420         /* end configuration */
2421         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2422
2423         switch (cmd->scan_begin_src) {
2424         case TRIG_TIMER:
2425                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2426                                    NISTC_AI_CMD1_SI_ARM |
2427                                    NISTC_AI_CMD1_DIV_ARM |
2428                                    NISTC_AI_CMD1_SC_ARM,
2429                               NISTC_AI_CMD1_REG);
2430                 break;
2431         case TRIG_EXT:
2432                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2433                                    NISTC_AI_CMD1_SI_ARM |       /* XXX ? */
2434                                    NISTC_AI_CMD1_DIV_ARM |
2435                                    NISTC_AI_CMD1_SC_ARM,
2436                               NISTC_AI_CMD1_REG);
2437                 break;
2438         }
2439
2440 #ifdef PCIDMA
2441         {
2442                 int retval = ni_ai_setup_MITE_dma(dev);
2443
2444                 if (retval)
2445                         return retval;
2446         }
2447 #endif
2448
2449         if (cmd->start_src == TRIG_NOW) {
2450                 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2451                                    devpriv->ai_cmd2,
2452                               NISTC_AI_CMD2_REG);
2453                 s->async->inttrig = NULL;
2454         } else if (cmd->start_src == TRIG_EXT) {
2455                 s->async->inttrig = NULL;
2456         } else {        /* TRIG_INT */
2457                 s->async->inttrig = ni_ai_inttrig;
2458         }
2459
2460         return 0;
2461 }
2462
2463 static int ni_ai_insn_config(struct comedi_device *dev,
2464                              struct comedi_subdevice *s,
2465                              struct comedi_insn *insn, unsigned int *data)
2466 {
2467         struct ni_private *devpriv = dev->private;
2468
2469         if (insn->n < 1)
2470                 return -EINVAL;
2471
2472         switch (data[0]) {
2473         case INSN_CONFIG_ALT_SOURCE:
2474                 if (devpriv->is_m_series) {
2475                         if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2476                                 return -EINVAL;
2477                         devpriv->ai_calib_source = data[1];
2478                 } else if (devpriv->is_6143) {
2479                         unsigned int calib_source;
2480
2481                         calib_source = data[1] & 0xf;
2482
2483                         devpriv->ai_calib_source = calib_source;
2484                         ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2485                 } else {
2486                         unsigned int calib_source;
2487                         unsigned int calib_source_adjust;
2488
2489                         calib_source = data[1] & 0xf;
2490                         calib_source_adjust = (data[1] >> 4) & 0xff;
2491
2492                         if (calib_source >= 8)
2493                                 return -EINVAL;
2494                         devpriv->ai_calib_source = calib_source;
2495                         if (devpriv->is_611x) {
2496                                 ni_writeb(dev, calib_source_adjust,
2497                                           NI611X_CAL_GAIN_SEL_REG);
2498                         }
2499                 }
2500                 return 2;
2501         default:
2502                 break;
2503         }
2504
2505         return -EINVAL;
2506 }
2507
2508 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2509                         void *data, unsigned int num_bytes,
2510                         unsigned int chan_index)
2511 {
2512         struct comedi_cmd *cmd = &s->async->cmd;
2513         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2514         unsigned short *array = data;
2515         unsigned int i;
2516 #ifdef PCIDMA
2517         __le16 buf, *barray = data;
2518 #endif
2519
2520         for (i = 0; i < nsamples; i++) {
2521                 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2522                 unsigned short val = array[i];
2523
2524                 /*
2525                  * Munge data from unsigned to two's complement for
2526                  * bipolar ranges.
2527                  */
2528                 if (comedi_range_is_bipolar(s, range))
2529                         val = comedi_offset_munge(s, val);
2530 #ifdef PCIDMA
2531                 buf = cpu_to_le16(val);
2532                 barray[i] = buf;
2533 #else
2534                 array[i] = val;
2535 #endif
2536                 chan_index++;
2537                 chan_index %= cmd->chanlist_len;
2538         }
2539 }
2540
2541 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2542                                           struct comedi_subdevice *s,
2543                                           unsigned int chanspec[],
2544                                           unsigned int n_chans, int timed)
2545 {
2546         struct ni_private *devpriv = dev->private;
2547         unsigned int range;
2548         unsigned int chan;
2549         unsigned int conf;
2550         int i;
2551         int invert = 0;
2552
2553         if (timed) {
2554                 for (i = 0; i < s->n_chan; ++i) {
2555                         devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2556                         ni_writeb(dev, devpriv->ao_conf[i],
2557                                   NI_M_AO_CFG_BANK_REG(i));
2558                         ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2559                 }
2560         }
2561         for (i = 0; i < n_chans; i++) {
2562                 const struct comedi_krange *krange;
2563
2564                 chan = CR_CHAN(chanspec[i]);
2565                 range = CR_RANGE(chanspec[i]);
2566                 krange = s->range_table->range + range;
2567                 invert = 0;
2568                 conf = 0;
2569                 switch (krange->max - krange->min) {
2570                 case 20000000:
2571                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2572                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2573                         break;
2574                 case 10000000:
2575                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2576                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2577                         break;
2578                 case 4000000:
2579                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2580                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2581                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2582                         break;
2583                 case 2000000:
2584                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2585                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2586                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2587                         break;
2588                 default:
2589                         dev_err(dev->class_dev,
2590                                 "bug! unhandled ao reference voltage\n");
2591                         break;
2592                 }
2593                 switch (krange->max + krange->min) {
2594                 case 0:
2595                         conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2596                         break;
2597                 case 10000000:
2598                         conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2599                         break;
2600                 default:
2601                         dev_err(dev->class_dev,
2602                                 "bug! unhandled ao offset voltage\n");
2603                         break;
2604                 }
2605                 if (timed)
2606                         conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2607                 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2608                 devpriv->ao_conf[chan] = conf;
2609                 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2610         }
2611         return invert;
2612 }
2613
2614 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2615                                      struct comedi_subdevice *s,
2616                                      unsigned int chanspec[],
2617                                      unsigned int n_chans)
2618 {
2619         struct ni_private *devpriv = dev->private;
2620         unsigned int range;
2621         unsigned int chan;
2622         unsigned int conf;
2623         int i;
2624         int invert = 0;
2625
2626         for (i = 0; i < n_chans; i++) {
2627                 chan = CR_CHAN(chanspec[i]);
2628                 range = CR_RANGE(chanspec[i]);
2629                 conf = NI_E_AO_DACSEL(chan);
2630
2631                 if (comedi_range_is_bipolar(s, range)) {
2632                         conf |= NI_E_AO_CFG_BIP;
2633                         invert = (s->maxdata + 1) >> 1;
2634                 } else {
2635                         invert = 0;
2636                 }
2637                 if (comedi_range_is_external(s, range))
2638                         conf |= NI_E_AO_EXT_REF;
2639
2640                 /* not all boards can deglitch, but this shouldn't hurt */
2641                 if (chanspec[i] & CR_DEGLITCH)
2642                         conf |= NI_E_AO_DEGLITCH;
2643
2644                 /* analog reference */
2645                 /* AREF_OTHER connects AO ground to AI ground, i think */
2646                 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2647                         conf |= NI_E_AO_GROUND_REF;
2648
2649                 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2650                 devpriv->ao_conf[chan] = conf;
2651         }
2652         return invert;
2653 }
2654
2655 static int ni_ao_config_chanlist(struct comedi_device *dev,
2656                                  struct comedi_subdevice *s,
2657                                  unsigned int chanspec[], unsigned int n_chans,
2658                                  int timed)
2659 {
2660         struct ni_private *devpriv = dev->private;
2661
2662         if (devpriv->is_m_series)
2663                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2664                                                       timed);
2665         else
2666                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2667 }
2668
2669 static int ni_ao_insn_write(struct comedi_device *dev,
2670                             struct comedi_subdevice *s,
2671                             struct comedi_insn *insn,
2672                             unsigned int *data)
2673 {
2674         struct ni_private *devpriv = dev->private;
2675         unsigned int chan = CR_CHAN(insn->chanspec);
2676         unsigned int range = CR_RANGE(insn->chanspec);
2677         int reg;
2678         int i;
2679
2680         if (devpriv->is_6xxx) {
2681                 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2682
2683                 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2684         } else if (devpriv->is_m_series) {
2685                 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2686         } else {
2687                 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2688         }
2689
2690         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2691
2692         for (i = 0; i < insn->n; i++) {
2693                 unsigned int val = data[i];
2694
2695                 s->readback[chan] = val;
2696
2697                 if (devpriv->is_6xxx) {
2698                         /*
2699                          * 6xxx boards have bipolar outputs, munge the
2700                          * unsigned comedi values to 2's complement
2701                          */
2702                         val = comedi_offset_munge(s, val);
2703
2704                         ni_ao_win_outw(dev, val, reg);
2705                 } else if (devpriv->is_m_series) {
2706                         /*
2707                          * M-series boards use offset binary values for
2708                          * bipolar and uinpolar outputs
2709                          */
2710                         ni_writew(dev, val, reg);
2711                 } else {
2712                         /*
2713                          * Non-M series boards need two's complement values
2714                          * for bipolar ranges.
2715                          */
2716                         if (comedi_range_is_bipolar(s, range))
2717                                 val = comedi_offset_munge(s, val);
2718
2719                         ni_writew(dev, val, reg);
2720                 }
2721         }
2722
2723         return insn->n;
2724 }
2725
2726 /*
2727  * Arms the AO device in preparation for a trigger event.
2728  * This function also allocates and prepares a DMA channel (or FIFO if DMA is
2729  * not used).  As a part of this preparation, this function preloads the DAC
2730  * registers with the first values of the output stream.  This ensures that the
2731  * first clock cycle after the trigger can be used for output.
2732  *
2733  * Note that this function _must_ happen after a user has written data to the
2734  * output buffers via either mmap or write(fileno,...).
2735  */
2736 static int ni_ao_arm(struct comedi_device *dev,
2737                      struct comedi_subdevice *s)
2738 {
2739         struct ni_private *devpriv = dev->private;
2740         int ret;
2741         int interrupt_b_bits;
2742         int i;
2743         static const int timeout = 1000;
2744
2745         /*
2746          * Prevent ao from doing things like trying to allocate the ao dma
2747          * channel multiple times.
2748          */
2749         if (!devpriv->ao_needs_arming) {
2750                 dev_dbg(dev->class_dev, "%s: device does not need arming!\n",
2751                         __func__);
2752                 return -EINVAL;
2753         }
2754
2755         devpriv->ao_needs_arming = 0;
2756
2757         ni_set_bits(dev, NISTC_INTB_ENA_REG,
2758                     NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2759         interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2760 #ifdef PCIDMA
2761         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2762         if (devpriv->is_6xxx)
2763                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2764         ret = ni_ao_setup_MITE_dma(dev);
2765         if (ret)
2766                 return ret;
2767         ret = ni_ao_wait_for_dma_load(dev);
2768         if (ret < 0)
2769                 return ret;
2770 #else
2771         ret = ni_ao_prep_fifo(dev, s);
2772         if (ret == 0)
2773                 return -EPIPE;
2774
2775         interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2776 #endif
2777
2778         ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2779                       NISTC_AO_MODE3_REG);
2780         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2781         /* wait for DACs to be loaded */
2782         for (i = 0; i < timeout; i++) {
2783                 udelay(1);
2784                 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2785                      NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2786                         break;
2787         }
2788         if (i == timeout) {
2789                 dev_err(dev->class_dev,
2790                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2791                 return -EIO;
2792         }
2793         /*
2794          * stc manual says we are need to clear error interrupt after
2795          * AO_TMRDACWRs_In_Progress_St clears
2796          */
2797         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2798
2799         ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2800
2801         ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2802                            NISTC_AO_CMD1_UC_ARM |
2803                            NISTC_AO_CMD1_BC_ARM |
2804                            devpriv->ao_cmd1,
2805                       NISTC_AO_CMD1_REG);
2806
2807         return 0;
2808 }
2809
2810 static int ni_ao_insn_config(struct comedi_device *dev,
2811                              struct comedi_subdevice *s,
2812                              struct comedi_insn *insn, unsigned int *data)
2813 {
2814         const struct ni_board_struct *board = dev->board_ptr;
2815         struct ni_private *devpriv = dev->private;
2816         unsigned int nbytes;
2817
2818         switch (data[0]) {
2819         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2820                 switch (data[1]) {
2821                 case COMEDI_OUTPUT:
2822                         nbytes = comedi_samples_to_bytes(s,
2823                                                          board->ao_fifo_depth);
2824                         data[2] = 1 + nbytes;
2825                         if (devpriv->mite)
2826                                 data[2] += devpriv->mite->fifo_size;
2827                         break;
2828                 case COMEDI_INPUT:
2829                         data[2] = 0;
2830                         break;
2831                 default:
2832                         return -EINVAL;
2833                 }
2834                 return 0;
2835         case INSN_CONFIG_ARM:
2836                 return ni_ao_arm(dev, s);
2837         default:
2838                 break;
2839         }
2840
2841         return -EINVAL;
2842 }
2843
2844 static int ni_ao_inttrig(struct comedi_device *dev,
2845                          struct comedi_subdevice *s,
2846                          unsigned int trig_num)
2847 {
2848         struct ni_private *devpriv = dev->private;
2849         struct comedi_cmd *cmd = &s->async->cmd;
2850         int ret;
2851
2852         /*
2853          * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT.
2854          * For backwards compatibility, also allow trig_num == 0 when
2855          * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT);
2856          * in that case, the internal trigger is being used as a pre-trigger
2857          * before the external trigger.
2858          */
2859         if (!(trig_num == cmd->start_arg ||
2860               (trig_num == 0 && cmd->start_src != TRIG_INT)))
2861                 return -EINVAL;
2862
2863         /*
2864          * Null trig at beginning prevent ao start trigger from executing more
2865          * than once per command.
2866          */
2867         s->async->inttrig = NULL;
2868
2869         if (devpriv->ao_needs_arming) {
2870                 /* only arm this device if it still needs arming */
2871                 ret = ni_ao_arm(dev, s);
2872                 if (ret)
2873                         return ret;
2874         }
2875
2876         ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2877                       NISTC_AO_CMD2_REG);
2878
2879         return 0;
2880 }
2881
2882 /*
2883  * begin ni_ao_cmd.
2884  * Organized similar to NI-STC and MHDDK examples.
2885  * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2886  */
2887
2888 static void ni_ao_cmd_personalize(struct comedi_device *dev,
2889                                   const struct comedi_cmd *cmd)
2890 {
2891         const struct ni_board_struct *board = dev->board_ptr;
2892         unsigned int bits;
2893
2894         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2895
2896         bits =
2897           /* fast CPU interface--only eseries */
2898           /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
2899           NISTC_AO_PERSONAL_BC_SRC_SEL  |
2900           0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
2901           /*
2902            * FIXME:  start setting following bit when appropriate.  Need to
2903            * determine whether board is E4 or E1.
2904            * FROM MHHDK:
2905            * if board is E4 or E1
2906            *   Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
2907            * else
2908            *   set it to 1
2909            */
2910           NISTC_AO_PERSONAL_UPDATE_PW   |
2911           /* FIXME:  when should we set following bit to zero? */
2912           NISTC_AO_PERSONAL_TMRDACWR_PW |
2913           (board->ao_fifo_depth ?
2914             NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
2915           ;
2916 #if 0
2917         /*
2918          * FIXME:
2919          * add something like ".has_individual_dacs = 0" to ni_board_struct
2920          * since, as F Hess pointed out, not all in m series have singles.  not
2921          * sure if e-series all have duals...
2922          */
2923
2924         /*
2925          * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
2926          * 6281, verified with bus analyzer.
2927          */
2928         if (devpriv->is_m_series)
2929                 bits |= NISTC_AO_PERSONAL_NUM_DAC;
2930 #endif
2931         ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2932
2933         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2934 }
2935
2936 static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
2937                                   const struct comedi_cmd *cmd)
2938 {
2939         struct ni_private *devpriv = dev->private;
2940         unsigned int trigsel;
2941
2942         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2943
2944         /* sync */
2945         if (cmd->stop_src == TRIG_NONE) {
2946                 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2947                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2948         } else {
2949                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2950                 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2951         }
2952         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2953
2954         if (cmd->start_src == TRIG_INT) {
2955                 trigsel = NISTC_AO_TRIG_START1_EDGE |
2956                           NISTC_AO_TRIG_START1_SYNC;
2957         } else { /* TRIG_EXT */
2958                 trigsel = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
2959                 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2960                 if (cmd->start_arg & CR_INVERT)
2961                         trigsel |= NISTC_AO_TRIG_START1_POLARITY;
2962                 /* 0=edge detection disabled, 1=enabled */
2963                 if (cmd->start_arg & CR_EDGE)
2964                         trigsel |= NISTC_AO_TRIG_START1_EDGE;
2965         }
2966         ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG);
2967
2968         /* AO_Delayed_START1 = 0, we do not support delayed start...yet */
2969
2970         /* sync */
2971         /* select DA_START1 as PFI6/AO_START1 when configured as an output */
2972         devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2973         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2974
2975         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2976 }
2977
2978 static void ni_ao_cmd_set_counters(struct comedi_device *dev,
2979                                    const struct comedi_cmd *cmd)
2980 {
2981         struct ni_private *devpriv = dev->private;
2982         /* Not supporting 'waveform staging' or 'local buffer with pauses' */
2983
2984         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2985         /*
2986          * This relies on ao_mode1/(Trigger_Once | Continuous) being set in
2987          * set_trigger above.  It is unclear whether we really need to re-write
2988          * this register with these values.  The mhddk examples for e-series
2989          * show writing this in both places, but the examples for m-series show
2990          * a single write in the set_counters function (here).
2991          */
2992         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2993
2994         /* sync (upload number of buffer iterations -1) */
2995         /* indicate that we want to use BC_Load_A_Register as the source */
2996         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
2997         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2998
2999         /*
3000          * if the BC_TC interrupt is still issued in spite of UC, BC, UI
3001          * ignoring BC_TC, then we will need to find a way to ignore that
3002          * interrupt in continuous mode.
3003          */
3004         ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
3005
3006         /* sync (issue command to load number of buffer iterations -1) */
3007         ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
3008
3009         /* sync (upload number of updates in buffer) */
3010         /* indicate that we want to use UC_Load_A_Register as the source */
3011         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
3012         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3013
3014         /*
3015          * if a user specifies '0', this automatically assumes the entire 24bit
3016          * address space is available for the (multiple iterations of single
3017          * buffer) MISB.  Otherwise, stop_arg specifies the MISB length that
3018          * will be used, regardless of whether we are in continuous mode or not.
3019          * In continuous mode, the output will just iterate indefinitely over
3020          * the MISB.
3021          */
3022         {
3023                 unsigned int stop_arg = cmd->stop_arg > 0 ?
3024                         (cmd->stop_arg & 0xffffff) : 0xffffff;
3025
3026                 if (devpriv->is_m_series) {
3027                         /*
3028                          * this is how the NI example code does it for m-series
3029                          * boards, verified correct with 6259
3030                          */
3031                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3032
3033                         /* sync (issue cmd to load number of updates in MISB) */
3034                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3035                                       NISTC_AO_CMD1_REG);
3036                 } else {
3037                         ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
3038
3039                         /* sync (issue cmd to load number of updates in MISB) */
3040                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3041                                       NISTC_AO_CMD1_REG);
3042
3043                         /*
3044                          * sync (upload number of updates-1 in MISB)
3045                          * --eseries only?
3046                          */
3047                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3048                 }
3049         }
3050
3051         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3052 }
3053
3054 static void ni_ao_cmd_set_update(struct comedi_device *dev,
3055                                  const struct comedi_cmd *cmd)
3056 {
3057         struct ni_private *devpriv = dev->private;
3058
3059         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3060
3061         /*
3062          * zero out these bit fields to be set below. Does an ao-reset do this
3063          * automatically?
3064          */
3065         devpriv->ao_mode1 &= ~(
3066           NISTC_AO_MODE1_UI_SRC_MASK         |
3067           NISTC_AO_MODE1_UI_SRC_POLARITY     |
3068           NISTC_AO_MODE1_UPDATE_SRC_MASK     |
3069           NISTC_AO_MODE1_UPDATE_SRC_POLARITY
3070         );
3071
3072         if (cmd->scan_begin_src == TRIG_TIMER) {
3073                 unsigned int trigvar;
3074
3075                 devpriv->ao_cmd2  &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3076
3077                 /*
3078                  * NOTE: there are several other ways of configuring internal
3079                  * updates, but we'll only support one for now:  using
3080                  * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
3081                  * START1 and first update, and also w/o local buffer mode w/
3082                  * pauses.
3083                  */
3084
3085                 /*
3086                  * This is already done above:
3087                  * devpriv->ao_mode1 &= ~(
3088                  *   // set UPDATE_Source to UI_TC:
3089                  *   NISTC_AO_MODE1_UPDATE_SRC_MASK |
3090                  *   // set UPDATE_Source_Polarity to rising (required?)
3091                  *   NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3092                  *   // set UI_Source to AO_IN_TIMEBASE1:
3093                  *   NISTC_AO_MODE1_UI_SRC_MASK     |
3094                  *   // set UI_Source_Polarity to rising (required?)
3095                  *   NISTC_AO_MODE1_UI_SRC_POLARITY
3096                  * );
3097                  */
3098
3099                 /*
3100                  * TODO:  use ao_ui_clock_source to allow all possible signals
3101                  * to be routed to UI_Source_Select.  See tSTC.h for
3102                  * eseries/ni67xx and tMSeries.h for mseries.
3103                  */
3104
3105                 trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg,
3106                                          CMDF_ROUND_NEAREST);
3107
3108                 /*
3109                  * Wait N TB3 ticks after the start trigger before
3110                  * clocking (N must be >=2).
3111                  */
3112                 /* following line: 2-1 per STC */
3113                 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3114                 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3115                 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3116         } else { /* TRIG_EXT */
3117                 /* FIXME:  assert scan_begin_arg != 0, ret failure otherwise */
3118                 devpriv->ao_cmd2  |= NISTC_AO_CMD2_BC_GATE_ENA;
3119                 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
3120                                         CR_CHAN(cmd->scan_begin_arg));
3121                 if (cmd->scan_begin_arg & CR_INVERT)
3122                         devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3123         }
3124
3125         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3126         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3127         devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3128                                NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3129         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3130
3131         /* Configure DAQ-STC for Timed update mode */
3132         devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3133                             NISTC_AO_CMD1_DAC0_UPDATE_MODE;
3134         /* We are not using UPDATE2-->don't have to set DACx_Source_Select */
3135         ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3136
3137         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3138 }
3139
3140 static void ni_ao_cmd_set_channels(struct comedi_device *dev,
3141                                    struct comedi_subdevice *s)
3142 {
3143         struct ni_private *devpriv = dev->private;
3144         const struct comedi_cmd *cmd = &s->async->cmd;
3145         unsigned int bits = 0;
3146
3147         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3148
3149         if (devpriv->is_6xxx) {
3150                 unsigned int i;
3151
3152                 bits = 0;
3153                 for (i = 0; i < cmd->chanlist_len; ++i) {
3154                         int chan = CR_CHAN(cmd->chanlist[i]);
3155
3156                         bits |= 1 << chan;
3157                         ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
3158                 }
3159                 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
3160         }
3161
3162         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3163
3164         if (cmd->scan_end_arg > 1) {
3165                 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3166                 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
3167                                  | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3168
3169         } else {
3170                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3171                 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3172                 if (devpriv->is_m_series | devpriv->is_6xxx)
3173                         bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3174                 else
3175                         bits |= NISTC_AO_OUT_CTRL_CHANS(
3176                                         CR_CHAN(cmd->chanlist[0]));
3177         }
3178
3179         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3180         ni_stc_writew(dev, bits,              NISTC_AO_OUT_CTRL_REG);
3181
3182         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3183 }
3184
3185 static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
3186                                           const struct comedi_cmd *cmd)
3187 {
3188         struct ni_private *devpriv = dev->private;
3189
3190         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3191
3192         devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3193         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3194
3195         /*
3196          * Since we are not supporting waveform staging, we ignore these errors:
3197          * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
3198          * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
3199          */
3200
3201         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3202 }
3203
3204 static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
3205 {
3206         struct ni_private *devpriv = dev->private;
3207
3208         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3209
3210         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3211 #ifdef PCIDMA
3212         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3213 #else
3214         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3215 #endif
3216         /* NOTE:  this is where use_onboard_memory=True would be implemented */
3217         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3218         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3219
3220         /* enable sending of ao fifo requests (dma request) */
3221         ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3222
3223         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3224
3225         /* we are not supporting boards with virtual fifos */
3226 }
3227
3228 static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
3229                                      struct comedi_subdevice *s)
3230 {
3231         if (s->async->cmd.stop_src == TRIG_COUNT)
3232                 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3233                             NISTC_INTB_ENA_AO_BC_TC, 1);
3234
3235         s->async->inttrig = ni_ao_inttrig;
3236 }
3237
3238 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3239 {
3240         struct ni_private *devpriv = dev->private;
3241         const struct comedi_cmd *cmd = &s->async->cmd;
3242
3243         if (dev->irq == 0) {
3244                 dev_err(dev->class_dev, "cannot run command without an irq");
3245                 return -EIO;
3246         }
3247
3248         /* ni_ao_reset should have already been done */
3249         ni_ao_cmd_personalize(dev, cmd);
3250         /* clearing fifo and preload happens elsewhere */
3251
3252         ni_ao_cmd_set_trigger(dev, cmd);
3253         ni_ao_cmd_set_counters(dev, cmd);
3254         ni_ao_cmd_set_update(dev, cmd);
3255         ni_ao_cmd_set_channels(dev, s);
3256         ni_ao_cmd_set_stop_conditions(dev, cmd);
3257         ni_ao_cmd_set_fifo_mode(dev);
3258         ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff);
3259         ni_ao_cmd_set_interrupts(dev, s);
3260
3261         /*
3262          * arm(ing) must happen later so that DMA can be setup and DACs
3263          * preloaded with the actual output buffer before starting.
3264          *
3265          * start(ing) must happen _after_ arming is completed.  Starting can be
3266          * done either via ni_ao_inttrig, or via an external trigger.
3267          *
3268          * **Currently, ni_ao_inttrig will automatically attempt a call to
3269          * ni_ao_arm if the device still needs arming at that point.  This
3270          * allows backwards compatibility.
3271          */
3272         devpriv->ao_needs_arming = 1;
3273         return 0;
3274 }
3275
3276 /* end ni_ao_cmd */
3277
3278 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3279                          struct comedi_cmd *cmd)
3280 {
3281         const struct ni_board_struct *board = dev->board_ptr;
3282         struct ni_private *devpriv = dev->private;
3283         int err = 0;
3284         unsigned int tmp;
3285
3286         /* Step 1 : check if triggers are trivially valid */
3287
3288         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3289         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3290                                         TRIG_TIMER | TRIG_EXT);
3291         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3292         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3293         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3294
3295         if (err)
3296                 return 1;
3297
3298         /* Step 2a : make sure trigger sources are unique */
3299
3300         err |= comedi_check_trigger_is_unique(cmd->start_src);
3301         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3302         err |= comedi_check_trigger_is_unique(cmd->stop_src);
3303
3304         /* Step 2b : and mutually compatible */
3305
3306         if (err)
3307                 return 2;
3308
3309         /* Step 3: check if arguments are trivially valid */
3310
3311         switch (cmd->start_src) {
3312         case TRIG_INT:
3313                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3314                 break;
3315         case TRIG_EXT:
3316                 tmp = CR_CHAN(cmd->start_arg);
3317
3318                 if (tmp > 18)
3319                         tmp = 18;
3320                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3321                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3322                 break;
3323         }
3324
3325         if (cmd->scan_begin_src == TRIG_TIMER) {
3326                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3327                                                     board->ao_speed);
3328                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3329                                                     devpriv->clock_ns *
3330                                                     0xffffff);
3331         }
3332
3333         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3334         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3335                                            cmd->chanlist_len);
3336         err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3337
3338         if (err)
3339                 return 3;
3340
3341         /* step 4: fix up any arguments */
3342         if (cmd->scan_begin_src == TRIG_TIMER) {
3343                 tmp = cmd->scan_begin_arg;
3344                 cmd->scan_begin_arg =
3345                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3346                                                        cmd->scan_begin_arg,
3347                                                        cmd->flags));
3348                 if (tmp != cmd->scan_begin_arg)
3349                         err++;
3350         }
3351         if (err)
3352                 return 4;
3353
3354         return 0;
3355 }
3356
3357 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3358 {
3359         /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */
3360
3361         /*
3362          * In the following, the "--sync" comments are meant to denote
3363          * asynchronous boundaries for setting the registers as described in the
3364          * DAQ-STC mostly in the order also described in the DAQ-STC.
3365          */
3366
3367         struct ni_private *devpriv = dev->private;
3368
3369         ni_release_ao_mite_channel(dev);
3370
3371         /* --sync (reset AO) */
3372         if (devpriv->is_m_series)
3373                 /* following example in mhddk for m-series */
3374                 ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG);
3375
3376         /*--sync (start config) */
3377         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3378
3379         /*--sync (Disarm) */
3380         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3381
3382         /*
3383          * --sync
3384          * (clear bunch of registers--mseries mhddk examples do not include
3385          * this)
3386          */
3387         devpriv->ao_cmd1  = 0;
3388         devpriv->ao_cmd2  = 0;
3389         devpriv->ao_mode1 = 0;
3390         devpriv->ao_mode2 = 0;
3391         if (devpriv->is_m_series)
3392                 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3393         else
3394                 devpriv->ao_mode3 = 0;
3395
3396         ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG);
3397         ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG);
3398         ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG);
3399         ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG);
3400         ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG);
3401         ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3402         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3403         ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3404         ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG);
3405
3406         /*--sync (disable interrupts) */
3407         ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3408
3409         /*--sync (ack) */
3410         ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3411         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3412
3413         /*--not in DAQ-STC.  which doc? */
3414         if (devpriv->is_6xxx) {
3415                 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u,
3416                                NI671X_AO_IMMEDIATE_REG);
3417                 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3418                                NI611X_AO_MISC_REG);
3419         }
3420         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3421         /*--end */
3422
3423         return 0;
3424 }
3425
3426 /* digital io */
3427
3428 static int ni_dio_insn_config(struct comedi_device *dev,
3429                               struct comedi_subdevice *s,
3430                               struct comedi_insn *insn,
3431                               unsigned int *data)
3432 {
3433         struct ni_private *devpriv = dev->private;
3434         int ret;
3435
3436         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3437         if (ret)
3438                 return ret;
3439
3440         devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3441         devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3442         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3443
3444         return insn->n;
3445 }
3446
3447 static int ni_dio_insn_bits(struct comedi_device *dev,
3448                             struct comedi_subdevice *s,
3449                             struct comedi_insn *insn,
3450                             unsigned int *data)
3451 {
3452         struct ni_private *devpriv = dev->private;
3453
3454         /* Make sure we're not using the serial part of the dio */
3455         if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3456             devpriv->serial_interval_ns)
3457                 return -EBUSY;
3458
3459         if (comedi_dio_update_state(s, data)) {
3460                 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3461                 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3462                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3463         }
3464
3465         data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3466
3467         return insn->n;
3468 }
3469
3470 #ifdef PCIDMA
3471 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3472                                        struct comedi_subdevice *s,
3473                                        struct comedi_insn *insn,
3474                                        unsigned int *data)
3475 {
3476         int ret;
3477
3478         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3479         if (ret)
3480                 return ret;
3481
3482         ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3483
3484         return insn->n;
3485 }
3486
3487 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3488                                      struct comedi_subdevice *s,
3489                                      struct comedi_insn *insn,
3490                                      unsigned int *data)
3491 {
3492         if (comedi_dio_update_state(s, data))
3493                 ni_writel(dev, s->state, NI_M_DIO_REG);
3494
3495         data[1] = ni_readl(dev, NI_M_DIO_REG);
3496
3497         return insn->n;
3498 }
3499
3500 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3501                                   struct comedi_subdevice *s,
3502                                   struct comedi_cmd *cmd)
3503 {
3504         int i;
3505
3506         for (i = 0; i < cmd->chanlist_len; ++i) {
3507                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3508
3509                 if (chan != i)
3510                         return -EINVAL;
3511         }
3512
3513         return 0;
3514 }
3515
3516 static int ni_cdio_cmdtest(struct comedi_device *dev,
3517                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3518 {
3519         unsigned int bytes_per_scan;
3520         int err = 0;
3521         int tmp;
3522
3523         /* Step 1 : check if triggers are trivially valid */
3524
3525         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3526         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3527         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3528         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3529         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3530
3531         if (err)
3532                 return 1;
3533
3534         /* Step 2a : make sure trigger sources are unique */
3535         /* Step 2b : and mutually compatible */
3536
3537         /* Step 3: check if arguments are trivially valid */
3538
3539         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3540
3541         tmp = cmd->scan_begin_arg;
3542         tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3543         if (tmp != cmd->scan_begin_arg)
3544                 err |= -EINVAL;
3545
3546         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3547         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3548                                            cmd->chanlist_len);
3549         bytes_per_scan = comedi_bytes_per_scan_cmd(s, cmd);
3550         if (bytes_per_scan) {
3551                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3552                                                     s->async->prealloc_bufsz /
3553                                                     bytes_per_scan);
3554         }
3555
3556         if (err)
3557                 return 3;
3558
3559         /* Step 4: fix up any arguments */
3560
3561         /* Step 5: check channel list if it exists */
3562
3563         if (cmd->chanlist && cmd->chanlist_len > 0)
3564                 err |= ni_cdio_check_chanlist(dev, s, cmd);
3565
3566         if (err)
3567                 return 5;
3568
3569         return 0;
3570 }
3571
3572 static int ni_cdo_inttrig(struct comedi_device *dev,
3573                           struct comedi_subdevice *s,
3574                           unsigned int trig_num)
3575 {
3576         struct comedi_cmd *cmd = &s->async->cmd;
3577         const unsigned int timeout = 1000;
3578         int retval = 0;
3579         unsigned int i;
3580         struct ni_private *devpriv = dev->private;
3581         unsigned long flags;
3582
3583         if (trig_num != cmd->start_arg)
3584                 return -EINVAL;
3585
3586         s->async->inttrig = NULL;
3587
3588         /* read alloc the entire buffer */
3589         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3590
3591         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3592         if (devpriv->cdo_mite_chan) {
3593                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3594                 mite_dma_arm(devpriv->cdo_mite_chan);
3595         } else {
3596                 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3597                 retval = -EIO;
3598         }
3599         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3600         if (retval < 0)
3601                 return retval;
3602
3603         /*
3604          * XXX not sure what interrupt C group does
3605          * wait for dma to fill output fifo
3606          * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3607          */
3608         for (i = 0; i < timeout; ++i) {
3609                 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3610                     NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3611                         break;
3612                 usleep_range(10, 100);
3613         }
3614         if (i == timeout) {
3615                 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3616                 s->cancel(dev, s);
3617                 return -EIO;
3618         }
3619         ni_writel(dev, NI_M_CDO_CMD_ARM |
3620                        NI_M_CDO_CMD_ERR_INT_ENA_SET |
3621                        NI_M_CDO_CMD_F_E_INT_ENA_SET,
3622                   NI_M_CDIO_CMD_REG);
3623         return retval;
3624 }
3625
3626 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3627 {
3628         struct ni_private *devpriv = dev->private;
3629         const struct comedi_cmd *cmd = &s->async->cmd;
3630         unsigned int cdo_mode_bits;
3631         int retval;
3632
3633         ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3634         cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3635                         NI_M_CDO_MODE_HALT_ON_ERROR |
3636                         NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3637         if (cmd->scan_begin_arg & CR_INVERT)
3638                 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3639         ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3640         if (s->io_bits) {
3641                 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3642                 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3643                 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3644         } else {
3645                 dev_err(dev->class_dev,
3646                         "attempted to run digital output command with no lines configured as outputs\n");
3647                 return -EIO;
3648         }
3649         retval = ni_request_cdo_mite_channel(dev);
3650         if (retval < 0)
3651                 return retval;
3652
3653         ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd,
3654                                  s->async->prealloc_bufsz /
3655                                  comedi_bytes_per_scan(s));
3656
3657         s->async->inttrig = ni_cdo_inttrig;
3658
3659         return 0;
3660 }
3661
3662 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3663 {
3664         ni_writel(dev, NI_M_CDO_CMD_DISARM |
3665                        NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3666                        NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3667                        NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3668                   NI_M_CDIO_CMD_REG);
3669         /*
3670          * XXX not sure what interrupt C group does
3671          * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3672          */
3673         ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3674         ni_release_cdo_mite_channel(dev);
3675         return 0;
3676 }
3677
3678 static void handle_cdio_interrupt(struct comedi_device *dev)
3679 {
3680         struct ni_private *devpriv = dev->private;
3681         unsigned int cdio_status;
3682         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3683         unsigned long flags;
3684
3685         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3686         if (devpriv->cdo_mite_chan)
3687                 mite_ack_linkc(devpriv->cdo_mite_chan, s, true);
3688         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3689
3690         cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3691         if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3692                 /* XXX just guessing this is needed and does something useful */
3693                 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3694                           NI_M_CDIO_CMD_REG);
3695                 s->async->events |= COMEDI_CB_OVERFLOW;
3696         }
3697         if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3698                 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3699                           NI_M_CDIO_CMD_REG);
3700                 /* s->async->events |= COMEDI_CB_EOA; */
3701         }
3702         comedi_handle_events(dev, s);
3703 }
3704 #endif /*  PCIDMA */
3705
3706 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3707                                    struct comedi_subdevice *s,
3708                                    unsigned char data_out,
3709                                    unsigned char *data_in)
3710 {
3711         struct ni_private *devpriv = dev->private;
3712         unsigned int status1;
3713         int err = 0, count = 20;
3714
3715         devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3716         devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3717         ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3718
3719         status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3720         if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3721                 err = -EBUSY;
3722                 goto error;
3723         }
3724
3725         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3726         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3727         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3728
3729         /* Wait until STC says we're done, but don't loop infinitely. */
3730         while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3731                NISTC_STATUS1_SERIO_IN_PROG) {
3732                 /* Delay one bit per loop */
3733                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3734                 if (--count < 0) {
3735                         dev_err(dev->class_dev,
3736                                 "SPI serial I/O didn't finish in time!\n");
3737                         err = -ETIME;
3738                         goto error;
3739                 }
3740         }
3741
3742         /*
3743          * Delay for last bit. This delay is absolutely necessary, because
3744          * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3745          */
3746         udelay((devpriv->serial_interval_ns + 999) / 1000);
3747
3748         if (data_in)
3749                 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3750
3751 error:
3752         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3753
3754         return err;
3755 }
3756
3757 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3758                                    struct comedi_subdevice *s,
3759                                    unsigned char data_out,
3760                                    unsigned char *data_in)
3761 {
3762         struct ni_private *devpriv = dev->private;
3763         unsigned char mask, input = 0;
3764
3765         /* Wait for one bit before transfer */
3766         udelay((devpriv->serial_interval_ns + 999) / 1000);
3767
3768         for (mask = 0x80; mask; mask >>= 1) {
3769                 /*
3770                  * Output current bit; note that we cannot touch s->state
3771                  * because it is a per-subdevice field, and serial is
3772                  * a separate subdevice from DIO.
3773                  */
3774                 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3775                 if (data_out & mask)
3776                         devpriv->dio_output |= NISTC_DIO_SDOUT;
3777                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3778
3779                 /*
3780                  * Assert SDCLK (active low, inverted), wait for half of
3781                  * the delay, deassert SDCLK, and wait for the other half.
3782                  */
3783                 devpriv->dio_control |= NISTC_DIO_SDCLK;
3784                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3785
3786                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3787
3788                 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3789                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3790
3791                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3792
3793                 /* Input current bit */
3794                 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3795                         input |= mask;
3796         }
3797
3798         if (data_in)
3799                 *data_in = input;
3800
3801         return 0;
3802 }
3803
3804 static int ni_serial_insn_config(struct comedi_device *dev,
3805                                  struct comedi_subdevice *s,
3806                                  struct comedi_insn *insn,
3807                                  unsigned int *data)
3808 {
3809         struct ni_private *devpriv = dev->private;
3810         unsigned int clk_fout = devpriv->clock_and_fout;
3811         int err = insn->n;
3812         unsigned char byte_out, byte_in = 0;
3813
3814         if (insn->n != 2)
3815                 return -EINVAL;
3816
3817         switch (data[0]) {
3818         case INSN_CONFIG_SERIAL_CLOCK:
3819                 devpriv->serial_hw_mode = 1;
3820                 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3821
3822                 if (data[1] == SERIAL_DISABLED) {
3823                         devpriv->serial_hw_mode = 0;
3824                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3825                                                   NISTC_DIO_SDCLK);
3826                         data[1] = SERIAL_DISABLED;
3827                         devpriv->serial_interval_ns = data[1];
3828                 } else if (data[1] <= SERIAL_600NS) {
3829                         /*
3830                          * Warning: this clock speed is too fast to reliably
3831                          * control SCXI.
3832                          */
3833                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3834                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3835                         clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3836                         data[1] = SERIAL_600NS;
3837                         devpriv->serial_interval_ns = data[1];
3838                 } else if (data[1] <= SERIAL_1_2US) {
3839                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3840                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3841                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3842                         data[1] = SERIAL_1_2US;
3843                         devpriv->serial_interval_ns = data[1];
3844                 } else if (data[1] <= SERIAL_10US) {
3845                         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3846                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3847                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3848                         /*
3849                          * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3850                          * 600ns/1.2us. If you turn divide_by_2 off with the
3851                          * slow clock, you will still get 10us, except then
3852                          * all your delays are wrong.
3853                          */
3854                         data[1] = SERIAL_10US;
3855                         devpriv->serial_interval_ns = data[1];
3856                 } else {
3857                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3858                                                   NISTC_DIO_SDCLK);
3859                         devpriv->serial_hw_mode = 0;
3860                         data[1] = (data[1] / 1000) * 1000;
3861                         devpriv->serial_interval_ns = data[1];
3862                 }
3863                 devpriv->clock_and_fout = clk_fout;
3864
3865                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3866                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3867                 return 1;
3868
3869         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3870
3871                 if (devpriv->serial_interval_ns == 0)
3872                         return -EINVAL;
3873
3874                 byte_out = data[1] & 0xFF;
3875
3876                 if (devpriv->serial_hw_mode) {
3877                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3878                                                       &byte_in);
3879                 } else if (devpriv->serial_interval_ns > 0) {
3880                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3881                                                       &byte_in);
3882                 } else {
3883                         dev_err(dev->class_dev, "serial disabled!\n");
3884                         return -EINVAL;
3885                 }
3886                 if (err < 0)
3887                         return err;
3888                 data[1] = byte_in & 0xFF;
3889                 return insn->n;
3890
3891                 break;
3892         default:
3893                 return -EINVAL;
3894         }
3895 }
3896
3897 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3898 {
3899         int i;
3900
3901         for (i = 0; i < s->n_chan; i++) {
3902                 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3903                                NI67XX_AO_CFG2_REG);
3904         }
3905         ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3906 }
3907
3908 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3909         [NITIO_G0_AUTO_INC]     = { NISTC_G0_AUTOINC_REG, 2 },
3910         [NITIO_G1_AUTO_INC]     = { NISTC_G1_AUTOINC_REG, 2 },
3911         [NITIO_G0_CMD]          = { NISTC_G0_CMD_REG, 2 },
3912         [NITIO_G1_CMD]          = { NISTC_G1_CMD_REG, 2 },
3913         [NITIO_G0_HW_SAVE]      = { NISTC_G0_HW_SAVE_REG, 4 },
3914         [NITIO_G1_HW_SAVE]      = { NISTC_G1_HW_SAVE_REG, 4 },
3915         [NITIO_G0_SW_SAVE]      = { NISTC_G0_SAVE_REG, 4 },
3916         [NITIO_G1_SW_SAVE]      = { NISTC_G1_SAVE_REG, 4 },
3917         [NITIO_G0_MODE]         = { NISTC_G0_MODE_REG, 2 },
3918         [NITIO_G1_MODE]         = { NISTC_G1_MODE_REG, 2 },
3919         [NITIO_G0_LOADA]        = { NISTC_G0_LOADA_REG, 4 },
3920         [NITIO_G1_LOADA]        = { NISTC_G1_LOADA_REG, 4 },
3921         [NITIO_G0_LOADB]        = { NISTC_G0_LOADB_REG, 4 },
3922         [NITIO_G1_LOADB]        = { NISTC_G1_LOADB_REG, 4 },
3923         [NITIO_G0_INPUT_SEL]    = { NISTC_G0_INPUT_SEL_REG, 2 },
3924         [NITIO_G1_INPUT_SEL]    = { NISTC_G1_INPUT_SEL_REG, 2 },
3925         [NITIO_G0_CNT_MODE]     = { 0x1b0, 2 }, /* M-Series only */
3926         [NITIO_G1_CNT_MODE]     = { 0x1b2, 2 }, /* M-Series only */
3927         [NITIO_G0_GATE2]        = { 0x1b4, 2 }, /* M-Series only */
3928         [NITIO_G1_GATE2]        = { 0x1b6, 2 }, /* M-Series only */
3929         [NITIO_G01_STATUS]      = { NISTC_G01_STATUS_REG, 2 },
3930         [NITIO_G01_RESET]       = { NISTC_RESET_REG, 2 },
3931         [NITIO_G01_STATUS1]     = { NISTC_STATUS1_REG, 2 },
3932         [NITIO_G01_STATUS2]     = { NISTC_STATUS2_REG, 2 },
3933         [NITIO_G0_DMA_CFG]      = { 0x1b8, 2 }, /* M-Series only */
3934         [NITIO_G1_DMA_CFG]      = { 0x1ba, 2 }, /* M-Series only */
3935         [NITIO_G0_DMA_STATUS]   = { 0x1b8, 2 }, /* M-Series only */
3936         [NITIO_G1_DMA_STATUS]   = { 0x1ba, 2 }, /* M-Series only */
3937         [NITIO_G0_ABZ]          = { 0x1c0, 2 }, /* M-Series only */
3938         [NITIO_G1_ABZ]          = { 0x1c2, 2 }, /* M-Series only */
3939         [NITIO_G0_INT_ACK]      = { NISTC_INTA_ACK_REG, 2 },
3940         [NITIO_G1_INT_ACK]      = { NISTC_INTB_ACK_REG, 2 },
3941         [NITIO_G0_STATUS]       = { NISTC_AI_STATUS1_REG, 2 },
3942         [NITIO_G1_STATUS]       = { NISTC_AO_STATUS1_REG, 2 },
3943         [NITIO_G0_INT_ENA]      = { NISTC_INTA_ENA_REG, 2 },
3944         [NITIO_G1_INT_ENA]      = { NISTC_INTB_ENA_REG, 2 },
3945 };
3946
3947 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3948                                             enum ni_gpct_register reg)
3949 {
3950         const struct mio_regmap *regmap;
3951
3952         if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3953                 regmap = &ni_gpct_to_stc_regmap[reg];
3954         } else {
3955                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
3956                          __func__, reg);
3957                 return 0;
3958         }
3959
3960         return regmap->mio_reg;
3961 }
3962
3963 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits,
3964                                    enum ni_gpct_register reg)
3965 {
3966         struct comedi_device *dev = counter->counter_dev->dev;
3967         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3968
3969         if (stc_register == 0)
3970                 return;
3971
3972         switch (reg) {
3973                 /* m-series only registers */
3974         case NITIO_G0_CNT_MODE:
3975         case NITIO_G1_CNT_MODE:
3976         case NITIO_G0_GATE2:
3977         case NITIO_G1_GATE2:
3978         case NITIO_G0_DMA_CFG:
3979         case NITIO_G1_DMA_CFG:
3980         case NITIO_G0_ABZ:
3981         case NITIO_G1_ABZ:
3982                 ni_writew(dev, bits, stc_register);
3983                 break;
3984
3985                 /* 32 bit registers */
3986         case NITIO_G0_LOADA:
3987         case NITIO_G1_LOADA:
3988         case NITIO_G0_LOADB:
3989         case NITIO_G1_LOADB:
3990                 ni_stc_writel(dev, bits, stc_register);
3991                 break;
3992
3993                 /* 16 bit registers */
3994         case NITIO_G0_INT_ENA:
3995                 ni_set_bitfield(dev, stc_register,
3996                                 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC,
3997                                 bits);
3998                 break;
3999         case NITIO_G1_INT_ENA:
4000                 ni_set_bitfield(dev, stc_register,
4001                                 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC,
4002                                 bits);
4003                 break;
4004         default:
4005                 ni_stc_writew(dev, bits, stc_register);
4006         }
4007 }
4008
4009 static unsigned int ni_gpct_read_register(struct ni_gpct *counter,
4010                                           enum ni_gpct_register reg)
4011 {
4012         struct comedi_device *dev = counter->counter_dev->dev;
4013         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4014
4015         if (stc_register == 0)
4016                 return 0;
4017
4018         switch (reg) {
4019                 /* m-series only registers */
4020         case NITIO_G0_DMA_STATUS:
4021         case NITIO_G1_DMA_STATUS:
4022                 return ni_readw(dev, stc_register);
4023
4024                 /* 32 bit registers */
4025         case NITIO_G0_HW_SAVE:
4026         case NITIO_G1_HW_SAVE:
4027         case NITIO_G0_SW_SAVE:
4028         case NITIO_G1_SW_SAVE:
4029                 return ni_stc_readl(dev, stc_register);
4030
4031                 /* 16 bit registers */
4032         default:
4033                 return ni_stc_readw(dev, stc_register);
4034         }
4035 }
4036
4037 static int ni_freq_out_insn_read(struct comedi_device *dev,
4038                                  struct comedi_subdevice *s,
4039                                  struct comedi_insn *insn,
4040                                  unsigned int *data)
4041 {
4042         struct ni_private *devpriv = dev->private;
4043         unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
4044         int i;
4045
4046         for (i = 0; i < insn->n; i++)
4047                 data[i] = val;
4048
4049         return insn->n;
4050 }
4051
4052 static int ni_freq_out_insn_write(struct comedi_device *dev,
4053                                   struct comedi_subdevice *s,
4054                                   struct comedi_insn *insn,
4055                                   unsigned int *data)
4056 {
4057         struct ni_private *devpriv = dev->private;
4058
4059         if (insn->n) {
4060                 unsigned int val = data[insn->n - 1];
4061
4062                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
4063                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4064                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
4065
4066                 /* use the last data value to set the fout divider */
4067                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
4068
4069                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
4070                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4071         }
4072         return insn->n;
4073 }
4074
4075 static int ni_freq_out_insn_config(struct comedi_device *dev,
4076                                    struct comedi_subdevice *s,
4077                                    struct comedi_insn *insn,
4078                                    unsigned int *data)
4079 {
4080         struct ni_private *devpriv = dev->private;
4081
4082         switch (data[0]) {
4083         case INSN_CONFIG_SET_CLOCK_SRC:
4084                 switch (data[1]) {
4085                 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4086                         devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
4087                         break;
4088                 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4089                         devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
4090                         break;
4091                 default:
4092                         return -EINVAL;
4093                 }
4094                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4095                 break;
4096         case INSN_CONFIG_GET_CLOCK_SRC:
4097                 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
4098                         data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4099                         data[2] = TIMEBASE_2_NS;
4100                 } else {
4101                         data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4102                         data[2] = TIMEBASE_1_NS * 2;
4103                 }
4104                 break;
4105         default:
4106                 return -EINVAL;
4107         }
4108         return insn->n;
4109 }
4110
4111 static int ni_8255_callback(struct comedi_device *dev,
4112                             int dir, int port, int data, unsigned long iobase)
4113 {
4114         if (dir) {
4115                 ni_writeb(dev, data, iobase + 2 * port);
4116                 return 0;
4117         }
4118
4119         return ni_readb(dev, iobase + 2 * port);
4120 }
4121
4122 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4123 {
4124         struct ni_private *devpriv = dev->private;
4125
4126         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4127         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4128         return 3;
4129 }
4130
4131 static int ni_m_series_pwm_config(struct comedi_device *dev,
4132                                   struct comedi_subdevice *s,
4133                                   struct comedi_insn *insn,
4134                                   unsigned int *data)
4135 {
4136         struct ni_private *devpriv = dev->private;
4137         unsigned int up_count, down_count;
4138
4139         switch (data[0]) {
4140         case INSN_CONFIG_PWM_OUTPUT:
4141                 switch (data[1]) {
4142                 case CMDF_ROUND_NEAREST:
4143                         up_count = DIV_ROUND_CLOSEST(data[2],
4144                                                      devpriv->clock_ns);
4145                         break;
4146                 case CMDF_ROUND_DOWN:
4147                         up_count = data[2] / devpriv->clock_ns;
4148                         break;
4149                 case CMDF_ROUND_UP:
4150                         up_count =
4151                             DIV_ROUND_UP(data[2], devpriv->clock_ns);
4152                         break;
4153                 default:
4154                         return -EINVAL;
4155                 }
4156                 switch (data[3]) {
4157                 case CMDF_ROUND_NEAREST:
4158                         down_count = DIV_ROUND_CLOSEST(data[4],
4159                                                        devpriv->clock_ns);
4160                         break;
4161                 case CMDF_ROUND_DOWN:
4162                         down_count = data[4] / devpriv->clock_ns;
4163                         break;
4164                 case CMDF_ROUND_UP:
4165                         down_count =
4166                             DIV_ROUND_UP(data[4], devpriv->clock_ns);
4167                         break;
4168                 default:
4169                         return -EINVAL;
4170                 }
4171                 if (up_count * devpriv->clock_ns != data[2] ||
4172                     down_count * devpriv->clock_ns != data[4]) {
4173                         data[2] = up_count * devpriv->clock_ns;
4174                         data[4] = down_count * devpriv->clock_ns;
4175                         return -EAGAIN;
4176                 }
4177                 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4178                                NI_M_CAL_PWM_LOW_TIME(down_count),
4179                           NI_M_CAL_PWM_REG);
4180                 devpriv->pwm_up_count = up_count;
4181                 devpriv->pwm_down_count = down_count;
4182                 return 5;
4183         case INSN_CONFIG_GET_PWM_OUTPUT:
4184                 return ni_get_pwm_config(dev, data);
4185         default:
4186                 return -EINVAL;
4187         }
4188         return 0;
4189 }
4190
4191 static int ni_6143_pwm_config(struct comedi_device *dev,
4192                               struct comedi_subdevice *s,
4193                               struct comedi_insn *insn,
4194                               unsigned int *data)
4195 {
4196         struct ni_private *devpriv = dev->private;
4197         unsigned int up_count, down_count;
4198
4199         switch (data[0]) {
4200         case INSN_CONFIG_PWM_OUTPUT:
4201                 switch (data[1]) {
4202                 case CMDF_ROUND_NEAREST:
4203                         up_count = DIV_ROUND_CLOSEST(data[2],
4204                                                      devpriv->clock_ns);
4205                         break;
4206                 case CMDF_ROUND_DOWN:
4207                         up_count = data[2] / devpriv->clock_ns;
4208                         break;
4209                 case CMDF_ROUND_UP:
4210                         up_count =
4211                             DIV_ROUND_UP(data[2], devpriv->clock_ns);
4212                         break;
4213                 default:
4214                         return -EINVAL;
4215                 }
4216                 switch (data[3]) {
4217                 case CMDF_ROUND_NEAREST:
4218                         down_count = DIV_ROUND_CLOSEST(data[4],
4219                                                        devpriv->clock_ns);
4220                         break;
4221                 case CMDF_ROUND_DOWN:
4222                         down_count = data[4] / devpriv->clock_ns;
4223                         break;
4224                 case CMDF_ROUND_UP:
4225                         down_count =
4226                             DIV_ROUND_UP(data[4], devpriv->clock_ns);
4227                         break;
4228                 default:
4229                         return -EINVAL;
4230                 }
4231                 if (up_count * devpriv->clock_ns != data[2] ||
4232                     down_count * devpriv->clock_ns != data[4]) {
4233                         data[2] = up_count * devpriv->clock_ns;
4234                         data[4] = down_count * devpriv->clock_ns;
4235                         return -EAGAIN;
4236                 }
4237                 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4238                 devpriv->pwm_up_count = up_count;
4239                 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4240                 devpriv->pwm_down_count = down_count;
4241                 return 5;
4242         case INSN_CONFIG_GET_PWM_OUTPUT:
4243                 return ni_get_pwm_config(dev, data);
4244         default:
4245                 return -EINVAL;
4246         }
4247         return 0;
4248 }
4249
4250 static int pack_mb88341(int addr, int val, int *bitstring)
4251 {
4252         /*
4253          * Fujitsu MB 88341
4254          * Note that address bits are reversed.  Thanks to
4255          * Ingo Keen for noticing this.
4256          *
4257          * Note also that the 88341 expects address values from
4258          * 1-12, whereas we use channel numbers 0-11.  The NI
4259          * docs use 1-12, also, so be careful here.
4260          */
4261         addr++;
4262         *bitstring = ((addr & 0x1) << 11) |
4263             ((addr & 0x2) << 9) |
4264             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4265         return 12;
4266 }
4267
4268 static int pack_dac8800(int addr, int val, int *bitstring)
4269 {
4270         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4271         return 11;
4272 }
4273
4274 static int pack_dac8043(int addr, int val, int *bitstring)
4275 {
4276         *bitstring = val & 0xfff;
4277         return 12;
4278 }
4279
4280 static int pack_ad8522(int addr, int val, int *bitstring)
4281 {
4282         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4283         return 16;
4284 }
4285
4286 static int pack_ad8804(int addr, int val, int *bitstring)
4287 {
4288         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4289         return 12;
4290 }
4291
4292 static int pack_ad8842(int addr, int val, int *bitstring)
4293 {
4294         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4295         return 12;
4296 }
4297
4298 struct caldac_struct {
4299         int n_chans;
4300         int n_bits;
4301         int (*packbits)(int address, int value, int *bitstring);
4302 };
4303
4304 static struct caldac_struct caldacs[] = {
4305         [mb88341] = {12, 8, pack_mb88341},
4306         [dac8800] = {8, 8, pack_dac8800},
4307         [dac8043] = {1, 12, pack_dac8043},
4308         [ad8522] = {2, 12, pack_ad8522},
4309         [ad8804] = {12, 8, pack_ad8804},
4310         [ad8842] = {8, 8, pack_ad8842},
4311         [ad8804_debug] = {16, 8, pack_ad8804},
4312 };
4313
4314 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4315 {
4316         const struct ni_board_struct *board = dev->board_ptr;
4317         struct ni_private *devpriv = dev->private;
4318         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4319         unsigned int cmd;
4320         int i;
4321         int type;
4322
4323         if (devpriv->caldacs[addr] == val)
4324                 return;
4325         devpriv->caldacs[addr] = val;
4326
4327         for (i = 0; i < 3; i++) {
4328                 type = board->caldac[i];
4329                 if (type == caldac_none)
4330                         break;
4331                 if (addr < caldacs[type].n_chans) {
4332                         bits = caldacs[type].packbits(addr, val, &bitstring);
4333                         loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4334                         break;
4335                 }
4336                 addr -= caldacs[type].n_chans;
4337         }
4338
4339         /* bits will be 0 if there is no caldac for the given addr */
4340         if (bits == 0)
4341                 return;
4342
4343         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4344                 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4345                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4346                 udelay(1);
4347                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4348                 udelay(1);
4349         }
4350         ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4351         udelay(1);
4352         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4353 }
4354
4355 static int ni_calib_insn_write(struct comedi_device *dev,
4356                                struct comedi_subdevice *s,
4357                                struct comedi_insn *insn,
4358                                unsigned int *data)
4359 {
4360         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4361
4362         return 1;
4363 }
4364
4365 static int ni_calib_insn_read(struct comedi_device *dev,
4366                               struct comedi_subdevice *s,
4367                               struct comedi_insn *insn,
4368                               unsigned int *data)
4369 {
4370         struct ni_private *devpriv = dev->private;
4371
4372         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4373
4374         return 1;
4375 }
4376
4377 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4378 {
4379         const struct ni_board_struct *board = dev->board_ptr;
4380         struct ni_private *devpriv = dev->private;
4381         int i, j;
4382         int n_dacs;
4383         int n_chans = 0;
4384         int n_bits;
4385         int diffbits = 0;
4386         int type;
4387         int chan;
4388
4389         type = board->caldac[0];
4390         if (type == caldac_none)
4391                 return;
4392         n_bits = caldacs[type].n_bits;
4393         for (i = 0; i < 3; i++) {
4394                 type = board->caldac[i];
4395                 if (type == caldac_none)
4396                         break;
4397                 if (caldacs[type].n_bits != n_bits)
4398                         diffbits = 1;
4399                 n_chans += caldacs[type].n_chans;
4400         }
4401         n_dacs = i;
4402         s->n_chan = n_chans;
4403
4404         if (diffbits) {
4405                 unsigned int *maxdata_list = devpriv->caldac_maxdata_list;
4406
4407                 if (n_chans > MAX_N_CALDACS)
4408                         dev_err(dev->class_dev,
4409                                 "BUG! MAX_N_CALDACS too small\n");
4410                 s->maxdata_list = maxdata_list;
4411                 chan = 0;
4412                 for (i = 0; i < n_dacs; i++) {
4413                         type = board->caldac[i];
4414                         for (j = 0; j < caldacs[type].n_chans; j++) {
4415                                 maxdata_list[chan] =
4416                                     (1 << caldacs[type].n_bits) - 1;
4417                                 chan++;
4418                         }
4419                 }
4420
4421                 for (chan = 0; chan < s->n_chan; chan++)
4422                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4423         } else {
4424                 type = board->caldac[0];
4425                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4426
4427                 for (chan = 0; chan < s->n_chan; chan++)
4428                         ni_write_caldac(dev, i, s->maxdata / 2);
4429         }
4430 }
4431
4432 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4433 {
4434         unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4435         int bit;
4436         int bitstring;
4437
4438         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4439         ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4440         for (bit = 0x8000; bit; bit >>= 1) {
4441                 if (bit & bitstring)
4442                         cmd |= NI_E_SERIAL_CMD_SDATA;
4443                 else
4444                         cmd &= ~NI_E_SERIAL_CMD_SDATA;
4445
4446                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4447                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4448         }
4449         cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4450         bitstring = 0;
4451         for (bit = 0x80; bit; bit >>= 1) {
4452                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4453                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4454                 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4455                         bitstring |= bit;
4456         }
4457         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4458
4459         return bitstring;
4460 }
4461
4462 static int ni_eeprom_insn_read(struct comedi_device *dev,
4463                                struct comedi_subdevice *s,
4464                                struct comedi_insn *insn,
4465                                unsigned int *data)
4466 {
4467         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4468
4469         return 1;
4470 }
4471
4472 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4473                                         struct comedi_subdevice *s,
4474                                         struct comedi_insn *insn,
4475                                         unsigned int *data)
4476 {
4477         struct ni_private *devpriv = dev->private;
4478
4479         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4480
4481         return 1;
4482 }
4483
4484 static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev,
4485                                            unsigned int chan)
4486 {
4487         /*  pre-m-series boards have fixed signals on pfi pins */
4488         switch (chan) {
4489         case 0:
4490                 return NI_PFI_OUTPUT_AI_START1;
4491         case 1:
4492                 return NI_PFI_OUTPUT_AI_START2;
4493         case 2:
4494                 return NI_PFI_OUTPUT_AI_CONVERT;
4495         case 3:
4496                 return NI_PFI_OUTPUT_G_SRC1;
4497         case 4:
4498                 return NI_PFI_OUTPUT_G_GATE1;
4499         case 5:
4500                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4501         case 6:
4502                 return NI_PFI_OUTPUT_AO_START1;
4503         case 7:
4504                 return NI_PFI_OUTPUT_AI_START_PULSE;
4505         case 8:
4506                 return NI_PFI_OUTPUT_G_SRC0;
4507         case 9:
4508                 return NI_PFI_OUTPUT_G_GATE0;
4509         default:
4510                 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4511                 break;
4512         }
4513         return 0;
4514 }
4515
4516 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4517                                   unsigned int chan, unsigned int source)
4518 {
4519         /*  pre-m-series boards have fixed signals on pfi pins */
4520         if (source != ni_old_get_pfi_routing(dev, chan))
4521                 return -EINVAL;
4522         return 2;
4523 }
4524
4525 static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev,
4526                                                 unsigned int chan)
4527 {
4528         struct ni_private *devpriv = dev->private;
4529         const unsigned int array_offset = chan / 3;
4530
4531         return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4532                                 devpriv->pfi_output_select_reg[array_offset]);
4533 }
4534
4535 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4536                                        unsigned int chan, unsigned int source)
4537 {
4538         struct ni_private *devpriv = dev->private;
4539         unsigned int index = chan / 3;
4540         unsigned short val = devpriv->pfi_output_select_reg[index];
4541
4542         if ((source & 0x1f) != source)
4543                 return -EINVAL;
4544
4545         val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4546         val |= NI_M_PFI_OUT_SEL(chan, source);
4547         ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4548         devpriv->pfi_output_select_reg[index] = val;
4549
4550         return 2;
4551 }
4552
4553 static unsigned int ni_get_pfi_routing(struct comedi_device *dev,
4554                                        unsigned int chan)
4555 {
4556         struct ni_private *devpriv = dev->private;
4557
4558         return (devpriv->is_m_series)
4559                         ? ni_m_series_get_pfi_routing(dev, chan)
4560                         : ni_old_get_pfi_routing(dev, chan);
4561 }
4562
4563 static int ni_set_pfi_routing(struct comedi_device *dev,
4564                               unsigned int chan, unsigned int source)
4565 {
4566         struct ni_private *devpriv = dev->private;
4567
4568         return (devpriv->is_m_series)
4569                         ? ni_m_series_set_pfi_routing(dev, chan, source)
4570                         : ni_old_set_pfi_routing(dev, chan, source);
4571 }
4572
4573 static int ni_config_filter(struct comedi_device *dev,
4574                             unsigned int pfi_channel,
4575                             enum ni_pfi_filter_select filter)
4576 {
4577         struct ni_private *devpriv = dev->private;
4578         unsigned int bits;
4579
4580         if (!devpriv->is_m_series)
4581                 return -ENOTSUPP;
4582
4583         bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4584         bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4585         bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4586         ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4587         return 0;
4588 }
4589
4590 static int ni_pfi_insn_config(struct comedi_device *dev,
4591                               struct comedi_subdevice *s,
4592                               struct comedi_insn *insn,
4593                               unsigned int *data)
4594 {
4595         struct ni_private *devpriv = dev->private;
4596         unsigned int chan;
4597
4598         if (insn->n < 1)
4599                 return -EINVAL;
4600
4601         chan = CR_CHAN(insn->chanspec);
4602
4603         switch (data[0]) {
4604         case COMEDI_OUTPUT:
4605                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4606                 break;
4607         case COMEDI_INPUT:
4608                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4609                 break;
4610         case INSN_CONFIG_DIO_QUERY:
4611                 data[1] =
4612                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4613                     COMEDI_OUTPUT : COMEDI_INPUT;
4614                 return 0;
4615         case INSN_CONFIG_SET_ROUTING:
4616                 return ni_set_pfi_routing(dev, chan, data[1]);
4617         case INSN_CONFIG_GET_ROUTING:
4618                 data[1] = ni_get_pfi_routing(dev, chan);
4619                 break;
4620         case INSN_CONFIG_FILTER:
4621                 return ni_config_filter(dev, chan, data[1]);
4622         default:
4623                 return -EINVAL;
4624         }
4625         return 0;
4626 }
4627
4628 static int ni_pfi_insn_bits(struct comedi_device *dev,
4629                             struct comedi_subdevice *s,
4630                             struct comedi_insn *insn,
4631                             unsigned int *data)
4632 {
4633         struct ni_private *devpriv = dev->private;
4634
4635         if (!devpriv->is_m_series)
4636                 return -ENOTSUPP;
4637
4638         if (comedi_dio_update_state(s, data))
4639                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4640
4641         data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4642
4643         return insn->n;
4644 }
4645
4646 static int cs5529_wait_for_idle(struct comedi_device *dev)
4647 {
4648         unsigned short status;
4649         const int timeout = HZ;
4650         int i;
4651
4652         for (i = 0; i < timeout; i++) {
4653                 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4654                 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4655                         break;
4656                 set_current_state(TASK_INTERRUPTIBLE);
4657                 if (schedule_timeout(1))
4658                         return -EIO;
4659         }
4660         if (i == timeout) {
4661                 dev_err(dev->class_dev, "timeout\n");
4662                 return -ETIME;
4663         }
4664         return 0;
4665 }
4666
4667 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4668 {
4669         static const int timeout = 100;
4670         int i;
4671
4672         ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4673         /* give time for command to start being serially clocked into cs5529.
4674          * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4675          * set before we exit this function.
4676          */
4677         for (i = 0; i < timeout; i++) {
4678                 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4679                     NI67XX_CAL_STATUS_BUSY)
4680                         break;
4681                 udelay(1);
4682         }
4683         if (i == timeout)
4684                 dev_err(dev->class_dev,
4685                         "possible problem - never saw adc go busy?\n");
4686 }
4687
4688 static int cs5529_do_conversion(struct comedi_device *dev,
4689                                 unsigned short *data)
4690 {
4691         int retval;
4692         unsigned short status;
4693
4694         cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4695         retval = cs5529_wait_for_idle(dev);
4696         if (retval) {
4697                 dev_err(dev->class_dev,
4698                         "timeout or signal in %s()\n", __func__);
4699                 return -ETIME;
4700         }
4701         status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4702         if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4703                 dev_err(dev->class_dev,
4704                         "cs5529 conversion error, status CSS_OSC_DETECT\n");
4705                 return -EIO;
4706         }
4707         if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4708                 dev_err(dev->class_dev,
4709                         "cs5529 conversion error, overrange (ignoring)\n");
4710         }
4711         if (data) {
4712                 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4713                 /* cs5529 returns 16 bit signed data in bipolar mode */
4714                 *data ^= (1 << 15);
4715         }
4716         return 0;
4717 }
4718
4719 static int cs5529_ai_insn_read(struct comedi_device *dev,
4720                                struct comedi_subdevice *s,
4721                                struct comedi_insn *insn,
4722                                unsigned int *data)
4723 {
4724         int n, retval;
4725         unsigned short sample;
4726         unsigned int channel_select;
4727         const unsigned int INTERNAL_REF = 0x1000;
4728
4729         /*
4730          * Set calibration adc source.  Docs lie, reference select bits 8 to 11
4731          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4732          * 13 causes the adc input to go overrange (maybe reads external
4733          * reference?)
4734          */
4735         if (insn->chanspec & CR_ALT_SOURCE)
4736                 channel_select = INTERNAL_REF;
4737         else
4738                 channel_select = CR_CHAN(insn->chanspec);
4739         ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4740
4741         for (n = 0; n < insn->n; n++) {
4742                 retval = cs5529_do_conversion(dev, &sample);
4743                 if (retval < 0)
4744                         return retval;
4745                 data[n] = sample;
4746         }
4747         return insn->n;
4748 }
4749
4750 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4751                                 unsigned int reg_select_bits)
4752 {
4753         ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4754         ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4755         reg_select_bits &= CS5529_CMD_REG_MASK;
4756         cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4757         if (cs5529_wait_for_idle(dev))
4758                 dev_err(dev->class_dev,
4759                         "timeout or signal in %s\n", __func__);
4760 }
4761
4762 static int init_cs5529(struct comedi_device *dev)
4763 {
4764         unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4765                                    CS5529_CFG_WORD_RATE_2180;
4766
4767 #if 1
4768         /* do self-calibration */
4769         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4770                             CS5529_CFG_REG);
4771         /* need to force a conversion for calibration to run */
4772         cs5529_do_conversion(dev, NULL);
4773 #else
4774         /* force gain calibration to 1 */
4775         cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4776         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4777                             CS5529_CFG_REG);
4778         if (cs5529_wait_for_idle(dev))
4779                 dev_err(dev->class_dev,
4780                         "timeout or signal in %s\n", __func__);
4781 #endif
4782         return 0;
4783 }
4784
4785 /*
4786  * Find best multiplier/divider to try and get the PLL running at 80 MHz
4787  * given an arbitrary frequency input clock.
4788  */
4789 static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns,
4790                                          unsigned int *freq_divider,
4791                                          unsigned int *freq_multiplier,
4792                                          unsigned int *actual_period_ns)
4793 {
4794         unsigned int div;
4795         unsigned int best_div = 1;
4796         unsigned int mult;
4797         unsigned int best_mult = 1;
4798         static const unsigned int pico_per_nano = 1000;
4799         const unsigned int reference_picosec = reference_period_ns *
4800                                                pico_per_nano;
4801         /*
4802          * m-series wants the phased-locked loop to output 80MHz, which is
4803          * divided by 4 to 20 MHz for most timing clocks
4804          */
4805         static const unsigned int target_picosec = 12500;
4806         int best_period_picosec = 0;
4807
4808         for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4809                 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4810                         unsigned int new_period_ps =
4811                             (reference_picosec * div) / mult;
4812                         if (abs(new_period_ps - target_picosec) <
4813                             abs(best_period_picosec - target_picosec)) {
4814                                 best_period_picosec = new_period_ps;
4815                                 best_div = div;
4816                                 best_mult = mult;
4817                         }
4818                 }
4819         }
4820         if (best_period_picosec == 0)
4821                 return -EIO;
4822
4823         *freq_divider = best_div;
4824         *freq_multiplier = best_mult;
4825         /* return the actual period (* fudge factor for 80 to 20 MHz) */
4826         *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4,
4827                                               pico_per_nano);
4828         return 0;
4829 }
4830
4831 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4832                                            unsigned int source,
4833                                            unsigned int period_ns)
4834 {
4835         struct ni_private *devpriv = dev->private;
4836         static const unsigned int min_period_ns = 50;
4837         static const unsigned int max_period_ns = 1000;
4838         static const unsigned int timeout = 1000;
4839         unsigned int pll_control_bits;
4840         unsigned int freq_divider;
4841         unsigned int freq_multiplier;
4842         unsigned int rtsi;
4843         unsigned int i;
4844         int retval;
4845
4846         if (source == NI_MIO_PLL_PXI10_CLOCK)
4847                 period_ns = 100;
4848         /*
4849          * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz
4850          * range so we'll use that.
4851          */
4852         if (period_ns < min_period_ns || period_ns > max_period_ns) {
4853                 dev_err(dev->class_dev,
4854                         "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4855                         __func__, min_period_ns, max_period_ns);
4856                 return -EINVAL;
4857         }
4858         devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4859         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4860                       NISTC_RTSI_TRIG_DIR_REG);
4861         pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4862         devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4863                                     NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4864         devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4865         switch (source) {
4866         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4867                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4868                 break;
4869         case NI_MIO_PLL_PXI10_CLOCK:
4870                 /* pxi clock is 10MHz */
4871                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4872                 break;
4873         default:
4874                 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4875                         if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4876                                 devpriv->clock_and_fout2 |=
4877                                         NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4878                                 break;
4879                         }
4880                 }
4881                 if (rtsi > NI_M_MAX_RTSI_CHAN)
4882                         return -EINVAL;
4883                 break;
4884         }
4885         retval = ni_mseries_get_pll_parameters(period_ns,
4886                                                &freq_divider,
4887                                                &freq_multiplier,
4888                                                &devpriv->clock_ns);
4889         if (retval < 0) {
4890                 dev_err(dev->class_dev,
4891                         "bug, failed to find pll parameters\n");
4892                 return retval;
4893         }
4894
4895         ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4896         pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4897                             NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4898
4899         ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4900         devpriv->clock_source = source;
4901         /* it takes a few hundred microseconds for PLL to lock */
4902         for (i = 0; i < timeout; ++i) {
4903                 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4904                         break;
4905                 udelay(1);
4906         }
4907         if (i == timeout) {
4908                 dev_err(dev->class_dev,
4909                         "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4910                         __func__, source, period_ns);
4911                 return -ETIMEDOUT;
4912         }
4913         return 3;
4914 }
4915
4916 static int ni_set_master_clock(struct comedi_device *dev,
4917                                unsigned int source, unsigned int period_ns)
4918 {
4919         struct ni_private *devpriv = dev->private;
4920
4921         if (source == NI_MIO_INTERNAL_CLOCK) {
4922                 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4923                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4924                               NISTC_RTSI_TRIG_DIR_REG);
4925                 devpriv->clock_ns = TIMEBASE_1_NS;
4926                 if (devpriv->is_m_series) {
4927                         devpriv->clock_and_fout2 &=
4928                             ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4929                               NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4930                         ni_writew(dev, devpriv->clock_and_fout2,
4931                                   NI_M_CLK_FOUT2_REG);
4932                         ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4933                 }
4934                 devpriv->clock_source = source;
4935         } else {
4936                 if (devpriv->is_m_series) {
4937                         return ni_mseries_set_pll_master_clock(dev, source,
4938                                                                period_ns);
4939                 } else {
4940                         if (source == NI_MIO_RTSI_CLOCK) {
4941                                 devpriv->rtsi_trig_direction_reg |=
4942                                     NISTC_RTSI_TRIG_USE_CLK;
4943                                 ni_stc_writew(dev,
4944                                               devpriv->rtsi_trig_direction_reg,
4945                                               NISTC_RTSI_TRIG_DIR_REG);
4946                                 if (period_ns == 0) {
4947                                         dev_err(dev->class_dev,
4948                                                 "we don't handle an unspecified clock period correctly yet, returning error\n");
4949                                         return -EINVAL;
4950                                 }
4951                                 devpriv->clock_ns = period_ns;
4952                                 devpriv->clock_source = source;
4953                         } else {
4954                                 return -EINVAL;
4955                         }
4956                 }
4957         }
4958         return 3;
4959 }
4960
4961 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4962                                        unsigned int chan, unsigned int source)
4963 {
4964         struct ni_private *devpriv = dev->private;
4965
4966         if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4967                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4968                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4969                                 return 1;
4970
4971                         dev_err(dev->class_dev,
4972                                 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4973                                 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
4974                         return 0;
4975                 }
4976                 return 0;
4977         }
4978         switch (source) {
4979         case NI_RTSI_OUTPUT_ADR_START1:
4980         case NI_RTSI_OUTPUT_ADR_START2:
4981         case NI_RTSI_OUTPUT_SCLKG:
4982         case NI_RTSI_OUTPUT_DACUPDN:
4983         case NI_RTSI_OUTPUT_DA_START1:
4984         case NI_RTSI_OUTPUT_G_SRC0:
4985         case NI_RTSI_OUTPUT_G_GATE0:
4986         case NI_RTSI_OUTPUT_RGOUT0:
4987         case NI_RTSI_OUTPUT_RTSI_BRD(0):
4988         case NI_RTSI_OUTPUT_RTSI_BRD(1):
4989         case NI_RTSI_OUTPUT_RTSI_BRD(2):
4990         case NI_RTSI_OUTPUT_RTSI_BRD(3):
4991                 return 1;
4992         case NI_RTSI_OUTPUT_RTSI_OSC:
4993                 return (devpriv->is_m_series) ? 1 : 0;
4994         default:
4995                 return 0;
4996         }
4997 }
4998
4999 static int ni_set_rtsi_routing(struct comedi_device *dev,
5000                                unsigned int chan, unsigned int src)
5001 {
5002         struct ni_private *devpriv = dev->private;
5003
5004         if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
5005                 return -EINVAL;
5006         if (chan < 4) {
5007                 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5008                 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
5009                 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5010                               NISTC_RTSI_TRIGA_OUT_REG);
5011         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5012                 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5013                 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
5014                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5015                               NISTC_RTSI_TRIGB_OUT_REG);
5016         } else if (chan != NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5017                 /* probably should never reach this, since the
5018                  * ni_valid_rtsi_output_source above errors out if chan is too
5019                  * high
5020                  */
5021                 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
5022                 return -EINVAL;
5023         }
5024         return 2;
5025 }
5026
5027 static unsigned int ni_get_rtsi_routing(struct comedi_device *dev,
5028                                         unsigned int chan)
5029 {
5030         struct ni_private *devpriv = dev->private;
5031
5032         if (chan < 4) {
5033                 return NISTC_RTSI_TRIG_TO_SRC(chan,
5034                                               devpriv->rtsi_trig_a_output_reg);
5035         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5036                 return NISTC_RTSI_TRIG_TO_SRC(chan,
5037                                               devpriv->rtsi_trig_b_output_reg);
5038         } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5039                 return NI_RTSI_OUTPUT_RTSI_OSC;
5040         }
5041
5042         dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
5043         return -EINVAL;
5044 }
5045
5046 static int ni_rtsi_insn_config(struct comedi_device *dev,
5047                                struct comedi_subdevice *s,
5048                                struct comedi_insn *insn,
5049                                unsigned int *data)
5050 {
5051         struct ni_private *devpriv = dev->private;
5052         unsigned int chan = CR_CHAN(insn->chanspec);
5053         unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5054
5055         switch (data[0]) {
5056         case INSN_CONFIG_DIO_OUTPUT:
5057                 if (chan < max_chan) {
5058                         devpriv->rtsi_trig_direction_reg |=
5059                             NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5060                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5061                         devpriv->rtsi_trig_direction_reg |=
5062                             NISTC_RTSI_TRIG_DRV_CLK;
5063                 }
5064                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5065                               NISTC_RTSI_TRIG_DIR_REG);
5066                 break;
5067         case INSN_CONFIG_DIO_INPUT:
5068                 if (chan < max_chan) {
5069                         devpriv->rtsi_trig_direction_reg &=
5070                             ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5071                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5072                         devpriv->rtsi_trig_direction_reg &=
5073                             ~NISTC_RTSI_TRIG_DRV_CLK;
5074                 }
5075                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5076                               NISTC_RTSI_TRIG_DIR_REG);
5077                 break;
5078         case INSN_CONFIG_DIO_QUERY:
5079                 if (chan < max_chan) {
5080                         data[1] =
5081                             (devpriv->rtsi_trig_direction_reg &
5082                              NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
5083                                 ? INSN_CONFIG_DIO_OUTPUT
5084                                 : INSN_CONFIG_DIO_INPUT;
5085                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5086                         data[1] = (devpriv->rtsi_trig_direction_reg &
5087                                    NISTC_RTSI_TRIG_DRV_CLK)
5088                                   ? INSN_CONFIG_DIO_OUTPUT
5089                                   : INSN_CONFIG_DIO_INPUT;
5090                 }
5091                 return 2;
5092         case INSN_CONFIG_SET_CLOCK_SRC:
5093                 return ni_set_master_clock(dev, data[1], data[2]);
5094         case INSN_CONFIG_GET_CLOCK_SRC:
5095                 data[1] = devpriv->clock_source;
5096                 data[2] = devpriv->clock_ns;
5097                 return 3;
5098         case INSN_CONFIG_SET_ROUTING:
5099                 return ni_set_rtsi_routing(dev, chan, data[1]);
5100         case INSN_CONFIG_GET_ROUTING:
5101                 data[1] = ni_get_rtsi_routing(dev, chan);
5102                 return 2;
5103         default:
5104                 return -EINVAL;
5105         }
5106         return 1;
5107 }
5108
5109 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5110                              struct comedi_subdevice *s,
5111                              struct comedi_insn *insn,
5112                              unsigned int *data)
5113 {
5114         data[1] = 0;
5115
5116         return insn->n;
5117 }
5118
5119 static void ni_rtsi_init(struct comedi_device *dev)
5120 {
5121         struct ni_private *devpriv = dev->private;
5122
5123         /*  Initialises the RTSI bus signal switch to a default state */
5124
5125         /*
5126          * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
5127          * to have no effect, at least on pxi-6281, which always uses
5128          * 20MHz rtsi clock frequency
5129          */
5130         devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
5131         /*  Set clock mode to internal */
5132         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5133                 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5134         /*  default internal lines routing to RTSI bus lines */
5135         devpriv->rtsi_trig_a_output_reg =
5136             NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
5137             NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
5138             NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
5139             NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
5140         ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5141                       NISTC_RTSI_TRIGA_OUT_REG);
5142         devpriv->rtsi_trig_b_output_reg =
5143             NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
5144             NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
5145             NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
5146         if (devpriv->is_m_series)
5147                 devpriv->rtsi_trig_b_output_reg |=
5148                     NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
5149         ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5150                       NISTC_RTSI_TRIGB_OUT_REG);
5151
5152         /*
5153          * Sets the source and direction of the 4 on board lines
5154          * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
5155          */
5156 }
5157
5158 #ifdef PCIDMA
5159 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5160 {
5161         struct ni_gpct *counter = s->private;
5162         int retval;
5163
5164         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5165                                               COMEDI_INPUT);
5166         if (retval) {
5167                 dev_err(dev->class_dev,
5168                         "no dma channel available for use by counter\n");
5169                 return retval;
5170         }
5171         ni_tio_acknowledge(counter);
5172         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5173
5174         return ni_tio_cmd(dev, s);
5175 }
5176
5177 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5178 {
5179         struct ni_gpct *counter = s->private;
5180         int retval;
5181
5182         retval = ni_tio_cancel(counter);
5183         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5184         ni_release_gpct_mite_channel(dev, counter->counter_index);
5185         return retval;
5186 }
5187 #endif
5188
5189 static irqreturn_t ni_E_interrupt(int irq, void *d)
5190 {
5191         struct comedi_device *dev = d;
5192         struct comedi_subdevice *s_ai = dev->read_subdev;
5193         struct comedi_subdevice *s_ao = dev->write_subdev;
5194         unsigned short a_status;
5195         unsigned short b_status;
5196         unsigned long flags;
5197 #ifdef PCIDMA
5198         struct ni_private *devpriv = dev->private;
5199 #endif
5200
5201         if (!dev->attached)
5202                 return IRQ_NONE;
5203         smp_mb();               /* make sure dev->attached is checked */
5204
5205         /*  lock to avoid race with comedi_poll */
5206         spin_lock_irqsave(&dev->spinlock, flags);
5207         a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5208         b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5209 #ifdef PCIDMA
5210         if (devpriv->mite) {
5211                 unsigned long flags_too;
5212
5213                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5214                 if (s_ai && devpriv->ai_mite_chan)
5215                         mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false);
5216                 if (s_ao && devpriv->ao_mite_chan)
5217                         mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false);
5218                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5219         }
5220 #endif
5221         ack_a_interrupt(dev, a_status);
5222         ack_b_interrupt(dev, b_status);
5223         if (s_ai) {
5224                 if (a_status & NISTC_AI_STATUS1_INTA)
5225                         handle_a_interrupt(dev, s_ai, a_status);
5226                 /* handle any interrupt or dma events */
5227                 comedi_handle_events(dev, s_ai);
5228         }
5229         if (s_ao) {
5230                 if (b_status & NISTC_AO_STATUS1_INTB)
5231                         handle_b_interrupt(dev, s_ao, b_status);
5232                 /* handle any interrupt or dma events */
5233                 comedi_handle_events(dev, s_ao);
5234         }
5235         handle_gpct_interrupt(dev, 0);
5236         handle_gpct_interrupt(dev, 1);
5237 #ifdef PCIDMA
5238         if (devpriv->is_m_series)
5239                 handle_cdio_interrupt(dev);
5240 #endif
5241
5242         spin_unlock_irqrestore(&dev->spinlock, flags);
5243         return IRQ_HANDLED;
5244 }
5245
5246 static int ni_alloc_private(struct comedi_device *dev)
5247 {
5248         struct ni_private *devpriv;
5249
5250         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5251         if (!devpriv)
5252                 return -ENOMEM;
5253
5254         spin_lock_init(&devpriv->window_lock);
5255         spin_lock_init(&devpriv->soft_reg_copy_lock);
5256         spin_lock_init(&devpriv->mite_channel_lock);
5257
5258         return 0;
5259 }
5260
5261 static int ni_E_init(struct comedi_device *dev,
5262                      unsigned int interrupt_pin, unsigned int irq_polarity)
5263 {
5264         const struct ni_board_struct *board = dev->board_ptr;
5265         struct ni_private *devpriv = dev->private;
5266         struct comedi_subdevice *s;
5267         int ret;
5268         int i;
5269
5270         if (board->n_aochan > MAX_N_AO_CHAN) {
5271                 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5272                 return -EINVAL;
5273         }
5274
5275         /* initialize clock dividers */
5276         devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5277                                   NISTC_CLK_FOUT_SLOW_TIMEBASE |
5278                                   NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5279                                   NISTC_CLK_FOUT_TO_BOARD;
5280         if (!devpriv->is_6xxx) {
5281                 /* BEAM is this needed for PCI-6143 ?? */
5282                 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5283                                             NISTC_CLK_FOUT_AO_OUT_DIV2);
5284         }
5285         ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5286
5287         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5288         if (ret)
5289                 return ret;
5290
5291         /* Analog Input subdevice */
5292         s = &dev->subdevices[NI_AI_SUBDEV];
5293         if (board->n_adchan) {
5294                 s->type         = COMEDI_SUBD_AI;
5295                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5296                 if (!devpriv->is_611x)
5297                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5298                 if (board->ai_maxdata > 0xffff)
5299                         s->subdev_flags |= SDF_LSAMPL;
5300                 if (devpriv->is_m_series)
5301                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5302                 s->n_chan       = board->n_adchan;
5303                 s->maxdata      = board->ai_maxdata;
5304                 s->range_table  = ni_range_lkup[board->gainlkup];
5305                 s->insn_read    = ni_ai_insn_read;
5306                 s->insn_config  = ni_ai_insn_config;
5307                 if (dev->irq) {
5308                         dev->read_subdev = s;
5309                         s->subdev_flags |= SDF_CMD_READ;
5310                         s->len_chanlist = 512;
5311                         s->do_cmdtest   = ni_ai_cmdtest;
5312                         s->do_cmd       = ni_ai_cmd;
5313                         s->cancel       = ni_ai_reset;
5314                         s->poll         = ni_ai_poll;
5315                         s->munge        = ni_ai_munge;
5316
5317                         if (devpriv->mite)
5318                                 s->async_dma_dir = DMA_FROM_DEVICE;
5319                 }
5320
5321                 /* reset the analog input configuration */
5322                 ni_ai_reset(dev, s);
5323         } else {
5324                 s->type         = COMEDI_SUBD_UNUSED;
5325         }
5326
5327         /* Analog Output subdevice */
5328         s = &dev->subdevices[NI_AO_SUBDEV];
5329         if (board->n_aochan) {
5330                 s->type         = COMEDI_SUBD_AO;
5331                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5332                 if (devpriv->is_m_series)
5333                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5334                 s->n_chan       = board->n_aochan;
5335                 s->maxdata      = board->ao_maxdata;
5336                 s->range_table  = board->ao_range_table;
5337                 s->insn_config  = ni_ao_insn_config;
5338                 s->insn_write   = ni_ao_insn_write;
5339
5340                 ret = comedi_alloc_subdev_readback(s);
5341                 if (ret)
5342                         return ret;
5343
5344                 /*
5345                  * Along with the IRQ we need either a FIFO or DMA for
5346                  * async command support.
5347                  */
5348                 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5349                         dev->write_subdev = s;
5350                         s->subdev_flags |= SDF_CMD_WRITE;
5351                         s->len_chanlist = s->n_chan;
5352                         s->do_cmdtest   = ni_ao_cmdtest;
5353                         s->do_cmd       = ni_ao_cmd;
5354                         s->cancel       = ni_ao_reset;
5355                         if (!devpriv->is_m_series)
5356                                 s->munge        = ni_ao_munge;
5357
5358                         if (devpriv->mite)
5359                                 s->async_dma_dir = DMA_TO_DEVICE;
5360                 }
5361
5362                 if (devpriv->is_67xx)
5363                         init_ao_67xx(dev, s);
5364
5365                 /* reset the analog output configuration */
5366                 ni_ao_reset(dev, s);
5367         } else {
5368                 s->type         = COMEDI_SUBD_UNUSED;
5369         }
5370
5371         /* Digital I/O subdevice */
5372         s = &dev->subdevices[NI_DIO_SUBDEV];
5373         s->type         = COMEDI_SUBD_DIO;
5374         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5375         s->n_chan       = board->has_32dio_chan ? 32 : 8;
5376         s->maxdata      = 1;
5377         s->range_table  = &range_digital;
5378         if (devpriv->is_m_series) {
5379 #ifdef PCIDMA
5380                 s->subdev_flags |= SDF_LSAMPL;
5381                 s->insn_bits    = ni_m_series_dio_insn_bits;
5382                 s->insn_config  = ni_m_series_dio_insn_config;
5383                 if (dev->irq) {
5384                         s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5385                         s->len_chanlist = s->n_chan;
5386                         s->do_cmdtest   = ni_cdio_cmdtest;
5387                         s->do_cmd       = ni_cdio_cmd;
5388                         s->cancel       = ni_cdio_cancel;
5389
5390                         /* M-series boards use DMA */
5391                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5392                 }
5393
5394                 /* reset DIO and set all channels to inputs */
5395                 ni_writel(dev, NI_M_CDO_CMD_RESET |
5396                                NI_M_CDI_CMD_RESET,
5397                           NI_M_CDIO_CMD_REG);
5398                 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5399 #endif /* PCIDMA */
5400         } else {
5401                 s->insn_bits    = ni_dio_insn_bits;
5402                 s->insn_config  = ni_dio_insn_config;
5403
5404                 /* set all channels to inputs */
5405                 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5406                 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5407         }
5408
5409         /* 8255 device */
5410         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5411         if (board->has_8255) {
5412                 ret = subdev_8255_init(dev, s, ni_8255_callback,
5413                                        NI_E_8255_BASE);
5414                 if (ret)
5415                         return ret;
5416         } else {
5417                 s->type = COMEDI_SUBD_UNUSED;
5418         }
5419
5420         /* formerly general purpose counter/timer device, but no longer used */
5421         s = &dev->subdevices[NI_UNUSED_SUBDEV];
5422         s->type = COMEDI_SUBD_UNUSED;
5423
5424         /* Calibration subdevice */
5425         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5426         s->type         = COMEDI_SUBD_CALIB;
5427         s->subdev_flags = SDF_INTERNAL;
5428         s->n_chan       = 1;
5429         s->maxdata      = 0;
5430         if (devpriv->is_m_series) {
5431                 /* internal PWM output used for AI nonlinearity calibration */
5432                 s->insn_config  = ni_m_series_pwm_config;
5433
5434                 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5435         } else if (devpriv->is_6143) {
5436                 /* internal PWM output used for AI nonlinearity calibration */
5437                 s->insn_config  = ni_6143_pwm_config;
5438         } else {
5439                 s->subdev_flags |= SDF_WRITABLE;
5440                 s->insn_read    = ni_calib_insn_read;
5441                 s->insn_write   = ni_calib_insn_write;
5442
5443                 /* setup the caldacs and find the real n_chan and maxdata */
5444                 caldac_setup(dev, s);
5445         }
5446
5447         /* EEPROM subdevice */
5448         s = &dev->subdevices[NI_EEPROM_SUBDEV];
5449         s->type         = COMEDI_SUBD_MEMORY;
5450         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5451         s->maxdata      = 0xff;
5452         if (devpriv->is_m_series) {
5453                 s->n_chan       = M_SERIES_EEPROM_SIZE;
5454                 s->insn_read    = ni_m_series_eeprom_insn_read;
5455         } else {
5456                 s->n_chan       = 512;
5457                 s->insn_read    = ni_eeprom_insn_read;
5458         }
5459
5460         /* Digital I/O (PFI) subdevice */
5461         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5462         s->type         = COMEDI_SUBD_DIO;
5463         s->maxdata      = 1;
5464         if (devpriv->is_m_series) {
5465                 s->n_chan       = 16;
5466                 s->insn_bits    = ni_pfi_insn_bits;
5467                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5468
5469                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5470                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5471                         ni_writew(dev, devpriv->pfi_output_select_reg[i],
5472                                   NI_M_PFI_OUT_SEL_REG(i));
5473                 }
5474         } else {
5475                 s->n_chan       = 10;
5476                 s->subdev_flags = SDF_INTERNAL;
5477         }
5478         s->insn_config  = ni_pfi_insn_config;
5479
5480         ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5481
5482         /* cs5529 calibration adc */
5483         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5484         if (devpriv->is_67xx) {
5485                 s->type = COMEDI_SUBD_AI;
5486                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5487                 /*  one channel for each analog output channel */
5488                 s->n_chan = board->n_aochan;
5489                 s->maxdata = (1 << 16) - 1;
5490                 s->range_table = &range_unknown;        /* XXX */
5491                 s->insn_read = cs5529_ai_insn_read;
5492                 s->insn_config = NULL;
5493                 init_cs5529(dev);
5494         } else {
5495                 s->type = COMEDI_SUBD_UNUSED;
5496         }
5497
5498         /* Serial */
5499         s = &dev->subdevices[NI_SERIAL_SUBDEV];
5500         s->type = COMEDI_SUBD_SERIAL;
5501         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5502         s->n_chan = 1;
5503         s->maxdata = 0xff;
5504         s->insn_config = ni_serial_insn_config;
5505         devpriv->serial_interval_ns = 0;
5506         devpriv->serial_hw_mode = 0;
5507
5508         /* RTSI */
5509         s = &dev->subdevices[NI_RTSI_SUBDEV];
5510         s->type = COMEDI_SUBD_DIO;
5511         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5512         s->n_chan = 8;
5513         s->maxdata = 1;
5514         s->insn_bits = ni_rtsi_insn_bits;
5515         s->insn_config = ni_rtsi_insn_config;
5516         ni_rtsi_init(dev);
5517
5518         /* allocate and initialize the gpct counter device */
5519         devpriv->counter_dev = ni_gpct_device_construct(dev,
5520                                         ni_gpct_write_register,
5521                                         ni_gpct_read_register,
5522                                         (devpriv->is_m_series)
5523                                                 ? ni_gpct_variant_m_series
5524                                                 : ni_gpct_variant_e_series,
5525                                         NUM_GPCT);
5526         if (!devpriv->counter_dev)
5527                 return -ENOMEM;
5528
5529         /* Counter (gpct) subdevices */
5530         for (i = 0; i < NUM_GPCT; ++i) {
5531                 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5532
5533                 /* setup and initialize the counter */
5534                 gpct->chip_index = 0;
5535                 gpct->counter_index = i;
5536                 ni_tio_init_counter(gpct);
5537
5538                 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5539                 s->type         = COMEDI_SUBD_COUNTER;
5540                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5541                 s->n_chan       = 3;
5542                 s->maxdata      = (devpriv->is_m_series) ? 0xffffffff
5543                                                          : 0x00ffffff;
5544                 s->insn_read    = ni_tio_insn_read;
5545                 s->insn_write   = ni_tio_insn_write;
5546                 s->insn_config  = ni_tio_insn_config;
5547 #ifdef PCIDMA
5548                 if (dev->irq && devpriv->mite) {
5549                         s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5550                         s->len_chanlist = 1;
5551                         s->do_cmdtest   = ni_tio_cmdtest;
5552                         s->do_cmd       = ni_gpct_cmd;
5553                         s->cancel       = ni_gpct_cancel;
5554
5555                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5556                 }
5557 #endif
5558                 s->private      = gpct;
5559         }
5560
5561         /* Frequency output subdevice */
5562         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5563         s->type         = COMEDI_SUBD_COUNTER;
5564         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5565         s->n_chan       = 1;
5566         s->maxdata      = 0xf;
5567         s->insn_read    = ni_freq_out_insn_read;
5568         s->insn_write   = ni_freq_out_insn_write;
5569         s->insn_config  = ni_freq_out_insn_config;
5570
5571         if (dev->irq) {
5572                 ni_stc_writew(dev,
5573                               (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5574                               (NISTC_INT_CTRL_3PIN_INT & 0) |
5575                               NISTC_INT_CTRL_INTA_ENA |
5576                               NISTC_INT_CTRL_INTB_ENA |
5577                               NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5578                               NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5579                               NISTC_INT_CTRL_REG);
5580         }
5581
5582         /* DMA setup */
5583         ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
5584         ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
5585
5586         if (devpriv->is_6xxx) {
5587                 ni_writeb(dev, 0, NI611X_MAGIC_REG);
5588         } else if (devpriv->is_m_series) {
5589                 int channel;
5590
5591                 for (channel = 0; channel < board->n_aochan; ++channel) {
5592                         ni_writeb(dev, 0xf,
5593                                   NI_M_AO_WAVEFORM_ORDER_REG(channel));
5594                         ni_writeb(dev, 0x0,
5595                                   NI_M_AO_REF_ATTENUATION_REG(channel));
5596                 }
5597                 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5598         }
5599
5600         return 0;
5601 }
5602
5603 static void mio_common_detach(struct comedi_device *dev)
5604 {
5605         struct ni_private *devpriv = dev->private;
5606
5607         if (devpriv)
5608                 ni_gpct_device_destroy(devpriv->counter_dev);
5609 }