1 // SPDX-License-Identifier: GPL-2.0+
3 * Comedi driver for NI PCI-MIO E series cards
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
11 * Description: National Instruments PCI-MIO-E series and M series (all boards)
12 * Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
13 * Herman Bruyninckx, Terry Barnaby
15 * Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
16 * PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014,
17 * PCI-6040E, PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E,
18 * PCI-6071E, PCI-6023E, PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E,
19 * PCI-6035E, PCI-6052E, PCI-6110, PCI-6111, PCI-6220, PXI-6220,
20 * PCI-6221, PXI-6221, PCI-6224, PXI-6224, PCI-6225, PXI-6225,
21 * PCI-6229, PXI-6229, PCI-6250, PXI-6250, PCI-6251, PXI-6251,
22 * PCIe-6251, PXIe-6251, PCI-6254, PXI-6254, PCI-6259, PXI-6259,
23 * PCIe-6259, PXIe-6259, PCI-6280, PXI-6280, PCI-6281, PXI-6281,
24 * PCI-6284, PXI-6284, PCI-6289, PXI-6289, PCI-6711, PXI-6711,
25 * PCI-6713, PXI-6713, PXI-6071E, PCI-6070E, PXI-6070E,
26 * PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
28 * Updated: Mon, 16 Jan 2017 12:56:04 +0000
30 * These boards are almost identical to the AT-MIO E series, except that
31 * they use the PCI bus instead of ISA (i.e., AT). See the notes for the
32 * ni_atmio.o driver for additional information about these boards.
34 * Autocalibration is supported on many of the devices, using the
35 * comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
36 * M-Series boards do analog input and analog output calibration entirely
37 * in software. The software calibration corrects the analog input for
38 * offset, gain and nonlinearity. The analog outputs are corrected for
39 * offset and gain. See the comedilib documentation on
40 * comedi_get_softcal_converter() for more information.
42 * By default, the driver uses DMA to transfer analog input data to
43 * memory. When DMA is enabled, not all triggering features are
46 * Digital I/O may not work on 673x.
48 * Note that the PCI-6143 is a simultaineous sampling device with 8
49 * convertors. With this board all of the convertors perform one
50 * simultaineous sample during a scan interval. The period for a scan
51 * is used for the convert time in a Comedi cmd. The convert trigger
52 * source is normally set to TRIG_NOW by default.
54 * The RTSI trigger bus is supported on these cards on subdevice 10.
55 * See the comedilib documentation for details.
57 * Information (number of channels, bits, etc.) for some devices may be
58 * incorrect. Please check this and submit a bug if there are problems
61 * SCXI is probably broken for m-series boards.
64 * - When DMA is enabled, COMEDI_EV_CONVERT does not work correctly.
68 * The PCI-MIO E series driver was originally written by
69 * Tomasz Motylewski <...>, and ported to comedi by ds.
72 * 341079b.pdf PCI E Series Register-Level Programmer Manual
73 * 340934b.pdf DAQ-STC reference manual
75 * 322080b.pdf 6711/6713/6715 User Manual
77 * 320945c.pdf PCI E Series User Manual
78 * 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
81 * - need to deal with external reference for DAC, and other DAC
82 * properties in board properties
83 * - deal with at-mio-16de-10 revision D to N changes, etc.
84 * - need to add other CALDAC type
85 * - need to slow down DAC loading. I don't trust NI's claim that
86 * two writes to the PCI bus slows IO enough. I would prefer to
88 * Timing specs: (clock)
95 #include <linux/module.h>
96 #include <linux/delay.h>
98 #include "../comedi_pci.h"
100 #include <asm/byteorder.h>
108 * These are not all the possible ao ranges for 628x boards.
109 * They can do OFFSET +- REFERENCE where OFFSET can be
110 * 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
111 * be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
112 * 63 different possibilities. An AO channel
113 * can not act as it's own OFFSET or REFERENCE.
115 static const struct comedi_lrange range_ni_M_628x_ao = {
129 static const struct comedi_lrange range_ni_M_625x_ao = {
137 enum ni_pcimio_boardid {
138 BOARD_PCIMIO_16XE_50,
139 BOARD_PCIMIO_16XE_10,
208 static const struct ni_board_struct ni_boards[] = {
209 [BOARD_PCIMIO_16XE_50] = {
210 .name = "pci-mio-16xe-50",
212 .ai_maxdata = 0xffff,
213 .ai_fifo_depth = 2048,
215 .gainlkup = ai_gain_8,
218 .ao_maxdata = 0x0fff,
219 .ao_range_table = &range_bipolar10,
221 .caldac = { dac8800, dac8043 },
223 [BOARD_PCIMIO_16XE_10] = {
224 .name = "pci-mio-16xe-10", /* aka pci-6030E */
226 .ai_maxdata = 0xffff,
227 .ai_fifo_depth = 512,
229 .gainlkup = ai_gain_14,
232 .ao_maxdata = 0xffff,
233 .ao_fifo_depth = 2048,
234 .ao_range_table = &range_ni_E_ao_ext,
236 .caldac = { dac8800, dac8043, ad8522 },
241 .ai_maxdata = 0xffff,
242 .ai_fifo_depth = 512,
244 .gainlkup = ai_gain_4,
247 .ao_maxdata = 0xffff,
248 .ao_range_table = &range_bipolar10,
250 .caldac = { ad8804_debug },
255 .ai_maxdata = 0xffff,
256 .ai_fifo_depth = 512,
258 .gainlkup = ai_gain_14,
261 .ao_maxdata = 0xffff,
262 .ao_fifo_depth = 2048,
263 .ao_range_table = &range_ni_E_ao_ext,
265 .caldac = { dac8800, dac8043, ad8522 },
267 [BOARD_PCIMIO_16E_1] = {
268 .name = "pci-mio-16e-1", /* aka pci-6070e */
270 .ai_maxdata = 0x0fff,
271 .ai_fifo_depth = 512,
272 .gainlkup = ai_gain_16,
275 .ao_maxdata = 0x0fff,
276 .ao_fifo_depth = 2048,
277 .ao_range_table = &range_ni_E_ao_ext,
279 .caldac = { mb88341 },
281 [BOARD_PCIMIO_16E_4] = {
282 .name = "pci-mio-16e-4", /* aka pci-6040e */
284 .ai_maxdata = 0x0fff,
285 .ai_fifo_depth = 512,
286 .gainlkup = ai_gain_16,
288 * there have been reported problems with
289 * full speed on this board
293 .ao_maxdata = 0x0fff,
294 .ao_fifo_depth = 512,
295 .ao_range_table = &range_ni_E_ao_ext,
297 .caldac = { ad8804_debug }, /* doc says mb88341 */
302 .ai_maxdata = 0x0fff,
303 .ai_fifo_depth = 512,
304 .gainlkup = ai_gain_16,
307 .ao_maxdata = 0x0fff,
308 .ao_fifo_depth = 512,
309 .ao_range_table = &range_ni_E_ao_ext,
311 .caldac = { mb88341 },
316 .ai_maxdata = 0xffff,
317 .ai_fifo_depth = 512,
319 .gainlkup = ai_gain_14,
322 .ao_maxdata = 0xffff,
323 .ao_fifo_depth = 2048,
324 .ao_range_table = &range_ni_E_ao_ext,
326 .caldac = { dac8800, dac8043, ad8522 },
331 .ai_maxdata = 0xffff,
332 .ai_fifo_depth = 512,
334 .gainlkup = ai_gain_14,
336 .caldac = { dac8800, dac8043, ad8522 },
341 .ai_maxdata = 0xffff,
342 .ai_fifo_depth = 512,
344 .gainlkup = ai_gain_14,
346 .caldac = { dac8800, dac8043, ad8522 },
351 .ai_maxdata = 0x0fff,
352 .ai_fifo_depth = 512,
354 .gainlkup = ai_gain_16,
357 .ao_maxdata = 0x0fff,
358 .ao_fifo_depth = 2048,
359 .ao_range_table = &range_ni_E_ao_ext,
361 .caldac = { ad8804_debug },
366 .ai_maxdata = 0x0fff,
367 .ai_fifo_depth = 512,
368 .gainlkup = ai_gain_4,
370 .caldac = { ad8804_debug }, /* manual is wrong */
375 .ai_maxdata = 0x0fff,
376 .ai_fifo_depth = 512,
377 .gainlkup = ai_gain_4,
380 .ao_maxdata = 0x0fff,
381 .ao_range_table = &range_bipolar10,
383 .caldac = { ad8804_debug }, /* manual is wrong */
388 .ai_maxdata = 0x0fff,
389 .ai_fifo_depth = 512,
390 .gainlkup = ai_gain_4,
393 .ao_maxdata = 0x0fff,
394 .ao_range_table = &range_bipolar10,
396 .caldac = { ad8804_debug }, /* manual is wrong */
402 .ai_maxdata = 0x0fff,
403 .ai_fifo_depth = 512,
404 .gainlkup = ai_gain_4,
407 .ao_maxdata = 0x0fff,
408 .ao_range_table = &range_ni_E_ao_ext,
410 .caldac = { ad8804_debug }, /* manual is wrong */
416 .ai_maxdata = 0xffff,
417 .ai_fifo_depth = 512,
419 .gainlkup = ai_gain_4,
421 .caldac = { ad8804_debug },
426 .ai_maxdata = 0xffff,
427 .ai_fifo_depth = 512,
429 .gainlkup = ai_gain_4,
432 .ao_maxdata = 0x0fff,
433 .ao_range_table = &range_bipolar10,
435 .caldac = { ad8804_debug },
440 .ai_maxdata = 0xffff,
441 .ai_fifo_depth = 512,
443 .gainlkup = ai_gain_16,
446 .ao_maxdata = 0xffff,
447 .ao_fifo_depth = 2048,
448 .ao_range_table = &range_ni_E_ao_ext,
450 /* manual is wrong */
451 .caldac = { ad8804_debug, ad8804_debug, ad8522 },
456 .ai_maxdata = 0x0fff,
457 .ai_fifo_depth = 8192,
459 .gainlkup = ai_gain_611x,
462 .ao_maxdata = 0xffff,
463 .reg_type = ni_reg_611x,
464 .ao_range_table = &range_bipolar10,
465 .ao_fifo_depth = 2048,
467 .caldac = { ad8804, ad8804 },
472 .ai_maxdata = 0x0fff,
473 .ai_fifo_depth = 8192,
474 .gainlkup = ai_gain_611x,
477 .ao_maxdata = 0xffff,
478 .reg_type = ni_reg_611x,
479 .ao_range_table = &range_bipolar10,
480 .ao_fifo_depth = 2048,
482 .caldac = { ad8804, ad8804 },
485 /* The 6115 boards probably need their own driver */
486 [BOARD_PCI6115] = { /* .device_id = 0x2ed0, */
489 .ai_maxdata = 0x0fff,
490 .ai_fifo_depth = 8192,
491 .gainlkup = ai_gain_611x,
494 .ao_maxdata = 0xffff,
496 .ao_fifo_depth = 2048,
500 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
504 [BOARD_PXI6115] = { /* .device_id = ????, */
507 .ai_maxdata = 0x0fff,
508 .ai_fifo_depth = 8192,
509 .gainlkup = ai_gain_611x,
512 .ao_maxdata = 0xffff,
514 .ao_fifo_depth = 2048,
518 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
524 .ao_maxdata = 0x0fff,
525 /* data sheet says 8192, but fifo really holds 16384 samples */
526 .ao_fifo_depth = 16384,
527 .ao_range_table = &range_bipolar10,
529 .reg_type = ni_reg_6711,
530 .caldac = { ad8804_debug },
535 .ao_maxdata = 0x0fff,
536 .ao_fifo_depth = 16384,
537 .ao_range_table = &range_bipolar10,
539 .reg_type = ni_reg_6711,
540 .caldac = { ad8804_debug },
545 .ao_maxdata = 0x0fff,
546 .ao_fifo_depth = 16384,
547 .ao_range_table = &range_bipolar10,
549 .reg_type = ni_reg_6713,
550 .caldac = { ad8804_debug, ad8804_debug },
555 .ao_maxdata = 0x0fff,
556 .ao_fifo_depth = 16384,
557 .ao_range_table = &range_bipolar10,
559 .reg_type = ni_reg_6713,
560 .caldac = { ad8804_debug, ad8804_debug },
565 .ao_maxdata = 0xffff,
566 .ao_fifo_depth = 8192,
567 .ao_range_table = &range_bipolar10,
569 .reg_type = ni_reg_6711,
570 .caldac = { ad8804_debug },
573 [BOARD_PXI6731] = { /* .device_id = ????, */
576 .ao_maxdata = 0xffff,
577 .ao_fifo_depth = 8192,
578 .ao_range_table = &range_bipolar10,
579 .reg_type = ni_reg_6711,
580 .caldac = { ad8804_debug },
586 .ao_maxdata = 0xffff,
587 .ao_fifo_depth = 16384,
588 .ao_range_table = &range_bipolar10,
590 .reg_type = ni_reg_6713,
591 .caldac = { ad8804_debug, ad8804_debug },
596 .ao_maxdata = 0xffff,
597 .ao_fifo_depth = 16384,
598 .ao_range_table = &range_bipolar10,
600 .reg_type = ni_reg_6713,
601 .caldac = { ad8804_debug, ad8804_debug },
606 .ai_maxdata = 0x0fff,
607 .ai_fifo_depth = 512,
609 .gainlkup = ai_gain_16,
612 .ao_maxdata = 0x0fff,
613 .ao_fifo_depth = 2048,
614 .ao_range_table = &range_ni_E_ao_ext,
616 .caldac = { ad8804_debug },
621 .ai_maxdata = 0x0fff,
622 .ai_fifo_depth = 512,
624 .gainlkup = ai_gain_16,
627 .ao_maxdata = 0x0fff,
628 .ao_fifo_depth = 2048,
629 .ao_range_table = &range_ni_E_ao_ext,
631 .caldac = { ad8804_debug },
636 .ai_maxdata = 0xffff,
637 .ai_fifo_depth = 512,
639 .gainlkup = ai_gain_16,
642 .ao_maxdata = 0xffff,
643 .ao_fifo_depth = 2048,
644 .ao_range_table = &range_ni_E_ao_ext,
646 .caldac = { mb88341, mb88341, ad8522 },
651 .ai_maxdata = 0xffff,
652 .ai_fifo_depth = 512,
654 .gainlkup = ai_gain_14,
657 .ao_maxdata = 0xffff,
658 .ao_fifo_depth = 2048,
659 .ao_range_table = &range_ni_E_ao_ext,
661 .caldac = { dac8800, dac8043, ad8522 },
666 .ai_maxdata = 0xffff,
667 .ai_fifo_depth = 512,
669 .gainlkup = ai_gain_4,
672 .ao_maxdata = 0xffff,
673 .ao_range_table = &range_bipolar10,
675 .caldac = { ad8804_debug },
680 .ai_maxdata = 0xffff,
681 .ai_fifo_depth = 512, /* FIXME: guess */
682 .gainlkup = ai_gain_622x,
684 .reg_type = ni_reg_622x,
685 .caldac = { caldac_none },
690 .ai_maxdata = 0xffff,
691 .ai_fifo_depth = 512, /* FIXME: guess */
692 .gainlkup = ai_gain_622x,
694 .reg_type = ni_reg_622x,
695 .caldac = { caldac_none },
700 .ai_maxdata = 0xffff,
701 .ai_fifo_depth = 4095,
702 .gainlkup = ai_gain_622x,
705 .ao_maxdata = 0xffff,
706 .ao_fifo_depth = 8191,
707 .ao_range_table = &range_bipolar10,
708 .reg_type = ni_reg_622x,
710 .caldac = { caldac_none },
712 [BOARD_PCI6221_37PIN] = {
713 .name = "pci-6221_37pin",
715 .ai_maxdata = 0xffff,
716 .ai_fifo_depth = 4095,
717 .gainlkup = ai_gain_622x,
720 .ao_maxdata = 0xffff,
721 .ao_fifo_depth = 8191,
722 .ao_range_table = &range_bipolar10,
723 .reg_type = ni_reg_622x,
725 .caldac = { caldac_none },
730 .ai_maxdata = 0xffff,
731 .ai_fifo_depth = 4095,
732 .gainlkup = ai_gain_622x,
735 .ao_maxdata = 0xffff,
736 .ao_fifo_depth = 8191,
737 .ao_range_table = &range_bipolar10,
738 .reg_type = ni_reg_622x,
740 .caldac = { caldac_none },
745 .ai_maxdata = 0xffff,
746 .ai_fifo_depth = 4095,
747 .gainlkup = ai_gain_622x,
749 .reg_type = ni_reg_622x,
751 .caldac = { caldac_none },
756 .ai_maxdata = 0xffff,
757 .ai_fifo_depth = 4095,
758 .gainlkup = ai_gain_622x,
760 .reg_type = ni_reg_622x,
762 .caldac = { caldac_none },
767 .ai_maxdata = 0xffff,
768 .ai_fifo_depth = 4095,
769 .gainlkup = ai_gain_622x,
772 .ao_maxdata = 0xffff,
773 .ao_fifo_depth = 8191,
774 .ao_range_table = &range_bipolar10,
775 .reg_type = ni_reg_622x,
778 .caldac = { caldac_none },
783 .ai_maxdata = 0xffff,
784 .ai_fifo_depth = 4095,
785 .gainlkup = ai_gain_622x,
788 .ao_maxdata = 0xffff,
789 .ao_fifo_depth = 8191,
790 .ao_range_table = &range_bipolar10,
791 .reg_type = ni_reg_622x,
794 .caldac = { caldac_none },
799 .ai_maxdata = 0xffff,
800 .ai_fifo_depth = 4095,
801 .gainlkup = ai_gain_622x,
804 .ao_maxdata = 0xffff,
805 .ao_fifo_depth = 8191,
806 .ao_range_table = &range_bipolar10,
807 .reg_type = ni_reg_622x,
810 .caldac = { caldac_none },
815 .ai_maxdata = 0xffff,
816 .ai_fifo_depth = 4095,
817 .gainlkup = ai_gain_622x,
820 .ao_maxdata = 0xffff,
821 .ao_fifo_depth = 8191,
822 .ao_range_table = &range_bipolar10,
823 .reg_type = ni_reg_622x,
826 .caldac = { caldac_none },
831 .ai_maxdata = 0xffff,
832 .ai_fifo_depth = 4095,
833 .gainlkup = ai_gain_628x,
835 .reg_type = ni_reg_625x,
836 .caldac = { caldac_none },
841 .ai_maxdata = 0xffff,
842 .ai_fifo_depth = 4095,
843 .gainlkup = ai_gain_628x,
845 .reg_type = ni_reg_625x,
846 .caldac = { caldac_none },
851 .ai_maxdata = 0xffff,
852 .ai_fifo_depth = 4095,
853 .gainlkup = ai_gain_628x,
856 .ao_maxdata = 0xffff,
857 .ao_fifo_depth = 8191,
858 .ao_range_table = &range_ni_M_625x_ao,
859 .reg_type = ni_reg_625x,
861 .caldac = { caldac_none },
866 .ai_maxdata = 0xffff,
867 .ai_fifo_depth = 4095,
868 .gainlkup = ai_gain_628x,
871 .ao_maxdata = 0xffff,
872 .ao_fifo_depth = 8191,
873 .ao_range_table = &range_ni_M_625x_ao,
874 .reg_type = ni_reg_625x,
876 .caldac = { caldac_none },
881 .ai_maxdata = 0xffff,
882 .ai_fifo_depth = 4095,
883 .gainlkup = ai_gain_628x,
886 .ao_maxdata = 0xffff,
887 .ao_fifo_depth = 8191,
888 .ao_range_table = &range_ni_M_625x_ao,
889 .reg_type = ni_reg_625x,
891 .caldac = { caldac_none },
896 .ai_maxdata = 0xffff,
897 .ai_fifo_depth = 4095,
898 .gainlkup = ai_gain_628x,
901 .ao_maxdata = 0xffff,
902 .ao_fifo_depth = 8191,
903 .ao_range_table = &range_ni_M_625x_ao,
904 .reg_type = ni_reg_625x,
906 .caldac = { caldac_none },
911 .ai_maxdata = 0xffff,
912 .ai_fifo_depth = 4095,
913 .gainlkup = ai_gain_628x,
915 .reg_type = ni_reg_625x,
917 .caldac = { caldac_none },
922 .ai_maxdata = 0xffff,
923 .ai_fifo_depth = 4095,
924 .gainlkup = ai_gain_628x,
926 .reg_type = ni_reg_625x,
928 .caldac = { caldac_none },
933 .ai_maxdata = 0xffff,
934 .ai_fifo_depth = 4095,
935 .gainlkup = ai_gain_628x,
938 .ao_maxdata = 0xffff,
939 .ao_fifo_depth = 8191,
940 .ao_range_table = &range_ni_M_625x_ao,
941 .reg_type = ni_reg_625x,
944 .caldac = { caldac_none },
949 .ai_maxdata = 0xffff,
950 .ai_fifo_depth = 4095,
951 .gainlkup = ai_gain_628x,
954 .ao_maxdata = 0xffff,
955 .ao_fifo_depth = 8191,
956 .ao_range_table = &range_ni_M_625x_ao,
957 .reg_type = ni_reg_625x,
960 .caldac = { caldac_none },
965 .ai_maxdata = 0xffff,
966 .ai_fifo_depth = 4095,
967 .gainlkup = ai_gain_628x,
970 .ao_maxdata = 0xffff,
971 .ao_fifo_depth = 8191,
972 .ao_range_table = &range_ni_M_625x_ao,
973 .reg_type = ni_reg_625x,
976 .caldac = { caldac_none },
981 .ai_maxdata = 0xffff,
982 .ai_fifo_depth = 4095,
983 .gainlkup = ai_gain_628x,
986 .ao_maxdata = 0xffff,
987 .ao_fifo_depth = 8191,
988 .ao_range_table = &range_ni_M_625x_ao,
989 .reg_type = ni_reg_625x,
992 .caldac = { caldac_none },
997 .ai_maxdata = 0x3ffff,
998 .ai_fifo_depth = 2047,
999 .gainlkup = ai_gain_628x,
1001 .ao_fifo_depth = 8191,
1002 .reg_type = ni_reg_628x,
1003 .caldac = { caldac_none },
1008 .ai_maxdata = 0x3ffff,
1009 .ai_fifo_depth = 2047,
1010 .gainlkup = ai_gain_628x,
1012 .ao_fifo_depth = 8191,
1013 .reg_type = ni_reg_628x,
1014 .caldac = { caldac_none },
1019 .ai_maxdata = 0x3ffff,
1020 .ai_fifo_depth = 2047,
1021 .gainlkup = ai_gain_628x,
1024 .ao_maxdata = 0xffff,
1025 .ao_fifo_depth = 8191,
1026 .ao_range_table = &range_ni_M_628x_ao,
1027 .reg_type = ni_reg_628x,
1029 .caldac = { caldac_none },
1034 .ai_maxdata = 0x3ffff,
1035 .ai_fifo_depth = 2047,
1036 .gainlkup = ai_gain_628x,
1039 .ao_maxdata = 0xffff,
1040 .ao_fifo_depth = 8191,
1041 .ao_range_table = &range_ni_M_628x_ao,
1042 .reg_type = ni_reg_628x,
1044 .caldac = { caldac_none },
1049 .ai_maxdata = 0x3ffff,
1050 .ai_fifo_depth = 2047,
1051 .gainlkup = ai_gain_628x,
1053 .reg_type = ni_reg_628x,
1054 .has_32dio_chan = 1,
1055 .caldac = { caldac_none },
1060 .ai_maxdata = 0x3ffff,
1061 .ai_fifo_depth = 2047,
1062 .gainlkup = ai_gain_628x,
1064 .reg_type = ni_reg_628x,
1065 .has_32dio_chan = 1,
1066 .caldac = { caldac_none },
1071 .ai_maxdata = 0x3ffff,
1072 .ai_fifo_depth = 2047,
1073 .gainlkup = ai_gain_628x,
1076 .ao_maxdata = 0xffff,
1077 .ao_fifo_depth = 8191,
1078 .ao_range_table = &range_ni_M_628x_ao,
1079 .reg_type = ni_reg_628x,
1081 .has_32dio_chan = 1,
1082 .caldac = { caldac_none },
1087 .ai_maxdata = 0x3ffff,
1088 .ai_fifo_depth = 2047,
1089 .gainlkup = ai_gain_628x,
1092 .ao_maxdata = 0xffff,
1093 .ao_fifo_depth = 8191,
1094 .ao_range_table = &range_ni_M_628x_ao,
1095 .reg_type = ni_reg_628x,
1097 .has_32dio_chan = 1,
1098 .caldac = { caldac_none },
1103 .ai_maxdata = 0xffff,
1104 .ai_fifo_depth = 1024,
1105 .gainlkup = ai_gain_6143,
1107 .reg_type = ni_reg_6143,
1108 .caldac = { ad8804_debug, ad8804_debug },
1113 .ai_maxdata = 0xffff,
1114 .ai_fifo_depth = 1024,
1115 .gainlkup = ai_gain_6143,
1117 .reg_type = ni_reg_6143,
1118 .caldac = { ad8804_debug, ad8804_debug },
1122 #include "ni_mio_common.c"
1124 static int pcimio_ai_change(struct comedi_device *dev,
1125 struct comedi_subdevice *s)
1127 struct ni_private *devpriv = dev->private;
1130 ret = mite_buf_change(devpriv->ai_mite_ring, s);
1137 static int pcimio_ao_change(struct comedi_device *dev,
1138 struct comedi_subdevice *s)
1140 struct ni_private *devpriv = dev->private;
1143 ret = mite_buf_change(devpriv->ao_mite_ring, s);
1150 static int pcimio_gpct0_change(struct comedi_device *dev,
1151 struct comedi_subdevice *s)
1153 struct ni_private *devpriv = dev->private;
1156 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s);
1163 static int pcimio_gpct1_change(struct comedi_device *dev,
1164 struct comedi_subdevice *s)
1166 struct ni_private *devpriv = dev->private;
1169 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s);
1176 static int pcimio_dio_change(struct comedi_device *dev,
1177 struct comedi_subdevice *s)
1179 struct ni_private *devpriv = dev->private;
1182 ret = mite_buf_change(devpriv->cdo_mite_ring, s);
1189 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1191 struct ni_private *devpriv = dev->private;
1192 struct mite *mite = devpriv->mite;
1193 resource_size_t daq_phys_addr;
1194 static const int Start_Cal_EEPROM = 0x400;
1195 static const unsigned int window_size = 10;
1196 unsigned int old_iodwbsr_bits;
1197 unsigned int old_iodwbsr1_bits;
1198 unsigned int old_iodwcr1_bits;
1201 /* IO Window 1 needs to be temporarily mapped to read the eeprom */
1202 daq_phys_addr = pci_resource_start(mite->pcidev, 1);
1204 old_iodwbsr_bits = readl(mite->mmio + MITE_IODWBSR);
1205 old_iodwbsr1_bits = readl(mite->mmio + MITE_IODWBSR_1);
1206 old_iodwcr1_bits = readl(mite->mmio + MITE_IODWCR_1);
1207 writel(0x0, mite->mmio + MITE_IODWBSR);
1208 writel(((0x80 | window_size) | daq_phys_addr),
1209 mite->mmio + MITE_IODWBSR_1);
1210 writel(0x1 | old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1211 writel(0xf, mite->mmio + 0x30);
1213 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1214 devpriv->eeprom_buffer[i] = ni_readb(dev, Start_Cal_EEPROM + i);
1216 writel(old_iodwbsr1_bits, mite->mmio + MITE_IODWBSR_1);
1217 writel(old_iodwbsr_bits, mite->mmio + MITE_IODWBSR);
1218 writel(old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1219 writel(0x0, mite->mmio + 0x30);
1222 static void init_6143(struct comedi_device *dev)
1224 const struct ni_board_struct *board = dev->board_ptr;
1225 struct ni_private *devpriv = dev->private;
1227 /* Disable interrupts */
1228 ni_stc_writew(dev, 0, NISTC_INT_CTRL_REG);
1230 /* Initialise 6143 AI specific bits */
1232 /* Set G0,G1 DMA mode to E series version */
1233 ni_writeb(dev, 0x00, NI6143_MAGIC_REG);
1234 /* Set EOCMode, ADCMode and pipelinedelay */
1235 ni_writeb(dev, 0x80, NI6143_PIPELINE_DELAY_REG);
1237 ni_writeb(dev, 0x00, NI6143_EOC_SET_REG);
1239 /* Set the FIFO half full level */
1240 ni_writel(dev, board->ai_fifo_depth / 2, NI6143_AI_FIFO_FLAG_REG);
1242 /* Strobe Relay disable bit */
1243 devpriv->ai_calib_source_enabled = 0;
1244 ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_OFF,
1245 NI6143_CALIB_CHAN_REG);
1246 ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG);
1249 static void pcimio_detach(struct comedi_device *dev)
1251 struct ni_private *devpriv = dev->private;
1253 mio_common_detach(dev);
1255 free_irq(dev->irq, dev);
1257 mite_free_ring(devpriv->ai_mite_ring);
1258 mite_free_ring(devpriv->ao_mite_ring);
1259 mite_free_ring(devpriv->cdo_mite_ring);
1260 mite_free_ring(devpriv->gpct_mite_ring[0]);
1261 mite_free_ring(devpriv->gpct_mite_ring[1]);
1262 mite_detach(devpriv->mite);
1266 comedi_pci_disable(dev);
1269 static int pcimio_auto_attach(struct comedi_device *dev,
1270 unsigned long context)
1272 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1273 const struct ni_board_struct *board = NULL;
1274 struct ni_private *devpriv;
1278 if (context < ARRAY_SIZE(ni_boards))
1279 board = &ni_boards[context];
1282 dev->board_ptr = board;
1283 dev->board_name = board->name;
1285 ret = comedi_pci_enable(dev);
1289 ret = ni_alloc_private(dev);
1292 devpriv = dev->private;
1294 devpriv->mite = mite_attach(dev, false); /* use win0 */
1298 if (board->reg_type & ni_reg_m_series_mask)
1299 devpriv->is_m_series = 1;
1300 if (board->reg_type & ni_reg_6xxx_mask)
1301 devpriv->is_6xxx = 1;
1302 if (board->reg_type == ni_reg_611x)
1303 devpriv->is_611x = 1;
1304 if (board->reg_type == ni_reg_6143)
1305 devpriv->is_6143 = 1;
1306 if (board->reg_type == ni_reg_622x)
1307 devpriv->is_622x = 1;
1308 if (board->reg_type == ni_reg_625x)
1309 devpriv->is_625x = 1;
1310 if (board->reg_type == ni_reg_628x)
1311 devpriv->is_628x = 1;
1312 if (board->reg_type & ni_reg_67xx_mask)
1313 devpriv->is_67xx = 1;
1314 if (board->reg_type == ni_reg_6711)
1315 devpriv->is_6711 = 1;
1316 if (board->reg_type == ni_reg_6713)
1317 devpriv->is_6713 = 1;
1319 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1320 if (!devpriv->ai_mite_ring)
1322 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1323 if (!devpriv->ao_mite_ring)
1325 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1326 if (!devpriv->cdo_mite_ring)
1328 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1329 if (!devpriv->gpct_mite_ring[0])
1331 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1332 if (!devpriv->gpct_mite_ring[1])
1335 if (devpriv->is_m_series)
1336 m_series_init_eeprom_buffer(dev);
1337 if (devpriv->is_6143)
1342 ret = request_irq(irq, ni_E_interrupt, IRQF_SHARED,
1343 dev->board_name, dev);
1348 ret = ni_E_init(dev, 0, 1);
1352 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1353 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1354 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1355 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1356 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1361 static struct comedi_driver ni_pcimio_driver = {
1362 .driver_name = "ni_pcimio",
1363 .module = THIS_MODULE,
1364 .auto_attach = pcimio_auto_attach,
1365 .detach = pcimio_detach,
1368 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1369 const struct pci_device_id *id)
1371 return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1374 static const struct pci_device_id ni_pcimio_pci_table[] = {
1375 { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 }, /* 0x1620? */
1376 { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1377 { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1378 { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1379 { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1380 { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1381 { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1382 { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1383 { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1384 { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1385 { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1386 { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1387 { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1388 { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1389 { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1390 { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1391 { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1392 { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1393 { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1394 { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1395 { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1396 { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1397 { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1398 { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1399 { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1400 { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1401 { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1402 { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1403 { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1404 { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1405 { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1406 { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1407 { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1408 { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1409 { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1410 { PCI_VDEVICE(NI, 0x70ad), BOARD_PXI6251 },
1411 { PCI_VDEVICE(NI, 0x70ae), BOARD_PXI6220 },
1412 { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1413 { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1414 { PCI_VDEVICE(NI, 0x70b1), BOARD_PXI6229 },
1415 { PCI_VDEVICE(NI, 0x70b2), BOARD_PXI6259 },
1416 { PCI_VDEVICE(NI, 0x70b3), BOARD_PXI6289 },
1417 { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1418 { PCI_VDEVICE(NI, 0x70b5), BOARD_PXI6221 },
1419 { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1420 { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1421 { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1422 { PCI_VDEVICE(NI, 0x70b9), BOARD_PXI6250 },
1423 { PCI_VDEVICE(NI, 0x70ba), BOARD_PXI6254 },
1424 { PCI_VDEVICE(NI, 0x70bb), BOARD_PXI6280 },
1425 { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1426 { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1427 { PCI_VDEVICE(NI, 0x70be), BOARD_PXI6284 },
1428 { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1429 { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1430 { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1431 { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1432 { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1433 { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1434 { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1435 { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1436 { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1437 { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1438 { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1439 { PCI_VDEVICE(NI, 0x72e9), BOARD_PXIE6259 },
1442 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1444 static struct pci_driver ni_pcimio_pci_driver = {
1445 .name = "ni_pcimio",
1446 .id_table = ni_pcimio_pci_table,
1447 .probe = ni_pcimio_pci_probe,
1448 .remove = comedi_pci_auto_unconfig,
1450 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1452 MODULE_AUTHOR("Comedi http://www.comedi.org");
1453 MODULE_DESCRIPTION("Comedi low-level driver");
1454 MODULE_LICENSE("GPL");