drivers/staging/comedi/drivers/ni_tio.c

   1 /*
   2  * Support for NI general purpose counters
   3  *
   4  * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 /*
  18  * Module: ni_tio
  19  * Description: National Instruments general purpose counters
  20  * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  21  *         Herman.Bruyninckx@mech.kuleuven.ac.be,
  22  *         Wim.Meeussen@mech.kuleuven.ac.be,
  23  *         Klaas.Gadeyne@mech.kuleuven.ac.be,
  24  *         Frank Mori Hess <fmhess@users.sourceforge.net>
  25  * Updated: Thu Nov 16 09:50:32 EST 2006
  26  * Status: works
  27  *
  28  * This module is not used directly by end-users.  Rather, it
  29  * is used by other drivers (for example ni_660x and ni_pcimio)
  30  * to provide support for NI's general purpose counters.  It was
  31  * originally based on the counter code from ni_660x.c and
  32  * ni_mio_common.c.
  33  *
  34  * References:
  35  * DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  36  * DAQ 6601/6602 User Manual (NI 322137B-01)
  37  * 340934b.pdf  DAQ-STC reference manual
  38  *
  39  * TODO: Support use of both banks X and Y
  40  */
  41
  42 #include <linux/module.h>
  43 #include <linux/slab.h>
  44
  45 #include "ni_tio_internal.h"
  46
  47 /*
  48  * clock sources for ni e and m series boards,
  49  * get bits with GI_SRC_SEL()
  50  */
  51 #define NI_M_TIMEBASE_1_CLK             0x0     /* 20MHz */
  52 #define NI_M_PFI_CLK(x)                 (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  53 #define NI_M_RTSI_CLK(x)                (((x) == 7) ? 0x1b : (0xb + (x)))
  54 #define NI_M_TIMEBASE_2_CLK             0x12    /* 100KHz */
  55 #define NI_M_NEXT_TC_CLK                0x13
  56 #define NI_M_NEXT_GATE_CLK              0x14    /* Gi_Src_SubSelect=0 */
  57 #define NI_M_PXI_STAR_TRIGGER_CLK       0x14    /* Gi_Src_SubSelect=1 */
  58 #define NI_M_PXI10_CLK                  0x1d
  59 #define NI_M_TIMEBASE_3_CLK             0x1e    /* 80MHz, Gi_Src_SubSelect=0 */
  60 #define NI_M_ANALOG_TRIGGER_OUT_CLK     0x1e    /* Gi_Src_SubSelect=1 */
  61 #define NI_M_LOGIC_LOW_CLK              0x1f
  62 #define NI_M_MAX_PFI_CHAN               15
  63 #define NI_M_MAX_RTSI_CHAN              7
  64
  65 /*
  66  * clock sources for ni_660x boards,
  67  * get bits with GI_SRC_SEL()
  68  */
  69 #define NI_660X_TIMEBASE_1_CLK          0x0     /* 20MHz */
  70 #define NI_660X_SRC_PIN_I_CLK           0x1
  71 #define NI_660X_SRC_PIN_CLK(x)          (0x2 + (x))
  72 #define NI_660X_NEXT_GATE_CLK           0xa
  73 #define NI_660X_RTSI_CLK(x)             (0xb + (x))
  74 #define NI_660X_TIMEBASE_2_CLK          0x12    /* 100KHz */
  75 #define NI_660X_NEXT_TC_CLK             0x13
  76 #define NI_660X_TIMEBASE_3_CLK          0x1e    /* 80MHz */
  77 #define NI_660X_LOGIC_LOW_CLK           0x1f
  78 #define NI_660X_MAX_SRC_PIN             7
  79 #define NI_660X_MAX_RTSI_CHAN           6
  80
  81 /* ni m series gate_select */
  82 #define NI_M_TIMESTAMP_MUX_GATE_SEL     0x0
  83 #define NI_M_PFI_GATE_SEL(x)            (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  84 #define NI_M_RTSI_GATE_SEL(x)           (((x) == 7) ? 0x1b : (0xb + (x)))
  85 #define NI_M_AI_START2_GATE_SEL         0x12
  86 #define NI_M_PXI_STAR_TRIGGER_GATE_SEL  0x13
  87 #define NI_M_NEXT_OUT_GATE_SEL          0x14
  88 #define NI_M_AI_START1_GATE_SEL         0x1c
  89 #define NI_M_NEXT_SRC_GATE_SEL          0x1d
  90 #define NI_M_ANALOG_TRIG_OUT_GATE_SEL   0x1e
  91 #define NI_M_LOGIC_LOW_GATE_SEL         0x1f
  92
  93 /* ni_660x gate select */
  94 #define NI_660X_SRC_PIN_I_GATE_SEL      0x0
  95 #define NI_660X_GATE_PIN_I_GATE_SEL     0x1
  96 #define NI_660X_PIN_GATE_SEL(x)         (0x2 + (x))
  97 #define NI_660X_NEXT_SRC_GATE_SEL       0xa
  98 #define NI_660X_RTSI_GATE_SEL(x)        (0xb + (x))
  99 #define NI_660X_NEXT_OUT_GATE_SEL       0x14
 100 #define NI_660X_LOGIC_LOW_GATE_SEL      0x1f
 101 #define NI_660X_MAX_GATE_PIN            7
 102
 103 /* ni_660x second gate select */
 104 #define NI_660X_SRC_PIN_I_GATE2_SEL     0x0
 105 #define NI_660X_UD_PIN_I_GATE2_SEL      0x1
 106 #define NI_660X_UD_PIN_GATE2_SEL(x)     (0x2 + (x))
 107 #define NI_660X_NEXT_SRC_GATE2_SEL      0xa
 108 #define NI_660X_RTSI_GATE2_SEL(x)       (0xb + (x))
 109 #define NI_660X_NEXT_OUT_GATE2_SEL      0x14
 110 #define NI_660X_SELECTED_GATE2_SEL      0x1e
 111 #define NI_660X_LOGIC_LOW_GATE2_SEL     0x1f
 112 #define NI_660X_MAX_UP_DOWN_PIN         7
 113
 114 static inline unsigned int GI_PRESCALE_X2(enum ni_gpct_variant variant)
 115 {
 116         switch (variant) {
 117         case ni_gpct_variant_e_series:
 118         default:
 119                 return 0;
 120         case ni_gpct_variant_m_series:
 121                 return GI_M_PRESCALE_X2;
 122         case ni_gpct_variant_660x:
 123                 return GI_660X_PRESCALE_X2;
 124         }
 125 }
 126
 127 static inline unsigned int GI_PRESCALE_X8(enum ni_gpct_variant variant)
 128 {
 129         switch (variant) {
 130         case ni_gpct_variant_e_series:
 131         default:
 132                 return 0;
 133         case ni_gpct_variant_m_series:
 134                 return GI_M_PRESCALE_X8;
 135         case ni_gpct_variant_660x:
 136                 return GI_660X_PRESCALE_X8;
 137         }
 138 }
 139
 140 static bool ni_tio_has_gate2_registers(const struct ni_gpct_device *counter_dev)
 141 {
 142         switch (counter_dev->variant) {
 143         case ni_gpct_variant_e_series:
 144         default:
 145                 return false;
 146         case ni_gpct_variant_m_series:
 147         case ni_gpct_variant_660x:
 148                 return true;
 149         }
 150 }
 151
 152 /**
 153  * ni_tio_write() - Write a TIO register using the driver provided callback.
 154  * @counter: struct ni_gpct counter.
 155  * @value: the value to write
 156  * @reg: the register to write.
 157  */
 158 void ni_tio_write(struct ni_gpct *counter, unsigned int value,
 159                   enum ni_gpct_register reg)
 160 {
 161         if (reg < NITIO_NUM_REGS)
 162                 counter->counter_dev->write(counter, value, reg);
 163 }
 164 EXPORT_SYMBOL_GPL(ni_tio_write);
 165
 166 /**
 167  * ni_tio_read() - Read a TIO register using the driver provided callback.
 168  * @counter: struct ni_gpct counter.
 169  * @reg: the register to read.
 170  */
 171 unsigned int ni_tio_read(struct ni_gpct *counter, enum ni_gpct_register reg)
 172 {
 173         if (reg < NITIO_NUM_REGS)
 174                 return counter->counter_dev->read(counter, reg);
 175         return 0;
 176 }
 177 EXPORT_SYMBOL_GPL(ni_tio_read);
 178
 179 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
 180 {
 181         unsigned int cidx = counter->counter_index;
 182
 183         ni_tio_write(counter, GI_RESET(cidx), NITIO_RESET_REG(cidx));
 184 }
 185
 186 static int ni_tio_clock_period_ps(const struct ni_gpct *counter,
 187                                   unsigned int generic_clock_source,
 188                                   u64 *period_ps)
 189 {
 190         u64 clock_period_ps;
 191
 192         switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 193         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 194                 clock_period_ps = 50000;
 195                 break;
 196         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 197                 clock_period_ps = 10000000;
 198                 break;
 199         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 200                 clock_period_ps = 12500;
 201                 break;
 202         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 203                 clock_period_ps = 100000;
 204                 break;
 205         default:
 206                 /*
 207                  * clock period is specified by user with prescaling
 208                  * already taken into account.
 209                  */
 210                 *period_ps = counter->clock_period_ps;
 211                 return 0;
 212         }
 213
 214         switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 215         case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 216                 break;
 217         case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 218                 clock_period_ps *= 2;
 219                 break;
 220         case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 221                 clock_period_ps *= 8;
 222                 break;
 223         default:
 224                 return -EINVAL;
 225         }
 226         *period_ps = clock_period_ps;
 227         return 0;
 228 }
 229
 230 static void ni_tio_set_bits_transient(struct ni_gpct *counter,
 231                                       enum ni_gpct_register reg,
 232                                       unsigned int mask, unsigned int value,
 233                                       unsigned int transient)
 234 {
 235         struct ni_gpct_device *counter_dev = counter->counter_dev;
 236         unsigned long flags;
 237
 238         if (reg < NITIO_NUM_REGS) {
 239                 spin_lock_irqsave(&counter_dev->regs_lock, flags);
 240                 counter_dev->regs[reg] &= ~mask;
 241                 counter_dev->regs[reg] |= (value & mask);
 242                 ni_tio_write(counter, counter_dev->regs[reg] | transient, reg);
 243                 mmiowb();
 244                 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 245         }
 246 }
 247
 248 /**
 249  * ni_tio_set_bits() - Safely write a counter register.
 250  * @counter: struct ni_gpct counter.
 251  * @reg: the register to write.
 252  * @mask: the bits to change.
 253  * @value: the new bits value.
 254  *
 255  * Used to write to, and update the software copy, a register whose bits may
 256  * be twiddled in interrupt context, or whose software copy may be read in
 257  * interrupt context.
 258  */
 259 void ni_tio_set_bits(struct ni_gpct *counter, enum ni_gpct_register reg,
 260                      unsigned int mask, unsigned int value)
 261 {
 262         ni_tio_set_bits_transient(counter, reg, mask, value, 0x0);
 263 }
 264 EXPORT_SYMBOL_GPL(ni_tio_set_bits);
 265
 266 /**
 267  * ni_tio_get_soft_copy() - Safely read the software copy of a counter register.
 268  * @counter: struct ni_gpct counter.
 269  * @reg: the register to read.
 270  *
 271  * Used to get the software copy of a register whose bits might be modified
 272  * in interrupt context, or whose software copy might need to be read in
 273  * interrupt context.
 274  */
 275 unsigned int ni_tio_get_soft_copy(const struct ni_gpct *counter,
 276                                   enum ni_gpct_register reg)
 277 {
 278         struct ni_gpct_device *counter_dev = counter->counter_dev;
 279         unsigned int value = 0;
 280         unsigned long flags;
 281
 282         if (reg < NITIO_NUM_REGS) {
 283                 spin_lock_irqsave(&counter_dev->regs_lock, flags);
 284                 value = counter_dev->regs[reg];
 285                 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 286         }
 287         return value;
 288 }
 289 EXPORT_SYMBOL_GPL(ni_tio_get_soft_copy);
 290
 291 static unsigned int ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
 292 {
 293         struct ni_gpct_device *counter_dev = counter->counter_dev;
 294         unsigned int cidx = counter->counter_index;
 295         unsigned int counting_mode_bits =
 296                 ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx));
 297         unsigned int bits = 0;
 298
 299         if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 300             GI_SRC_POL_INVERT)
 301                 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
 302         if (counting_mode_bits & GI_PRESCALE_X2(counter_dev->variant))
 303                 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
 304         if (counting_mode_bits & GI_PRESCALE_X8(counter_dev->variant))
 305                 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
 306         return bits;
 307 }
 308
 309 static int ni_m_series_clock_src_select(const struct ni_gpct *counter,
 310                                         unsigned int *clk_src)
 311 {
 312         struct ni_gpct_device *counter_dev = counter->counter_dev;
 313         unsigned int cidx = counter->counter_index;
 314         unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
 315         unsigned int clock_source = 0;
 316         unsigned int src;
 317         unsigned int i;
 318
 319         src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
 320                                                   NITIO_INPUT_SEL_REG(cidx)));
 321
 322         switch (src) {
 323         case NI_M_TIMEBASE_1_CLK:
 324                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 325                 break;
 326         case NI_M_TIMEBASE_2_CLK:
 327                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 328                 break;
 329         case NI_M_TIMEBASE_3_CLK:
 330                 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
 331                         clock_source =
 332                             NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
 333                 else
 334                         clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 335                 break;
 336         case NI_M_LOGIC_LOW_CLK:
 337                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 338                 break;
 339         case NI_M_NEXT_GATE_CLK:
 340                 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
 341                         clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
 342                 else
 343                         clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 344                 break;
 345         case NI_M_PXI10_CLK:
 346                 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
 347                 break;
 348         case NI_M_NEXT_TC_CLK:
 349                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 350                 break;
 351         default:
 352                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 353                         if (src == NI_M_RTSI_CLK(i)) {
 354                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 355                                 break;
 356                         }
 357                 }
 358                 if (i <= NI_M_MAX_RTSI_CHAN)
 359                         break;
 360                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 361                         if (src == NI_M_PFI_CLK(i)) {
 362                                 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
 363                                 break;
 364                         }
 365                 }
 366                 if (i <= NI_M_MAX_PFI_CHAN)
 367                         break;
 368                 return -EINVAL;
 369         }
 370         clock_source |= ni_tio_clock_src_modifiers(counter);
 371         *clk_src = clock_source;
 372         return 0;
 373 }
 374
 375 static int ni_660x_clock_src_select(const struct ni_gpct *counter,
 376                                     unsigned int *clk_src)
 377 {
 378         unsigned int clock_source = 0;
 379         unsigned int cidx = counter->counter_index;
 380         unsigned int src;
 381         unsigned int i;
 382
 383         src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
 384                                                   NITIO_INPUT_SEL_REG(cidx)));
 385
 386         switch (src) {
 387         case NI_660X_TIMEBASE_1_CLK:
 388                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 389                 break;
 390         case NI_660X_TIMEBASE_2_CLK:
 391                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 392                 break;
 393         case NI_660X_TIMEBASE_3_CLK:
 394                 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 395                 break;
 396         case NI_660X_LOGIC_LOW_CLK:
 397                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 398                 break;
 399         case NI_660X_SRC_PIN_I_CLK:
 400                 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
 401                 break;
 402         case NI_660X_NEXT_GATE_CLK:
 403                 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 404                 break;
 405         case NI_660X_NEXT_TC_CLK:
 406                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 407                 break;
 408         default:
 409                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 410                         if (src == NI_660X_RTSI_CLK(i)) {
 411                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 412                                 break;
 413                         }
 414                 }
 415                 if (i <= NI_660X_MAX_RTSI_CHAN)
 416                         break;
 417                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 418                         if (src == NI_660X_SRC_PIN_CLK(i)) {
 419                                 clock_source =
 420                                     NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
 421                                 break;
 422                         }
 423                 }
 424                 if (i <= NI_660X_MAX_SRC_PIN)
 425                         break;
 426                 return -EINVAL;
 427         }
 428         clock_source |= ni_tio_clock_src_modifiers(counter);
 429         *clk_src = clock_source;
 430         return 0;
 431 }
 432
 433 static int ni_tio_generic_clock_src_select(const struct ni_gpct *counter,
 434                                            unsigned int *clk_src)
 435 {
 436         switch (counter->counter_dev->variant) {
 437         case ni_gpct_variant_e_series:
 438         case ni_gpct_variant_m_series:
 439         default:
 440                 return ni_m_series_clock_src_select(counter, clk_src);
 441         case ni_gpct_variant_660x:
 442                 return ni_660x_clock_src_select(counter, clk_src);
 443         }
 444 }
 445
 446 static void ni_tio_set_sync_mode(struct ni_gpct *counter)
 447 {
 448         struct ni_gpct_device *counter_dev = counter->counter_dev;
 449         unsigned int cidx = counter->counter_index;
 450         static const u64 min_normal_sync_period_ps = 25000;
 451         unsigned int mask = 0;
 452         unsigned int bits = 0;
 453         unsigned int reg;
 454         unsigned int mode;
 455         unsigned int clk_src = 0;
 456         u64 ps = 0;
 457         int ret;
 458         bool force_alt_sync;
 459
 460         /* only m series and 660x variants have counting mode registers */
 461         switch (counter_dev->variant) {
 462         case ni_gpct_variant_e_series:
 463         default:
 464                 return;
 465         case ni_gpct_variant_m_series:
 466                 mask = GI_M_ALT_SYNC;
 467                 break;
 468         case ni_gpct_variant_660x:
 469                 mask = GI_660X_ALT_SYNC;
 470                 break;
 471         }
 472
 473         reg = NITIO_CNT_MODE_REG(cidx);
 474         mode = ni_tio_get_soft_copy(counter, reg);
 475         switch (mode & GI_CNT_MODE_MASK) {
 476         case GI_CNT_MODE_QUADX1:
 477         case GI_CNT_MODE_QUADX2:
 478         case GI_CNT_MODE_QUADX4:
 479         case GI_CNT_MODE_SYNC_SRC:
 480                 force_alt_sync = true;
 481                 break;
 482         default:
 483                 force_alt_sync = false;
 484                 break;
 485         }
 486
 487         ret = ni_tio_generic_clock_src_select(counter, &clk_src);
 488         if (ret)
 489                 return;
 490         ret = ni_tio_clock_period_ps(counter, clk_src, &ps);
 491         if (ret)
 492                 return;
 493         /*
 494          * It's not clear what we should do if clock_period is unknown, so we
 495          * are not using the alt sync bit in that case.
 496          */
 497         if (force_alt_sync || (ps && ps < min_normal_sync_period_ps))
 498                 bits = mask;
 499
 500         ni_tio_set_bits(counter, reg, mask, bits);
 501 }
 502
 503 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned int mode)
 504 {
 505         struct ni_gpct_device *counter_dev = counter->counter_dev;
 506         unsigned int cidx = counter->counter_index;
 507         unsigned int mode_reg_mask;
 508         unsigned int mode_reg_values;
 509         unsigned int input_select_bits = 0;
 510         /* these bits map directly on to the mode register */
 511         static const unsigned int mode_reg_direct_mask =
 512             NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
 513             NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
 514             NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
 515             NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
 516
 517         mode_reg_mask = mode_reg_direct_mask | GI_RELOAD_SRC_SWITCHING;
 518         mode_reg_values = mode & mode_reg_direct_mask;
 519         switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
 520         case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
 521                 break;
 522         case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
 523                 mode_reg_values |= GI_RELOAD_SRC_SWITCHING;
 524                 break;
 525         case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
 526                 input_select_bits |= GI_GATE_SEL_LOAD_SRC;
 527                 mode_reg_mask |= GI_GATING_MODE_MASK;
 528                 mode_reg_values |= GI_LEVEL_GATING;
 529                 break;
 530         default:
 531                 break;
 532         }
 533         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 534                         mode_reg_mask, mode_reg_values);
 535
 536         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 537                 unsigned int bits = 0;
 538
 539                 bits |= GI_CNT_MODE(mode >> NI_GPCT_COUNTING_MODE_SHIFT);
 540                 bits |= GI_INDEX_PHASE((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT));
 541                 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
 542                         bits |= GI_INDEX_MODE;
 543                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 544                                 GI_CNT_MODE_MASK | GI_INDEX_PHASE_MASK |
 545                                 GI_INDEX_MODE, bits);
 546                 ni_tio_set_sync_mode(counter);
 547         }
 548
 549         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_CNT_DIR_MASK,
 550                         GI_CNT_DIR(mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT));
 551
 552         if (mode & NI_GPCT_OR_GATE_BIT)
 553                 input_select_bits |= GI_OR_GATE;
 554         if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
 555                 input_select_bits |= GI_OUTPUT_POL_INVERT;
 556         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 557                         GI_GATE_SEL_LOAD_SRC | GI_OR_GATE |
 558                         GI_OUTPUT_POL_INVERT, input_select_bits);
 559
 560         return 0;
 561 }
 562
 563 int ni_tio_arm(struct ni_gpct *counter, bool arm, unsigned int start_trigger)
 564 {
 565         struct ni_gpct_device *counter_dev = counter->counter_dev;
 566         unsigned int cidx = counter->counter_index;
 567         unsigned int transient_bits = 0;
 568
 569         if (arm) {
 570                 unsigned int mask = 0;
 571                 unsigned int bits = 0;
 572
 573                 /* only m series and 660x have counting mode registers */
 574                 switch (counter_dev->variant) {
 575                 case ni_gpct_variant_e_series:
 576                 default:
 577                         break;
 578                 case ni_gpct_variant_m_series:
 579                         mask = GI_M_HW_ARM_SEL_MASK;
 580                         break;
 581                 case ni_gpct_variant_660x:
 582                         mask = GI_660X_HW_ARM_SEL_MASK;
 583                         break;
 584                 }
 585
 586                 switch (start_trigger) {
 587                 case NI_GPCT_ARM_IMMEDIATE:
 588                         transient_bits |= GI_ARM;
 589                         break;
 590                 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
 591                         transient_bits |= GI_ARM | GI_ARM_COPY;
 592                         break;
 593                 default:
 594                         /*
 595                          * for m series and 660x, pass-through the least
 596                          * significant bits so we can figure out what select
 597                          * later
 598                          */
 599                         if (mask && (start_trigger & NI_GPCT_ARM_UNKNOWN)) {
 600                                 bits |= GI_HW_ARM_ENA |
 601                                         (GI_HW_ARM_SEL(start_trigger) & mask);
 602                         } else {
 603                                 return -EINVAL;
 604                         }
 605                         break;
 606                 }
 607
 608                 if (mask)
 609                         ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 610                                         GI_HW_ARM_ENA | mask, bits);
 611         } else {
 612                 transient_bits |= GI_DISARM;
 613         }
 614         ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
 615                                   0, 0, transient_bits);
 616         return 0;
 617 }
 618 EXPORT_SYMBOL_GPL(ni_tio_arm);
 619
 620 static int ni_660x_clk_src(unsigned int clock_source, unsigned int *bits)
 621 {
 622         unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 623         unsigned int ni_660x_clock;
 624         unsigned int i;
 625
 626         switch (clk_src) {
 627         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 628                 ni_660x_clock = NI_660X_TIMEBASE_1_CLK;
 629                 break;
 630         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 631                 ni_660x_clock = NI_660X_TIMEBASE_2_CLK;
 632                 break;
 633         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 634                 ni_660x_clock = NI_660X_TIMEBASE_3_CLK;
 635                 break;
 636         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 637                 ni_660x_clock = NI_660X_LOGIC_LOW_CLK;
 638                 break;
 639         case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
 640                 ni_660x_clock = NI_660X_SRC_PIN_I_CLK;
 641                 break;
 642         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 643                 ni_660x_clock = NI_660X_NEXT_GATE_CLK;
 644                 break;
 645         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 646                 ni_660x_clock = NI_660X_NEXT_TC_CLK;
 647                 break;
 648         default:
 649                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 650                         if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 651                                 ni_660x_clock = NI_660X_RTSI_CLK(i);
 652                                 break;
 653                         }
 654                 }
 655                 if (i <= NI_660X_MAX_RTSI_CHAN)
 656                         break;
 657                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 658                         if (clk_src == NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
 659                                 ni_660x_clock = NI_660X_SRC_PIN_CLK(i);
 660                                 break;
 661                         }
 662                 }
 663                 if (i <= NI_660X_MAX_SRC_PIN)
 664                         break;
 665                 return -EINVAL;
 666         }
 667         *bits = GI_SRC_SEL(ni_660x_clock);
 668         return 0;
 669 }
 670
 671 static int ni_m_clk_src(unsigned int clock_source, unsigned int *bits)
 672 {
 673         unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 674         unsigned int ni_m_series_clock;
 675         unsigned int i;
 676
 677         switch (clk_src) {
 678         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 679                 ni_m_series_clock = NI_M_TIMEBASE_1_CLK;
 680                 break;
 681         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 682                 ni_m_series_clock = NI_M_TIMEBASE_2_CLK;
 683                 break;
 684         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 685                 ni_m_series_clock = NI_M_TIMEBASE_3_CLK;
 686                 break;
 687         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 688                 ni_m_series_clock = NI_M_LOGIC_LOW_CLK;
 689                 break;
 690         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 691                 ni_m_series_clock = NI_M_NEXT_GATE_CLK;
 692                 break;
 693         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 694                 ni_m_series_clock = NI_M_NEXT_TC_CLK;
 695                 break;
 696         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 697                 ni_m_series_clock = NI_M_PXI10_CLK;
 698                 break;
 699         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 700                 ni_m_series_clock = NI_M_PXI_STAR_TRIGGER_CLK;
 701                 break;
 702         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 703                 ni_m_series_clock = NI_M_ANALOG_TRIGGER_OUT_CLK;
 704                 break;
 705         default:
 706                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 707                         if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 708                                 ni_m_series_clock = NI_M_RTSI_CLK(i);
 709                                 break;
 710                         }
 711                 }
 712                 if (i <= NI_M_MAX_RTSI_CHAN)
 713                         break;
 714                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 715                         if (clk_src == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
 716                                 ni_m_series_clock = NI_M_PFI_CLK(i);
 717                                 break;
 718                         }
 719                 }
 720                 if (i <= NI_M_MAX_PFI_CHAN)
 721                         break;
 722                 return -EINVAL;
 723         }
 724         *bits = GI_SRC_SEL(ni_m_series_clock);
 725         return 0;
 726 };
 727
 728 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
 729                                         unsigned int clock_source)
 730 {
 731         struct ni_gpct_device *counter_dev = counter->counter_dev;
 732         unsigned int cidx = counter->counter_index;
 733         unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
 734
 735         if (counter_dev->variant != ni_gpct_variant_m_series)
 736                 return;
 737         switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 738                 /* Gi_Source_Subselect is zero */
 739         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 740         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 741                 counter_dev->regs[second_gate_reg] &= ~GI_SRC_SUBSEL;
 742                 break;
 743                 /* Gi_Source_Subselect is one */
 744         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 745         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 746                 counter_dev->regs[second_gate_reg] |= GI_SRC_SUBSEL;
 747                 break;
 748                 /* Gi_Source_Subselect doesn't matter */
 749         default:
 750                 return;
 751         }
 752         ni_tio_write(counter, counter_dev->regs[second_gate_reg],
 753                      second_gate_reg);
 754 }
 755
 756 static int ni_tio_set_clock_src(struct ni_gpct *counter,
 757                                 unsigned int clock_source,
 758                                 unsigned int period_ns)
 759 {
 760         struct ni_gpct_device *counter_dev = counter->counter_dev;
 761         unsigned int cidx = counter->counter_index;
 762         unsigned int bits = 0;
 763         int ret;
 764
 765         switch (counter_dev->variant) {
 766         case ni_gpct_variant_660x:
 767                 ret = ni_660x_clk_src(clock_source, &bits);
 768                 break;
 769         case ni_gpct_variant_e_series:
 770         case ni_gpct_variant_m_series:
 771         default:
 772                 ret = ni_m_clk_src(clock_source, &bits);
 773                 break;
 774         }
 775         if (ret) {
 776                 struct comedi_device *dev = counter_dev->dev;
 777
 778                 dev_err(dev->class_dev, "invalid clock source 0x%x\n",
 779                         clock_source);
 780                 return ret;
 781         }
 782
 783         if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
 784                 bits |= GI_SRC_POL_INVERT;
 785         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 786                         GI_SRC_SEL_MASK | GI_SRC_POL_INVERT, bits);
 787         ni_tio_set_source_subselect(counter, clock_source);
 788
 789         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 790                 bits = 0;
 791                 switch (clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 792                 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 793                         break;
 794                 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 795                         bits |= GI_PRESCALE_X2(counter_dev->variant);
 796                         break;
 797                 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 798                         bits |= GI_PRESCALE_X8(counter_dev->variant);
 799                         break;
 800                 default:
 801                         return -EINVAL;
 802                 }
 803                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 804                                 GI_PRESCALE_X2(counter_dev->variant) |
 805                                 GI_PRESCALE_X8(counter_dev->variant), bits);
 806         }
 807         counter->clock_period_ps = period_ns * 1000;
 808         ni_tio_set_sync_mode(counter);
 809         return 0;
 810 }
 811
 812 static int ni_tio_get_clock_src(struct ni_gpct *counter,
 813                                 unsigned int *clock_source,
 814                                 unsigned int *period_ns)
 815 {
 816         u64 temp64 = 0;
 817         int ret;
 818
 819         ret = ni_tio_generic_clock_src_select(counter, clock_source);
 820         if (ret)
 821                 return ret;
 822         ret = ni_tio_clock_period_ps(counter, *clock_source, &temp64);
 823         if (ret)
 824                 return ret;
 825         do_div(temp64, 1000);   /* ps to ns */
 826         *period_ns = temp64;
 827         return 0;
 828 }
 829
 830 static int ni_660x_set_gate(struct ni_gpct *counter, unsigned int gate_source)
 831 {
 832         unsigned int chan = CR_CHAN(gate_source);
 833         unsigned int cidx = counter->counter_index;
 834         unsigned int gate_sel;
 835         unsigned int i;
 836
 837         switch (chan) {
 838         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 839                 gate_sel = NI_660X_NEXT_SRC_GATE_SEL;
 840                 break;
 841         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 842         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 843         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 844         case NI_GPCT_GATE_PIN_i_GATE_SELECT:
 845                 gate_sel = chan & 0x1f;
 846                 break;
 847         default:
 848                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 849                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 850                                 gate_sel = chan & 0x1f;
 851                                 break;
 852                         }
 853                 }
 854                 if (i <= NI_660X_MAX_RTSI_CHAN)
 855                         break;
 856                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
 857                         if (chan == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
 858                                 gate_sel = chan & 0x1f;
 859                                 break;
 860                         }
 861                 }
 862                 if (i <= NI_660X_MAX_GATE_PIN)
 863                         break;
 864                 return -EINVAL;
 865         }
 866         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 867                         GI_GATE_SEL_MASK, GI_GATE_SEL(gate_sel));
 868         return 0;
 869 }
 870
 871 static int ni_m_set_gate(struct ni_gpct *counter, unsigned int gate_source)
 872 {
 873         unsigned int chan = CR_CHAN(gate_source);
 874         unsigned int cidx = counter->counter_index;
 875         unsigned int gate_sel;
 876         unsigned int i;
 877
 878         switch (chan) {
 879         case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
 880         case NI_GPCT_AI_START2_GATE_SELECT:
 881         case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
 882         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 883         case NI_GPCT_AI_START1_GATE_SELECT:
 884         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 885         case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
 886         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 887                 gate_sel = chan & 0x1f;
 888                 break;
 889         default:
 890                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 891                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 892                                 gate_sel = chan & 0x1f;
 893                                 break;
 894                         }
 895                 }
 896                 if (i <= NI_M_MAX_RTSI_CHAN)
 897                         break;
 898                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 899                         if (chan == NI_GPCT_PFI_GATE_SELECT(i)) {
 900                                 gate_sel = chan & 0x1f;
 901                                 break;
 902                         }
 903                 }
 904                 if (i <= NI_M_MAX_PFI_CHAN)
 905                         break;
 906                 return -EINVAL;
 907         }
 908         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 909                         GI_GATE_SEL_MASK, GI_GATE_SEL(gate_sel));
 910         return 0;
 911 }
 912
 913 static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
 914 {
 915         struct ni_gpct_device *counter_dev = counter->counter_dev;
 916         unsigned int cidx = counter->counter_index;
 917         unsigned int chan = CR_CHAN(gate_source);
 918         unsigned int gate2_reg = NITIO_GATE2_REG(cidx);
 919         unsigned int gate2_sel;
 920         unsigned int i;
 921
 922         switch (chan) {
 923         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 924         case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
 925         case NI_GPCT_SELECTED_GATE_GATE_SELECT:
 926         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 927         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 928                 gate2_sel = chan & 0x1f;
 929                 break;
 930         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 931                 gate2_sel = NI_660X_NEXT_SRC_GATE2_SEL;
 932                 break;
 933         default:
 934                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 935                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 936                                 gate2_sel = chan & 0x1f;
 937                                 break;
 938                         }
 939                 }
 940                 if (i <= NI_660X_MAX_RTSI_CHAN)
 941                         break;
 942                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
 943                         if (chan == NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
 944                                 gate2_sel = chan & 0x1f;
 945                                 break;
 946                         }
 947                 }
 948                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
 949                         break;
 950                 return -EINVAL;
 951         }
 952         counter_dev->regs[gate2_reg] |= GI_GATE2_MODE;
 953         counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK;
 954         counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel);
 955         ni_tio_write(counter, counter_dev->regs[gate2_reg], gate2_reg);
 956         return 0;
 957 }
 958
 959 static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
 960 {
 961         struct ni_gpct_device *counter_dev = counter->counter_dev;
 962         unsigned int cidx = counter->counter_index;
 963         unsigned int chan = CR_CHAN(gate_source);
 964         unsigned int gate2_reg = NITIO_GATE2_REG(cidx);
 965         unsigned int gate2_sel;
 966
 967         /*
 968          * FIXME: We don't know what the m-series second gate codes are,
 969          * so we'll just pass the bits through for now.
 970          */
 971         switch (chan) {
 972         default:
 973                 gate2_sel = chan & 0x1f;
 974                 break;
 975         }
 976         counter_dev->regs[gate2_reg] |= GI_GATE2_MODE;
 977         counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK;
 978         counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel);
 979         ni_tio_write(counter, counter_dev->regs[gate2_reg], gate2_reg);
 980         return 0;
 981 }
 982
 983 int ni_tio_set_gate_src(struct ni_gpct *counter,
 984                         unsigned int gate, unsigned int src)
 985 {
 986         struct ni_gpct_device *counter_dev = counter->counter_dev;
 987         unsigned int cidx = counter->counter_index;
 988         unsigned int chan = CR_CHAN(src);
 989         unsigned int gate2_reg = NITIO_GATE2_REG(cidx);
 990         unsigned int mode = 0;
 991
 992         switch (gate) {
 993         case 0:
 994                 if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
 995                         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 996                                         GI_GATING_MODE_MASK,
 997                                         GI_GATING_DISABLED);
 998                         return 0;
 999                 }
1000                 if (src & CR_INVERT)
1001                         mode |= GI_GATE_POL_INVERT;
1002                 if (src & CR_EDGE)
1003                         mode |= GI_RISING_EDGE_GATING;
1004                 else
1005                         mode |= GI_LEVEL_GATING;
1006                 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
1007                                 GI_GATE_POL_INVERT | GI_GATING_MODE_MASK,
1008                                 mode);
1009                 switch (counter_dev->variant) {
1010                 case ni_gpct_variant_e_series:
1011                 case ni_gpct_variant_m_series:
1012                 default:
1013                         return ni_m_set_gate(counter, src);
1014                 case ni_gpct_variant_660x:
1015                         return ni_660x_set_gate(counter, src);
1016                 }
1017                 break;
1018         case 1:
1019                 if (!ni_tio_has_gate2_registers(counter_dev))
1020                         return -EINVAL;
1021
1022                 if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
1023                         counter_dev->regs[gate2_reg] &= ~GI_GATE2_MODE;
1024                         ni_tio_write(counter, counter_dev->regs[gate2_reg],
1025                                      gate2_reg);
1026                         return 0;
1027                 }
1028                 if (src & CR_INVERT)
1029                         counter_dev->regs[gate2_reg] |= GI_GATE2_POL_INVERT;
1030                 else
1031                         counter_dev->regs[gate2_reg] &= ~GI_GATE2_POL_INVERT;
1032                 switch (counter_dev->variant) {
1033                 case ni_gpct_variant_m_series:
1034                         return ni_m_set_gate2(counter, src);
1035                 case ni_gpct_variant_660x:
1036                         return ni_660x_set_gate2(counter, src);
1037                 default:
1038                         return -EINVAL;
1039                 }
1040                 break;
1041         default:
1042                 return -EINVAL;
1043         }
1044         return 0;
1045 }
1046 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1047
1048 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned int index,
1049                                 unsigned int source)
1050 {
1051         struct ni_gpct_device *counter_dev = counter->counter_dev;
1052         unsigned int cidx = counter->counter_index;
1053         unsigned int abz_reg, shift, mask;
1054
1055         if (counter_dev->variant != ni_gpct_variant_m_series)
1056                 return -EINVAL;
1057
1058         abz_reg = NITIO_ABZ_REG(cidx);
1059         switch (index) {
1060         case NI_GPCT_SOURCE_ENCODER_A:
1061                 shift = 10;
1062                 break;
1063         case NI_GPCT_SOURCE_ENCODER_B:
1064                 shift = 5;
1065                 break;
1066         case NI_GPCT_SOURCE_ENCODER_Z:
1067                 shift = 0;
1068                 break;
1069         default:
1070                 return -EINVAL;
1071         }
1072         mask = 0x1f << shift;
1073         if (source > 0x1f)
1074                 source = 0x1f;  /* Disable gate */
1075
1076         counter_dev->regs[abz_reg] &= ~mask;
1077         counter_dev->regs[abz_reg] |= (source << shift) & mask;
1078         ni_tio_write(counter, counter_dev->regs[abz_reg], abz_reg);
1079         return 0;
1080 }
1081
1082 static int ni_660x_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1083 {
1084         unsigned int source;
1085         unsigned int i;
1086
1087         switch (gate) {
1088         case NI_660X_SRC_PIN_I_GATE_SEL:
1089                 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1090                 break;
1091         case NI_660X_GATE_PIN_I_GATE_SEL:
1092                 source = NI_GPCT_GATE_PIN_i_GATE_SELECT;
1093                 break;
1094         case NI_660X_NEXT_SRC_GATE_SEL:
1095                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1096                 break;
1097         case NI_660X_NEXT_OUT_GATE_SEL:
1098                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1099                 break;
1100         case NI_660X_LOGIC_LOW_GATE_SEL:
1101                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1102                 break;
1103         default:
1104                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1105                         if (gate == NI_660X_RTSI_GATE_SEL(i)) {
1106                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1107                                 break;
1108                         }
1109                 }
1110                 if (i <= NI_660X_MAX_RTSI_CHAN)
1111                         break;
1112                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
1113                         if (gate == NI_660X_PIN_GATE_SEL(i)) {
1114                                 source = NI_GPCT_GATE_PIN_GATE_SELECT(i);
1115                                 break;
1116                         }
1117                 }
1118                 if (i <= NI_660X_MAX_GATE_PIN)
1119                         break;
1120                 return -EINVAL;
1121         }
1122         *src = source;
1123         return 0;
1124 };
1125
1126 static int ni_m_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1127 {
1128         unsigned int source;
1129         unsigned int i;
1130
1131         switch (gate) {
1132         case NI_M_TIMESTAMP_MUX_GATE_SEL:
1133                 source = NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1134                 break;
1135         case NI_M_AI_START2_GATE_SEL:
1136                 source = NI_GPCT_AI_START2_GATE_SELECT;
1137                 break;
1138         case NI_M_PXI_STAR_TRIGGER_GATE_SEL:
1139                 source = NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1140                 break;
1141         case NI_M_NEXT_OUT_GATE_SEL:
1142                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1143                 break;
1144         case NI_M_AI_START1_GATE_SEL:
1145                 source = NI_GPCT_AI_START1_GATE_SELECT;
1146                 break;
1147         case NI_M_NEXT_SRC_GATE_SEL:
1148                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1149                 break;
1150         case NI_M_ANALOG_TRIG_OUT_GATE_SEL:
1151                 source = NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1152                 break;
1153         case NI_M_LOGIC_LOW_GATE_SEL:
1154                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1155                 break;
1156         default:
1157                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
1158                         if (gate == NI_M_RTSI_GATE_SEL(i)) {
1159                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1160                                 break;
1161                         }
1162                 }
1163                 if (i <= NI_M_MAX_RTSI_CHAN)
1164                         break;
1165                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
1166                         if (gate == NI_M_PFI_GATE_SEL(i)) {
1167                                 source = NI_GPCT_PFI_GATE_SELECT(i);
1168                                 break;
1169                         }
1170                 }
1171                 if (i <= NI_M_MAX_PFI_CHAN)
1172                         break;
1173                 return -EINVAL;
1174         }
1175         *src = source;
1176         return 0;
1177 };
1178
1179 static int ni_660x_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1180 {
1181         unsigned int source;
1182         unsigned int i;
1183
1184         switch (gate) {
1185         case NI_660X_SRC_PIN_I_GATE2_SEL:
1186                 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1187                 break;
1188         case NI_660X_UD_PIN_I_GATE2_SEL:
1189                 source = NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1190                 break;
1191         case NI_660X_NEXT_SRC_GATE2_SEL:
1192                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1193                 break;
1194         case NI_660X_NEXT_OUT_GATE2_SEL:
1195                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1196                 break;
1197         case NI_660X_SELECTED_GATE2_SEL:
1198                 source = NI_GPCT_SELECTED_GATE_GATE_SELECT;
1199                 break;
1200         case NI_660X_LOGIC_LOW_GATE2_SEL:
1201                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1202                 break;
1203         default:
1204                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1205                         if (gate == NI_660X_RTSI_GATE2_SEL(i)) {
1206                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1207                                 break;
1208                         }
1209                 }
1210                 if (i <= NI_660X_MAX_RTSI_CHAN)
1211                         break;
1212                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
1213                         if (gate == NI_660X_UD_PIN_GATE2_SEL(i)) {
1214                                 source = NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1215                                 break;
1216                         }
1217                 }
1218                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
1219                         break;
1220                 return -EINVAL;
1221         }
1222         *src = source;
1223         return 0;
1224 };
1225
1226 static int ni_m_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1227 {
1228         /*
1229          * FIXME: the second gate sources for the m series are undocumented,
1230          * so we just return the raw bits for now.
1231          */
1232         *src = gate;
1233         return 0;
1234 };
1235
1236 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned int gate_index,
1237                                unsigned int *gate_source)
1238 {
1239         struct ni_gpct_device *counter_dev = counter->counter_dev;
1240         unsigned int cidx = counter->counter_index;
1241         unsigned int mode;
1242         unsigned int reg;
1243         unsigned int gate;
1244         int ret;
1245
1246         mode = ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx));
1247         if (((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED) ||
1248             (gate_index == 1 &&
1249              !(counter_dev->regs[NITIO_GATE2_REG(cidx)] & GI_GATE2_MODE))) {
1250                 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1251                 return 0;
1252         }
1253
1254         switch (gate_index) {
1255         case 0:
1256                 reg = NITIO_INPUT_SEL_REG(cidx);
1257                 gate = GI_BITS_TO_GATE(ni_tio_get_soft_copy(counter, reg));
1258
1259                 switch (counter_dev->variant) {
1260                 case ni_gpct_variant_e_series:
1261                 case ni_gpct_variant_m_series:
1262                 default:
1263                         ret = ni_m_gate_to_generic_gate(gate, gate_source);
1264                         break;
1265                 case ni_gpct_variant_660x:
1266                         ret = ni_660x_gate_to_generic_gate(gate, gate_source);
1267                         break;
1268                 }
1269                 if (ret)
1270                         return ret;
1271                 if (mode & GI_GATE_POL_INVERT)
1272                         *gate_source |= CR_INVERT;
1273                 if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
1274                         *gate_source |= CR_EDGE;
1275                 break;
1276         case 1:
1277                 reg = NITIO_GATE2_REG(cidx);
1278                 gate = GI_BITS_TO_GATE2(counter_dev->regs[reg]);
1279
1280                 switch (counter_dev->variant) {
1281                 case ni_gpct_variant_e_series:
1282                 case ni_gpct_variant_m_series:
1283                 default:
1284                         ret = ni_m_gate2_to_generic_gate(gate, gate_source);
1285                         break;
1286                 case ni_gpct_variant_660x:
1287                         ret = ni_660x_gate2_to_generic_gate(gate, gate_source);
1288                         break;
1289                 }
1290                 if (ret)
1291                         return ret;
1292                 if (counter_dev->regs[reg] & GI_GATE2_POL_INVERT)
1293                         *gate_source |= CR_INVERT;
1294                 /* second gate can't have edge/level mode set independently */
1295                 if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
1296                         *gate_source |= CR_EDGE;
1297                 break;
1298         default:
1299                 return -EINVAL;
1300         }
1301         return 0;
1302 }
1303
1304 int ni_tio_insn_config(struct comedi_device *dev,
1305                        struct comedi_subdevice *s,
1306                        struct comedi_insn *insn,
1307                        unsigned int *data)
1308 {
1309         struct ni_gpct *counter = s->private;
1310         unsigned int cidx = counter->counter_index;
1311         unsigned int status;
1312         int ret = 0;
1313
1314         switch (data[0]) {
1315         case INSN_CONFIG_SET_COUNTER_MODE:
1316                 ret = ni_tio_set_counter_mode(counter, data[1]);
1317                 break;
1318         case INSN_CONFIG_ARM:
1319                 ret = ni_tio_arm(counter, true, data[1]);
1320                 break;
1321         case INSN_CONFIG_DISARM:
1322                 ret = ni_tio_arm(counter, false, 0);
1323                 break;
1324         case INSN_CONFIG_GET_COUNTER_STATUS:
1325                 data[1] = 0;
1326                 status = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1327                 if (status & GI_ARMED(cidx)) {
1328                         data[1] |= COMEDI_COUNTER_ARMED;
1329                         if (status & GI_COUNTING(cidx))
1330                                 data[1] |= COMEDI_COUNTER_COUNTING;
1331                 }
1332                 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
1333                 break;
1334         case INSN_CONFIG_SET_CLOCK_SRC:
1335                 ret = ni_tio_set_clock_src(counter, data[1], data[2]);
1336                 break;
1337         case INSN_CONFIG_GET_CLOCK_SRC:
1338                 ret = ni_tio_get_clock_src(counter, &data[1], &data[2]);
1339                 break;
1340         case INSN_CONFIG_SET_GATE_SRC:
1341                 ret = ni_tio_set_gate_src(counter, data[1], data[2]);
1342                 break;
1343         case INSN_CONFIG_GET_GATE_SRC:
1344                 ret = ni_tio_get_gate_src(counter, data[1], &data[2]);
1345                 break;
1346         case INSN_CONFIG_SET_OTHER_SRC:
1347                 ret = ni_tio_set_other_src(counter, data[1], data[2]);
1348                 break;
1349         case INSN_CONFIG_RESET:
1350                 ni_tio_reset_count_and_disarm(counter);
1351                 break;
1352         default:
1353                 return -EINVAL;
1354         }
1355         return ret ? ret : insn->n;
1356 }
1357 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1358
1359 static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev,
1360                                             struct comedi_subdevice *s)
1361 {
1362         struct ni_gpct *counter = s->private;
1363         unsigned int cidx = counter->counter_index;
1364         unsigned int val;
1365
1366         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
1367         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1368                         GI_SAVE_TRACE, GI_SAVE_TRACE);
1369
1370         /*
1371          * The count doesn't get latched until the next clock edge, so it is
1372          * possible the count may change (once) while we are reading. Since
1373          * the read of the SW_Save_Reg isn't atomic (apparently even when it's
1374          * a 32 bit register according to 660x docs), we need to read twice
1375          * and make sure the reading hasn't changed. If it has, a third read
1376          * will be correct since the count value will definitely have latched
1377          * by then.
1378          */
1379         val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1380         if (val != ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx)))
1381                 val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1382
1383         return val;
1384 }
1385
1386 int ni_tio_insn_read(struct comedi_device *dev,
1387                      struct comedi_subdevice *s,
1388                      struct comedi_insn *insn,
1389                      unsigned int *data)
1390 {
1391         struct ni_gpct *counter = s->private;
1392         struct ni_gpct_device *counter_dev = counter->counter_dev;
1393         unsigned int channel = CR_CHAN(insn->chanspec);
1394         unsigned int cidx = counter->counter_index;
1395         int i;
1396
1397         for (i = 0; i < insn->n; i++) {
1398                 switch (channel) {
1399                 case 0:
1400                         data[i] = ni_tio_read_sw_save_reg(dev, s);
1401                         break;
1402                 case 1:
1403                         data[i] = counter_dev->regs[NITIO_LOADA_REG(cidx)];
1404                         break;
1405                 case 2:
1406                         data[i] = counter_dev->regs[NITIO_LOADB_REG(cidx)];
1407                         break;
1408                 }
1409         }
1410         return insn->n;
1411 }
1412 EXPORT_SYMBOL_GPL(ni_tio_insn_read);
1413
1414 static unsigned int ni_tio_next_load_register(struct ni_gpct *counter)
1415 {
1416         unsigned int cidx = counter->counter_index;
1417         unsigned int bits = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1418
1419         return (bits & GI_NEXT_LOAD_SRC(cidx))
1420                         ? NITIO_LOADB_REG(cidx)
1421                         : NITIO_LOADA_REG(cidx);
1422 }
1423
1424 int ni_tio_insn_write(struct comedi_device *dev,
1425                       struct comedi_subdevice *s,
1426                       struct comedi_insn *insn,
1427                       unsigned int *data)
1428 {
1429         struct ni_gpct *counter = s->private;
1430         struct ni_gpct_device *counter_dev = counter->counter_dev;
1431         unsigned int channel = CR_CHAN(insn->chanspec);
1432         unsigned int cidx = counter->counter_index;
1433         unsigned int load_reg;
1434
1435         if (insn->n < 1)
1436                 return 0;
1437         switch (channel) {
1438         case 0:
1439                 /*
1440                  * Unsafe if counter is armed.
1441                  * Should probably check status and return -EBUSY if armed.
1442                  */
1443
1444                 /*
1445                  * Don't disturb load source select, just use whichever
1446                  * load register is already selected.
1447                  */
1448                 load_reg = ni_tio_next_load_register(counter);
1449                 ni_tio_write(counter, data[0], load_reg);
1450                 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
1451                                           0, 0, GI_LOAD);
1452                 /* restore load reg */
1453                 ni_tio_write(counter, counter_dev->regs[load_reg], load_reg);
1454                 break;
1455         case 1:
1456                 counter_dev->regs[NITIO_LOADA_REG(cidx)] = data[0];
1457                 ni_tio_write(counter, data[0], NITIO_LOADA_REG(cidx));
1458                 break;
1459         case 2:
1460                 counter_dev->regs[NITIO_LOADB_REG(cidx)] = data[0];
1461                 ni_tio_write(counter, data[0], NITIO_LOADB_REG(cidx));
1462                 break;
1463         default:
1464                 return -EINVAL;
1465         }
1466         return 0;
1467 }
1468 EXPORT_SYMBOL_GPL(ni_tio_insn_write);
1469
1470 void ni_tio_init_counter(struct ni_gpct *counter)
1471 {
1472         struct ni_gpct_device *counter_dev = counter->counter_dev;
1473         unsigned int cidx = counter->counter_index;
1474
1475         ni_tio_reset_count_and_disarm(counter);
1476
1477         /* initialize counter registers */
1478         counter_dev->regs[NITIO_AUTO_INC_REG(cidx)] = 0x0;
1479         ni_tio_write(counter, 0x0, NITIO_AUTO_INC_REG(cidx));
1480
1481         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1482                         ~0, GI_SYNC_GATE);
1483
1484         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0);
1485
1486         counter_dev->regs[NITIO_LOADA_REG(cidx)] = 0x0;
1487         ni_tio_write(counter, 0x0, NITIO_LOADA_REG(cidx));
1488
1489         counter_dev->regs[NITIO_LOADB_REG(cidx)] = 0x0;
1490         ni_tio_write(counter, 0x0, NITIO_LOADB_REG(cidx));
1491
1492         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0);
1493
1494         if (ni_tio_counting_mode_registers_present(counter_dev))
1495                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0);
1496
1497         if (ni_tio_has_gate2_registers(counter_dev)) {
1498                 counter_dev->regs[NITIO_GATE2_REG(cidx)] = 0x0;
1499                 ni_tio_write(counter, 0x0, NITIO_GATE2_REG(cidx));
1500         }
1501
1502         ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0);
1503
1504         ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0);
1505 }
1506 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
1507
1508 struct ni_gpct_device *
1509 ni_gpct_device_construct(struct comedi_device *dev,
1510                          void (*write)(struct ni_gpct *counter,
1511                                        unsigned int value,
1512                                        enum ni_gpct_register reg),
1513                          unsigned int (*read)(struct ni_gpct *counter,
1514                                               enum ni_gpct_register reg),
1515                          enum ni_gpct_variant variant,
1516                          unsigned int num_counters)
1517 {
1518         struct ni_gpct_device *counter_dev;
1519         struct ni_gpct *counter;
1520         unsigned int i;
1521
1522         if (num_counters == 0)
1523                 return NULL;
1524
1525         counter_dev = kzalloc(sizeof(*counter_dev), GFP_KERNEL);
1526         if (!counter_dev)
1527                 return NULL;
1528
1529         counter_dev->dev = dev;
1530         counter_dev->write = write;
1531         counter_dev->read = read;
1532         counter_dev->variant = variant;
1533
1534         spin_lock_init(&counter_dev->regs_lock);
1535
1536         counter_dev->counters = kcalloc(num_counters, sizeof(*counter),
1537                                         GFP_KERNEL);
1538         if (!counter_dev->counters) {
1539                 kfree(counter_dev);
1540                 return NULL;
1541         }
1542
1543         for (i = 0; i < num_counters; ++i) {
1544                 counter = &counter_dev->counters[i];
1545                 counter->counter_dev = counter_dev;
1546                 spin_lock_init(&counter->lock);
1547         }
1548         counter_dev->num_counters = num_counters;
1549
1550         return counter_dev;
1551 }
1552 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
1553
1554 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
1555 {
1556         if (!counter_dev)
1557                 return;
1558         kfree(counter_dev->counters);
1559         kfree(counter_dev);
1560 }
1561 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
1562
1563 static int __init ni_tio_init_module(void)
1564 {
1565         return 0;
1566 }
1567 module_init(ni_tio_init_module);
1568
1569 static void __exit ni_tio_cleanup_module(void)
1570 {
1571 }
1572 module_exit(ni_tio_cleanup_module);
1573
1574 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
1575 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
1576 MODULE_LICENSE("GPL");