drivers/staging/comedi/drivers/ni_tio.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Support for NI general purpose counters
   4  *
   5  * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   6  */
   7
   8 /*
   9  * Module: ni_tio
  10  * Description: National Instruments general purpose counters
  11  * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  12  *         Herman.Bruyninckx@mech.kuleuven.ac.be,
  13  *         Wim.Meeussen@mech.kuleuven.ac.be,
  14  *         Klaas.Gadeyne@mech.kuleuven.ac.be,
  15  *         Frank Mori Hess <fmhess@users.sourceforge.net>
  16  * Updated: Thu Nov 16 09:50:32 EST 2006
  17  * Status: works
  18  *
  19  * This module is not used directly by end-users.  Rather, it
  20  * is used by other drivers (for example ni_660x and ni_pcimio)
  21  * to provide support for NI's general purpose counters.  It was
  22  * originally based on the counter code from ni_660x.c and
  23  * ni_mio_common.c.
  24  *
  25  * References:
  26  * DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  27  * DAQ 6601/6602 User Manual (NI 322137B-01)
  28  * 340934b.pdf  DAQ-STC reference manual
  29  *
  30  * TODO: Support use of both banks X and Y
  31  */
  32
  33 #include <linux/module.h>
  34 #include <linux/slab.h>
  35
  36 #include "ni_tio_internal.h"
  37
  38 /*
  39  * clock sources for ni e and m series boards,
  40  * get bits with GI_SRC_SEL()
  41  */
  42 #define NI_M_TIMEBASE_1_CLK             0x0     /* 20MHz */
  43 #define NI_M_PFI_CLK(x)                 (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  44 #define NI_M_RTSI_CLK(x)                (((x) == 7) ? 0x1b : (0xb + (x)))
  45 #define NI_M_TIMEBASE_2_CLK             0x12    /* 100KHz */
  46 #define NI_M_NEXT_TC_CLK                0x13
  47 #define NI_M_NEXT_GATE_CLK              0x14    /* Gi_Src_SubSelect=0 */
  48 #define NI_M_PXI_STAR_TRIGGER_CLK       0x14    /* Gi_Src_SubSelect=1 */
  49 #define NI_M_PXI10_CLK                  0x1d
  50 #define NI_M_TIMEBASE_3_CLK             0x1e    /* 80MHz, Gi_Src_SubSelect=0 */
  51 #define NI_M_ANALOG_TRIGGER_OUT_CLK     0x1e    /* Gi_Src_SubSelect=1 */
  52 #define NI_M_LOGIC_LOW_CLK              0x1f
  53 #define NI_M_MAX_PFI_CHAN               15
  54 #define NI_M_MAX_RTSI_CHAN              7
  55
  56 /*
  57  * clock sources for ni_660x boards,
  58  * get bits with GI_SRC_SEL()
  59  */
  60 #define NI_660X_TIMEBASE_1_CLK          0x0     /* 20MHz */
  61 #define NI_660X_SRC_PIN_I_CLK           0x1
  62 #define NI_660X_SRC_PIN_CLK(x)          (0x2 + (x))
  63 #define NI_660X_NEXT_GATE_CLK           0xa
  64 #define NI_660X_RTSI_CLK(x)             (0xb + (x))
  65 #define NI_660X_TIMEBASE_2_CLK          0x12    /* 100KHz */
  66 #define NI_660X_NEXT_TC_CLK             0x13
  67 #define NI_660X_TIMEBASE_3_CLK          0x1e    /* 80MHz */
  68 #define NI_660X_LOGIC_LOW_CLK           0x1f
  69 #define NI_660X_MAX_SRC_PIN             7
  70 #define NI_660X_MAX_RTSI_CHAN           6
  71
  72 /* ni m series gate_select */
  73 #define NI_M_TIMESTAMP_MUX_GATE_SEL     0x0
  74 #define NI_M_PFI_GATE_SEL(x)            (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  75 #define NI_M_RTSI_GATE_SEL(x)           (((x) == 7) ? 0x1b : (0xb + (x)))
  76 #define NI_M_AI_START2_GATE_SEL         0x12
  77 #define NI_M_PXI_STAR_TRIGGER_GATE_SEL  0x13
  78 #define NI_M_NEXT_OUT_GATE_SEL          0x14
  79 #define NI_M_AI_START1_GATE_SEL         0x1c
  80 #define NI_M_NEXT_SRC_GATE_SEL          0x1d
  81 #define NI_M_ANALOG_TRIG_OUT_GATE_SEL   0x1e
  82 #define NI_M_LOGIC_LOW_GATE_SEL         0x1f
  83
  84 /* ni_660x gate select */
  85 #define NI_660X_SRC_PIN_I_GATE_SEL      0x0
  86 #define NI_660X_GATE_PIN_I_GATE_SEL     0x1
  87 #define NI_660X_PIN_GATE_SEL(x)         (0x2 + (x))
  88 #define NI_660X_NEXT_SRC_GATE_SEL       0xa
  89 #define NI_660X_RTSI_GATE_SEL(x)        (0xb + (x))
  90 #define NI_660X_NEXT_OUT_GATE_SEL       0x14
  91 #define NI_660X_LOGIC_LOW_GATE_SEL      0x1f
  92 #define NI_660X_MAX_GATE_PIN            7
  93
  94 /* ni_660x second gate select */
  95 #define NI_660X_SRC_PIN_I_GATE2_SEL     0x0
  96 #define NI_660X_UD_PIN_I_GATE2_SEL      0x1
  97 #define NI_660X_UD_PIN_GATE2_SEL(x)     (0x2 + (x))
  98 #define NI_660X_NEXT_SRC_GATE2_SEL      0xa
  99 #define NI_660X_RTSI_GATE2_SEL(x)       (0xb + (x))
 100 #define NI_660X_NEXT_OUT_GATE2_SEL      0x14
 101 #define NI_660X_SELECTED_GATE2_SEL      0x1e
 102 #define NI_660X_LOGIC_LOW_GATE2_SEL     0x1f
 103 #define NI_660X_MAX_UP_DOWN_PIN         7
 104
 105 static inline unsigned int GI_PRESCALE_X2(enum ni_gpct_variant variant)
 106 {
 107         switch (variant) {
 108         case ni_gpct_variant_e_series:
 109         default:
 110                 return 0;
 111         case ni_gpct_variant_m_series:
 112                 return GI_M_PRESCALE_X2;
 113         case ni_gpct_variant_660x:
 114                 return GI_660X_PRESCALE_X2;
 115         }
 116 }
 117
 118 static inline unsigned int GI_PRESCALE_X8(enum ni_gpct_variant variant)
 119 {
 120         switch (variant) {
 121         case ni_gpct_variant_e_series:
 122         default:
 123                 return 0;
 124         case ni_gpct_variant_m_series:
 125                 return GI_M_PRESCALE_X8;
 126         case ni_gpct_variant_660x:
 127                 return GI_660X_PRESCALE_X8;
 128         }
 129 }
 130
 131 static bool ni_tio_has_gate2_registers(const struct ni_gpct_device *counter_dev)
 132 {
 133         switch (counter_dev->variant) {
 134         case ni_gpct_variant_e_series:
 135         default:
 136                 return false;
 137         case ni_gpct_variant_m_series:
 138         case ni_gpct_variant_660x:
 139                 return true;
 140         }
 141 }
 142
 143 /**
 144  * ni_tio_write() - Write a TIO register using the driver provided callback.
 145  * @counter: struct ni_gpct counter.
 146  * @value: the value to write
 147  * @reg: the register to write.
 148  */
 149 void ni_tio_write(struct ni_gpct *counter, unsigned int value,
 150                   enum ni_gpct_register reg)
 151 {
 152         if (reg < NITIO_NUM_REGS)
 153                 counter->counter_dev->write(counter, value, reg);
 154 }
 155 EXPORT_SYMBOL_GPL(ni_tio_write);
 156
 157 /**
 158  * ni_tio_read() - Read a TIO register using the driver provided callback.
 159  * @counter: struct ni_gpct counter.
 160  * @reg: the register to read.
 161  */
 162 unsigned int ni_tio_read(struct ni_gpct *counter, enum ni_gpct_register reg)
 163 {
 164         if (reg < NITIO_NUM_REGS)
 165                 return counter->counter_dev->read(counter, reg);
 166         return 0;
 167 }
 168 EXPORT_SYMBOL_GPL(ni_tio_read);
 169
 170 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
 171 {
 172         unsigned int cidx = counter->counter_index;
 173
 174         ni_tio_write(counter, GI_RESET(cidx), NITIO_RESET_REG(cidx));
 175 }
 176
 177 static int ni_tio_clock_period_ps(const struct ni_gpct *counter,
 178                                   unsigned int generic_clock_source,
 179                                   u64 *period_ps)
 180 {
 181         u64 clock_period_ps;
 182
 183         switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 184         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 185                 clock_period_ps = 50000;
 186                 break;
 187         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 188                 clock_period_ps = 10000000;
 189                 break;
 190         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 191                 clock_period_ps = 12500;
 192                 break;
 193         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 194                 clock_period_ps = 100000;
 195                 break;
 196         default:
 197                 /*
 198                  * clock period is specified by user with prescaling
 199                  * already taken into account.
 200                  */
 201                 *period_ps = counter->clock_period_ps;
 202                 return 0;
 203         }
 204
 205         switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 206         case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 207                 break;
 208         case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 209                 clock_period_ps *= 2;
 210                 break;
 211         case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 212                 clock_period_ps *= 8;
 213                 break;
 214         default:
 215                 return -EINVAL;
 216         }
 217         *period_ps = clock_period_ps;
 218         return 0;
 219 }
 220
 221 static void ni_tio_set_bits_transient(struct ni_gpct *counter,
 222                                       enum ni_gpct_register reg,
 223                                       unsigned int mask, unsigned int value,
 224                                       unsigned int transient)
 225 {
 226         struct ni_gpct_device *counter_dev = counter->counter_dev;
 227         unsigned long flags;
 228
 229         if (reg < NITIO_NUM_REGS) {
 230                 spin_lock_irqsave(&counter_dev->regs_lock, flags);
 231                 counter_dev->regs[reg] &= ~mask;
 232                 counter_dev->regs[reg] |= (value & mask);
 233                 ni_tio_write(counter, counter_dev->regs[reg] | transient, reg);
 234                 mmiowb();
 235                 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 236         }
 237 }
 238
 239 /**
 240  * ni_tio_set_bits() - Safely write a counter register.
 241  * @counter: struct ni_gpct counter.
 242  * @reg: the register to write.
 243  * @mask: the bits to change.
 244  * @value: the new bits value.
 245  *
 246  * Used to write to, and update the software copy, a register whose bits may
 247  * be twiddled in interrupt context, or whose software copy may be read in
 248  * interrupt context.
 249  */
 250 void ni_tio_set_bits(struct ni_gpct *counter, enum ni_gpct_register reg,
 251                      unsigned int mask, unsigned int value)
 252 {
 253         ni_tio_set_bits_transient(counter, reg, mask, value, 0x0);
 254 }
 255 EXPORT_SYMBOL_GPL(ni_tio_set_bits);
 256
 257 /**
 258  * ni_tio_get_soft_copy() - Safely read the software copy of a counter register.
 259  * @counter: struct ni_gpct counter.
 260  * @reg: the register to read.
 261  *
 262  * Used to get the software copy of a register whose bits might be modified
 263  * in interrupt context, or whose software copy might need to be read in
 264  * interrupt context.
 265  */
 266 unsigned int ni_tio_get_soft_copy(const struct ni_gpct *counter,
 267                                   enum ni_gpct_register reg)
 268 {
 269         struct ni_gpct_device *counter_dev = counter->counter_dev;
 270         unsigned int value = 0;
 271         unsigned long flags;
 272
 273         if (reg < NITIO_NUM_REGS) {
 274                 spin_lock_irqsave(&counter_dev->regs_lock, flags);
 275                 value = counter_dev->regs[reg];
 276                 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 277         }
 278         return value;
 279 }
 280 EXPORT_SYMBOL_GPL(ni_tio_get_soft_copy);
 281
 282 static unsigned int ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
 283 {
 284         struct ni_gpct_device *counter_dev = counter->counter_dev;
 285         unsigned int cidx = counter->counter_index;
 286         unsigned int counting_mode_bits =
 287                 ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx));
 288         unsigned int bits = 0;
 289
 290         if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 291             GI_SRC_POL_INVERT)
 292                 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
 293         if (counting_mode_bits & GI_PRESCALE_X2(counter_dev->variant))
 294                 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
 295         if (counting_mode_bits & GI_PRESCALE_X8(counter_dev->variant))
 296                 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
 297         return bits;
 298 }
 299
 300 static int ni_m_series_clock_src_select(const struct ni_gpct *counter,
 301                                         unsigned int *clk_src)
 302 {
 303         struct ni_gpct_device *counter_dev = counter->counter_dev;
 304         unsigned int cidx = counter->counter_index;
 305         unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
 306         unsigned int clock_source = 0;
 307         unsigned int src;
 308         unsigned int i;
 309
 310         src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
 311                                                   NITIO_INPUT_SEL_REG(cidx)));
 312
 313         switch (src) {
 314         case NI_M_TIMEBASE_1_CLK:
 315                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 316                 break;
 317         case NI_M_TIMEBASE_2_CLK:
 318                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 319                 break;
 320         case NI_M_TIMEBASE_3_CLK:
 321                 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
 322                         clock_source =
 323                             NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
 324                 else
 325                         clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 326                 break;
 327         case NI_M_LOGIC_LOW_CLK:
 328                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 329                 break;
 330         case NI_M_NEXT_GATE_CLK:
 331                 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
 332                         clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
 333                 else
 334                         clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 335                 break;
 336         case NI_M_PXI10_CLK:
 337                 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
 338                 break;
 339         case NI_M_NEXT_TC_CLK:
 340                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 341                 break;
 342         default:
 343                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 344                         if (src == NI_M_RTSI_CLK(i)) {
 345                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 346                                 break;
 347                         }
 348                 }
 349                 if (i <= NI_M_MAX_RTSI_CHAN)
 350                         break;
 351                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 352                         if (src == NI_M_PFI_CLK(i)) {
 353                                 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
 354                                 break;
 355                         }
 356                 }
 357                 if (i <= NI_M_MAX_PFI_CHAN)
 358                         break;
 359                 return -EINVAL;
 360         }
 361         clock_source |= ni_tio_clock_src_modifiers(counter);
 362         *clk_src = clock_source;
 363         return 0;
 364 }
 365
 366 static int ni_660x_clock_src_select(const struct ni_gpct *counter,
 367                                     unsigned int *clk_src)
 368 {
 369         unsigned int clock_source = 0;
 370         unsigned int cidx = counter->counter_index;
 371         unsigned int src;
 372         unsigned int i;
 373
 374         src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
 375                                                   NITIO_INPUT_SEL_REG(cidx)));
 376
 377         switch (src) {
 378         case NI_660X_TIMEBASE_1_CLK:
 379                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 380                 break;
 381         case NI_660X_TIMEBASE_2_CLK:
 382                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 383                 break;
 384         case NI_660X_TIMEBASE_3_CLK:
 385                 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 386                 break;
 387         case NI_660X_LOGIC_LOW_CLK:
 388                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 389                 break;
 390         case NI_660X_SRC_PIN_I_CLK:
 391                 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
 392                 break;
 393         case NI_660X_NEXT_GATE_CLK:
 394                 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 395                 break;
 396         case NI_660X_NEXT_TC_CLK:
 397                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 398                 break;
 399         default:
 400                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 401                         if (src == NI_660X_RTSI_CLK(i)) {
 402                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 403                                 break;
 404                         }
 405                 }
 406                 if (i <= NI_660X_MAX_RTSI_CHAN)
 407                         break;
 408                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 409                         if (src == NI_660X_SRC_PIN_CLK(i)) {
 410                                 clock_source =
 411                                     NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
 412                                 break;
 413                         }
 414                 }
 415                 if (i <= NI_660X_MAX_SRC_PIN)
 416                         break;
 417                 return -EINVAL;
 418         }
 419         clock_source |= ni_tio_clock_src_modifiers(counter);
 420         *clk_src = clock_source;
 421         return 0;
 422 }
 423
 424 static int ni_tio_generic_clock_src_select(const struct ni_gpct *counter,
 425                                            unsigned int *clk_src)
 426 {
 427         switch (counter->counter_dev->variant) {
 428         case ni_gpct_variant_e_series:
 429         case ni_gpct_variant_m_series:
 430         default:
 431                 return ni_m_series_clock_src_select(counter, clk_src);
 432         case ni_gpct_variant_660x:
 433                 return ni_660x_clock_src_select(counter, clk_src);
 434         }
 435 }
 436
 437 static void ni_tio_set_sync_mode(struct ni_gpct *counter)
 438 {
 439         struct ni_gpct_device *counter_dev = counter->counter_dev;
 440         unsigned int cidx = counter->counter_index;
 441         static const u64 min_normal_sync_period_ps = 25000;
 442         unsigned int mask = 0;
 443         unsigned int bits = 0;
 444         unsigned int reg;
 445         unsigned int mode;
 446         unsigned int clk_src = 0;
 447         u64 ps = 0;
 448         int ret;
 449         bool force_alt_sync;
 450
 451         /* only m series and 660x variants have counting mode registers */
 452         switch (counter_dev->variant) {
 453         case ni_gpct_variant_e_series:
 454         default:
 455                 return;
 456         case ni_gpct_variant_m_series:
 457                 mask = GI_M_ALT_SYNC;
 458                 break;
 459         case ni_gpct_variant_660x:
 460                 mask = GI_660X_ALT_SYNC;
 461                 break;
 462         }
 463
 464         reg = NITIO_CNT_MODE_REG(cidx);
 465         mode = ni_tio_get_soft_copy(counter, reg);
 466         switch (mode & GI_CNT_MODE_MASK) {
 467         case GI_CNT_MODE_QUADX1:
 468         case GI_CNT_MODE_QUADX2:
 469         case GI_CNT_MODE_QUADX4:
 470         case GI_CNT_MODE_SYNC_SRC:
 471                 force_alt_sync = true;
 472                 break;
 473         default:
 474                 force_alt_sync = false;
 475                 break;
 476         }
 477
 478         ret = ni_tio_generic_clock_src_select(counter, &clk_src);
 479         if (ret)
 480                 return;
 481         ret = ni_tio_clock_period_ps(counter, clk_src, &ps);
 482         if (ret)
 483                 return;
 484         /*
 485          * It's not clear what we should do if clock_period is unknown, so we
 486          * are not using the alt sync bit in that case.
 487          */
 488         if (force_alt_sync || (ps && ps < min_normal_sync_period_ps))
 489                 bits = mask;
 490
 491         ni_tio_set_bits(counter, reg, mask, bits);
 492 }
 493
 494 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned int mode)
 495 {
 496         struct ni_gpct_device *counter_dev = counter->counter_dev;
 497         unsigned int cidx = counter->counter_index;
 498         unsigned int mode_reg_mask;
 499         unsigned int mode_reg_values;
 500         unsigned int input_select_bits = 0;
 501         /* these bits map directly on to the mode register */
 502         static const unsigned int mode_reg_direct_mask =
 503             NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
 504             NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
 505             NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
 506             NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
 507
 508         mode_reg_mask = mode_reg_direct_mask | GI_RELOAD_SRC_SWITCHING;
 509         mode_reg_values = mode & mode_reg_direct_mask;
 510         switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
 511         case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
 512                 break;
 513         case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
 514                 mode_reg_values |= GI_RELOAD_SRC_SWITCHING;
 515                 break;
 516         case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
 517                 input_select_bits |= GI_GATE_SEL_LOAD_SRC;
 518                 mode_reg_mask |= GI_GATING_MODE_MASK;
 519                 mode_reg_values |= GI_LEVEL_GATING;
 520                 break;
 521         default:
 522                 break;
 523         }
 524         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 525                         mode_reg_mask, mode_reg_values);
 526
 527         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 528                 unsigned int bits = 0;
 529
 530                 bits |= GI_CNT_MODE(mode >> NI_GPCT_COUNTING_MODE_SHIFT);
 531                 bits |= GI_INDEX_PHASE((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT));
 532                 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
 533                         bits |= GI_INDEX_MODE;
 534                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 535                                 GI_CNT_MODE_MASK | GI_INDEX_PHASE_MASK |
 536                                 GI_INDEX_MODE, bits);
 537                 ni_tio_set_sync_mode(counter);
 538         }
 539
 540         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_CNT_DIR_MASK,
 541                         GI_CNT_DIR(mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT));
 542
 543         if (mode & NI_GPCT_OR_GATE_BIT)
 544                 input_select_bits |= GI_OR_GATE;
 545         if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
 546                 input_select_bits |= GI_OUTPUT_POL_INVERT;
 547         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 548                         GI_GATE_SEL_LOAD_SRC | GI_OR_GATE |
 549                         GI_OUTPUT_POL_INVERT, input_select_bits);
 550
 551         return 0;
 552 }
 553
 554 int ni_tio_arm(struct ni_gpct *counter, bool arm, unsigned int start_trigger)
 555 {
 556         struct ni_gpct_device *counter_dev = counter->counter_dev;
 557         unsigned int cidx = counter->counter_index;
 558         unsigned int transient_bits = 0;
 559
 560         if (arm) {
 561                 unsigned int mask = 0;
 562                 unsigned int bits = 0;
 563
 564                 /* only m series and 660x have counting mode registers */
 565                 switch (counter_dev->variant) {
 566                 case ni_gpct_variant_e_series:
 567                 default:
 568                         break;
 569                 case ni_gpct_variant_m_series:
 570                         mask = GI_M_HW_ARM_SEL_MASK;
 571                         break;
 572                 case ni_gpct_variant_660x:
 573                         mask = GI_660X_HW_ARM_SEL_MASK;
 574                         break;
 575                 }
 576
 577                 switch (start_trigger) {
 578                 case NI_GPCT_ARM_IMMEDIATE:
 579                         transient_bits |= GI_ARM;
 580                         break;
 581                 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
 582                         transient_bits |= GI_ARM | GI_ARM_COPY;
 583                         break;
 584                 default:
 585                         /*
 586                          * for m series and 660x, pass-through the least
 587                          * significant bits so we can figure out what select
 588                          * later
 589                          */
 590                         if (mask && (start_trigger & NI_GPCT_ARM_UNKNOWN)) {
 591                                 bits |= GI_HW_ARM_ENA |
 592                                         (GI_HW_ARM_SEL(start_trigger) & mask);
 593                         } else {
 594                                 return -EINVAL;
 595                         }
 596                         break;
 597                 }
 598
 599                 if (mask)
 600                         ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 601                                         GI_HW_ARM_ENA | mask, bits);
 602         } else {
 603                 transient_bits |= GI_DISARM;
 604         }
 605         ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
 606                                   0, 0, transient_bits);
 607         return 0;
 608 }
 609 EXPORT_SYMBOL_GPL(ni_tio_arm);
 610
 611 static int ni_660x_clk_src(unsigned int clock_source, unsigned int *bits)
 612 {
 613         unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 614         unsigned int ni_660x_clock;
 615         unsigned int i;
 616
 617         switch (clk_src) {
 618         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 619                 ni_660x_clock = NI_660X_TIMEBASE_1_CLK;
 620                 break;
 621         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 622                 ni_660x_clock = NI_660X_TIMEBASE_2_CLK;
 623                 break;
 624         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 625                 ni_660x_clock = NI_660X_TIMEBASE_3_CLK;
 626                 break;
 627         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 628                 ni_660x_clock = NI_660X_LOGIC_LOW_CLK;
 629                 break;
 630         case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
 631                 ni_660x_clock = NI_660X_SRC_PIN_I_CLK;
 632                 break;
 633         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 634                 ni_660x_clock = NI_660X_NEXT_GATE_CLK;
 635                 break;
 636         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 637                 ni_660x_clock = NI_660X_NEXT_TC_CLK;
 638                 break;
 639         default:
 640                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 641                         if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 642                                 ni_660x_clock = NI_660X_RTSI_CLK(i);
 643                                 break;
 644                         }
 645                 }
 646                 if (i <= NI_660X_MAX_RTSI_CHAN)
 647                         break;
 648                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 649                         if (clk_src == NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
 650                                 ni_660x_clock = NI_660X_SRC_PIN_CLK(i);
 651                                 break;
 652                         }
 653                 }
 654                 if (i <= NI_660X_MAX_SRC_PIN)
 655                         break;
 656                 return -EINVAL;
 657         }
 658         *bits = GI_SRC_SEL(ni_660x_clock);
 659         return 0;
 660 }
 661
 662 static int ni_m_clk_src(unsigned int clock_source, unsigned int *bits)
 663 {
 664         unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 665         unsigned int ni_m_series_clock;
 666         unsigned int i;
 667
 668         switch (clk_src) {
 669         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 670                 ni_m_series_clock = NI_M_TIMEBASE_1_CLK;
 671                 break;
 672         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 673                 ni_m_series_clock = NI_M_TIMEBASE_2_CLK;
 674                 break;
 675         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 676                 ni_m_series_clock = NI_M_TIMEBASE_3_CLK;
 677                 break;
 678         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 679                 ni_m_series_clock = NI_M_LOGIC_LOW_CLK;
 680                 break;
 681         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 682                 ni_m_series_clock = NI_M_NEXT_GATE_CLK;
 683                 break;
 684         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 685                 ni_m_series_clock = NI_M_NEXT_TC_CLK;
 686                 break;
 687         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 688                 ni_m_series_clock = NI_M_PXI10_CLK;
 689                 break;
 690         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 691                 ni_m_series_clock = NI_M_PXI_STAR_TRIGGER_CLK;
 692                 break;
 693         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 694                 ni_m_series_clock = NI_M_ANALOG_TRIGGER_OUT_CLK;
 695                 break;
 696         default:
 697                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 698                         if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 699                                 ni_m_series_clock = NI_M_RTSI_CLK(i);
 700                                 break;
 701                         }
 702                 }
 703                 if (i <= NI_M_MAX_RTSI_CHAN)
 704                         break;
 705                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 706                         if (clk_src == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
 707                                 ni_m_series_clock = NI_M_PFI_CLK(i);
 708                                 break;
 709                         }
 710                 }
 711                 if (i <= NI_M_MAX_PFI_CHAN)
 712                         break;
 713                 return -EINVAL;
 714         }
 715         *bits = GI_SRC_SEL(ni_m_series_clock);
 716         return 0;
 717 };
 718
 719 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
 720                                         unsigned int clock_source)
 721 {
 722         struct ni_gpct_device *counter_dev = counter->counter_dev;
 723         unsigned int cidx = counter->counter_index;
 724         unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
 725
 726         if (counter_dev->variant != ni_gpct_variant_m_series)
 727                 return;
 728         switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 729                 /* Gi_Source_Subselect is zero */
 730         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 731         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 732                 counter_dev->regs[second_gate_reg] &= ~GI_SRC_SUBSEL;
 733                 break;
 734                 /* Gi_Source_Subselect is one */
 735         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 736         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 737                 counter_dev->regs[second_gate_reg] |= GI_SRC_SUBSEL;
 738                 break;
 739                 /* Gi_Source_Subselect doesn't matter */
 740         default:
 741                 return;
 742         }
 743         ni_tio_write(counter, counter_dev->regs[second_gate_reg],
 744                      second_gate_reg);
 745 }
 746
 747 static int ni_tio_set_clock_src(struct ni_gpct *counter,
 748                                 unsigned int clock_source,
 749                                 unsigned int period_ns)
 750 {
 751         struct ni_gpct_device *counter_dev = counter->counter_dev;
 752         unsigned int cidx = counter->counter_index;
 753         unsigned int bits = 0;
 754         int ret;
 755
 756         switch (counter_dev->variant) {
 757         case ni_gpct_variant_660x:
 758                 ret = ni_660x_clk_src(clock_source, &bits);
 759                 break;
 760         case ni_gpct_variant_e_series:
 761         case ni_gpct_variant_m_series:
 762         default:
 763                 ret = ni_m_clk_src(clock_source, &bits);
 764                 break;
 765         }
 766         if (ret) {
 767                 struct comedi_device *dev = counter_dev->dev;
 768
 769                 dev_err(dev->class_dev, "invalid clock source 0x%x\n",
 770                         clock_source);
 771                 return ret;
 772         }
 773
 774         if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
 775                 bits |= GI_SRC_POL_INVERT;
 776         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 777                         GI_SRC_SEL_MASK | GI_SRC_POL_INVERT, bits);
 778         ni_tio_set_source_subselect(counter, clock_source);
 779
 780         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 781                 bits = 0;
 782                 switch (clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 783                 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 784                         break;
 785                 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 786                         bits |= GI_PRESCALE_X2(counter_dev->variant);
 787                         break;
 788                 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 789                         bits |= GI_PRESCALE_X8(counter_dev->variant);
 790                         break;
 791                 default:
 792                         return -EINVAL;
 793                 }
 794                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 795                                 GI_PRESCALE_X2(counter_dev->variant) |
 796                                 GI_PRESCALE_X8(counter_dev->variant), bits);
 797         }
 798         counter->clock_period_ps = period_ns * 1000;
 799         ni_tio_set_sync_mode(counter);
 800         return 0;
 801 }
 802
 803 static int ni_tio_get_clock_src(struct ni_gpct *counter,
 804                                 unsigned int *clock_source,
 805                                 unsigned int *period_ns)
 806 {
 807         u64 temp64 = 0;
 808         int ret;
 809
 810         ret = ni_tio_generic_clock_src_select(counter, clock_source);
 811         if (ret)
 812                 return ret;
 813         ret = ni_tio_clock_period_ps(counter, *clock_source, &temp64);
 814         if (ret)
 815                 return ret;
 816         do_div(temp64, 1000);   /* ps to ns */
 817         *period_ns = temp64;
 818         return 0;
 819 }
 820
 821 static int ni_660x_set_gate(struct ni_gpct *counter, unsigned int gate_source)
 822 {
 823         unsigned int chan = CR_CHAN(gate_source);
 824         unsigned int cidx = counter->counter_index;
 825         unsigned int gate_sel;
 826         unsigned int i;
 827
 828         switch (chan) {
 829         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 830                 gate_sel = NI_660X_NEXT_SRC_GATE_SEL;
 831                 break;
 832         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 833         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 834         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 835         case NI_GPCT_GATE_PIN_i_GATE_SELECT:
 836                 gate_sel = chan & 0x1f;
 837                 break;
 838         default:
 839                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 840                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 841                                 gate_sel = chan & 0x1f;
 842                                 break;
 843                         }
 844                 }
 845                 if (i <= NI_660X_MAX_RTSI_CHAN)
 846                         break;
 847                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
 848                         if (chan == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
 849                                 gate_sel = chan & 0x1f;
 850                                 break;
 851                         }
 852                 }
 853                 if (i <= NI_660X_MAX_GATE_PIN)
 854                         break;
 855                 return -EINVAL;
 856         }
 857         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 858                         GI_GATE_SEL_MASK, GI_GATE_SEL(gate_sel));
 859         return 0;
 860 }
 861
 862 static int ni_m_set_gate(struct ni_gpct *counter, unsigned int gate_source)
 863 {
 864         unsigned int chan = CR_CHAN(gate_source);
 865         unsigned int cidx = counter->counter_index;
 866         unsigned int gate_sel;
 867         unsigned int i;
 868
 869         switch (chan) {
 870         case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
 871         case NI_GPCT_AI_START2_GATE_SELECT:
 872         case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
 873         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 874         case NI_GPCT_AI_START1_GATE_SELECT:
 875         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 876         case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
 877         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 878                 gate_sel = chan & 0x1f;
 879                 break;
 880         default:
 881                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 882                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 883                                 gate_sel = chan & 0x1f;
 884                                 break;
 885                         }
 886                 }
 887                 if (i <= NI_M_MAX_RTSI_CHAN)
 888                         break;
 889                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 890                         if (chan == NI_GPCT_PFI_GATE_SELECT(i)) {
 891                                 gate_sel = chan & 0x1f;
 892                                 break;
 893                         }
 894                 }
 895                 if (i <= NI_M_MAX_PFI_CHAN)
 896                         break;
 897                 return -EINVAL;
 898         }
 899         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 900                         GI_GATE_SEL_MASK, GI_GATE_SEL(gate_sel));
 901         return 0;
 902 }
 903
 904 static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
 905 {
 906         struct ni_gpct_device *counter_dev = counter->counter_dev;
 907         unsigned int cidx = counter->counter_index;
 908         unsigned int chan = CR_CHAN(gate_source);
 909         unsigned int gate2_reg = NITIO_GATE2_REG(cidx);
 910         unsigned int gate2_sel;
 911         unsigned int i;
 912
 913         switch (chan) {
 914         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 915         case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
 916         case NI_GPCT_SELECTED_GATE_GATE_SELECT:
 917         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 918         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 919                 gate2_sel = chan & 0x1f;
 920                 break;
 921         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 922                 gate2_sel = NI_660X_NEXT_SRC_GATE2_SEL;
 923                 break;
 924         default:
 925                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 926                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 927                                 gate2_sel = chan & 0x1f;
 928                                 break;
 929                         }
 930                 }
 931                 if (i <= NI_660X_MAX_RTSI_CHAN)
 932                         break;
 933                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
 934                         if (chan == NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
 935                                 gate2_sel = chan & 0x1f;
 936                                 break;
 937                         }
 938                 }
 939                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
 940                         break;
 941                 return -EINVAL;
 942         }
 943         counter_dev->regs[gate2_reg] |= GI_GATE2_MODE;
 944         counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK;
 945         counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel);
 946         ni_tio_write(counter, counter_dev->regs[gate2_reg], gate2_reg);
 947         return 0;
 948 }
 949
 950 static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
 951 {
 952         struct ni_gpct_device *counter_dev = counter->counter_dev;
 953         unsigned int cidx = counter->counter_index;
 954         unsigned int chan = CR_CHAN(gate_source);
 955         unsigned int gate2_reg = NITIO_GATE2_REG(cidx);
 956         unsigned int gate2_sel;
 957
 958         /*
 959          * FIXME: We don't know what the m-series second gate codes are,
 960          * so we'll just pass the bits through for now.
 961          */
 962         switch (chan) {
 963         default:
 964                 gate2_sel = chan & 0x1f;
 965                 break;
 966         }
 967         counter_dev->regs[gate2_reg] |= GI_GATE2_MODE;
 968         counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK;
 969         counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel);
 970         ni_tio_write(counter, counter_dev->regs[gate2_reg], gate2_reg);
 971         return 0;
 972 }
 973
 974 int ni_tio_set_gate_src(struct ni_gpct *counter,
 975                         unsigned int gate, unsigned int src)
 976 {
 977         struct ni_gpct_device *counter_dev = counter->counter_dev;
 978         unsigned int cidx = counter->counter_index;
 979         unsigned int chan = CR_CHAN(src);
 980         unsigned int gate2_reg = NITIO_GATE2_REG(cidx);
 981         unsigned int mode = 0;
 982
 983         switch (gate) {
 984         case 0:
 985                 if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
 986                         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 987                                         GI_GATING_MODE_MASK,
 988                                         GI_GATING_DISABLED);
 989                         return 0;
 990                 }
 991                 if (src & CR_INVERT)
 992                         mode |= GI_GATE_POL_INVERT;
 993                 if (src & CR_EDGE)
 994                         mode |= GI_RISING_EDGE_GATING;
 995                 else
 996                         mode |= GI_LEVEL_GATING;
 997                 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 998                                 GI_GATE_POL_INVERT | GI_GATING_MODE_MASK,
 999                                 mode);
1000                 switch (counter_dev->variant) {
1001                 case ni_gpct_variant_e_series:
1002                 case ni_gpct_variant_m_series:
1003                 default:
1004                         return ni_m_set_gate(counter, src);
1005                 case ni_gpct_variant_660x:
1006                         return ni_660x_set_gate(counter, src);
1007                 }
1008                 break;
1009         case 1:
1010                 if (!ni_tio_has_gate2_registers(counter_dev))
1011                         return -EINVAL;
1012
1013                 if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
1014                         counter_dev->regs[gate2_reg] &= ~GI_GATE2_MODE;
1015                         ni_tio_write(counter, counter_dev->regs[gate2_reg],
1016                                      gate2_reg);
1017                         return 0;
1018                 }
1019                 if (src & CR_INVERT)
1020                         counter_dev->regs[gate2_reg] |= GI_GATE2_POL_INVERT;
1021                 else
1022                         counter_dev->regs[gate2_reg] &= ~GI_GATE2_POL_INVERT;
1023                 switch (counter_dev->variant) {
1024                 case ni_gpct_variant_m_series:
1025                         return ni_m_set_gate2(counter, src);
1026                 case ni_gpct_variant_660x:
1027                         return ni_660x_set_gate2(counter, src);
1028                 default:
1029                         return -EINVAL;
1030                 }
1031                 break;
1032         default:
1033                 return -EINVAL;
1034         }
1035         return 0;
1036 }
1037 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1038
1039 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned int index,
1040                                 unsigned int source)
1041 {
1042         struct ni_gpct_device *counter_dev = counter->counter_dev;
1043         unsigned int cidx = counter->counter_index;
1044         unsigned int abz_reg, shift, mask;
1045
1046         if (counter_dev->variant != ni_gpct_variant_m_series)
1047                 return -EINVAL;
1048
1049         abz_reg = NITIO_ABZ_REG(cidx);
1050         switch (index) {
1051         case NI_GPCT_SOURCE_ENCODER_A:
1052                 shift = 10;
1053                 break;
1054         case NI_GPCT_SOURCE_ENCODER_B:
1055                 shift = 5;
1056                 break;
1057         case NI_GPCT_SOURCE_ENCODER_Z:
1058                 shift = 0;
1059                 break;
1060         default:
1061                 return -EINVAL;
1062         }
1063         mask = 0x1f << shift;
1064         if (source > 0x1f)
1065                 source = 0x1f;  /* Disable gate */
1066
1067         counter_dev->regs[abz_reg] &= ~mask;
1068         counter_dev->regs[abz_reg] |= (source << shift) & mask;
1069         ni_tio_write(counter, counter_dev->regs[abz_reg], abz_reg);
1070         return 0;
1071 }
1072
1073 static int ni_660x_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1074 {
1075         unsigned int source;
1076         unsigned int i;
1077
1078         switch (gate) {
1079         case NI_660X_SRC_PIN_I_GATE_SEL:
1080                 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1081                 break;
1082         case NI_660X_GATE_PIN_I_GATE_SEL:
1083                 source = NI_GPCT_GATE_PIN_i_GATE_SELECT;
1084                 break;
1085         case NI_660X_NEXT_SRC_GATE_SEL:
1086                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1087                 break;
1088         case NI_660X_NEXT_OUT_GATE_SEL:
1089                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1090                 break;
1091         case NI_660X_LOGIC_LOW_GATE_SEL:
1092                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1093                 break;
1094         default:
1095                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1096                         if (gate == NI_660X_RTSI_GATE_SEL(i)) {
1097                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1098                                 break;
1099                         }
1100                 }
1101                 if (i <= NI_660X_MAX_RTSI_CHAN)
1102                         break;
1103                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
1104                         if (gate == NI_660X_PIN_GATE_SEL(i)) {
1105                                 source = NI_GPCT_GATE_PIN_GATE_SELECT(i);
1106                                 break;
1107                         }
1108                 }
1109                 if (i <= NI_660X_MAX_GATE_PIN)
1110                         break;
1111                 return -EINVAL;
1112         }
1113         *src = source;
1114         return 0;
1115 };
1116
1117 static int ni_m_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1118 {
1119         unsigned int source;
1120         unsigned int i;
1121
1122         switch (gate) {
1123         case NI_M_TIMESTAMP_MUX_GATE_SEL:
1124                 source = NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1125                 break;
1126         case NI_M_AI_START2_GATE_SEL:
1127                 source = NI_GPCT_AI_START2_GATE_SELECT;
1128                 break;
1129         case NI_M_PXI_STAR_TRIGGER_GATE_SEL:
1130                 source = NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1131                 break;
1132         case NI_M_NEXT_OUT_GATE_SEL:
1133                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1134                 break;
1135         case NI_M_AI_START1_GATE_SEL:
1136                 source = NI_GPCT_AI_START1_GATE_SELECT;
1137                 break;
1138         case NI_M_NEXT_SRC_GATE_SEL:
1139                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1140                 break;
1141         case NI_M_ANALOG_TRIG_OUT_GATE_SEL:
1142                 source = NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1143                 break;
1144         case NI_M_LOGIC_LOW_GATE_SEL:
1145                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1146                 break;
1147         default:
1148                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
1149                         if (gate == NI_M_RTSI_GATE_SEL(i)) {
1150                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1151                                 break;
1152                         }
1153                 }
1154                 if (i <= NI_M_MAX_RTSI_CHAN)
1155                         break;
1156                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
1157                         if (gate == NI_M_PFI_GATE_SEL(i)) {
1158                                 source = NI_GPCT_PFI_GATE_SELECT(i);
1159                                 break;
1160                         }
1161                 }
1162                 if (i <= NI_M_MAX_PFI_CHAN)
1163                         break;
1164                 return -EINVAL;
1165         }
1166         *src = source;
1167         return 0;
1168 };
1169
1170 static int ni_660x_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1171 {
1172         unsigned int source;
1173         unsigned int i;
1174
1175         switch (gate) {
1176         case NI_660X_SRC_PIN_I_GATE2_SEL:
1177                 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1178                 break;
1179         case NI_660X_UD_PIN_I_GATE2_SEL:
1180                 source = NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1181                 break;
1182         case NI_660X_NEXT_SRC_GATE2_SEL:
1183                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1184                 break;
1185         case NI_660X_NEXT_OUT_GATE2_SEL:
1186                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1187                 break;
1188         case NI_660X_SELECTED_GATE2_SEL:
1189                 source = NI_GPCT_SELECTED_GATE_GATE_SELECT;
1190                 break;
1191         case NI_660X_LOGIC_LOW_GATE2_SEL:
1192                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1193                 break;
1194         default:
1195                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1196                         if (gate == NI_660X_RTSI_GATE2_SEL(i)) {
1197                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1198                                 break;
1199                         }
1200                 }
1201                 if (i <= NI_660X_MAX_RTSI_CHAN)
1202                         break;
1203                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
1204                         if (gate == NI_660X_UD_PIN_GATE2_SEL(i)) {
1205                                 source = NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1206                                 break;
1207                         }
1208                 }
1209                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
1210                         break;
1211                 return -EINVAL;
1212         }
1213         *src = source;
1214         return 0;
1215 };
1216
1217 static int ni_m_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1218 {
1219         /*
1220          * FIXME: the second gate sources for the m series are undocumented,
1221          * so we just return the raw bits for now.
1222          */
1223         *src = gate;
1224         return 0;
1225 };
1226
1227 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned int gate_index,
1228                                unsigned int *gate_source)
1229 {
1230         struct ni_gpct_device *counter_dev = counter->counter_dev;
1231         unsigned int cidx = counter->counter_index;
1232         unsigned int mode;
1233         unsigned int reg;
1234         unsigned int gate;
1235         int ret;
1236
1237         mode = ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx));
1238         if (((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED) ||
1239             (gate_index == 1 &&
1240              !(counter_dev->regs[NITIO_GATE2_REG(cidx)] & GI_GATE2_MODE))) {
1241                 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1242                 return 0;
1243         }
1244
1245         switch (gate_index) {
1246         case 0:
1247                 reg = NITIO_INPUT_SEL_REG(cidx);
1248                 gate = GI_BITS_TO_GATE(ni_tio_get_soft_copy(counter, reg));
1249
1250                 switch (counter_dev->variant) {
1251                 case ni_gpct_variant_e_series:
1252                 case ni_gpct_variant_m_series:
1253                 default:
1254                         ret = ni_m_gate_to_generic_gate(gate, gate_source);
1255                         break;
1256                 case ni_gpct_variant_660x:
1257                         ret = ni_660x_gate_to_generic_gate(gate, gate_source);
1258                         break;
1259                 }
1260                 if (ret)
1261                         return ret;
1262                 if (mode & GI_GATE_POL_INVERT)
1263                         *gate_source |= CR_INVERT;
1264                 if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
1265                         *gate_source |= CR_EDGE;
1266                 break;
1267         case 1:
1268                 reg = NITIO_GATE2_REG(cidx);
1269                 gate = GI_BITS_TO_GATE2(counter_dev->regs[reg]);
1270
1271                 switch (counter_dev->variant) {
1272                 case ni_gpct_variant_e_series:
1273                 case ni_gpct_variant_m_series:
1274                 default:
1275                         ret = ni_m_gate2_to_generic_gate(gate, gate_source);
1276                         break;
1277                 case ni_gpct_variant_660x:
1278                         ret = ni_660x_gate2_to_generic_gate(gate, gate_source);
1279                         break;
1280                 }
1281                 if (ret)
1282                         return ret;
1283                 if (counter_dev->regs[reg] & GI_GATE2_POL_INVERT)
1284                         *gate_source |= CR_INVERT;
1285                 /* second gate can't have edge/level mode set independently */
1286                 if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
1287                         *gate_source |= CR_EDGE;
1288                 break;
1289         default:
1290                 return -EINVAL;
1291         }
1292         return 0;
1293 }
1294
1295 int ni_tio_insn_config(struct comedi_device *dev,
1296                        struct comedi_subdevice *s,
1297                        struct comedi_insn *insn,
1298                        unsigned int *data)
1299 {
1300         struct ni_gpct *counter = s->private;
1301         unsigned int cidx = counter->counter_index;
1302         unsigned int status;
1303         int ret = 0;
1304
1305         switch (data[0]) {
1306         case INSN_CONFIG_SET_COUNTER_MODE:
1307                 ret = ni_tio_set_counter_mode(counter, data[1]);
1308                 break;
1309         case INSN_CONFIG_ARM:
1310                 ret = ni_tio_arm(counter, true, data[1]);
1311                 break;
1312         case INSN_CONFIG_DISARM:
1313                 ret = ni_tio_arm(counter, false, 0);
1314                 break;
1315         case INSN_CONFIG_GET_COUNTER_STATUS:
1316                 data[1] = 0;
1317                 status = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1318                 if (status & GI_ARMED(cidx)) {
1319                         data[1] |= COMEDI_COUNTER_ARMED;
1320                         if (status & GI_COUNTING(cidx))
1321                                 data[1] |= COMEDI_COUNTER_COUNTING;
1322                 }
1323                 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
1324                 break;
1325         case INSN_CONFIG_SET_CLOCK_SRC:
1326                 ret = ni_tio_set_clock_src(counter, data[1], data[2]);
1327                 break;
1328         case INSN_CONFIG_GET_CLOCK_SRC:
1329                 ret = ni_tio_get_clock_src(counter, &data[1], &data[2]);
1330                 break;
1331         case INSN_CONFIG_SET_GATE_SRC:
1332                 ret = ni_tio_set_gate_src(counter, data[1], data[2]);
1333                 break;
1334         case INSN_CONFIG_GET_GATE_SRC:
1335                 ret = ni_tio_get_gate_src(counter, data[1], &data[2]);
1336                 break;
1337         case INSN_CONFIG_SET_OTHER_SRC:
1338                 ret = ni_tio_set_other_src(counter, data[1], data[2]);
1339                 break;
1340         case INSN_CONFIG_RESET:
1341                 ni_tio_reset_count_and_disarm(counter);
1342                 break;
1343         default:
1344                 return -EINVAL;
1345         }
1346         return ret ? ret : insn->n;
1347 }
1348 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1349
1350 static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev,
1351                                             struct comedi_subdevice *s)
1352 {
1353         struct ni_gpct *counter = s->private;
1354         unsigned int cidx = counter->counter_index;
1355         unsigned int val;
1356
1357         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
1358         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1359                         GI_SAVE_TRACE, GI_SAVE_TRACE);
1360
1361         /*
1362          * The count doesn't get latched until the next clock edge, so it is
1363          * possible the count may change (once) while we are reading. Since
1364          * the read of the SW_Save_Reg isn't atomic (apparently even when it's
1365          * a 32 bit register according to 660x docs), we need to read twice
1366          * and make sure the reading hasn't changed. If it has, a third read
1367          * will be correct since the count value will definitely have latched
1368          * by then.
1369          */
1370         val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1371         if (val != ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx)))
1372                 val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1373
1374         return val;
1375 }
1376
1377 int ni_tio_insn_read(struct comedi_device *dev,
1378                      struct comedi_subdevice *s,
1379                      struct comedi_insn *insn,
1380                      unsigned int *data)
1381 {
1382         struct ni_gpct *counter = s->private;
1383         struct ni_gpct_device *counter_dev = counter->counter_dev;
1384         unsigned int channel = CR_CHAN(insn->chanspec);
1385         unsigned int cidx = counter->counter_index;
1386         int i;
1387
1388         for (i = 0; i < insn->n; i++) {
1389                 switch (channel) {
1390                 case 0:
1391                         data[i] = ni_tio_read_sw_save_reg(dev, s);
1392                         break;
1393                 case 1:
1394                         data[i] = counter_dev->regs[NITIO_LOADA_REG(cidx)];
1395                         break;
1396                 case 2:
1397                         data[i] = counter_dev->regs[NITIO_LOADB_REG(cidx)];
1398                         break;
1399                 }
1400         }
1401         return insn->n;
1402 }
1403 EXPORT_SYMBOL_GPL(ni_tio_insn_read);
1404
1405 static unsigned int ni_tio_next_load_register(struct ni_gpct *counter)
1406 {
1407         unsigned int cidx = counter->counter_index;
1408         unsigned int bits = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1409
1410         return (bits & GI_NEXT_LOAD_SRC(cidx))
1411                         ? NITIO_LOADB_REG(cidx)
1412                         : NITIO_LOADA_REG(cidx);
1413 }
1414
1415 int ni_tio_insn_write(struct comedi_device *dev,
1416                       struct comedi_subdevice *s,
1417                       struct comedi_insn *insn,
1418                       unsigned int *data)
1419 {
1420         struct ni_gpct *counter = s->private;
1421         struct ni_gpct_device *counter_dev = counter->counter_dev;
1422         unsigned int channel = CR_CHAN(insn->chanspec);
1423         unsigned int cidx = counter->counter_index;
1424         unsigned int load_reg;
1425
1426         if (insn->n < 1)
1427                 return 0;
1428         switch (channel) {
1429         case 0:
1430                 /*
1431                  * Unsafe if counter is armed.
1432                  * Should probably check status and return -EBUSY if armed.
1433                  */
1434
1435                 /*
1436                  * Don't disturb load source select, just use whichever
1437                  * load register is already selected.
1438                  */
1439                 load_reg = ni_tio_next_load_register(counter);
1440                 ni_tio_write(counter, data[0], load_reg);
1441                 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
1442                                           0, 0, GI_LOAD);
1443                 /* restore load reg */
1444                 ni_tio_write(counter, counter_dev->regs[load_reg], load_reg);
1445                 break;
1446         case 1:
1447                 counter_dev->regs[NITIO_LOADA_REG(cidx)] = data[0];
1448                 ni_tio_write(counter, data[0], NITIO_LOADA_REG(cidx));
1449                 break;
1450         case 2:
1451                 counter_dev->regs[NITIO_LOADB_REG(cidx)] = data[0];
1452                 ni_tio_write(counter, data[0], NITIO_LOADB_REG(cidx));
1453                 break;
1454         default:
1455                 return -EINVAL;
1456         }
1457         return 0;
1458 }
1459 EXPORT_SYMBOL_GPL(ni_tio_insn_write);
1460
1461 void ni_tio_init_counter(struct ni_gpct *counter)
1462 {
1463         struct ni_gpct_device *counter_dev = counter->counter_dev;
1464         unsigned int cidx = counter->counter_index;
1465
1466         ni_tio_reset_count_and_disarm(counter);
1467
1468         /* initialize counter registers */
1469         counter_dev->regs[NITIO_AUTO_INC_REG(cidx)] = 0x0;
1470         ni_tio_write(counter, 0x0, NITIO_AUTO_INC_REG(cidx));
1471
1472         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1473                         ~0, GI_SYNC_GATE);
1474
1475         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0);
1476
1477         counter_dev->regs[NITIO_LOADA_REG(cidx)] = 0x0;
1478         ni_tio_write(counter, 0x0, NITIO_LOADA_REG(cidx));
1479
1480         counter_dev->regs[NITIO_LOADB_REG(cidx)] = 0x0;
1481         ni_tio_write(counter, 0x0, NITIO_LOADB_REG(cidx));
1482
1483         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0);
1484
1485         if (ni_tio_counting_mode_registers_present(counter_dev))
1486                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0);
1487
1488         if (ni_tio_has_gate2_registers(counter_dev)) {
1489                 counter_dev->regs[NITIO_GATE2_REG(cidx)] = 0x0;
1490                 ni_tio_write(counter, 0x0, NITIO_GATE2_REG(cidx));
1491         }
1492
1493         ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0);
1494
1495         ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0);
1496 }
1497 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
1498
1499 struct ni_gpct_device *
1500 ni_gpct_device_construct(struct comedi_device *dev,
1501                          void (*write)(struct ni_gpct *counter,
1502                                        unsigned int value,
1503                                        enum ni_gpct_register reg),
1504                          unsigned int (*read)(struct ni_gpct *counter,
1505                                               enum ni_gpct_register reg),
1506                          enum ni_gpct_variant variant,
1507                          unsigned int num_counters)
1508 {
1509         struct ni_gpct_device *counter_dev;
1510         struct ni_gpct *counter;
1511         unsigned int i;
1512
1513         if (num_counters == 0)
1514                 return NULL;
1515
1516         counter_dev = kzalloc(sizeof(*counter_dev), GFP_KERNEL);
1517         if (!counter_dev)
1518                 return NULL;
1519
1520         counter_dev->dev = dev;
1521         counter_dev->write = write;
1522         counter_dev->read = read;
1523         counter_dev->variant = variant;
1524
1525         spin_lock_init(&counter_dev->regs_lock);
1526
1527         counter_dev->counters = kcalloc(num_counters, sizeof(*counter),
1528                                         GFP_KERNEL);
1529         if (!counter_dev->counters) {
1530                 kfree(counter_dev);
1531                 return NULL;
1532         }
1533
1534         for (i = 0; i < num_counters; ++i) {
1535                 counter = &counter_dev->counters[i];
1536                 counter->counter_dev = counter_dev;
1537                 spin_lock_init(&counter->lock);
1538         }
1539         counter_dev->num_counters = num_counters;
1540
1541         return counter_dev;
1542 }
1543 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
1544
1545 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
1546 {
1547         if (!counter_dev)
1548                 return;
1549         kfree(counter_dev->counters);
1550         kfree(counter_dev);
1551 }
1552 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
1553
1554 static int __init ni_tio_init_module(void)
1555 {
1556         return 0;
1557 }
1558 module_init(ni_tio_init_module);
1559
1560 static void __exit ni_tio_cleanup_module(void)
1561 {
1562 }
1563 module_exit(ni_tio_cleanup_module);
1564
1565 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
1566 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
1567 MODULE_LICENSE("GPL");