2 * Command support for NI general purpose counters
4 * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
19 * Description: National Instruments general purpose counters command support
20 * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
21 * Herman.Bruyninckx@mech.kuleuven.ac.be,
22 * Wim.Meeussen@mech.kuleuven.ac.be,
23 * Klaas.Gadeyne@mech.kuleuven.ac.be,
24 * Frank Mori Hess <fmhess@users.sourceforge.net>
25 * Updated: Fri, 11 Apr 2008 12:32:35 +0100
28 * This module is not used directly by end-users. Rather, it
29 * is used by other drivers (for example ni_660x and ni_pcimio)
30 * to provide command support for NI's general purpose counters.
31 * It was originally split out of ni_tio.c to stop the 'ni_tio'
32 * module depending on the 'mite' module.
35 * DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
36 * DAQ 6601/6602 User Manual (NI 322137B-01)
37 * 340934b.pdf DAQ-STC reference manual
39 * TODO: Support use of both banks X and Y
42 #include <linux/module.h>
43 #include "ni_tio_internal.h"
46 static void ni_tio_configure_dma(struct ni_gpct *counter,
47 bool enable, bool read)
49 struct ni_gpct_device *counter_dev = counter->counter_dev;
50 unsigned int cidx = counter->counter_index;
54 mask = GI_READ_ACKS_IRQ | GI_WRITE_ACKS_IRQ;
59 bits |= GI_READ_ACKS_IRQ;
61 bits |= GI_WRITE_ACKS_IRQ;
63 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), mask, bits);
65 switch (counter_dev->variant) {
66 case ni_gpct_variant_e_series:
68 case ni_gpct_variant_m_series:
69 case ni_gpct_variant_660x:
70 mask = GI_DMA_ENABLE | GI_DMA_INT_ENA | GI_DMA_WRITE;
74 bits |= GI_DMA_ENABLE | GI_DMA_INT_ENA;
77 ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), mask, bits);
82 static int ni_tio_input_inttrig(struct comedi_device *dev,
83 struct comedi_subdevice *s,
84 unsigned int trig_num)
86 struct ni_gpct *counter = s->private;
87 struct comedi_cmd *cmd = &s->async->cmd;
91 if (trig_num != cmd->start_arg)
94 spin_lock_irqsave(&counter->lock, flags);
95 if (counter->mite_chan)
96 mite_dma_arm(counter->mite_chan);
99 spin_unlock_irqrestore(&counter->lock, flags);
102 ret = ni_tio_arm(counter, true, NI_GPCT_ARM_IMMEDIATE);
103 s->async->inttrig = NULL;
108 static int ni_tio_input_cmd(struct comedi_subdevice *s)
110 struct ni_gpct *counter = s->private;
111 struct ni_gpct_device *counter_dev = counter->counter_dev;
112 unsigned int cidx = counter->counter_index;
113 struct comedi_async *async = s->async;
114 struct comedi_cmd *cmd = &async->cmd;
117 /* write alloc the entire buffer */
118 comedi_buf_write_alloc(s, async->prealloc_bufsz);
119 counter->mite_chan->dir = COMEDI_INPUT;
120 switch (counter_dev->variant) {
121 case ni_gpct_variant_m_series:
122 case ni_gpct_variant_660x:
123 mite_prep_dma(counter->mite_chan, 32, 32);
125 case ni_gpct_variant_e_series:
126 mite_prep_dma(counter->mite_chan, 16, 32);
129 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
130 ni_tio_configure_dma(counter, true, true);
132 if (cmd->start_src == TRIG_INT) {
133 async->inttrig = &ni_tio_input_inttrig;
134 } else { /* TRIG_NOW || TRIG_EXT || TRIG_OTHER */
135 async->inttrig = NULL;
136 mite_dma_arm(counter->mite_chan);
138 if (cmd->start_src == TRIG_NOW)
139 ret = ni_tio_arm(counter, true, NI_GPCT_ARM_IMMEDIATE);
140 else if (cmd->start_src == TRIG_EXT)
141 ret = ni_tio_arm(counter, true, cmd->start_arg);
146 static int ni_tio_output_cmd(struct comedi_subdevice *s)
148 struct ni_gpct *counter = s->private;
150 dev_err(counter->counter_dev->dev->class_dev,
151 "output commands not yet implemented.\n");
155 static int ni_tio_cmd_setup(struct comedi_subdevice *s)
157 struct comedi_cmd *cmd = &s->async->cmd;
158 struct ni_gpct *counter = s->private;
159 unsigned int cidx = counter->counter_index;
160 int set_gate_source = 0;
161 unsigned int gate_source;
164 if (cmd->scan_begin_src == TRIG_EXT) {
166 gate_source = cmd->scan_begin_arg;
167 } else if (cmd->convert_src == TRIG_EXT) {
169 gate_source = cmd->convert_arg;
172 retval = ni_tio_set_gate_src(counter, 0, gate_source);
173 if (cmd->flags & CMDF_WAKE_EOS) {
174 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
175 GI_GATE_INTERRUPT_ENABLE(cidx),
176 GI_GATE_INTERRUPT_ENABLE(cidx));
181 int ni_tio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
183 struct ni_gpct *counter = s->private;
184 struct comedi_async *async = s->async;
185 struct comedi_cmd *cmd = &async->cmd;
189 spin_lock_irqsave(&counter->lock, flags);
190 if (!counter->mite_chan) {
191 dev_err(counter->counter_dev->dev->class_dev,
192 "commands only supported with DMA. ");
193 dev_err(counter->counter_dev->dev->class_dev,
194 "Interrupt-driven commands not yet implemented.\n");
197 retval = ni_tio_cmd_setup(s);
199 if (cmd->flags & CMDF_WRITE)
200 retval = ni_tio_output_cmd(s);
202 retval = ni_tio_input_cmd(s);
205 spin_unlock_irqrestore(&counter->lock, flags);
208 EXPORT_SYMBOL_GPL(ni_tio_cmd);
210 int ni_tio_cmdtest(struct comedi_device *dev,
211 struct comedi_subdevice *s,
212 struct comedi_cmd *cmd)
214 struct ni_gpct *counter = s->private;
216 unsigned int sources;
218 /* Step 1 : check if triggers are trivially valid */
220 sources = TRIG_NOW | TRIG_INT | TRIG_OTHER;
221 if (ni_tio_counting_mode_registers_present(counter->counter_dev))
223 err |= comedi_check_trigger_src(&cmd->start_src, sources);
225 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
226 TRIG_FOLLOW | TRIG_EXT | TRIG_OTHER);
227 err |= comedi_check_trigger_src(&cmd->convert_src,
228 TRIG_NOW | TRIG_EXT | TRIG_OTHER);
229 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
230 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
235 /* Step 2a : make sure trigger sources are unique */
237 err |= comedi_check_trigger_is_unique(cmd->start_src);
238 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
239 err |= comedi_check_trigger_is_unique(cmd->convert_src);
241 /* Step 2b : and mutually compatible */
243 if (cmd->convert_src != TRIG_NOW && cmd->scan_begin_src != TRIG_FOLLOW)
249 /* Step 3: check if arguments are trivially valid */
251 switch (cmd->start_src) {
255 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
258 /* start_arg is the start_trigger passed to ni_tio_arm() */
262 if (cmd->scan_begin_src != TRIG_EXT)
263 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
265 if (cmd->convert_src != TRIG_EXT)
266 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
268 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
270 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
275 /* Step 4: fix up any arguments */
277 /* Step 5: check channel list if it exists */
281 EXPORT_SYMBOL_GPL(ni_tio_cmdtest);
283 int ni_tio_cancel(struct ni_gpct *counter)
285 unsigned int cidx = counter->counter_index;
288 ni_tio_arm(counter, false, 0);
289 spin_lock_irqsave(&counter->lock, flags);
290 if (counter->mite_chan)
291 mite_dma_disarm(counter->mite_chan);
292 spin_unlock_irqrestore(&counter->lock, flags);
293 ni_tio_configure_dma(counter, false, false);
295 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
296 GI_GATE_INTERRUPT_ENABLE(cidx), 0x0);
299 EXPORT_SYMBOL_GPL(ni_tio_cancel);
301 static int should_ack_gate(struct ni_gpct *counter)
306 switch (counter->counter_dev->variant) {
307 case ni_gpct_variant_m_series:
308 case ni_gpct_variant_660x:
310 * not sure if 660x really supports gate interrupts
311 * (the bits are not listed in register-level manual)
314 case ni_gpct_variant_e_series:
316 * During buffered input counter operation for e-series,
317 * the gate interrupt is acked automatically by the dma
318 * controller, due to the Gi_Read/Write_Acknowledges_IRQ
319 * bits in the input select register.
321 spin_lock_irqsave(&counter->lock, flags);
323 if (!counter->mite_chan ||
324 counter->mite_chan->dir != COMEDI_INPUT ||
325 (mite_done(counter->mite_chan))) {
329 spin_unlock_irqrestore(&counter->lock, flags);
335 static void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter,
338 int *perm_stale_data)
340 unsigned int cidx = counter->counter_index;
341 const unsigned short gxx_status = ni_tio_read(counter,
342 NITIO_SHARED_STATUS_REG(cidx));
343 const unsigned short gi_status = ni_tio_read(counter,
344 NITIO_STATUS_REG(cidx));
345 unsigned int ack = 0;
352 *perm_stale_data = 0;
354 if (gxx_status & GI_GATE_ERROR(cidx)) {
355 ack |= GI_GATE_ERROR_CONFIRM(cidx);
358 * 660x don't support automatic acknowledgment
359 * of gate interrupt via dma read/write
360 * and report bogus gate errors
362 if (counter->counter_dev->variant !=
363 ni_gpct_variant_660x)
367 if (gxx_status & GI_TC_ERROR(cidx)) {
368 ack |= GI_TC_ERROR_CONFIRM(cidx);
372 if (gi_status & GI_TC)
373 ack |= GI_TC_INTERRUPT_ACK;
374 if (gi_status & GI_GATE_INTERRUPT) {
375 if (should_ack_gate(counter))
376 ack |= GI_GATE_INTERRUPT_ACK;
379 ni_tio_write(counter, ack, NITIO_INT_ACK_REG(cidx));
380 if (ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)) &
381 GI_LOADING_ON_GATE) {
382 if (ni_tio_read(counter, NITIO_STATUS2_REG(cidx)) &
383 GI_PERMANENT_STALE(cidx)) {
384 dev_info(counter->counter_dev->dev->class_dev,
385 "%s: Gi_Permanent_Stale_Data detected.\n",
388 *perm_stale_data = 1;
393 void ni_tio_acknowledge(struct ni_gpct *counter)
395 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL);
397 EXPORT_SYMBOL_GPL(ni_tio_acknowledge);
399 void ni_tio_handle_interrupt(struct ni_gpct *counter,
400 struct comedi_subdevice *s)
402 unsigned int cidx = counter->counter_index;
408 ni_tio_acknowledge_and_confirm(counter, &gate_error, &tc_error,
411 dev_notice(counter->counter_dev->dev->class_dev,
412 "%s: Gi_Gate_Error detected.\n", __func__);
413 s->async->events |= COMEDI_CB_OVERFLOW;
416 s->async->events |= COMEDI_CB_ERROR;
417 switch (counter->counter_dev->variant) {
418 case ni_gpct_variant_m_series:
419 case ni_gpct_variant_660x:
420 if (ni_tio_read(counter, NITIO_DMA_STATUS_REG(cidx)) &
422 dev_notice(counter->counter_dev->dev->class_dev,
423 "%s: Gi_DRQ_Error detected.\n", __func__);
424 s->async->events |= COMEDI_CB_OVERFLOW;
427 case ni_gpct_variant_e_series:
430 spin_lock_irqsave(&counter->lock, flags);
431 if (counter->mite_chan)
432 mite_ack_linkc(counter->mite_chan, s, true);
433 spin_unlock_irqrestore(&counter->lock, flags);
435 EXPORT_SYMBOL_GPL(ni_tio_handle_interrupt);
437 void ni_tio_set_mite_channel(struct ni_gpct *counter,
438 struct mite_channel *mite_chan)
442 spin_lock_irqsave(&counter->lock, flags);
443 counter->mite_chan = mite_chan;
444 spin_unlock_irqrestore(&counter->lock, flags);
446 EXPORT_SYMBOL_GPL(ni_tio_set_mite_channel);
448 static int __init ni_tiocmd_init_module(void)
452 module_init(ni_tiocmd_init_module);
454 static void __exit ni_tiocmd_cleanup_module(void)
457 module_exit(ni_tiocmd_cleanup_module);
459 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
460 MODULE_DESCRIPTION("Comedi command support for NI general-purpose counters");
461 MODULE_LICENSE("GPL");