2 * AD7152 capacitive sensor driver supporting AD7152/3
4 * Copyright 2010-2011a Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/delay.h>
18 #include <linux/iio/iio.h>
19 #include <linux/iio/sysfs.h>
22 * TODO: Check compliance of calibbias with abi (units)
25 * AD7152 registers definition
28 #define AD7152_REG_STATUS 0
29 #define AD7152_REG_CH1_DATA_HIGH 1
30 #define AD7152_REG_CH2_DATA_HIGH 3
31 #define AD7152_REG_CH1_OFFS_HIGH 5
32 #define AD7152_REG_CH2_OFFS_HIGH 7
33 #define AD7152_REG_CH1_GAIN_HIGH 9
34 #define AD7152_REG_CH1_SETUP 11
35 #define AD7152_REG_CH2_GAIN_HIGH 12
36 #define AD7152_REG_CH2_SETUP 14
37 #define AD7152_REG_CFG 15
38 #define AD7152_REG_RESEVERD 16
39 #define AD7152_REG_CAPDAC_POS 17
40 #define AD7152_REG_CAPDAC_NEG 18
41 #define AD7152_REG_CFG2 26
43 /* Status Register Bit Designations (AD7152_REG_STATUS) */
44 #define AD7152_STATUS_RDY1 BIT(0)
45 #define AD7152_STATUS_RDY2 BIT(1)
46 #define AD7152_STATUS_C1C2 BIT(2)
47 #define AD7152_STATUS_PWDN BIT(7)
49 /* Setup Register Bit Designations (AD7152_REG_CHx_SETUP) */
50 #define AD7152_SETUP_CAPDIFF BIT(5)
51 #define AD7152_SETUP_RANGE_2pF (0 << 6)
52 #define AD7152_SETUP_RANGE_0_5pF (1 << 6)
53 #define AD7152_SETUP_RANGE_1pF (2 << 6)
54 #define AD7152_SETUP_RANGE_4pF (3 << 6)
55 #define AD7152_SETUP_RANGE(x) ((x) << 6)
57 /* Config Register Bit Designations (AD7152_REG_CFG) */
58 #define AD7152_CONF_CH2EN BIT(3)
59 #define AD7152_CONF_CH1EN BIT(4)
60 #define AD7152_CONF_MODE_IDLE (0 << 0)
61 #define AD7152_CONF_MODE_CONT_CONV (1 << 0)
62 #define AD7152_CONF_MODE_SINGLE_CONV (2 << 0)
63 #define AD7152_CONF_MODE_OFFS_CAL (5 << 0)
64 #define AD7152_CONF_MODE_GAIN_CAL (6 << 0)
66 /* Capdac Register Bit Designations (AD7152_REG_CAPDAC_XXX) */
67 #define AD7152_CAPDAC_DACEN BIT(7)
68 #define AD7152_CAPDAC_DACP(x) ((x) & 0x1F)
70 /* CFG2 Register Bit Designations (AD7152_REG_CFG2) */
71 #define AD7152_CFG2_OSR(x) (((x) & 0x3) << 4)
81 * struct ad7152_chip_info - chip specific information
84 struct ad7152_chip_info {
85 struct i2c_client *client;
87 * Capacitive channel digital filter setup;
88 * conversion time/update rate setup per channel
92 struct mutex state_lock; /* protect hardware state */
95 static inline ssize_t ad7152_start_calib(struct device *dev,
96 struct device_attribute *attr,
101 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
102 struct ad7152_chip_info *chip = iio_priv(indio_dev);
103 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
105 int ret, timeout = 10;
107 ret = strtobool(buf, &doit);
114 if (this_attr->address == 0)
115 regval |= AD7152_CONF_CH1EN;
117 regval |= AD7152_CONF_CH2EN;
119 mutex_lock(&chip->state_lock);
120 ret = i2c_smbus_write_byte_data(chip->client, AD7152_REG_CFG, regval);
126 ret = i2c_smbus_read_byte_data(chip->client, AD7152_REG_CFG);
130 } while ((ret == regval) && timeout--);
132 mutex_unlock(&chip->state_lock);
136 mutex_unlock(&chip->state_lock);
140 static ssize_t ad7152_start_offset_calib(struct device *dev,
141 struct device_attribute *attr,
145 return ad7152_start_calib(dev, attr, buf, len,
146 AD7152_CONF_MODE_OFFS_CAL);
149 static ssize_t ad7152_start_gain_calib(struct device *dev,
150 struct device_attribute *attr,
154 return ad7152_start_calib(dev, attr, buf, len,
155 AD7152_CONF_MODE_GAIN_CAL);
158 static IIO_DEVICE_ATTR(in_capacitance0_calibbias_calibration,
159 0200, NULL, ad7152_start_offset_calib, 0);
160 static IIO_DEVICE_ATTR(in_capacitance1_calibbias_calibration,
161 0200, NULL, ad7152_start_offset_calib, 1);
162 static IIO_DEVICE_ATTR(in_capacitance0_calibscale_calibration,
163 0200, NULL, ad7152_start_gain_calib, 0);
164 static IIO_DEVICE_ATTR(in_capacitance1_calibscale_calibration,
165 0200, NULL, ad7152_start_gain_calib, 1);
167 /* Values are Update Rate (Hz), Conversion Time (ms) + 1*/
168 static const unsigned char ad7152_filter_rate_table[][2] = {
169 {200, 5 + 1}, {50, 20 + 1}, {20, 50 + 1}, {17, 60 + 1},
172 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("200 50 20 17");
174 static IIO_CONST_ATTR(in_capacitance_scale_available,
175 "0.000061050 0.000030525 0.000015263 0.000007631");
177 static struct attribute *ad7152_attributes[] = {
178 &iio_dev_attr_in_capacitance0_calibbias_calibration.dev_attr.attr,
179 &iio_dev_attr_in_capacitance1_calibbias_calibration.dev_attr.attr,
180 &iio_dev_attr_in_capacitance0_calibscale_calibration.dev_attr.attr,
181 &iio_dev_attr_in_capacitance1_calibscale_calibration.dev_attr.attr,
182 &iio_const_attr_in_capacitance_scale_available.dev_attr.attr,
183 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
187 static const struct attribute_group ad7152_attribute_group = {
188 .attrs = ad7152_attributes,
191 static const u8 ad7152_addresses[][4] = {
192 { AD7152_REG_CH1_DATA_HIGH, AD7152_REG_CH1_OFFS_HIGH,
193 AD7152_REG_CH1_GAIN_HIGH, AD7152_REG_CH1_SETUP },
194 { AD7152_REG_CH2_DATA_HIGH, AD7152_REG_CH2_OFFS_HIGH,
195 AD7152_REG_CH2_GAIN_HIGH, AD7152_REG_CH2_SETUP },
198 /* Values are nano relative to pf base. */
199 static const int ad7152_scale_table[] = {
200 30525, 7631, 15263, 61050
204 * read_raw handler for IIO_CHAN_INFO_SAMP_FREQ
208 static int ad7152_read_raw_samp_freq(struct device *dev, int *val)
210 struct ad7152_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
212 *val = ad7152_filter_rate_table[chip->filter_rate_setup][0];
218 * write_raw handler for IIO_CHAN_INFO_SAMP_FREQ
222 static int ad7152_write_raw_samp_freq(struct device *dev, int val)
224 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
225 struct ad7152_chip_info *chip = iio_priv(indio_dev);
228 for (i = 0; i < ARRAY_SIZE(ad7152_filter_rate_table); i++)
229 if (val >= ad7152_filter_rate_table[i][0])
232 if (i >= ARRAY_SIZE(ad7152_filter_rate_table))
233 i = ARRAY_SIZE(ad7152_filter_rate_table) - 1;
235 ret = i2c_smbus_write_byte_data(chip->client,
236 AD7152_REG_CFG2, AD7152_CFG2_OSR(i));
240 chip->filter_rate_setup = i;
245 static int ad7152_write_raw(struct iio_dev *indio_dev,
246 struct iio_chan_spec const *chan,
251 struct ad7152_chip_info *chip = iio_priv(indio_dev);
254 mutex_lock(&chip->state_lock);
257 case IIO_CHAN_INFO_CALIBSCALE:
263 val = (val2 * 1024) / 15625;
265 ret = i2c_smbus_write_word_data(chip->client,
266 ad7152_addresses[chan->channel][AD7152_GAIN],
274 case IIO_CHAN_INFO_CALIBBIAS:
275 if ((val < 0) | (val > 0xFFFF)) {
279 ret = i2c_smbus_write_word_data(chip->client,
280 ad7152_addresses[chan->channel][AD7152_OFFS],
287 case IIO_CHAN_INFO_SCALE:
292 for (i = 0; i < ARRAY_SIZE(ad7152_scale_table); i++)
293 if (val2 == ad7152_scale_table[i])
296 chip->setup[chan->channel] &= ~AD7152_SETUP_RANGE_4pF;
297 chip->setup[chan->channel] |= AD7152_SETUP_RANGE(i);
299 ret = i2c_smbus_write_byte_data(chip->client,
300 ad7152_addresses[chan->channel][AD7152_SETUP],
301 chip->setup[chan->channel]);
307 case IIO_CHAN_INFO_SAMP_FREQ:
312 ret = ad7152_write_raw_samp_freq(&indio_dev->dev, val);
323 mutex_unlock(&chip->state_lock);
327 static int ad7152_read_raw(struct iio_dev *indio_dev,
328 struct iio_chan_spec const *chan,
332 struct ad7152_chip_info *chip = iio_priv(indio_dev);
336 mutex_lock(&chip->state_lock);
339 case IIO_CHAN_INFO_RAW:
340 /* First set whether in differential mode */
342 regval = chip->setup[chan->channel];
344 if (chan->differential)
345 chip->setup[chan->channel] |= AD7152_SETUP_CAPDIFF;
347 chip->setup[chan->channel] &= ~AD7152_SETUP_CAPDIFF;
349 if (regval != chip->setup[chan->channel]) {
350 ret = i2c_smbus_write_byte_data(chip->client,
351 ad7152_addresses[chan->channel][AD7152_SETUP],
352 chip->setup[chan->channel]);
356 /* Make sure the channel is enabled */
357 if (chan->channel == 0)
358 regval = AD7152_CONF_CH1EN;
360 regval = AD7152_CONF_CH2EN;
362 /* Trigger a single read */
363 regval |= AD7152_CONF_MODE_SINGLE_CONV;
364 ret = i2c_smbus_write_byte_data(chip->client, AD7152_REG_CFG,
369 msleep(ad7152_filter_rate_table[chip->filter_rate_setup][1]);
370 /* Now read the actual register */
371 ret = i2c_smbus_read_word_data(chip->client,
372 ad7152_addresses[chan->channel][AD7152_DATA]);
377 if (chan->differential)
382 case IIO_CHAN_INFO_CALIBSCALE:
384 ret = i2c_smbus_read_word_data(chip->client,
385 ad7152_addresses[chan->channel][AD7152_GAIN]);
388 /* 1 + gain_val / 2^16 */
390 *val2 = (15625 * swab16(ret)) / 1024;
392 ret = IIO_VAL_INT_PLUS_MICRO;
394 case IIO_CHAN_INFO_CALIBBIAS:
395 ret = i2c_smbus_read_word_data(chip->client,
396 ad7152_addresses[chan->channel][AD7152_OFFS]);
403 case IIO_CHAN_INFO_SCALE:
404 ret = i2c_smbus_read_byte_data(chip->client,
405 ad7152_addresses[chan->channel][AD7152_SETUP]);
409 *val2 = ad7152_scale_table[ret >> 6];
411 ret = IIO_VAL_INT_PLUS_NANO;
413 case IIO_CHAN_INFO_SAMP_FREQ:
414 ret = ad7152_read_raw_samp_freq(&indio_dev->dev, val);
424 mutex_unlock(&chip->state_lock);
428 static int ad7152_write_raw_get_fmt(struct iio_dev *indio_dev,
429 struct iio_chan_spec const *chan,
433 case IIO_CHAN_INFO_SCALE:
434 return IIO_VAL_INT_PLUS_NANO;
436 return IIO_VAL_INT_PLUS_MICRO;
440 static const struct iio_info ad7152_info = {
441 .attrs = &ad7152_attribute_group,
442 .read_raw = ad7152_read_raw,
443 .write_raw = ad7152_write_raw,
444 .write_raw_get_fmt = ad7152_write_raw_get_fmt,
447 static const struct iio_chan_spec ad7152_channels[] = {
449 .type = IIO_CAPACITANCE,
452 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
453 BIT(IIO_CHAN_INFO_CALIBSCALE) |
454 BIT(IIO_CHAN_INFO_CALIBBIAS) |
455 BIT(IIO_CHAN_INFO_SCALE),
456 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
458 .type = IIO_CAPACITANCE,
463 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
464 BIT(IIO_CHAN_INFO_CALIBSCALE) |
465 BIT(IIO_CHAN_INFO_CALIBBIAS) |
466 BIT(IIO_CHAN_INFO_SCALE),
467 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
469 .type = IIO_CAPACITANCE,
472 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
473 BIT(IIO_CHAN_INFO_CALIBSCALE) |
474 BIT(IIO_CHAN_INFO_CALIBBIAS) |
475 BIT(IIO_CHAN_INFO_SCALE),
476 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
478 .type = IIO_CAPACITANCE,
483 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
484 BIT(IIO_CHAN_INFO_CALIBSCALE) |
485 BIT(IIO_CHAN_INFO_CALIBBIAS) |
486 BIT(IIO_CHAN_INFO_SCALE),
487 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
492 * device probe and remove
495 static int ad7152_probe(struct i2c_client *client,
496 const struct i2c_device_id *id)
499 struct ad7152_chip_info *chip;
500 struct iio_dev *indio_dev;
502 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
505 chip = iio_priv(indio_dev);
506 /* this is only used for device removal purposes */
507 i2c_set_clientdata(client, indio_dev);
509 chip->client = client;
510 mutex_init(&chip->state_lock);
512 /* Establish that the iio_dev is a child of the i2c device */
513 indio_dev->name = id->name;
514 indio_dev->dev.parent = &client->dev;
515 indio_dev->info = &ad7152_info;
516 indio_dev->channels = ad7152_channels;
517 if (id->driver_data == 0)
518 indio_dev->num_channels = ARRAY_SIZE(ad7152_channels);
520 indio_dev->num_channels = 2;
521 indio_dev->num_channels = ARRAY_SIZE(ad7152_channels);
522 indio_dev->modes = INDIO_DIRECT_MODE;
524 ret = devm_iio_device_register(indio_dev->dev.parent, indio_dev);
528 dev_err(&client->dev, "%s capacitive sensor registered\n", id->name);
533 static const struct i2c_device_id ad7152_id[] = {
539 MODULE_DEVICE_TABLE(i2c, ad7152_id);
541 static struct i2c_driver ad7152_driver = {
543 .name = KBUILD_MODNAME,
545 .probe = ad7152_probe,
546 .id_table = ad7152_id,
548 module_i2c_driver(ad7152_driver);
550 MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
551 MODULE_DESCRIPTION("Analog Devices AD7152/3 capacitive sensor driver");
552 MODULE_LICENSE("GPL v2");