drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_device_local.h

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2010-2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef __GP_DEVICE_LOCAL_H_INCLUDED__
  16 #define __GP_DEVICE_LOCAL_H_INCLUDED__
  17
  18 #include "gp_device_global.h"
  19
  20 /* @ GP_REGS_BASE -> GP_DEVICE_BASE */
  21 #define _REG_GP_SDRAM_WAKEUP_ADDR                                       0x00
  22 #define _REG_GP_IDLE_ADDR                                                       0x04
  23 /* #define _REG_GP_IRQ_REQ0_ADDR                                        0x08 */
  24 /* #define _REG_GP_IRQ_REQ1_ADDR                                        0x0C */
  25 #define _REG_GP_SP_STREAM_STAT_ADDR                                     0x10
  26 #define _REG_GP_SP_STREAM_STAT_B_ADDR                           0x14
  27 #define _REG_GP_ISP_STREAM_STAT_ADDR                            0x18
  28 #define _REG_GP_MOD_STREAM_STAT_ADDR                            0x1C
  29 #define _REG_GP_SP_STREAM_STAT_IRQ_COND_ADDR            0x20
  30 #define _REG_GP_SP_STREAM_STAT_B_IRQ_COND_ADDR          0x24
  31 #define _REG_GP_ISP_STREAM_STAT_IRQ_COND_ADDR           0x28
  32 #define _REG_GP_MOD_STREAM_STAT_IRQ_COND_ADDR           0x2C
  33 #define _REG_GP_SP_STREAM_STAT_IRQ_ENABLE_ADDR          0x30
  34 #define _REG_GP_SP_STREAM_STAT_B_IRQ_ENABLE_ADDR        0x34
  35 #define _REG_GP_ISP_STREAM_STAT_IRQ_ENABLE_ADDR         0x38
  36 #define _REG_GP_MOD_STREAM_STAT_IRQ_ENABLE_ADDR         0x3C
  37 /*
  38 #define _REG_GP_SWITCH_IF_ADDR                                          0x40
  39 #define _REG_GP_SWITCH_GDC1_ADDR                                        0x44
  40 #define _REG_GP_SWITCH_GDC2_ADDR                                        0x48
  41 */
  42 #define _REG_GP_SLV_REG_RST_ADDR                                        0x50
  43 #define _REG_GP_SWITCH_ISYS2401_ADDR                            0x54
  44
  45 /* @ INPUT_FORMATTER_BASE -> GP_DEVICE_BASE */
  46 /*
  47 #define _REG_GP_IFMT_input_switch_lut_reg0                      0x00030800
  48 #define _REG_GP_IFMT_input_switch_lut_reg1                      0x00030804
  49 #define _REG_GP_IFMT_input_switch_lut_reg2                      0x00030808
  50 #define _REG_GP_IFMT_input_switch_lut_reg3                      0x0003080C
  51 #define _REG_GP_IFMT_input_switch_lut_reg4                      0x00030810
  52 #define _REG_GP_IFMT_input_switch_lut_reg5                      0x00030814
  53 #define _REG_GP_IFMT_input_switch_lut_reg6                      0x00030818
  54 #define _REG_GP_IFMT_input_switch_lut_reg7                      0x0003081C
  55 #define _REG_GP_IFMT_input_switch_fsync_lut                     0x00030820
  56 #define _REG_GP_IFMT_srst                                                       0x00030824
  57 #define _REG_GP_IFMT_slv_reg_srst                                       0x00030828
  58 #define _REG_GP_IFMT_input_switch_ch_id_fmt_type        0x0003082C
  59 */
  60 /* @ GP_DEVICE_BASE */
  61 /*
  62 #define _REG_GP_SYNCGEN_ENABLE_ADDR                                     0x00090000
  63 #define _REG_GP_SYNCGEN_FREE_RUNNING_ADDR                       0x00090004
  64 #define _REG_GP_SYNCGEN_PAUSE_ADDR                                      0x00090008
  65 #define _REG_GP_NR_FRAMES_ADDR                                          0x0009000C
  66 #define _REG_GP_SYNGEN_NR_PIX_ADDR                                      0x00090010
  67 #define _REG_GP_SYNGEN_NR_LINES_ADDR                            0x00090014
  68 #define _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR                       0x00090018
  69 #define _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR                       0x0009001C
  70 #define _REG_GP_ISEL_SOF_ADDR                                           0x00090020
  71 #define _REG_GP_ISEL_EOF_ADDR                                           0x00090024
  72 #define _REG_GP_ISEL_SOL_ADDR                                           0x00090028
  73 #define _REG_GP_ISEL_EOL_ADDR                                           0x0009002C
  74 #define _REG_GP_ISEL_LFSR_ENABLE_ADDR                           0x00090030
  75 #define _REG_GP_ISEL_LFSR_ENABLE_B_ADDR                         0x00090034
  76 #define _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR                      0x00090038
  77 #define _REG_GP_ISEL_TPG_ENABLE_ADDR                            0x0009003C
  78 #define _REG_GP_ISEL_TPG_ENABLE_B_ADDR                          0x00090040
  79 #define _REG_GP_ISEL_HOR_CNT_MASK_ADDR                          0x00090044
  80 #define _REG_GP_ISEL_VER_CNT_MASK_ADDR                          0x00090048
  81 #define _REG_GP_ISEL_XY_CNT_MASK_ADDR                           0x0009004C
  82 #define _REG_GP_ISEL_HOR_CNT_DELTA_ADDR                         0x00090050
  83 #define _REG_GP_ISEL_VER_CNT_DELTA_ADDR                         0x00090054
  84 #define _REG_GP_ISEL_TPG_MODE_ADDR                                      0x00090058
  85 #define _REG_GP_ISEL_TPG_RED1_ADDR                                      0x0009005C
  86 #define _REG_GP_ISEL_TPG_GREEN1_ADDR                            0x00090060
  87 #define _REG_GP_ISEL_TPG_BLUE1_ADDR                                     0x00090064
  88 #define _REG_GP_ISEL_TPG_RED2_ADDR                                      0x00090068
  89 #define _REG_GP_ISEL_TPG_GREEN2_ADDR                            0x0009006C
  90 #define _REG_GP_ISEL_TPG_BLUE2_ADDR                                     0x00090070
  91 #define _REG_GP_ISEL_CH_ID_ADDR                                         0x00090074
  92 #define _REG_GP_ISEL_FMT_TYPE_ADDR                                      0x00090078
  93 #define _REG_GP_ISEL_DATA_SEL_ADDR                                      0x0009007C
  94 #define _REG_GP_ISEL_SBAND_SEL_ADDR                                     0x00090080
  95 #define _REG_GP_ISEL_SYNC_SEL_ADDR                                      0x00090084
  96 #define _REG_GP_SYNCGEN_HOR_CNT_ADDR                            0x00090088
  97 #define _REG_GP_SYNCGEN_VER_CNT_ADDR                            0x0009008C
  98 #define _REG_GP_SYNCGEN_FRAME_CNT_ADDR                          0x00090090
  99 #define _REG_GP_SOFT_RESET_ADDR                                         0x00090094
 100 */
 101
 102 struct gp_device_state_s {
 103         int syncgen_enable;
 104         int syncgen_free_running;
 105         int syncgen_pause;
 106         int nr_frames;
 107         int syngen_nr_pix;
 108         int syngen_nr_lines;
 109         int syngen_hblank_cycles;
 110         int syngen_vblank_cycles;
 111         int isel_sof;
 112         int isel_eof;
 113         int isel_sol;
 114         int isel_eol;
 115         int isel_lfsr_enable;
 116         int isel_lfsr_enable_b;
 117         int isel_lfsr_reset_value;
 118         int isel_tpg_enable;
 119         int isel_tpg_enable_b;
 120         int isel_hor_cnt_mask;
 121         int isel_ver_cnt_mask;
 122         int isel_xy_cnt_mask;
 123         int isel_hor_cnt_delta;
 124         int isel_ver_cnt_delta;
 125         int isel_tpg_mode;
 126         int isel_tpg_red1;
 127         int isel_tpg_green1;
 128         int isel_tpg_blue1;
 129         int isel_tpg_red2;
 130         int isel_tpg_green2;
 131         int isel_tpg_blue2;
 132         int isel_ch_id;
 133         int isel_fmt_type;
 134         int isel_data_sel;
 135         int isel_sband_sel;
 136         int isel_sync_sel;
 137         int syncgen_hor_cnt;
 138         int syncgen_ver_cnt;
 139         int syncgen_frame_cnt;
 140         int soft_reset;
 141 };
 142
 143 #endif /* __GP_DEVICE_LOCAL_H_INCLUDED__ */