drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/timed_ctrl_global.h

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef __TIMED_CTRL_GLOBAL_H_INCLUDED__
  16 #define __TIMED_CTRL_GLOBAL_H_INCLUDED__
  17
  18 #define IS_TIMED_CTRL_VERSION_1
  19
  20 #include <timed_controller_defs.h>
  21
  22 /**
  23  * Order of the input bits for the timed controller taken from
  24  * ISP_CSS_2401 System Architecture Description valid for
  25  * 2400, 2401.
  26  *
  27  * Check for other systems.
  28  */
  29 #define HIVE_TIMED_CTRL_GPIO_PIN_0_BIT_ID                       0
  30 #define HIVE_TIMED_CTRL_GPIO_PIN_1_BIT_ID                       1
  31 #define HIVE_TIMED_CTRL_GPIO_PIN_2_BIT_ID                       2
  32 #define HIVE_TIMED_CTRL_GPIO_PIN_3_BIT_ID                       3
  33 #define HIVE_TIMED_CTRL_GPIO_PIN_4_BIT_ID                       4
  34 #define HIVE_TIMED_CTRL_GPIO_PIN_5_BIT_ID                       5
  35 #define HIVE_TIMED_CTRL_GPIO_PIN_6_BIT_ID                       6
  36 #define HIVE_TIMED_CTRL_GPIO_PIN_7_BIT_ID                       7
  37 #define HIVE_TIMED_CTRL_GPIO_PIN_8_BIT_ID                       8
  38 #define HIVE_TIMED_CTRL_GPIO_PIN_9_BIT_ID                       9
  39 #define HIVE_TIMED_CTRL_GPIO_PIN_10_BIT_ID                      10
  40 #define HIVE_TIMED_CTRL_GPIO_PIN_11_BIT_ID                      11
  41 #define HIVE_TIMED_CTRL_IRQ_SP_BIT_ID                           12
  42 #define HIVE_TIMED_CTRL_IRQ_ISP_BIT_ID                          13
  43 #define HIVE_TIMED_CTRL_IRQ_INPUT_SYSTEM_BIT_ID                 14
  44 #define HIVE_TIMED_CTRL_IRQ_INPUT_SELECTOR_BIT_ID               15
  45 #define HIVE_TIMED_CTRL_IRQ_IF_BLOCK_BIT_ID                     16
  46 #define HIVE_TIMED_CTRL_IRQ_GP_TIMER_0_BIT_ID                   17
  47 #define HIVE_TIMED_CTRL_IRQ_GP_TIMER_1_BIT_ID                   18
  48 #define HIVE_TIMED_CTRL_CSI_SOL_BIT_ID                          19
  49 #define HIVE_TIMED_CTRL_CSI_EOL_BIT_ID                          20
  50 #define HIVE_TIMED_CTRL_CSI_SOF_BIT_ID                          21
  51 #define HIVE_TIMED_CTRL_CSI_EOF_BIT_ID                          22
  52 #define HIVE_TIMED_CTRL_IRQ_IS_STREAMING_MONITOR_BIT_ID         23
  53
  54
  55
  56 #endif /* __TIMED_CTRL_GLOBAL_H_INCLUDED__ */