drivers/staging/rtl8188eu/hal/bb_cfg.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /******************************************************************************
   3 *
   4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5 *
   6 ******************************************************************************/
   7
   8 #include "odm_precomp.h"
   9
  10 #include <phy.h>
  11
  12 /* AGC_TAB_1T.TXT */
  13
  14 static u32 array_agc_tab_1t_8188e[] = {
  15                 0xC78, 0xFB000001,
  16                 0xC78, 0xFB010001,
  17                 0xC78, 0xFB020001,
  18                 0xC78, 0xFB030001,
  19                 0xC78, 0xFB040001,
  20                 0xC78, 0xFB050001,
  21                 0xC78, 0xFA060001,
  22                 0xC78, 0xF9070001,
  23                 0xC78, 0xF8080001,
  24                 0xC78, 0xF7090001,
  25                 0xC78, 0xF60A0001,
  26                 0xC78, 0xF50B0001,
  27                 0xC78, 0xF40C0001,
  28                 0xC78, 0xF30D0001,
  29                 0xC78, 0xF20E0001,
  30                 0xC78, 0xF10F0001,
  31                 0xC78, 0xF0100001,
  32                 0xC78, 0xEF110001,
  33                 0xC78, 0xEE120001,
  34                 0xC78, 0xED130001,
  35                 0xC78, 0xEC140001,
  36                 0xC78, 0xEB150001,
  37                 0xC78, 0xEA160001,
  38                 0xC78, 0xE9170001,
  39                 0xC78, 0xE8180001,
  40                 0xC78, 0xE7190001,
  41                 0xC78, 0xE61A0001,
  42                 0xC78, 0xE51B0001,
  43                 0xC78, 0xE41C0001,
  44                 0xC78, 0xE31D0001,
  45                 0xC78, 0xE21E0001,
  46                 0xC78, 0xE11F0001,
  47                 0xC78, 0x8A200001,
  48                 0xC78, 0x89210001,
  49                 0xC78, 0x88220001,
  50                 0xC78, 0x87230001,
  51                 0xC78, 0x86240001,
  52                 0xC78, 0x85250001,
  53                 0xC78, 0x84260001,
  54                 0xC78, 0x83270001,
  55                 0xC78, 0x82280001,
  56                 0xC78, 0x6B290001,
  57                 0xC78, 0x6A2A0001,
  58                 0xC78, 0x692B0001,
  59                 0xC78, 0x682C0001,
  60                 0xC78, 0x672D0001,
  61                 0xC78, 0x662E0001,
  62                 0xC78, 0x652F0001,
  63                 0xC78, 0x64300001,
  64                 0xC78, 0x63310001,
  65                 0xC78, 0x62320001,
  66                 0xC78, 0x61330001,
  67                 0xC78, 0x46340001,
  68                 0xC78, 0x45350001,
  69                 0xC78, 0x44360001,
  70                 0xC78, 0x43370001,
  71                 0xC78, 0x42380001,
  72                 0xC78, 0x41390001,
  73                 0xC78, 0x403A0001,
  74                 0xC78, 0x403B0001,
  75                 0xC78, 0x403C0001,
  76                 0xC78, 0x403D0001,
  77                 0xC78, 0x403E0001,
  78                 0xC78, 0x403F0001,
  79                 0xC78, 0xFB400001,
  80                 0xC78, 0xFB410001,
  81                 0xC78, 0xFB420001,
  82                 0xC78, 0xFB430001,
  83                 0xC78, 0xFB440001,
  84                 0xC78, 0xFB450001,
  85                 0xC78, 0xFB460001,
  86                 0xC78, 0xFB470001,
  87                 0xC78, 0xFB480001,
  88                 0xC78, 0xFA490001,
  89                 0xC78, 0xF94A0001,
  90                 0xC78, 0xF84B0001,
  91                 0xC78, 0xF74C0001,
  92                 0xC78, 0xF64D0001,
  93                 0xC78, 0xF54E0001,
  94                 0xC78, 0xF44F0001,
  95                 0xC78, 0xF3500001,
  96                 0xC78, 0xF2510001,
  97                 0xC78, 0xF1520001,
  98                 0xC78, 0xF0530001,
  99                 0xC78, 0xEF540001,
 100                 0xC78, 0xEE550001,
 101                 0xC78, 0xED560001,
 102                 0xC78, 0xEC570001,
 103                 0xC78, 0xEB580001,
 104                 0xC78, 0xEA590001,
 105                 0xC78, 0xE95A0001,
 106                 0xC78, 0xE85B0001,
 107                 0xC78, 0xE75C0001,
 108                 0xC78, 0xE65D0001,
 109                 0xC78, 0xE55E0001,
 110                 0xC78, 0xE45F0001,
 111                 0xC78, 0xE3600001,
 112                 0xC78, 0xE2610001,
 113                 0xC78, 0xC3620001,
 114                 0xC78, 0xC2630001,
 115                 0xC78, 0xC1640001,
 116                 0xC78, 0x8B650001,
 117                 0xC78, 0x8A660001,
 118                 0xC78, 0x89670001,
 119                 0xC78, 0x88680001,
 120                 0xC78, 0x87690001,
 121                 0xC78, 0x866A0001,
 122                 0xC78, 0x856B0001,
 123                 0xC78, 0x846C0001,
 124                 0xC78, 0x676D0001,
 125                 0xC78, 0x666E0001,
 126                 0xC78, 0x656F0001,
 127                 0xC78, 0x64700001,
 128                 0xC78, 0x63710001,
 129                 0xC78, 0x62720001,
 130                 0xC78, 0x61730001,
 131                 0xC78, 0x60740001,
 132                 0xC78, 0x46750001,
 133                 0xC78, 0x45760001,
 134                 0xC78, 0x44770001,
 135                 0xC78, 0x43780001,
 136                 0xC78, 0x42790001,
 137                 0xC78, 0x417A0001,
 138                 0xC78, 0x407B0001,
 139                 0xC78, 0x407C0001,
 140                 0xC78, 0x407D0001,
 141                 0xC78, 0x407E0001,
 142                 0xC78, 0x407F0001,
 143 };
 144
 145 static bool set_baseband_agc_config(struct adapter *adapt)
 146 {
 147         u32 i;
 148         const u32 arraylen = ARRAY_SIZE(array_agc_tab_1t_8188e);
 149         u32 *array = array_agc_tab_1t_8188e;
 150
 151         for (i = 0; i < arraylen; i += 2) {
 152                 u32 v1 = array[i];
 153                 u32 v2 = array[i + 1];
 154
 155                 if (v1 < 0xCDCDCDCD) {
 156                         phy_set_bb_reg(adapt, v1, bMaskDWord, v2);
 157                         udelay(1);
 158                 }
 159         }
 160         return true;
 161 }
 162
 163 /*  PHY_REG_1T.TXT  */
 164
 165 static u32 array_phy_reg_1t_8188e[] = {
 166                 0x800, 0x80040000,
 167                 0x804, 0x00000003,
 168                 0x808, 0x0000FC00,
 169                 0x80C, 0x0000000A,
 170                 0x810, 0x10001331,
 171                 0x814, 0x020C3D10,
 172                 0x818, 0x02200385,
 173                 0x81C, 0x00000000,
 174                 0x820, 0x01000100,
 175                 0x824, 0x00390204,
 176                 0x828, 0x00000000,
 177                 0x82C, 0x00000000,
 178                 0x830, 0x00000000,
 179                 0x834, 0x00000000,
 180                 0x838, 0x00000000,
 181                 0x83C, 0x00000000,
 182                 0x840, 0x00010000,
 183                 0x844, 0x00000000,
 184                 0x848, 0x00000000,
 185                 0x84C, 0x00000000,
 186                 0x850, 0x00000000,
 187                 0x854, 0x00000000,
 188                 0x858, 0x569A11A9,
 189                 0x85C, 0x01000014,
 190                 0x860, 0x66F60110,
 191                 0x864, 0x061F0649,
 192                 0x868, 0x00000000,
 193                 0x86C, 0x27272700,
 194                 0x870, 0x07000760,
 195                 0x874, 0x25004000,
 196                 0x878, 0x00000808,
 197                 0x87C, 0x00000000,
 198                 0x880, 0xB0000C1C,
 199                 0x884, 0x00000001,
 200                 0x888, 0x00000000,
 201                 0x88C, 0xCCC000C0,
 202                 0x890, 0x00000800,
 203                 0x894, 0xFFFFFFFE,
 204                 0x898, 0x40302010,
 205                 0x89C, 0x00706050,
 206                 0x900, 0x00000000,
 207                 0x904, 0x00000023,
 208                 0x908, 0x00000000,
 209                 0x90C, 0x81121111,
 210                 0x910, 0x00000002,
 211                 0x914, 0x00000201,
 212                 0xA00, 0x00D047C8,
 213                 0xA04, 0x80FF000C,
 214                 0xA08, 0x8C838300,
 215                 0xA0C, 0x2E7F120F,
 216                 0xA10, 0x9500BB78,
 217                 0xA14, 0x1114D028,
 218                 0xA18, 0x00881117,
 219                 0xA1C, 0x89140F00,
 220                 0xA20, 0x1A1B0000,
 221                 0xA24, 0x090E1317,
 222                 0xA28, 0x00000204,
 223                 0xA2C, 0x00D30000,
 224                 0xA70, 0x101FBF00,
 225                 0xA74, 0x00000007,
 226                 0xA78, 0x00000900,
 227                 0xA7C, 0x225B0606,
 228                 0xA80, 0x218075B1,
 229                 0xB2C, 0x80000000,
 230                 0xC00, 0x48071D40,
 231                 0xC04, 0x03A05611,
 232                 0xC08, 0x000000E4,
 233                 0xC0C, 0x6C6C6C6C,
 234                 0xC10, 0x08800000,
 235                 0xC14, 0x40000100,
 236                 0xC18, 0x08800000,
 237                 0xC1C, 0x40000100,
 238                 0xC20, 0x00000000,
 239                 0xC24, 0x00000000,
 240                 0xC28, 0x00000000,
 241                 0xC2C, 0x00000000,
 242                 0xC30, 0x69E9AC47,
 243                 0xC34, 0x469652AF,
 244                 0xC38, 0x49795994,
 245                 0xC3C, 0x0A97971C,
 246                 0xC40, 0x1F7C403F,
 247                 0xC44, 0x000100B7,
 248                 0xC48, 0xEC020107,
 249                 0xC4C, 0x007F037F,
 250                 0xC50, 0x69553420,
 251                 0xC54, 0x43BC0094,
 252                 0xC58, 0x00013169,
 253                 0xC5C, 0x00250492,
 254                 0xC60, 0x00000000,
 255                 0xC64, 0x7112848B,
 256                 0xC68, 0x47C00BFF,
 257                 0xC6C, 0x00000036,
 258                 0xC70, 0x2C7F000D,
 259                 0xC74, 0x020610DB,
 260                 0xC78, 0x0000001F,
 261                 0xC7C, 0x00B91612,
 262                 0xC80, 0x390000E4,
 263                 0xC84, 0x20F60000,
 264                 0xC88, 0x40000100,
 265                 0xC8C, 0x20200000,
 266                 0xC90, 0x00091521,
 267                 0xC94, 0x00000000,
 268                 0xC98, 0x00121820,
 269                 0xC9C, 0x00007F7F,
 270                 0xCA0, 0x00000000,
 271                 0xCA4, 0x000300A0,
 272                 0xCA8, 0x00000000,
 273                 0xCAC, 0x00000000,
 274                 0xCB0, 0x00000000,
 275                 0xCB4, 0x00000000,
 276                 0xCB8, 0x00000000,
 277                 0xCBC, 0x28000000,
 278                 0xCC0, 0x00000000,
 279                 0xCC4, 0x00000000,
 280                 0xCC8, 0x00000000,
 281                 0xCCC, 0x00000000,
 282                 0xCD0, 0x00000000,
 283                 0xCD4, 0x00000000,
 284                 0xCD8, 0x64B22427,
 285                 0xCDC, 0x00766932,
 286                 0xCE0, 0x00222222,
 287                 0xCE4, 0x00000000,
 288                 0xCE8, 0x37644302,
 289                 0xCEC, 0x2F97D40C,
 290                 0xD00, 0x00000740,
 291                 0xD04, 0x00020401,
 292                 0xD08, 0x0000907F,
 293                 0xD0C, 0x20010201,
 294                 0xD10, 0xA0633333,
 295                 0xD14, 0x3333BC43,
 296                 0xD18, 0x7A8F5B6F,
 297                 0xD2C, 0xCC979975,
 298                 0xD30, 0x00000000,
 299                 0xD34, 0x80608000,
 300                 0xD38, 0x00000000,
 301                 0xD3C, 0x00127353,
 302                 0xD40, 0x00000000,
 303                 0xD44, 0x00000000,
 304                 0xD48, 0x00000000,
 305                 0xD4C, 0x00000000,
 306                 0xD50, 0x6437140A,
 307                 0xD54, 0x00000000,
 308                 0xD58, 0x00000282,
 309                 0xD5C, 0x30032064,
 310                 0xD60, 0x4653DE68,
 311                 0xD64, 0x04518A3C,
 312                 0xD68, 0x00002101,
 313                 0xD6C, 0x2A201C16,
 314                 0xD70, 0x1812362E,
 315                 0xD74, 0x322C2220,
 316                 0xD78, 0x000E3C24,
 317                 0xE00, 0x2D2D2D2D,
 318                 0xE04, 0x2D2D2D2D,
 319                 0xE08, 0x0390272D,
 320                 0xE10, 0x2D2D2D2D,
 321                 0xE14, 0x2D2D2D2D,
 322                 0xE18, 0x2D2D2D2D,
 323                 0xE1C, 0x2D2D2D2D,
 324                 0xE28, 0x00000000,
 325                 0xE30, 0x1000DC1F,
 326                 0xE34, 0x10008C1F,
 327                 0xE38, 0x02140102,
 328                 0xE3C, 0x681604C2,
 329                 0xE40, 0x01007C00,
 330                 0xE44, 0x01004800,
 331                 0xE48, 0xFB000000,
 332                 0xE4C, 0x000028D1,
 333                 0xE50, 0x1000DC1F,
 334                 0xE54, 0x10008C1F,
 335                 0xE58, 0x02140102,
 336                 0xE5C, 0x28160D05,
 337                 0xE60, 0x00000008,
 338                 0xE68, 0x001B25A4,
 339                 0xE6C, 0x00C00014,
 340                 0xE70, 0x00C00014,
 341                 0xE74, 0x01000014,
 342                 0xE78, 0x01000014,
 343                 0xE7C, 0x01000014,
 344                 0xE80, 0x01000014,
 345                 0xE84, 0x00C00014,
 346                 0xE88, 0x01000014,
 347                 0xE8C, 0x00C00014,
 348                 0xED0, 0x00C00014,
 349                 0xED4, 0x00C00014,
 350                 0xED8, 0x00C00014,
 351                 0xEDC, 0x00000014,
 352                 0xEE0, 0x00000014,
 353                 0xEEC, 0x01C00014,
 354                 0xF14, 0x00000003,
 355                 0xF4C, 0x00000000,
 356                 0xF00, 0x00000300,
 357 };
 358
 359 static void rtl_bb_delay(struct adapter *adapt, u32 addr, u32 data)
 360 {
 361         if (addr == 0xfe) {
 362                 msleep(50);
 363         } else if (addr == 0xfd) {
 364                 mdelay(5);
 365         } else if (addr == 0xfc) {
 366                 mdelay(1);
 367         } else if (addr == 0xfb) {
 368                 udelay(50);
 369         } else if (addr == 0xfa) {
 370                 udelay(5);
 371         } else if (addr == 0xf9) {
 372                 udelay(1);
 373         } else {
 374                 phy_set_bb_reg(adapt, addr, bMaskDWord, data);
 375                 /*  Add 1us delay between BB/RF register setting. */
 376                 udelay(1);
 377         }
 378 }
 379
 380 static bool set_baseband_phy_config(struct adapter *adapt)
 381 {
 382         u32 i;
 383         const u32 arraylen = ARRAY_SIZE(array_phy_reg_1t_8188e);
 384         u32 *array = array_phy_reg_1t_8188e;
 385
 386         for (i = 0; i < arraylen; i += 2) {
 387                 u32 v1 = array[i];
 388                 u32 v2 = array[i + 1];
 389
 390                 if (v1 < 0xCDCDCDCD)
 391                         rtl_bb_delay(adapt, v1, v2);
 392         }
 393         return true;
 394 }
 395
 396 /*  PHY_REG_PG.TXT  */
 397
 398 static u32 array_phy_reg_pg_8188e[] = {
 399                 0xE00, 0xFFFFFFFF, 0x06070809,
 400                 0xE04, 0xFFFFFFFF, 0x02020405,
 401                 0xE08, 0x0000FF00, 0x00000006,
 402                 0x86C, 0xFFFFFF00, 0x00020400,
 403                 0xE10, 0xFFFFFFFF, 0x08090A0B,
 404                 0xE14, 0xFFFFFFFF, 0x01030607,
 405                 0xE18, 0xFFFFFFFF, 0x08090A0B,
 406                 0xE1C, 0xFFFFFFFF, 0x01030607,
 407                 0xE00, 0xFFFFFFFF, 0x00000000,
 408                 0xE04, 0xFFFFFFFF, 0x00000000,
 409                 0xE08, 0x0000FF00, 0x00000000,
 410                 0x86C, 0xFFFFFF00, 0x00000000,
 411                 0xE10, 0xFFFFFFFF, 0x00000000,
 412                 0xE14, 0xFFFFFFFF, 0x00000000,
 413                 0xE18, 0xFFFFFFFF, 0x00000000,
 414                 0xE1C, 0xFFFFFFFF, 0x00000000,
 415                 0xE00, 0xFFFFFFFF, 0x02020202,
 416                 0xE04, 0xFFFFFFFF, 0x00020202,
 417                 0xE08, 0x0000FF00, 0x00000000,
 418                 0x86C, 0xFFFFFF00, 0x00000000,
 419                 0xE10, 0xFFFFFFFF, 0x04040404,
 420                 0xE14, 0xFFFFFFFF, 0x00020404,
 421                 0xE18, 0xFFFFFFFF, 0x00000000,
 422                 0xE1C, 0xFFFFFFFF, 0x00000000,
 423                 0xE00, 0xFFFFFFFF, 0x02020202,
 424                 0xE04, 0xFFFFFFFF, 0x00020202,
 425                 0xE08, 0x0000FF00, 0x00000000,
 426                 0x86C, 0xFFFFFF00, 0x00000000,
 427                 0xE10, 0xFFFFFFFF, 0x04040404,
 428                 0xE14, 0xFFFFFFFF, 0x00020404,
 429                 0xE18, 0xFFFFFFFF, 0x00000000,
 430                 0xE1C, 0xFFFFFFFF, 0x00000000,
 431                 0xE00, 0xFFFFFFFF, 0x00000000,
 432                 0xE04, 0xFFFFFFFF, 0x00000000,
 433                 0xE08, 0x0000FF00, 0x00000000,
 434                 0x86C, 0xFFFFFF00, 0x00000000,
 435                 0xE10, 0xFFFFFFFF, 0x00000000,
 436                 0xE14, 0xFFFFFFFF, 0x00000000,
 437                 0xE18, 0xFFFFFFFF, 0x00000000,
 438                 0xE1C, 0xFFFFFFFF, 0x00000000,
 439                 0xE00, 0xFFFFFFFF, 0x02020202,
 440                 0xE04, 0xFFFFFFFF, 0x00020202,
 441                 0xE08, 0x0000FF00, 0x00000000,
 442                 0x86C, 0xFFFFFF00, 0x00000000,
 443                 0xE10, 0xFFFFFFFF, 0x04040404,
 444                 0xE14, 0xFFFFFFFF, 0x00020404,
 445                 0xE18, 0xFFFFFFFF, 0x00000000,
 446                 0xE1C, 0xFFFFFFFF, 0x00000000,
 447                 0xE00, 0xFFFFFFFF, 0x00000000,
 448                 0xE04, 0xFFFFFFFF, 0x00000000,
 449                 0xE08, 0x0000FF00, 0x00000000,
 450                 0x86C, 0xFFFFFF00, 0x00000000,
 451                 0xE10, 0xFFFFFFFF, 0x00000000,
 452                 0xE14, 0xFFFFFFFF, 0x00000000,
 453                 0xE18, 0xFFFFFFFF, 0x00000000,
 454                 0xE1C, 0xFFFFFFFF, 0x00000000,
 455                 0xE00, 0xFFFFFFFF, 0x00000000,
 456                 0xE04, 0xFFFFFFFF, 0x00000000,
 457                 0xE08, 0x0000FF00, 0x00000000,
 458                 0x86C, 0xFFFFFF00, 0x00000000,
 459                 0xE10, 0xFFFFFFFF, 0x00000000,
 460                 0xE14, 0xFFFFFFFF, 0x00000000,
 461                 0xE18, 0xFFFFFFFF, 0x00000000,
 462                 0xE1C, 0xFFFFFFFF, 0x00000000,
 463                 0xE00, 0xFFFFFFFF, 0x00000000,
 464                 0xE04, 0xFFFFFFFF, 0x00000000,
 465                 0xE08, 0x0000FF00, 0x00000000,
 466                 0x86C, 0xFFFFFF00, 0x00000000,
 467                 0xE10, 0xFFFFFFFF, 0x00000000,
 468                 0xE14, 0xFFFFFFFF, 0x00000000,
 469                 0xE18, 0xFFFFFFFF, 0x00000000,
 470                 0xE1C, 0xFFFFFFFF, 0x00000000,
 471                 0xE00, 0xFFFFFFFF, 0x00000000,
 472                 0xE04, 0xFFFFFFFF, 0x00000000,
 473                 0xE08, 0x0000FF00, 0x00000000,
 474                 0x86C, 0xFFFFFF00, 0x00000000,
 475                 0xE10, 0xFFFFFFFF, 0x00000000,
 476                 0xE14, 0xFFFFFFFF, 0x00000000,
 477                 0xE18, 0xFFFFFFFF, 0x00000000,
 478                 0xE1C, 0xFFFFFFFF, 0x00000000,
 479                 0xE00, 0xFFFFFFFF, 0x00000000,
 480                 0xE04, 0xFFFFFFFF, 0x00000000,
 481                 0xE08, 0x0000FF00, 0x00000000,
 482                 0x86C, 0xFFFFFF00, 0x00000000,
 483                 0xE10, 0xFFFFFFFF, 0x00000000,
 484                 0xE14, 0xFFFFFFFF, 0x00000000,
 485                 0xE18, 0xFFFFFFFF, 0x00000000,
 486                 0xE1C, 0xFFFFFFFF, 0x00000000,
 487
 488 };
 489
 490 static void store_pwrindex_offset(struct adapter *adapter,
 491                                   u32 regaddr, u32 bitmask, u32 data)
 492 {
 493         struct hal_data_8188e *hal_data = adapter->HalData;
 494         u32 * const power_level_offset =
 495                 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt];
 496
 497         if (regaddr == rTxAGC_A_Rate18_06)
 498                 power_level_offset[0] = data;
 499         if (regaddr == rTxAGC_A_Rate54_24)
 500                 power_level_offset[1] = data;
 501         if (regaddr == rTxAGC_A_CCK1_Mcs32)
 502                 power_level_offset[6] = data;
 503         if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
 504                 power_level_offset[7] = data;
 505         if (regaddr == rTxAGC_A_Mcs03_Mcs00)
 506                 power_level_offset[2] = data;
 507         if (regaddr == rTxAGC_A_Mcs07_Mcs04)
 508                 power_level_offset[3] = data;
 509         if (regaddr == rTxAGC_A_Mcs11_Mcs08)
 510                 power_level_offset[4] = data;
 511         if (regaddr == rTxAGC_A_Mcs15_Mcs12) {
 512                 power_level_offset[5] = data;
 513                 hal_data->pwrGroupCnt++;
 514         }
 515         if (regaddr == rTxAGC_B_Rate18_06)
 516                 power_level_offset[8] = data;
 517         if (regaddr == rTxAGC_B_Rate54_24)
 518                 power_level_offset[9] = data;
 519         if (regaddr == rTxAGC_B_CCK1_55_Mcs32)
 520                 power_level_offset[14] = data;
 521         if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
 522                 power_level_offset[15] = data;
 523         if (regaddr == rTxAGC_B_Mcs03_Mcs00)
 524                 power_level_offset[10] = data;
 525         if (regaddr == rTxAGC_B_Mcs07_Mcs04)
 526                 power_level_offset[11] = data;
 527         if (regaddr == rTxAGC_B_Mcs11_Mcs08)
 528                 power_level_offset[12] = data;
 529         if (regaddr == rTxAGC_B_Mcs15_Mcs12)
 530                 power_level_offset[13] = data;
 531 }
 532
 533 static void rtl_addr_delay(struct adapter *adapt,
 534                            u32 addr, u32 bit_mask, u32 data)
 535 {
 536         switch (addr) {
 537         case 0xfe:
 538                 msleep(50);
 539                 break;
 540         case 0xfd:
 541                 mdelay(5);
 542                 break;
 543         case 0xfc:
 544                 mdelay(1);
 545                 break;
 546         case 0xfb:
 547                 udelay(50);
 548                 break;
 549         case 0xfa:
 550                 udelay(5);
 551                 break;
 552         case 0xf9:
 553                 udelay(1);
 554                 break;
 555         default:
 556                 store_pwrindex_offset(adapt, addr, bit_mask, data);
 557         }
 558 }
 559
 560 static bool config_bb_with_pgheader(struct adapter *adapt)
 561 {
 562         u32 i;
 563         const u32 arraylen = ARRAY_SIZE(array_phy_reg_pg_8188e);
 564         u32 *array = array_phy_reg_pg_8188e;
 565
 566         for (i = 0; i < arraylen; i += 3) {
 567                 u32 v1 = array[i];
 568                 u32 v2 = array[i + 1];
 569                 u32 v3 = array[i + 2];
 570
 571                 if (v1 < 0xCDCDCDCD)
 572                         rtl_addr_delay(adapt, v1, v2, v3);
 573         }
 574         return true;
 575 }
 576
 577 static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *adapter)
 578 {
 579         struct bb_reg_def               *reg[4];
 580
 581         reg[RF_PATH_A] = &adapter->HalData->PHYRegDef[RF_PATH_A];
 582         reg[RF_PATH_B] = &adapter->HalData->PHYRegDef[RF_PATH_B];
 583
 584         reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
 585         reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
 586
 587         reg[RF_PATH_A]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
 588         reg[RF_PATH_B]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
 589
 590         reg[RF_PATH_A]->rfintfo = rFPGA0_XA_RFInterfaceOE;
 591         reg[RF_PATH_B]->rfintfo = rFPGA0_XB_RFInterfaceOE;
 592
 593         reg[RF_PATH_A]->rfintfe = rFPGA0_XA_RFInterfaceOE;
 594         reg[RF_PATH_B]->rfintfe = rFPGA0_XB_RFInterfaceOE;
 595
 596         reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter;
 597         reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter;
 598
 599         reg[RF_PATH_A]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
 600         reg[RF_PATH_B]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
 601
 602         reg[RF_PATH_A]->rfTxGainStage = rFPGA0_TxGainStage;
 603         reg[RF_PATH_B]->rfTxGainStage = rFPGA0_TxGainStage;
 604
 605         reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
 606         reg[RF_PATH_B]->rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
 607
 608         reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
 609         reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
 610
 611         reg[RF_PATH_A]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
 612         reg[RF_PATH_B]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
 613
 614         reg[RF_PATH_A]->rfAGCControl1 = rOFDM0_XAAGCCore1;
 615         reg[RF_PATH_B]->rfAGCControl1 = rOFDM0_XBAGCCore1;
 616
 617         reg[RF_PATH_A]->rfAGCControl2 = rOFDM0_XAAGCCore2;
 618         reg[RF_PATH_B]->rfAGCControl2 = rOFDM0_XBAGCCore2;
 619
 620         reg[RF_PATH_A]->rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 621         reg[RF_PATH_B]->rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 622
 623         reg[RF_PATH_A]->rfRxAFE = rOFDM0_XARxAFE;
 624         reg[RF_PATH_B]->rfRxAFE = rOFDM0_XBRxAFE;
 625
 626         reg[RF_PATH_A]->rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 627         reg[RF_PATH_B]->rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 628
 629         reg[RF_PATH_A]->rfTxAFE = rOFDM0_XATxAFE;
 630         reg[RF_PATH_B]->rfTxAFE = rOFDM0_XBTxAFE;
 631
 632         reg[RF_PATH_A]->rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 633         reg[RF_PATH_B]->rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 634
 635         reg[RF_PATH_A]->rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
 636         reg[RF_PATH_B]->rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
 637 }
 638
 639 static bool config_parafile(struct adapter *adapt)
 640 {
 641         struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
 642
 643         set_baseband_phy_config(adapt);
 644
 645         /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
 646         if (!eeprom->bautoload_fail_flag) {
 647                 adapt->HalData->pwrGroupCnt = 0;
 648                 config_bb_with_pgheader(adapt);
 649         }
 650         set_baseband_agc_config(adapt);
 651         return true;
 652 }
 653
 654 bool rtl88eu_phy_bb_config(struct adapter *adapt)
 655 {
 656         int rtstatus = true;
 657         u32 regval;
 658         u8 crystal_cap;
 659
 660         rtl88e_phy_init_bb_rf_register_definition(adapt);
 661
 662         /*  Enable BB and RF */
 663         regval = usb_read16(adapt, REG_SYS_FUNC_EN);
 664         usb_write16(adapt, REG_SYS_FUNC_EN,
 665                     (u16)(regval | BIT(13) | BIT(0) | BIT(1)));
 666
 667         usb_write8(adapt, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
 668
 669         usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA |
 670                    FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
 671
 672         /*  Config BB and AGC */
 673         rtstatus = config_parafile(adapt);
 674
 675         /*  write 0x24[16:11] = 0x24[22:17] = crystal_cap */
 676         crystal_cap = adapt->HalData->CrystalCap & 0x3F;
 677         phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800,
 678                        (crystal_cap | (crystal_cap << 6)));
 679
 680         return rtstatus;
 681 }